1 | |
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2 | # -*- python -*- |
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3 | |
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4 | Module('caba:reconfiguration:tsar_iob_cluster', |
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5 | classname = 'soclib::caba::TsarIobCluster', |
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6 | |
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7 | tmpl_parameters = [ |
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8 | parameter.Module('vci_param_int', default = 'caba:vci_param', |
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9 | cell_size = parameter.Reference('vci_data_width_int')), |
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10 | parameter.Module('vci_param_ext', default = 'caba:vci_param', |
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11 | cell_size = parameter.Reference('vci_data_width_ext')), |
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12 | parameter.Int('dspin_int_cmd_width'), |
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13 | parameter.Int('dspin_int_rsp_width'), |
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14 | parameter.Int('dspin_ram_cmd_width'), |
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15 | parameter.Int('dspin_ram_rsp_width'), |
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16 | ], |
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17 | |
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18 | header_files = [ |
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19 | '../source/include/tsar_iob_cluster.h', |
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20 | ], |
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21 | |
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22 | implementation_files = [ |
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23 | '../source/src/tsar_iob_cluster.cpp', |
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24 | ], |
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25 | |
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26 | uses = [ |
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27 | Uses('caba:base_module'), |
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28 | Uses('common:mapping_table'), |
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29 | Uses('common:iss2'), |
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30 | Uses('common:elf_file_loader'), |
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31 | |
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32 | # internal network components |
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33 | Uses('caba:vci_cc_vcache_wrapper', |
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34 | cell_size = parameter.Reference('vci_data_width_int'), |
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35 | dspin_in_width = parameter.Reference('dspin_int_cmd_width'), |
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36 | dspin_out_width = parameter.Reference('dspin_int_rsp_width'), |
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37 | iss_t = 'common:gdb_iss', |
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38 | gdb_iss_t = 'common:mips32el'), |
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39 | |
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40 | Uses('caba:vci_mem_cache', |
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41 | memc_cell_size_int = parameter.Reference('vci_data_width_int'), |
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42 | memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), |
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43 | dspin_in_width = parameter.Reference('dspin_int_rsp_width'), |
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44 | dspin_out_width = parameter.Reference('dspin_int_cmd_width')), |
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45 | |
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46 | Uses('caba:vci_xicu', |
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47 | cell_size = parameter.Reference('vci_data_width_int')), |
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48 | |
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49 | Uses('caba:vci_multi_dma', |
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50 | cell_size = parameter.Reference('vci_data_width_int')), |
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51 | |
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52 | Uses('caba:vci_simple_rom', |
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53 | cell_size = parameter.Reference('vci_data_width_int')), |
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54 | |
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55 | Uses('caba:vci_local_crossbar', |
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56 | cell_size = parameter.Reference('vci_data_width_int')), |
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57 | |
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58 | Uses('caba:dspin_local_crossbar', |
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59 | flit_width = parameter.Reference('dspin_int_cmd_width')), |
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60 | |
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61 | Uses('caba:dspin_local_crossbar', |
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62 | flit_width = parameter.Reference('dspin_int_rsp_width')), |
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63 | |
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64 | Uses('caba:dspin_local_crossbar', |
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65 | flit_width = parameter.Reference('dspin_ram_cmd_width')), |
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66 | |
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67 | Uses('caba:dspin_local_crossbar', |
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68 | flit_width = parameter.Reference('dspin_ram_rsp_width')), |
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69 | |
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70 | Uses('caba:vci_dspin_initiator_wrapper', |
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71 | cell_size = parameter.Reference('vci_data_width_int'), |
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72 | dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), |
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73 | dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), |
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74 | |
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75 | Uses('caba:vci_dspin_target_wrapper', |
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76 | cell_size = parameter.Reference('vci_data_width_int'), |
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77 | dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), |
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78 | dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), |
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79 | |
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80 | Uses('caba:virtual_dspin_router', |
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81 | flit_width = parameter.Reference('dspin_int_cmd_width')), |
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82 | |
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83 | Uses('caba:virtual_dspin_router', |
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84 | flit_width = parameter.Reference('dspin_int_rsp_width')), |
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85 | |
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86 | # RAM network components |
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87 | Uses('caba:vci_dspin_initiator_wrapper', |
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88 | cell_size = parameter.Reference('vci_data_width_ext'), |
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89 | dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), |
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90 | dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), |
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91 | |
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92 | Uses('caba:vci_dspin_target_wrapper', |
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93 | cell_size = parameter.Reference('vci_data_width_ext'), |
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94 | dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), |
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95 | dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), |
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96 | |
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97 | Uses('caba:dspin_router', |
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98 | flit_width = parameter.Reference('dspin_ram_cmd_width')), |
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99 | |
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100 | Uses('caba:dspin_router', |
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101 | flit_width = parameter.Reference('dspin_ram_rsp_width')), |
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102 | |
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103 | Uses('caba:vci_simple_ram', |
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104 | cell_size = parameter.Reference('vci_data_width_ext')), |
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105 | |
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106 | # IOX network components |
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107 | Uses('caba:vci_io_bridge', |
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108 | iob_cell_size_int = parameter.Reference('vci_data_width_int'), |
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109 | iob_cell_size_ext = parameter.Reference('vci_data_width_ext')), |
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110 | ], |
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111 | |
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112 | ports = [ |
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113 | Port('caba:bit_in', 'p_resetn', auto = 'resetn'), |
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114 | Port('caba:clock_in', 'p_clk', auto = 'clock'), |
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115 | |
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116 | Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], |
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117 | dspin_data_size = parameter.Reference('dspin_int_cmd_width')), |
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118 | Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], |
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119 | dspin_data_size = parameter.Reference('dspin_int_cmd_width')), |
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120 | Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], |
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121 | dspin_data_size = parameter.Reference('dspin_int_rsp_width')), |
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122 | Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], |
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123 | dspin_data_size = parameter.Reference('dspin_int_rsp_width')), |
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124 | |
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125 | Port('caba:dspin_output', 'p_ram_cmd_out', [4], |
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126 | dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), |
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127 | Port('caba:dspin_input', 'p_ram_cmd_in', [4], |
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128 | dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), |
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129 | Port('caba:dspin_output', 'p_ram_rsp_out', [4], |
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130 | dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), |
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131 | Port('caba:dspin_input', 'p_ram_rsp_in', [4], |
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132 | dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), |
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133 | ], |
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134 | ) |
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135 | |
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136 | |
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