1 | ////////////////////////////////////////////////////////////////////////////// |
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2 | // File: tsar_iob_cluster.h |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : april 2013 |
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6 | // This program is released under the GNU public license |
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7 | ////////////////////////////////////////////////////////////////////////////// |
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8 | |
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9 | #ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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10 | #define SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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11 | |
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12 | #include <systemc> |
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13 | #include <sys/time.h> |
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14 | #include <iostream> |
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15 | #include <sstream> |
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16 | #include <cstdlib> |
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17 | #include <cstdarg> |
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18 | |
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19 | #include "gdbserver.h" |
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20 | #include "mapping_table.h" |
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21 | #include "mips32.h" |
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22 | #include "vci_simple_ram.h" |
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23 | #include "vci_xicu.h" |
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24 | #include "vci_local_crossbar.h" |
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25 | #include "dspin_local_crossbar.h" |
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26 | #include "vci_dspin_initiator_wrapper.h" |
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27 | #include "vci_dspin_target_wrapper.h" |
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28 | #include "dspin_router.h" |
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29 | #include "virtual_dspin_router.h" |
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30 | #include "vci_multi_dma.h" |
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31 | #include "vci_mem_cache.h" |
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32 | #include "vci_cc_vcache_wrapper.h" |
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33 | #include "vci_io_bridge.h" |
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34 | #include "vci_simple_rom.h" |
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35 | |
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36 | namespace soclib { namespace caba { |
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37 | |
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38 | /////////////////////////////////////////////////////////////////////////// |
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39 | template<typename vci_param_int, |
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40 | typename vci_param_ext, |
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41 | size_t dspin_int_cmd_width, |
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42 | size_t dspin_int_rsp_width, |
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43 | size_t dspin_ram_cmd_width, |
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44 | size_t dspin_ram_rsp_width> |
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45 | class TsarIobCluster |
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46 | /////////////////////////////////////////////////////////////////////////// |
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47 | : public soclib::caba::BaseModule |
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48 | { |
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49 | |
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50 | public: |
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51 | |
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52 | // Ports |
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53 | sc_in<bool> p_clk; |
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54 | sc_in<bool> p_resetn; |
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55 | |
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56 | // Thes two ports are used to connect IOB to IOX nework in top cell |
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57 | soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; |
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58 | soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; |
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59 | |
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60 | // These arrays of ports are used to connect the INT & RAM networks in top cell |
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61 | soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; |
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62 | soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; |
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63 | soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out; |
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64 | soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in; |
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65 | |
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66 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; |
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67 | soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; |
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68 | soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; |
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69 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; |
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70 | |
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71 | // interrupt signals |
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72 | sc_signal<bool> signal_false; |
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73 | sc_signal<bool> signal_proc_it[16]; |
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74 | sc_signal<bool> signal_irq_mdma[8]; |
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75 | sc_signal<bool> signal_irq_memc; |
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76 | |
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77 | // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars |
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78 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; |
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79 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; |
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80 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; |
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81 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; |
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82 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; |
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83 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; |
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84 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; |
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85 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; |
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86 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; |
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87 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; |
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88 | |
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89 | // INT network VCI signals between VCI components and VCI local crossbar |
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90 | VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; |
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91 | VciSignals<vci_param_int> signal_int_vci_ini_mdma; |
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92 | VciSignals<vci_param_int> signal_int_vci_ini_iobx; |
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93 | |
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94 | VciSignals<vci_param_int> signal_int_vci_tgt_memc; |
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95 | VciSignals<vci_param_int> signal_int_vci_tgt_xicu; |
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96 | VciSignals<vci_param_int> signal_int_vci_tgt_mdma; |
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97 | VciSignals<vci_param_int> signal_int_vci_tgt_brom; |
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98 | VciSignals<vci_param_int> signal_int_vci_tgt_iobx; |
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99 | |
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100 | VciSignals<vci_param_int> signal_int_vci_l2g; |
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101 | VciSignals<vci_param_int> signal_int_vci_g2l; |
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102 | |
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103 | // Coherence DSPIN signals between DSPIN local crossbars and CC components |
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104 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; |
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105 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; |
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106 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; |
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107 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; |
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108 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; |
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109 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; |
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110 | |
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111 | // RAM network VCI signals between VCI components and VCI/DSPIN wrappers |
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112 | VciSignals<vci_param_ext> signal_ram_vci_ini_memc; |
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113 | VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; |
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114 | VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; |
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115 | |
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116 | // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar |
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117 | // and routers |
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118 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; |
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119 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; |
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120 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; |
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121 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; |
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122 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i; |
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123 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i; |
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124 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar; |
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125 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar; |
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126 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false; |
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127 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false; |
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128 | |
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129 | ////////////////////////////////////// |
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130 | // Hardwate Components (pointers) |
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131 | ////////////////////////////////////// |
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132 | VciCcVCacheWrapper<vci_param_int, |
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133 | dspin_int_cmd_width, |
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134 | dspin_int_rsp_width, |
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135 | GdbServer<Mips32ElIss> >* proc[8]; |
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136 | |
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137 | VciMemCache<vci_param_int, |
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138 | vci_param_ext, |
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139 | dspin_int_rsp_width, |
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140 | dspin_int_cmd_width>* memc; |
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141 | |
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142 | VciDspinInitiatorWrapper<vci_param_ext, |
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143 | dspin_ram_cmd_width, |
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144 | dspin_ram_rsp_width>* memc_ram_wi; |
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145 | |
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146 | VciXicu<vci_param_int>* xicu; |
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147 | |
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148 | VciMultiDma<vci_param_int>* mdma; |
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149 | |
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150 | VciSimpleRom<vci_param_int>* brom; |
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151 | |
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152 | VciLocalCrossbar<vci_param_int>* int_xbar_d; |
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153 | |
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154 | VciDspinInitiatorWrapper<vci_param_int, |
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155 | dspin_int_cmd_width, |
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156 | dspin_int_rsp_width>* int_wi_gate_d; |
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157 | |
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158 | VciDspinTargetWrapper<vci_param_int, |
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159 | dspin_int_cmd_width, |
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160 | dspin_int_rsp_width>* int_wt_gate_d; |
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161 | |
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162 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; |
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163 | DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; |
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164 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; |
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165 | |
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166 | VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd; |
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167 | VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp; |
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168 | |
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169 | VciSimpleRam<vci_param_ext>* xram; |
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170 | |
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171 | VciDspinTargetWrapper<vci_param_ext, |
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172 | dspin_ram_cmd_width, |
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173 | dspin_ram_rsp_width>* xram_ram_wt; |
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174 | |
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175 | DspinRouter<dspin_ram_cmd_width>* ram_router_cmd; |
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176 | DspinRouter<dspin_ram_rsp_width>* ram_router_rsp; |
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177 | |
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178 | DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd; |
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179 | DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp; |
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180 | |
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181 | |
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182 | // IO Network Components (not instanciated in all clusters) |
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183 | |
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184 | VciIoBridge<vci_param_int, |
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185 | vci_param_ext>* iob; |
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186 | |
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187 | VciDspinInitiatorWrapper<vci_param_ext, |
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188 | dspin_ram_cmd_width, |
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189 | dspin_ram_rsp_width>* iob_ram_wi; |
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190 | |
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191 | // cluster constructor |
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192 | TsarIobCluster( sc_module_name insname, |
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193 | size_t nb_procs, |
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194 | size_t nb_dmas, |
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195 | size_t x, // x coordinate |
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196 | size_t y, // y coordinate |
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197 | size_t x_size, |
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198 | size_t y_size, |
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199 | |
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200 | size_t p_width, // pid field bits |
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201 | |
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202 | const soclib::common::MappingTable &mt_int, |
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203 | const soclib::common::MappingTable &mt_ext, |
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204 | const soclib::common::MappingTable &mt_iox, |
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205 | |
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206 | size_t x_width, // x field bits |
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207 | size_t y_width, // y field bits |
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208 | size_t l_width, // l field bits |
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209 | |
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210 | size_t int_memc_tgt_id, |
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211 | size_t int_xicu_tgt_id, |
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212 | size_t int_mdma_tgt_id, |
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213 | size_t int_brom_tgt_id, |
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214 | size_t int_iobx_tgt_id, |
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215 | size_t int_proc_ini_id, |
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216 | size_t int_mdma_ini_id, |
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217 | size_t int_iobx_ini_id, |
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218 | |
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219 | size_t ram_xram_tgt_id, |
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220 | size_t ram_memc_ini_id, |
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221 | size_t ram_iobx_ini_id, |
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222 | |
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223 | bool is_io, |
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224 | size_t iox_iobx_tgt_id, |
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225 | size_t iox_iobx_ini_id, |
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226 | |
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227 | size_t memc_ways, |
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228 | size_t memc_sets, |
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229 | size_t l1_i_ways, |
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230 | size_t l1_i_sets, |
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231 | size_t l1_d_ways, |
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232 | size_t l1_d_sets, |
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233 | size_t xram_latency, |
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234 | size_t xcu_nb_inputs, |
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235 | |
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236 | bool distboot, |
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237 | |
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238 | const Loader &loader, // loader for XRAM |
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239 | |
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240 | uint32_t frozen_cycles, |
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241 | uint32_t start_debug_cycle, |
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242 | bool memc_debug_ok, |
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243 | bool proc_debug_ok, |
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244 | bool iob0_debug_ok ); |
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245 | |
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246 | protected: |
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247 | |
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248 | SC_HAS_PROCESS(TsarIobCluster); |
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249 | |
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250 | void init(); |
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251 | |
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252 | |
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253 | }; |
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254 | |
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255 | }} |
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256 | |
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257 | #endif |
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258 | |
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259 | // Local Variables: |
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260 | // tab-width: 3 |
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261 | // c-basic-offset: 3 |
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262 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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263 | // indent-tabs-mode: nil |
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264 | // End: |
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265 | |
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266 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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267 | // |
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