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tsar_iob_cluster.cpp

Last change on this file was 1027, checked in by cfuguet, 9 years ago
Improving documentation of the reconfiguration/tsar_generic_iob platform.
File size: 35.5 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_drom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_hwi,
76	size_t xcu_nb_pti,
77	size_t xcu_nb_wti,
78	size_t xcu_nb_out,
79	size_t irq_per_proc,
80
81	bool disable_procs,
82
83	const Loader &loader,
84
85	uint32_t frozen_cycles,
86	uint32_t debug_start_cycle,
87	bool memc_debug_ok,
88	bool proc_debug_ok,
89	bool iob_debug_ok ) :
90
91	// constructor initialization list
92
93	soclib::caba::BaseModule(insname),
94	p_clk("clk"),
95	p_resetn("resetn"),
96	p_false("false"),
97	m_nb_procs(nb_procs),
98	m_disable_procs(disable_procs)
99	{
100
101	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
102
103	size_t cluster_id = (x_id << y_width) \| y_id;
104
105	// Vectors of DSPIN ports for inter-cluster communications
106	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
107	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
108	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
109	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
110
111	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
112	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
113	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
114	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
115
116	// VCI ports from IOB to IOX network (only in IO clusters)
117	if (is_io)
118	{
119	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
120	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
121	}
122
123	/////////////////////////////////////////////////////////////////////////////
124	// Hardware components
125	/////////////////////////////////////////////////////////////////////////////
126
127	//////////// PROCS
128	for (size_t p = 0; p < nb_procs && !m_disable_procs; p++)
129	{
130	std::ostringstream s_proc;
131	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
132	proc[p] = new VciCcVCacheWrapper<vci_param_int,
133	dspin_int_cmd_width,
134	dspin_int_rsp_width,
135	GdbServer<Mips32ElIss> >(
136	s_proc.str().c_str(),
137	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
138	mt_int, // Mapping Table INT network
139	IntTab(cluster_id,p), // SRCID
140	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
141	8, // ITLB ways
142	8, // ITLB sets
143	8, // DTLB ways
144	8, // DTLB sets
145	l1_i_ways, l1_i_sets, 16, // ICACHE size
146	l1_d_ways, l1_d_sets, 16, // DCACHE size
147	4, // WBUF nlines
148	4, // WBUF nwords
149	x_width, // number of bits for x coordinate
150	y_width, // number of bits for y coordinate
151	frozen_cycles, // max frozen cycles
152	debug_start_cycle,
153	proc_debug_ok);
154
155	// initialize physical address extension with cluster ID when using
156	// distributed boot
157	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
158	proc[p]->set_icache_paddr_ext_reset(cluster_id);
159	}
160
161	/////////// MEMC
162	std::ostringstream s_memc;
163	s_memc << "memc_" << x_id << "_" << y_id;
164	memc = new VciMemCache<vci_param_int,
165	vci_param_ext,
166	dspin_int_rsp_width,
167	dspin_int_cmd_width>(
168	s_memc.str().c_str(),
169	mt_int, // Mapping Table INT network
170	mt_ram, // Mapping Table RAM network
171	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
172	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
173	x_width, // number of bits for x coordinate
174	y_width, // number of bits for y coordinate
175	memc_ways, memc_sets, 16, // CACHE SIZE
176	3, // MAX NUMBER OF COPIES
177	4096, // HEAP SIZE
178	8, // TRANSACTION TABLE DEPTH
179	8, // UPDATE TABLE DEPTH
180	8, // INVALIDATE TABLE DEPTH
181	debug_start_cycle,
182	memc_debug_ok );
183
184	std::ostringstream s_wi_memc;
185	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
186	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
187	dspin_ram_cmd_width,
188	dspin_ram_rsp_width>(
189	s_wi_memc.str().c_str(),
190	x_width + y_width + l_width);
191
192	/////////// XICU
193	std::ostringstream s_xicu;
194	s_xicu << "xicu_" << x_id << "_" << y_id;
195	xicu = new VciXicu<vci_param_int>(
196	s_xicu.str().c_str(),
197	mt_int, // mapping table INT network
198	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
199	xcu_nb_pti, // number of timer IRQs
200	xcu_nb_hwi, // number of hard IRQs
201	xcu_nb_wti, // number of soft IRQs
202	xcu_nb_out, // number of output IRQs
203	6); // number of config regs
204
205	//////////// MDMA
206	std::ostringstream s_mdma;
207	s_mdma << "mdma_" << x_id << "_" << y_id;
208	mdma = new VciMultiDma<vci_param_int>(
209	s_mdma.str().c_str(),
210	mt_int,
211	IntTab(cluster_id, nb_procs), // SRCID
212	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
213	64, // burst size
214	nb_dmas); // number of IRQs
215
216	/////////// DISTRIBUTED ROM
217	std::ostringstream s_drom;
218	s_drom << "drom_" << x_id << "_" << y_id;
219	drom = new VciSimpleRom<vci_param_int>(
220	s_drom.str().c_str(),
221	IntTab(cluster_id, int_drom_tgt_id),
222	mt_int,
223	loader,
224	x_width + y_width); // msb drop bits
225
226	/////////// Direct LOCAL_XBAR(S)
227	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
228	size_t nb_direct_targets = is_io ? 5 : 4;
229
230	std::ostringstream s_int_xbar_d;
231	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
232	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
233	s_int_xbar_d.str().c_str(),
234	mt_int, // mapping table
235	cluster_id, // cluster id
236	nb_direct_initiators, // number of local initiators
237	nb_direct_targets, // number of local targets
238	0, // default target
239	true ); // hardware barrier
240
241	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
242	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
243	<< x_id << "_" << y_id;
244	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
245	dspin_int_cmd_width,
246	dspin_int_rsp_width>(
247	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
248	x_width + y_width + l_width);
249
250	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
251	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
252	<< x_id << "_" << y_id;
253	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
254	dspin_int_cmd_width,
255	dspin_int_rsp_width>(
256	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
257	x_width + y_width + l_width);
258
259	//////////// Coherence LOCAL_XBAR(S)
260	std::ostringstream s_int_xbar_m2p_c;
261	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
262	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
263	s_int_xbar_m2p_c.str().c_str(),
264	mt_int, // mapping table
265	x_id, y_id, // cluster coordinates
266	x_width, y_width, l_width, // several dests
267	1, // number of local sources
268	nb_procs, // number of local dests
269	2, 2, // fifo depths
270	true, // pseudo CMD
271	false, // no routing table
272	true, // broacast
273	true ); // hardware barrier
274
275	std::ostringstream s_int_xbar_p2m_c;
276	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
277	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
278	s_int_xbar_p2m_c.str().c_str(),
279	mt_int, // mapping table
280	x_id, y_id, // cluster coordinates
281	x_width, y_width, 0, // only one dest
282	nb_procs, // number of local sources
283	1, // number of local dests
284	2, 2, // fifo depths
285	false, // pseudo RSP
286	false, // no routing table
287	false, // no broacast
288	true ); // hardware barrier
289
290	std::ostringstream s_int_xbar_clack_c;
291	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
292	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
293	s_int_xbar_clack_c.str().c_str(),
294	mt_int, // mapping table
295	x_id, y_id, // cluster coordinates
296	x_width, y_width, l_width,
297	1, // number of local sources
298	nb_procs, // number of local targets
299	1, 1, // fifo depths
300	true, // CMD
301	false, // no routing table
302	false, // broadcast
303	true ); // hardware barrier
304
305	const bool ROUTER_CONFIG_SUPPORTED = true;
306
307	////////////// INT ROUTER(S)
308	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
309	for (int k = 0; k < 3; k++)
310	{
311	std::ostringstream s_int_router_cmd;
312	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
313	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
314	s_int_router_cmd.str().c_str(),
315	x_id, y_id,
316	x_width, y_width,
317	4, 4,
318	(k == 1),
319	ROUTER_CONFIG_SUPPORTED);
320	}
321
322	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
323	for (int k = 0; k < 2; k++)
324	{
325	std::ostringstream s_int_router_rsp;
326	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
327	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
328	s_int_router_rsp.str().c_str(),
329	x_id, y_id,
330	x_width, y_width,
331	4, 4,
332	false,
333	ROUTER_CONFIG_SUPPORTED);
334	}
335
336	////////////// XRAM
337	std::ostringstream s_xram;
338	s_xram << "xram_" << x_id << "_" << y_id;
339	xram = new VciSimpleRam<vci_param_ext>(
340	s_xram.str().c_str(),
341	IntTab(cluster_id, ram_xram_tgt_id),
342	mt_ram,
343	loader,
344	xram_latency);
345
346	std::ostringstream s_wt_xram;
347	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
348	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
349	dspin_ram_cmd_width,
350	dspin_ram_rsp_width>(
351	s_wt_xram.str().c_str(),
352	x_width + y_width + l_width);
353
354	///////////// RAM ROUTER(S)
355	std::ostringstream s_ram_router_cmd;
356	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
357	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
358	s_ram_router_cmd.str().c_str(),
359	x_id, y_id, // router coordinates in mesh
360	x_width, // x field width in first flit
361	y_width, // y field width in first flit
362	4, 4); // input & output fifo depths
363
364	std::ostringstream s_ram_router_rsp;
365	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
366	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
367	s_ram_router_rsp.str().c_str(),
368	x_id, y_id, // coordinates in mesh
369	x_width, // x field width in first flit
370	y_width, // y field width in first flit
371	4, 4); // input & output fifo depths
372
373
374	////////////////////// I/O CLUSTER ONLY ///////////////////////
375	if ( is_io )
376	{
377	/////////// IO_BRIDGE
378	std::ostringstream s_iob;
379	s_iob << "iob_" << x_id << "_" << y_id;
380	iob = new VciIoBridge<vci_param_int,
381	vci_param_ext>(
382	s_iob.str().c_str(),
383	mt_ram, // EXT network maptab
384	mt_int, // INT network maptab
385	mt_iox, // IOX network maptab
386	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
387	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
388	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
389	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
390	16, // cache line words
391	8, // IOTLB ways
392	8, // IOTLB sets
393	debug_start_cycle,
394	iob_debug_ok );
395
396	std::ostringstream s_iob_ram_wi;
397	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
398	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
399	dspin_ram_cmd_width,
400	dspin_ram_rsp_width>(
401	s_iob_ram_wi.str().c_str(),
402	vci_param_int::S);
403
404	std::ostringstream s_ram_xbar_cmd;
405	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
406	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
407	s_ram_xbar_cmd.str().c_str(), // name
408	mt_ram, // mapping table
409	x_id, y_id, // x, y
410	x_width, y_width, l_width, // x_width, y_width, l_width
411	2, 0, // local inputs, local outputs
412	2, 2, // in fifo, out fifo depths
413	true, // is cmd ?
414	false, // use routing table ?
415	false); // support broadcast ?
416
417	std::ostringstream s_ram_xbar_rsp;
418	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
419	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
420	s_ram_xbar_rsp.str().c_str(), // name
421	mt_ram, // mapping table
422	x_id, y_id, // x, y
423	x_width, y_width, l_width, // x_width, y_width, l_width
424	0, 2, // local inputs, local outputs
425	2, 2, // in fifo, out fifo depths
426	false, // is cmd ?
427	true, // use routing table ?
428	false); // support broadcast ?
429	} // end if IO
430
431	////////////////////////////////////
432	// Connections are defined here
433	////////////////////////////////////
434
435	// on coherence network : local srcid[proc] in [0...nb_procs-1]
436	// : local srcid[memc] = nb_procs
437
438	//////////////////////// internal CMD & RSP routers
439	for(int k = 0; k < 3; k++)
440	{
441	int_router_cmd[k]->p_clk (this->p_clk);
442	int_router_cmd[k]->p_resetn (this->p_resetn);
443	int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]);
444	for (int i = 0; i < 4; i++)
445	{
446	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
447	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
448	}
449	}
450
451	for(int k = 0; k < 2; k++)
452	{
453	int_router_rsp[k]->p_clk (this->p_clk);
454	int_router_rsp[k]->p_resetn (this->p_resetn);
455	int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]);
456	for (int i = 0; i < 4; i++)
457	{
458	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
459	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
460	}
461	}
462
463	// local ports
464	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
465	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
466	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
467	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
468	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
469	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
470
471	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
472	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
473	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
474	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
475
476	///////////////////// CMD & RSP local crossbar
477	int_xbar_d->p_clk (this->p_clk);
478	int_xbar_d->p_resetn (this->p_resetn);
479	(*int_xbar_d->p_barrier_enable) (signal_cfg_xbar_barrier);
480	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
481	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
482
483	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
484	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
485	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
486	int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom);
487	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
488	for (size_t p = 0; p < nb_procs; p++)
489	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
490
491	if ( is_io )
492	{
493	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
494	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
495	}
496
497	int_wi_gate_d->p_clk (this->p_clk);
498	int_wi_gate_d->p_resetn (this->p_resetn);
499	int_wi_gate_d->p_vci (signal_int_vci_l2g);
500	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
501	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
502
503	int_wt_gate_d->p_clk (this->p_clk);
504	int_wt_gate_d->p_resetn (this->p_resetn);
505	int_wt_gate_d->p_vci (signal_int_vci_g2l);
506	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
507	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
508
509	////////////////////// M2P DSPIN local crossbar coherence
510	int_xbar_m2p_c->p_clk (this->p_clk);
511	int_xbar_m2p_c->p_resetn (this->p_resetn);
512	(*int_xbar_m2p_c->p_barrier_enable) (signal_cfg_xbar_barrier);
513	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
514	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
515	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
516	for (size_t p = 0; p < nb_procs; p++)
517	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
518
519	////////////////////////// P2M DSPIN local crossbar coherence
520	int_xbar_p2m_c->p_clk (this->p_clk);
521	int_xbar_p2m_c->p_resetn (this->p_resetn);
522	(*int_xbar_p2m_c->p_barrier_enable) (signal_cfg_xbar_barrier);
523	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
524	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
525	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
526	for (size_t p = 0; p < nb_procs; p++)
527	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
528
529	////////////////////// CLACK DSPIN local crossbar coherence
530	int_xbar_clack_c->p_clk (this->p_clk);
531	int_xbar_clack_c->p_resetn (this->p_resetn);
532	(*int_xbar_clack_c->p_barrier_enable) (signal_cfg_xbar_barrier);
533	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
534	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
535	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
536	for (size_t p = 0; p < nb_procs; p++)
537	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
538
539	//////////////////////////////////// Processors
540	for (size_t p = 0; p < nb_procs && !m_disable_procs; p++)
541	{
542	proc[p]->p_clk (this->p_clk);
543	proc[p]->p_resetn (this->p_resetn);
544	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
545	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
546	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
547	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
548
549	for ( size_t j = 0 ; j < 6 ; j++)
550	{
551	if ( j < irq_per_proc )
552	{
553	proc[p]->p_irq[j] (signal_proc_it[irq_per_proc*p + j]);
554	}
555	else
556	{
557	proc[p]->p_irq[j] (this->p_false);
558	}
559	}
560	}
561
562	///////////////////////////////////// XICU
563	xicu->p_clk (this->p_clk);
564	xicu->p_resetn (this->p_resetn);
565	xicu->p_vci (signal_int_vci_tgt_xicu);
566	for ( size_t i=0 ; i < xcu_nb_out ; i++)
567	{
568	xicu->p_irq[i] (signal_proc_it[i]);
569	}
570	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
571	{
572	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
573	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
574	else xicu->p_hwi[i] (this->p_false);
575	}
576	xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD
577	xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP
578	xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P
579	xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M
580	xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK
581	xicu->p_cfg[5] (signal_cfg_xbar_barrier); // CLACK
582
583	///////////////////////////////////// MEMC
584	memc->p_clk (this->p_clk);
585	memc->p_resetn (this->p_resetn);
586	memc->p_vci_ixr (signal_ram_vci_ini_memc);
587	memc->p_vci_tgt (signal_int_vci_tgt_memc);
588	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
589	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
590	memc->p_dspin_clack (signal_int_dspin_clack_memc);
591	memc->p_irq (signal_irq_memc);
592
593	// wrapper to RAM network
594	memc_ram_wi->p_clk (this->p_clk);
595	memc_ram_wi->p_resetn (this->p_resetn);
596	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
597	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
598	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
599
600	//////////////////////////////////// XRAM
601	xram->p_clk (this->p_clk);
602	xram->p_resetn (this->p_resetn);
603	xram->p_vci (signal_ram_vci_tgt_xram);
604
605	// wrapper to RAM network
606	xram_ram_wt->p_clk (this->p_clk);
607	xram_ram_wt->p_resetn (this->p_resetn);
608	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
609	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
610	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
611
612	/////////////////////////////////// MDMA
613	mdma->p_clk (this->p_clk);
614	mdma->p_resetn (this->p_resetn);
615	mdma->p_vci_target (signal_int_vci_tgt_mdma);
616	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
617	for (size_t i=0 ; i<nb_dmas ; i++)
618	mdma->p_irq[i] (signal_irq_mdma[i]);
619
620	/////////////////////////////////// DROM
621	drom->p_clk (this->p_clk);
622	drom->p_resetn (this->p_resetn);
623	drom->p_vci (signal_int_vci_tgt_drom);
624
625	//////////////////////////// RAM network CMD & RSP routers
626	ram_router_cmd->p_clk (this->p_clk);
627	ram_router_cmd->p_resetn (this->p_resetn);
628	ram_router_rsp->p_clk (this->p_clk);
629	ram_router_rsp->p_resetn (this->p_resetn);
630	for( size_t n=0 ; n<4 ; n++)
631	{
632	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
633	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
634	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
635	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
636	}
637
638	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
639	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
640
641	if ( is_io )
642	{
643	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
644	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
645	}
646	else
647	{
648	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
649	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
650	}
651
652	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
653	if ( is_io )
654	{
655	// IO bridge
656	iob->p_clk (this->p_clk);
657	iob->p_resetn (this->p_resetn);
658	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
659	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
660	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
661	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
662	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
663
664	// initiator wrapper to RAM network
665	iob_ram_wi->p_clk (this->p_clk);
666	iob_ram_wi->p_resetn (this->p_resetn);
667	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
668	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
669	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
670
671	// crossbar between MEMC and IOB to RAM network
672	ram_xbar_cmd->p_clk (this->p_clk);
673	ram_xbar_cmd->p_resetn (this->p_resetn);
674	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
675	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
676	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
677	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
678
679	ram_xbar_rsp->p_clk (this->p_clk);
680	ram_xbar_rsp->p_resetn (this->p_resetn);
681	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
682	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
683	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
684	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
685	}
686
687	SC_METHOD(init);
688
689	} // end constructor
690
691	tmpl(void)::init()
692	{
693	for (size_t p = 0; p < m_nb_procs && m_disable_procs; p++)
694	{
695	signal_int_vci_ini_proc[p].cmdval = false;
696	signal_int_vci_ini_proc[p].rspack = true;
697	signal_int_dspin_m2p_proc[p].read = true;
698	signal_int_dspin_p2m_proc[p].write = false;
699	signal_int_dspin_clack_proc[p].write = false;
700	}
701
702	signal_ram_dspin_cmd_false.write = false;
703	signal_ram_dspin_rsp_false.read = true;
704	} // end init
705
706	tmpl(/**/)::~TsarIobCluster()
707	{
708	for (int k = 0; k < 3; k++)
709	{
710	delete int_router_cmd[k];
711	}
712	delete [] int_router_cmd;
713
714	for (int k = 0; k < 2; k++)
715	{
716	delete int_router_rsp[k];
717	}
718	delete [] int_router_rsp;
719	}
720
721	}}
722
723
724	// Local Variables:
725	// tab-width: 4
726	// c-basic-offset: 4
727	// c-file-offsets:((innamespace . 0)(inline-open . 0))
728	// indent-tabs-mode: nil
729	// End:
730
731	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
732

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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp

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