source: branches/reconfiguration/softs/mach/cpu_registers.h @ 985

Last change on this file since 985 was 850, checked in by cfuguet, 10 years ago

reconf: introducing a softs directory in the reconfiguration branch

  • This softs directory contains a minimalistic (giet-like) library of drivers and some utility functions.
  • Introducing a simple unit test in the vci_cc_vcache_wrapper component to test the newly introduced watchdog timer mechanism. This unit test uses the minimalistic library.
File size: 2.9 KB
Line 
1/**
2 * \file   cpu_registers.h
3 * \author Cesar Fuguet <cesar.fuguet-tortolero@lip6.fr>
4 * \date   26/03/2012
5 * \note   The mnemonics definitions for MIPS32 registers
6 */
7
8#ifndef _CPU_REGISTERS_H
9#define _CPU_REGISTERS_H
10
11/* processor registers */
12
13#define zero $0
14#define at   $at
15#define v0   $2
16#define v1   $3
17#define a0   $4
18#define a1   $5
19#define a2   $6
20#define a3   $7
21#define t0   $8
22#define t1   $9
23#define t2   $10
24#define t3   $11
25#define t4   $12
26#define t5   $13
27#define t6   $14
28#define t7   $15
29#define s0   $16
30#define s1   $17
31#define s2   $18
32#define s3   $19
33#define s4   $20
34#define s5   $21
35#define s6   $22
36#define s7   $23
37#define t8   $24
38#define t9   $25
39#define k0   $26
40#define k1   $27
41#define gp   $28
42#define sp   $29
43#define fp   $30
44#define ra   $31
45
46/* CP0 registers */
47
48#define CP0_COUNT  $9
49#define CP0_STATUS $12,0
50#define CP0_CAUSE  $13,0
51#define CP0_EPC    $14,0
52#define CP0_EBASE  $15,1
53#define CP0_PROCID $15,1
54
55/* CP0 cause register exception codes */
56
57#define CR_INT  0x0
58#define CR_ADEL 0x4
59#define CR_ADES 0x5
60#define CR_IBE  0x6
61#define CR_DBE  0x7
62#define CR_SYS  0x8
63#define CR_RI   0xA
64
65/* MMU (CP2) registers */
66
67#define MMU_PTPR            $0
68#define MMU_MODE            $1
69#define MMU_ICACHE_FLUSH    $2
70#define MMU_DCACHE_FLUSH    $3
71#define MMU_ITLB_INVAL      $4
72#define MMU_DTLB_INVAL      $5
73#define MMU_ICACHE_INVAL    $6
74#define MMU_DCACHE_INVAL    $7
75#define MMU_ICACHE_PREFETCH $8
76#define MMU_DCACHE_PREFETCH $9
77#define MMU_SYNC            $10
78#define MMU_IETR            $11
79#define MMU_DETR            $12
80#define MMU_IBVAR           $13
81#define MMU_DBVAR           $14
82#define MMU_PARAMS          $15
83#define MMU_RELEASE         $16
84#define MMU_DATA_LO         $17
85#define MMU_DATA_HI         $18
86#define MMU_ICACHE_INVAL_PA $19
87#define MMU_DCACHE_INVAL_PA $20
88#define MMU_DATA_PADDR_EXT  $24
89#define MMU_INST_PADDR_EXT  $25
90
91/* MMU IETR and DETR exception types */
92#define MMU_NONE                      0x0000
93#define MMU_WRITE_PT1_UNMAPPED        0x0001
94#define MMU_WRITE_PT2_UNMAPPED        0x0002
95#define MMU_WRITE_PRIVILEGE_VIOLATION 0x0004
96#define MMU_WRITE_ACCES_VIOLATION     0x0008
97#define MMU_WRITE_UNDEFINED_XTN       0x0020
98#define MMU_WRITE_PT1_ILLEGAL_ACCESS  0x0040
99#define MMU_WRITE_PT2_ILLEGAL_ACCESS  0x0080
100#define MMU_WRITE_DATA_ILLEGAL_ACCESS 0x0100
101#define MMU_READ_PT1_UNMAPPED         0x1001
102#define MMU_READ_PT2_UNMAPPED         0x1002
103#define MMU_READ_PRIVILEGE_VIOLATION  0x1004
104#define MMU_READ_EXEC_VIOLATION       0x1010
105#define MMU_READ_UNDEFINED_XTN        0x1020
106#define MMU_READ_PT1_ILLEGAL_ACCESS   0x1040
107#define MMU_READ_PT2_ILLEGAL_ACCESS   0x1080
108#define MMU_READ_DATA_ILLEGAL_ACCESS  0x1100
109#define MMU_READ_DATA_TIMEOUT         0x1200
110
111/* CP2 MODE bit masks */
112
113#define CP2_DCACHE_EN 0x1
114#define CP2_ICACHE_EN 0x2
115#define CP2_DTLB_EN   0x4
116#define CP2_ITLB_EN   0x8
117
118#endif                          /* _CPU_REGISTERS_H */
119
120/*
121 * vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab
122 */
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