[151] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, Asim |
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| 24 | * alain.greiner@lip6.fr april 2011 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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[407] | 29 | #include <unistd.h> |
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[151] | 30 | #include <stdint.h> |
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| 31 | #include <iostream> |
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| 32 | #include <fcntl.h> |
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[164] | 33 | #include "vci_block_device_tsar_v4.h" |
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[151] | 34 | |
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| 35 | namespace soclib { namespace caba { |
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| 36 | |
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| 37 | #define tmpl(t) template<typename vci_param> t VciBlockDeviceTsarV4<vci_param> |
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| 38 | |
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| 39 | using namespace soclib::caba; |
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| 40 | using namespace soclib::common; |
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| 41 | |
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| 42 | //////////////////////// |
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| 43 | tmpl(void)::transition() |
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| 44 | { |
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| 45 | if(p_resetn.read() == false) |
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| 46 | { |
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| 47 | r_initiator_fsm = M_IDLE; |
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[260] | 48 | r_target_fsm = T_IDLE; |
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| 49 | r_irq_enable = true; |
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| 50 | r_go = false; |
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| 51 | return; |
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[151] | 52 | } |
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| 53 | |
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| 54 | ////////////////////////////////////////////////////////////////////////////// |
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| 55 | // The Target FSM controls the following registers: |
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| 56 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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| 57 | ////////////////////////////////////////////////////////////////////////////// |
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| 58 | |
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| 59 | switch(r_target_fsm) { |
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[260] | 60 | //////////// |
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[151] | 61 | case T_IDLE: |
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| 62 | { |
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| 63 | if ( p_vci_target.cmdval.read() ) |
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| 64 | { |
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| 65 | r_srcid = p_vci_target.srcid.read(); |
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| 66 | r_trdid = p_vci_target.trdid.read(); |
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| 67 | r_pktid = p_vci_target.pktid.read(); |
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[260] | 68 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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[151] | 69 | bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); |
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| 70 | uint32_t cell = (uint32_t)((address & 0x1F)>>2); |
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| 71 | |
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[260] | 72 | if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; |
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| 73 | else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR; |
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| 74 | else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; |
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| 75 | else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; |
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| 76 | else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; |
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| 77 | else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; |
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| 78 | else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; |
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| 79 | else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; |
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| 80 | else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; |
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| 81 | else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; |
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| 82 | else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; |
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| 83 | else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; |
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| 84 | else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; |
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| 85 | else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; |
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| 86 | else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; |
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| 87 | else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; |
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[151] | 88 | } |
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| 89 | break; |
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| 90 | } |
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[260] | 91 | //////////////////// |
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[151] | 92 | case T_WRITE_BUFFER: |
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| 93 | { |
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| 94 | if ( r_initiator_fsm == M_IDLE ) r_buf_address = (uint32_t)p_vci_target.wdata.read(); |
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| 95 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 96 | break; |
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| 97 | } |
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[260] | 98 | /////////////////// |
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[151] | 99 | case T_WRITE_COUNT: |
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| 100 | { |
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| 101 | if ( r_initiator_fsm == M_IDLE ) r_nblocks = (uint32_t)p_vci_target.wdata.read(); |
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| 102 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 103 | break; |
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| 104 | } |
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[260] | 105 | ///////////////// |
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[151] | 106 | case T_WRITE_LBA: |
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| 107 | { |
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| 108 | if ( r_initiator_fsm == M_IDLE ) r_lba = (uint32_t)p_vci_target.wdata.read(); |
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| 109 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 110 | break; |
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| 111 | } |
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[260] | 112 | //////////////// |
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[151] | 113 | case T_WRITE_OP: |
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| 114 | { |
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| 115 | if ( r_initiator_fsm == M_IDLE ) |
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| 116 | { |
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| 117 | if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ ) |
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| 118 | { |
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| 119 | r_read = true; |
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| 120 | r_go = true; |
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| 121 | } |
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| 122 | else if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE) |
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| 123 | { |
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| 124 | r_read = false; |
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| 125 | r_go = true; |
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| 126 | } |
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| 127 | } |
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| 128 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 129 | break; |
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| 130 | } |
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[260] | 131 | /////////////////// |
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[151] | 132 | case T_WRITE_IRQEN: |
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| 133 | { |
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| 134 | r_irq_enable = (p_vci_target.wdata.read() != 0); |
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| 135 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 136 | break; |
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| 137 | } |
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[260] | 138 | /////////////////// |
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[151] | 139 | case T_READ_BUFFER: |
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| 140 | case T_READ_COUNT: |
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| 141 | case T_READ_LBA: |
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| 142 | case T_READ_IRQEN: |
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| 143 | case T_READ_SIZE: |
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| 144 | case T_READ_BLOCK: |
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| 145 | case T_READ_ERROR: |
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| 146 | case T_WRITE_ERROR: |
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| 147 | { |
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| 148 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 149 | break; |
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| 150 | } |
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[260] | 151 | /////////////////// |
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[151] | 152 | case T_READ_STATUS: |
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| 153 | { |
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| 154 | if ( p_vci_target.rspack.read() ) |
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| 155 | { |
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| 156 | r_target_fsm = T_IDLE; |
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| 157 | if( (r_initiator_fsm == M_READ_SUCCESS ) || |
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| 158 | (r_initiator_fsm == M_READ_ERROR ) || |
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| 159 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
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| 160 | (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; |
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| 161 | } |
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| 162 | break; |
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| 163 | } |
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| 164 | } // end switch target fsm |
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| 165 | |
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[260] | 166 | ////////////////////////////////////////////////////////////////////////////// |
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| 167 | // The initiator FSM executes a loop, transfering one block per iteration. |
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| 168 | // Each block is split in bursts, and the number of bursts depends |
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| 169 | // on the memory buffer alignment on a burst boundary: |
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| 170 | // - If buffer aligned, all burst have the same length (m_flits_per burst) |
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| 171 | // and the number of bursts is (m_bursts_per_block). |
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| 172 | // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) |
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| 173 | // and first and last burst are shorter, because all flits in a burst |
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| 174 | // must be contained in a single cache line. |
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| 175 | // first burst => nflits = m_flits_per_burst - offset |
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| 176 | // last burst => nflits = offset |
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| 177 | // other burst => nflits = m_flits_per_burst |
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| 178 | ////////////////////////////////////////////////////////////////////////////// |
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| 179 | |
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| 180 | switch( r_initiator_fsm.read() ) { |
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| 181 | //////////// |
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| 182 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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[151] | 183 | { |
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[260] | 184 | if ( r_go.read() ) |
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[151] | 185 | { |
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[260] | 186 | r_index = 0; |
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[151] | 187 | r_block_count = 0; |
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| 188 | r_burst_count = 0; |
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| 189 | r_flit_count = 0; |
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| 190 | r_latency_count = m_latency; |
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| 191 | |
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[260] | 192 | // compute r_burst_offset (zero when buffer aligned) |
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| 193 | r_burst_offset = (r_buf_address.read()>>2) % m_flits_per_burst; |
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| 194 | |
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| 195 | // start tranfer |
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| 196 | if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; |
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| 197 | else r_initiator_fsm = M_WRITE_BURST; |
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[151] | 198 | } |
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| 199 | break; |
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[260] | 200 | } |
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| 201 | ////////////////// |
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[228] | 202 | case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles |
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[151] | 203 | { |
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[260] | 204 | if ( r_latency_count.read() == 0 ) |
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[151] | 205 | { |
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| 206 | r_latency_count = m_latency; |
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[260] | 207 | ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*4, SEEK_SET); |
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| 208 | if( ::read(m_fd, r_local_buffer, m_flits_per_block*4) < 0 ) |
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[151] | 209 | { |
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[260] | 210 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 211 | } |
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| 212 | else |
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| 213 | { |
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[260] | 214 | r_burst_count = 0; |
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| 215 | r_flit_count = 0; |
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| 216 | r_initiator_fsm = M_READ_BURST; |
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[151] | 217 | } |
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| 218 | } |
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| 219 | else |
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| 220 | { |
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[260] | 221 | r_latency_count = r_latency_count.read() - 1; |
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[151] | 222 | } |
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| 223 | break; |
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| 224 | } |
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[260] | 225 | ////////////////// |
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| 226 | case M_READ_BURST: // Compute the number of flits in the burst |
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[151] | 227 | { |
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[260] | 228 | uint32_t offset = r_burst_offset.read(); |
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| 229 | |
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| 230 | if ( offset ) // buffer not aligned |
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| 231 | { |
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| 232 | if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; |
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| 233 | else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; |
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| 234 | else r_burst_nflits = m_flits_per_burst; |
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| 235 | } |
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| 236 | else // buffer aligned |
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| 237 | { |
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| 238 | r_burst_nflits = m_flits_per_burst; |
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| 239 | } |
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| 240 | r_initiator_fsm = M_READ_CMD; |
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| 241 | break; |
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| 242 | } |
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| 243 | //////////////// |
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| 244 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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| 245 | { |
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[151] | 246 | if ( p_vci_initiator.cmdack.read() ) |
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| 247 | { |
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[260] | 248 | if ( r_flit_count == (r_burst_nflits.read() - 1) ) // last flit in a burst |
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[151] | 249 | { |
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| 250 | r_initiator_fsm = M_READ_RSP; |
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| 251 | r_flit_count = 0; |
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| 252 | } |
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[260] | 253 | else // not the last flit |
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[151] | 254 | { |
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[260] | 255 | r_flit_count = r_flit_count.read() + 1; |
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[151] | 256 | } |
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[260] | 257 | |
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| 258 | // compute next flit address and next local buffer index |
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| 259 | r_buf_address = r_buf_address.read() + 4; |
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| 260 | r_index = r_index.read() + 1; |
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[151] | 261 | } |
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| 262 | break; |
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| 263 | } |
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[260] | 264 | //////////////// |
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| 265 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
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[151] | 266 | { |
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| 267 | if ( p_vci_initiator.rspval.read() ) |
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| 268 | { |
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[260] | 269 | bool aligned = (r_burst_offset.read() == 0); |
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| 270 | |
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| 271 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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[151] | 272 | { |
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[260] | 273 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 274 | } |
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[260] | 275 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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| 276 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) |
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[151] | 277 | { |
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[260] | 278 | if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block |
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| 279 | { |
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| 280 | r_initiator_fsm = M_READ_SUCCESS; |
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| 281 | } |
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| 282 | else // last burst not last block |
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| 283 | { |
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| 284 | r_index = 0; |
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| 285 | r_burst_count = 0; |
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| 286 | r_block_count = r_block_count.read() + 1; |
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| 287 | r_initiator_fsm = M_READ_BLOCK; |
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| 288 | } |
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[151] | 289 | } |
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[260] | 290 | else // not the last burst |
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| 291 | { |
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| 292 | r_burst_count = r_burst_count.read() + 1; |
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| 293 | r_initiator_fsm = M_READ_BURST; |
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| 294 | } |
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[151] | 295 | } |
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| 296 | break; |
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| 297 | } |
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[260] | 298 | /////////////////// |
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[151] | 299 | case M_READ_SUCCESS: |
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[260] | 300 | case M_READ_ERROR: |
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[151] | 301 | { |
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| 302 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 303 | break; |
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| 304 | } |
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[260] | 305 | /////////////////// |
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| 306 | case M_WRITE_BURST: // Compute the number of flits in the burst |
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[151] | 307 | { |
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[260] | 308 | uint32_t offset = r_burst_offset.read(); |
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| 309 | |
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| 310 | if ( offset ) // buffer not aligned |
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| 311 | { |
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| 312 | if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; |
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| 313 | else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; |
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| 314 | else r_burst_nflits = m_flits_per_burst; |
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| 315 | } |
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| 316 | else // buffer aligned |
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| 317 | { |
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| 318 | r_burst_nflits = m_flits_per_burst; |
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| 319 | } |
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| 320 | r_initiator_fsm = M_WRITE_CMD; |
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[151] | 321 | break; |
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| 322 | } |
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[260] | 323 | ///////////////// |
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[151] | 324 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
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| 325 | { |
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[228] | 326 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
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[151] | 327 | break; |
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| 328 | } |
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[260] | 329 | ///////////////// |
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[151] | 330 | case M_WRITE_RSP: // This is actually a multi-flits VCI READ response |
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| 331 | { |
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[260] | 332 | bool aligned = (r_burst_offset.read() == 0); |
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| 333 | |
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[151] | 334 | if ( p_vci_initiator.rspval.read() ) |
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| 335 | { |
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[260] | 336 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
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| 337 | r_index = r_index.read() + 1; |
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| 338 | |
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| 339 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
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[151] | 340 | { |
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[272] | 341 | r_flit_count = 0; |
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| 342 | r_buf_address = r_buf_address.read() + (r_burst_nflits.read()<<2); |
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[260] | 343 | |
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[272] | 344 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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[260] | 345 | { |
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| 346 | r_initiator_fsm = M_WRITE_ERROR; |
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| 347 | } |
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| 348 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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| 349 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst |
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| 350 | { |
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| 351 | r_initiator_fsm = M_WRITE_BLOCK; |
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| 352 | } |
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| 353 | else // not the last burst |
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| 354 | { |
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| 355 | r_burst_count = r_burst_count.read() + 1; |
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| 356 | r_initiator_fsm = M_WRITE_BURST; |
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| 357 | } |
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[151] | 358 | } |
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| 359 | else |
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| 360 | { |
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[228] | 361 | r_flit_count = r_flit_count.read() + 1; |
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[151] | 362 | } |
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| 363 | } |
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| 364 | break; |
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| 365 | } |
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[260] | 366 | /////////////////// |
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[151] | 367 | case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles |
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| 368 | { |
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| 369 | if ( r_latency_count == 0 ) |
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| 370 | { |
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| 371 | r_latency_count = m_latency; |
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[216] | 372 | ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); |
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[260] | 373 | if( ::write(m_fd, r_local_buffer, m_flits_per_block*vci_param::B) < 0 ) |
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[151] | 374 | { |
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| 375 | r_initiator_fsm = M_WRITE_ERROR; |
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| 376 | } |
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[272] | 377 | else if ( r_block_count.read() == r_nblocks.read() - 1 ) |
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[151] | 378 | { |
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| 379 | r_initiator_fsm = M_WRITE_SUCCESS; |
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| 380 | } |
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| 381 | else |
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| 382 | { |
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[272] | 383 | r_burst_count = 0; |
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| 384 | r_index = 0; |
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| 385 | r_block_count = r_block_count.read() + 1; |
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[260] | 386 | r_initiator_fsm = M_WRITE_BURST; |
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[151] | 387 | } |
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| 388 | } |
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| 389 | else |
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| 390 | { |
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| 391 | r_latency_count = r_latency_count - 1; |
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| 392 | } |
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| 393 | break; |
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| 394 | } |
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[260] | 395 | ///////////////////// |
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[151] | 396 | case M_WRITE_SUCCESS: |
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| 397 | case M_WRITE_ERROR: |
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| 398 | { |
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| 399 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 400 | break; |
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| 401 | } |
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| 402 | } // end switch r_initiator_fsm |
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| 403 | } // end transition |
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| 404 | |
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| 405 | ////////////////////// |
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| 406 | tmpl(void)::genMoore() |
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| 407 | { |
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| 408 | // p_vci_target port |
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[164] | 409 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
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| 410 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
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| 411 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
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[151] | 412 | p_vci_target.reop = true; |
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| 413 | |
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| 414 | switch(r_target_fsm) { |
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| 415 | case T_IDLE: |
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| 416 | p_vci_target.cmdack = true; |
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[260] | 417 | p_vci_target.rspval = false; |
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[151] | 418 | break; |
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| 419 | case T_READ_STATUS: |
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| 420 | p_vci_target.cmdack = false; |
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[260] | 421 | p_vci_target.rspval = true; |
---|
| 422 | if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; |
---|
| 423 | else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; |
---|
| 424 | else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; |
---|
[151] | 425 | else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; |
---|
| 426 | else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; |
---|
| 427 | else p_vci_target.rdata = BLOCK_DEVICE_BUSY; |
---|
| 428 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 429 | break; |
---|
| 430 | case T_READ_BUFFER: |
---|
| 431 | p_vci_target.cmdack = false; |
---|
[260] | 432 | p_vci_target.rspval = true; |
---|
| 433 | p_vci_target.rdata = (uint32_t)r_buf_address.read(); |
---|
[151] | 434 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 435 | break; |
---|
| 436 | case T_READ_COUNT: |
---|
| 437 | p_vci_target.cmdack = false; |
---|
[260] | 438 | p_vci_target.rspval = true; |
---|
| 439 | p_vci_target.rdata = (uint32_t)r_nblocks.read(); |
---|
[151] | 440 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 441 | break; |
---|
| 442 | case T_READ_LBA: |
---|
| 443 | p_vci_target.cmdack = false; |
---|
[260] | 444 | p_vci_target.rspval = true; |
---|
| 445 | p_vci_target.rdata = (uint32_t)r_lba.read(); |
---|
[151] | 446 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 447 | break; |
---|
| 448 | case T_READ_IRQEN: |
---|
| 449 | p_vci_target.cmdack = false; |
---|
[260] | 450 | p_vci_target.rspval = true; |
---|
| 451 | p_vci_target.rdata = (uint32_t)r_irq_enable.read(); |
---|
[151] | 452 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 453 | break; |
---|
| 454 | case T_READ_SIZE: |
---|
| 455 | p_vci_target.cmdack = false; |
---|
[260] | 456 | p_vci_target.rspval = true; |
---|
[151] | 457 | p_vci_target.rdata = (uint32_t)m_device_size; |
---|
| 458 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 459 | break; |
---|
| 460 | case T_READ_BLOCK: |
---|
| 461 | p_vci_target.cmdack = false; |
---|
[260] | 462 | p_vci_target.rspval = true; |
---|
[216] | 463 | p_vci_target.rdata = (uint32_t)m_flits_per_block*vci_param::B; |
---|
[151] | 464 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 465 | break; |
---|
| 466 | case T_READ_ERROR: |
---|
| 467 | p_vci_target.cmdack = false; |
---|
[260] | 468 | p_vci_target.rspval = true; |
---|
[151] | 469 | p_vci_target.rdata = 0; |
---|
| 470 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
| 471 | break; |
---|
| 472 | case T_WRITE_ERROR: |
---|
| 473 | p_vci_target.cmdack = false; |
---|
[260] | 474 | p_vci_target.rspval = true; |
---|
[151] | 475 | p_vci_target.rdata = 0; |
---|
| 476 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
| 477 | break; |
---|
| 478 | default: |
---|
| 479 | p_vci_target.cmdack = false; |
---|
| 480 | p_vci_target.rspval = true; |
---|
| 481 | p_vci_target.rdata = 0; |
---|
| 482 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
| 483 | break; |
---|
| 484 | } // end switch target fsm |
---|
| 485 | |
---|
| 486 | // p_vci_initiator port |
---|
[164] | 487 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
[151] | 488 | p_vci_initiator.trdid = 0; |
---|
| 489 | p_vci_initiator.contig = true; |
---|
| 490 | p_vci_initiator.cons = false; |
---|
| 491 | p_vci_initiator.wrap = false; |
---|
| 492 | p_vci_initiator.cfixed = false; |
---|
| 493 | p_vci_initiator.clen = 0; |
---|
| 494 | |
---|
| 495 | switch (r_initiator_fsm) { |
---|
| 496 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
| 497 | p_vci_initiator.rspack = false; |
---|
| 498 | p_vci_initiator.cmdval = true; |
---|
[260] | 499 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 500 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
[284] | 501 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; // or _MISS ? |
---|
[151] | 502 | p_vci_initiator.wdata = 0; |
---|
| 503 | p_vci_initiator.be = (uint32_t)0xF; |
---|
[260] | 504 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2); |
---|
[151] | 505 | p_vci_initiator.eop = true; |
---|
| 506 | break; |
---|
| 507 | case M_READ_CMD: // It is actually a multi-flits VCI WRITE command |
---|
| 508 | p_vci_initiator.rspack = false; |
---|
| 509 | p_vci_initiator.cmdval = true; |
---|
[260] | 510 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 511 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
[284] | 512 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
[260] | 513 | p_vci_initiator.wdata = (uint32_t)r_local_buffer[r_index.read()]; |
---|
[151] | 514 | p_vci_initiator.be = 0xF; |
---|
[260] | 515 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2); |
---|
| 516 | p_vci_initiator.eop = ( r_flit_count.read() == (r_burst_nflits.read() - 1) ); |
---|
[151] | 517 | break; |
---|
| 518 | case M_READ_RSP: |
---|
| 519 | case M_WRITE_RSP: |
---|
| 520 | p_vci_initiator.rspack = true; |
---|
| 521 | p_vci_initiator.cmdval = false; |
---|
[260] | 522 | break; |
---|
[151] | 523 | default: |
---|
[260] | 524 | p_vci_initiator.rspack = false; |
---|
| 525 | p_vci_initiator.cmdval = false; |
---|
| 526 | break; |
---|
[151] | 527 | } |
---|
| 528 | |
---|
| 529 | // IRQ signal |
---|
| 530 | if(((r_initiator_fsm == M_READ_SUCCESS) || |
---|
| 531 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
---|
| 532 | (r_initiator_fsm == M_READ_ERROR) || |
---|
| 533 | (r_initiator_fsm == M_WRITE_ERROR) ) && r_irq_enable) p_irq = true; |
---|
| 534 | else p_irq = false; |
---|
| 535 | } // end GenMoore() |
---|
| 536 | |
---|
| 537 | ////////////////////////////////////////////////////////////////////////////// |
---|
[260] | 538 | tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_name name, |
---|
| 539 | const soclib::common::MappingTable &mt, |
---|
| 540 | const soclib::common::IntTab &srcid, |
---|
| 541 | const soclib::common::IntTab &tgtid, |
---|
| 542 | const std::string &filename, |
---|
| 543 | const uint32_t block_size, |
---|
| 544 | const uint32_t burst_size, |
---|
| 545 | const uint32_t latency) |
---|
[151] | 546 | |
---|
| 547 | : caba::BaseModule(name), |
---|
| 548 | m_segment(mt.getSegment(tgtid)), |
---|
| 549 | m_srcid(mt.indexForId(srcid)), |
---|
| 550 | m_flits_per_block(block_size/vci_param::B), |
---|
| 551 | m_flits_per_burst(burst_size/vci_param::B), |
---|
| 552 | m_bursts_per_block(block_size/burst_size), |
---|
| 553 | m_latency(latency), |
---|
| 554 | p_clk("p_clk"), |
---|
| 555 | p_resetn("p_resetn"), |
---|
| 556 | p_vci_initiator("p_vci_initiator"), |
---|
| 557 | p_vci_target("p_vci_target"), |
---|
| 558 | p_irq("p_irq") |
---|
| 559 | { |
---|
| 560 | SC_METHOD(transition); |
---|
| 561 | sensitive_pos << p_clk; |
---|
| 562 | |
---|
| 563 | SC_METHOD(genMoore); |
---|
| 564 | sensitive_neg << p_clk; |
---|
| 565 | |
---|
[256] | 566 | if( (block_size != 64 ) && |
---|
| 567 | (block_size != 128) && |
---|
| 568 | (block_size != 256) && |
---|
| 569 | (block_size != 512) && |
---|
| 570 | (block_size != 1024) && |
---|
| 571 | (block_size != 2048) && |
---|
| 572 | (block_size != 4096) ) |
---|
[151] | 573 | { |
---|
| 574 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
---|
[256] | 575 | std::cout << "The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" << std::endl; |
---|
[151] | 576 | exit(1); |
---|
| 577 | } |
---|
[260] | 578 | if( (burst_size != 1 ) && |
---|
| 579 | (burst_size != 2 ) && |
---|
| 580 | (burst_size != 4 ) && |
---|
| 581 | (burst_size != 8 ) && |
---|
| 582 | (burst_size != 16) && |
---|
| 583 | (burst_size != 32) && |
---|
| 584 | (burst_size != 64) ) |
---|
| 585 | { |
---|
| 586 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
---|
| 587 | std::cout << "The burst size must be 1, 2, 4, 8, 16, 32 or 64 bytes" << std::endl; |
---|
| 588 | exit(1); |
---|
| 589 | } |
---|
[151] | 590 | if ( m_segment.size() < 32 ) |
---|
| 591 | { |
---|
| 592 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
---|
| 593 | std::cout << "The size of the segment cannot be smaller than 32 bytes" << std::endl; |
---|
| 594 | exit(1); |
---|
| 595 | } |
---|
| 596 | if ( (m_segment.baseAddress() & 0x0000001F) != 0 ) |
---|
| 597 | { |
---|
| 598 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
---|
| 599 | std::cout << "The base address of the segment must be multiple of 32 bytes" << std::endl; |
---|
| 600 | exit(1); |
---|
| 601 | } |
---|
| 602 | if ( vci_param::B != 4 ) |
---|
| 603 | { |
---|
| 604 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
---|
| 605 | std::cout << "The VCI data fields must have 32 bits" << std::endl; |
---|
| 606 | exit(1); |
---|
| 607 | } |
---|
| 608 | m_fd = ::open(filename.c_str(), O_RDWR); |
---|
| 609 | if ( m_fd < 0 ) |
---|
| 610 | { |
---|
| 611 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
---|
| 612 | std::cout << "Unable to open file " << filename << std::endl; |
---|
| 613 | exit(1); |
---|
| 614 | } |
---|
| 615 | m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; |
---|
| 616 | if ( m_device_size > ((uint64_t)1<<32) ) |
---|
| 617 | { |
---|
| 618 | std::cout << "Warning: block device " << name << std::endl; |
---|
| 619 | std::cout << "The file " << filename << std::endl; |
---|
| 620 | std::cout << "has more blocks than addressable with the 32 bits PIBUS address" << std::endl; |
---|
| 621 | m_device_size = ((uint64_t)1<<32); |
---|
| 622 | } |
---|
| 623 | |
---|
[260] | 624 | r_local_buffer = new uint32_t[m_flits_per_block]; |
---|
| 625 | |
---|
[151] | 626 | } // end constructor |
---|
| 627 | |
---|
| 628 | ////////////////////////// |
---|
| 629 | tmpl(void)::print_trace() |
---|
| 630 | { |
---|
| 631 | const char* initiator_str[] = { |
---|
[260] | 632 | "IDLE", |
---|
| 633 | |
---|
| 634 | "READ_BLOCK", |
---|
| 635 | "READ_BURST", |
---|
| 636 | "READ_CMD", |
---|
| 637 | "READ_RSP", |
---|
| 638 | "READ_TEST", |
---|
| 639 | "READ_SUCCESS", |
---|
| 640 | "READ_ERROR", |
---|
| 641 | |
---|
| 642 | "WRITE_BURST", |
---|
| 643 | "WRITE_CMD", |
---|
| 644 | "WRITE_RSP", |
---|
| 645 | "WRITE_BLOCK", |
---|
[151] | 646 | "WRITE_SUCCESS", |
---|
[260] | 647 | "WRITE_ERROR", |
---|
[151] | 648 | }; |
---|
| 649 | const char* target_str[] = { |
---|
| 650 | "IDLE ", |
---|
| 651 | "WRITE_BUFFER", |
---|
| 652 | "READ_BUFFER ", |
---|
| 653 | "WRITE_COUNT ", |
---|
| 654 | "READ_COUNT ", |
---|
| 655 | "WRITE_LBA ", |
---|
| 656 | "READ_LBA ", |
---|
| 657 | "WRITE_OP ", |
---|
| 658 | "READ_STATUS ", |
---|
| 659 | "WRITE_IRQEN ", |
---|
| 660 | "READ_IRQEN ", |
---|
| 661 | "READ_SIZE ", |
---|
| 662 | "READ_BLOCK ", |
---|
| 663 | "READ_ERROR ", |
---|
| 664 | "WRITE_ERROR ", |
---|
| 665 | }; |
---|
| 666 | |
---|
| 667 | std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()] |
---|
| 668 | << " BDEV_INI : " << initiator_str[r_initiator_fsm.read()] |
---|
| 669 | << " block = " << r_block_count.read() |
---|
| 670 | << " burst = " << r_burst_count.read() |
---|
| 671 | << " flit = " << r_flit_count.read() <<std::endl; |
---|
| 672 | } |
---|
| 673 | |
---|
| 674 | |
---|
| 675 | }} // end namespace |
---|
| 676 | |
---|
| 677 | // Local Variables: |
---|
| 678 | // tab-width: 4 |
---|
| 679 | // c-basic-offset: 4 |
---|
| 680 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 681 | // indent-tabs-mode: nil |
---|
| 682 | // End: |
---|
| 683 | |
---|
| 684 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 685 | |
---|