1 | /* -*- c++ -*- |
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2 | * |
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3 | * SOCLIB_LGPL_HEADER_BEGIN |
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4 | * |
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5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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6 | * |
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7 | * SoCLib is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU Lesser General Public License as published |
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9 | * by the Free Software Foundation; version 2.1 of the License. |
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10 | * |
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11 | * SoCLib is distributed in the hope that it will be useful, but |
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12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with SoCLib; if not, write to the Free Software |
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18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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19 | * 02110-1301 USA |
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20 | * |
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21 | * SOCLIB_LGPL_HEADER_END |
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22 | * |
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23 | * Copyright (c) UPMC, Lip6, SoC |
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24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
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25 | * |
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26 | * Maintainers: alain |
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27 | */ |
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28 | |
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29 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_H |
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30 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_H |
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31 | |
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32 | #include <inttypes.h> |
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33 | #include <systemc> |
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34 | #include "caba_base_module.h" |
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35 | #include "write_buffer.h" |
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36 | #include "generic_cache.h" |
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37 | #include "vci_initiator.h" |
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38 | #include "vci_target.h" |
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39 | #include "mapping_table.h" |
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40 | #include "static_assert.h" |
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41 | |
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42 | namespace soclib { |
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43 | namespace caba { |
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44 | |
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45 | using namespace sc_core; |
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46 | |
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47 | //////////////////////////////////////////// |
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48 | template<typename vci_param, typename iss_t> |
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49 | class VciCcXcacheWrapper |
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50 | /////////////////////////////////////////// |
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51 | : public soclib::caba::BaseModule |
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52 | { |
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53 | typedef uint32_t addr_t; |
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54 | typedef uint32_t data_t; |
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55 | typedef uint32_t tag_t; |
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56 | typedef uint32_t be_t; |
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57 | |
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58 | enum dcache_fsm_state_e { |
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59 | DCACHE_IDLE, |
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60 | DCACHE_WRITE_UPDT, |
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61 | DCACHE_WRITE_REQ, |
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62 | DCACHE_MISS_WAIT, |
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63 | DCACHE_MISS_UPDT, |
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64 | DCACHE_UNC_WAIT, |
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65 | DCACHE_INVAL, |
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66 | DCACHE_ERROR, |
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67 | DCACHE_CC_CHECK, |
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68 | DCACHE_CC_INVAL, |
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69 | DCACHE_CC_UPDT, |
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70 | DCACHE_CC_NOP, |
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71 | }; |
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72 | |
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73 | enum icache_fsm_state_e { |
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74 | ICACHE_IDLE, |
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75 | ICACHE_MISS_WAIT, |
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76 | ICACHE_MISS_UPDT, |
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77 | ICACHE_UNC_WAIT, |
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78 | ICACHE_ERROR, |
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79 | ICACHE_CC_INVAL, |
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80 | }; |
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81 | |
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82 | enum cmd_fsm_state_e { |
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83 | CMD_IDLE, |
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84 | CMD_INS_MISS, |
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85 | CMD_INS_UNC, |
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86 | CMD_DATA_MISS, |
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87 | CMD_DATA_UNC, |
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88 | CMD_DATA_WRITE, |
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89 | CMD_INS_CLEANUP, |
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90 | CMD_DATA_CLEANUP, |
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91 | }; |
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92 | |
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93 | enum rsp_fsm_state_e { |
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94 | RSP_IDLE, |
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95 | RSP_INS_MISS, |
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96 | RSP_INS_UNC, |
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97 | RSP_DATA_MISS, |
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98 | RSP_DATA_UNC, |
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99 | RSP_DATA_WRITE, |
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100 | RSP_INS_CLEANUP, |
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101 | RSP_DATA_CLEANUP, |
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102 | }; |
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103 | |
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104 | enum tgt_fsm_state_e { |
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105 | TGT_IDLE, |
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106 | TGT_UPDT_WORD, |
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107 | TGT_UPDT_DATA, |
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108 | TGT_REQ_BROADCAST, |
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109 | TGT_REQ_DCACHE, |
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110 | TGT_RSP_BROADCAST, |
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111 | TGT_RSP_DCACHE, |
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112 | }; |
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113 | |
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114 | public: |
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115 | |
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116 | // PORTS |
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117 | sc_in<bool> p_clk; |
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118 | sc_in<bool> p_resetn; |
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119 | sc_in<bool> p_irq[iss_t::n_irq]; |
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120 | soclib::caba::VciInitiator<vci_param> p_vci_ini; |
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121 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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122 | |
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123 | private: |
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124 | |
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125 | // STRUCTURAL PARAMETERS |
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126 | const soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; |
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127 | const soclib::common::Segment m_segment; |
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128 | iss_t m_iss; |
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129 | const uint32_t m_srcid; |
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130 | addr_t m_cleanup_address; |
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131 | |
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132 | const size_t m_dcache_ways; |
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133 | const size_t m_dcache_words; |
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134 | const size_t m_dcache_yzmask; |
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135 | const size_t m_icache_ways; |
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136 | const size_t m_icache_words; |
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137 | const size_t m_icache_yzmask; |
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138 | |
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139 | // REGISTERS |
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140 | sc_signal<int> r_dcache_fsm; |
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141 | sc_signal<int> r_dcache_fsm_save; |
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142 | sc_signal<addr_t> r_dcache_addr_save; |
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143 | sc_signal<data_t> r_dcache_wdata_save; |
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144 | sc_signal<data_t> r_dcache_rdata_save; |
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145 | sc_signal<int> r_dcache_type_save; |
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146 | sc_signal<be_t> r_dcache_be_save; |
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147 | sc_signal<bool> r_dcache_cached_save; |
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148 | sc_signal<bool> r_dcache_cleanup_req; |
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149 | sc_signal<data_t> r_dcache_cleanup_line; |
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150 | sc_signal<bool> r_dcache_miss_req; |
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151 | sc_signal<bool> r_dcache_unc_req; |
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152 | sc_signal<bool> r_dcache_write_req; |
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153 | sc_signal<bool> r_dcache_inval_rsp; |
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154 | |
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155 | sc_signal<int> r_icache_fsm; |
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156 | sc_signal<int> r_icache_fsm_save; |
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157 | sc_signal<addr_t> r_icache_addr_save; |
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158 | sc_signal<bool> r_icache_miss_req; |
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159 | sc_signal<bool> r_icache_unc_req; |
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160 | sc_signal<bool> r_icache_cleanup_req; |
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161 | sc_signal<data_t> r_icache_cleanup_line; |
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162 | sc_signal<bool> r_icache_inval_rsp; |
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163 | |
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164 | sc_signal<int> r_vci_cmd_fsm; |
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165 | sc_signal<size_t> r_vci_cmd_min; |
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166 | sc_signal<size_t> r_vci_cmd_max; |
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167 | sc_signal<size_t> r_vci_cmd_cpt; |
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168 | |
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169 | sc_signal<int> r_vci_rsp_fsm; |
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170 | sc_signal<bool> r_vci_rsp_ins_error; |
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171 | sc_signal<bool> r_vci_rsp_data_error; |
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172 | sc_signal<size_t> r_vci_rsp_cpt; |
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173 | |
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174 | data_t *r_icache_miss_buf; |
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175 | data_t *r_dcache_miss_buf; |
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176 | sc_signal<bool> r_icache_buf_unc_valid; |
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177 | sc_signal<bool> r_dcache_buf_unc_valid; |
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178 | |
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179 | data_t *r_tgt_buf; |
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180 | bool *r_tgt_val; |
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181 | |
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182 | sc_signal<int> r_vci_tgt_fsm; |
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183 | sc_signal<size_t> r_tgt_addr; |
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184 | sc_signal<size_t> r_tgt_word; |
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185 | sc_signal<bool> r_tgt_update; |
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186 | sc_signal<size_t> r_tgt_srcid; |
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187 | sc_signal<size_t> r_tgt_pktid; |
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188 | sc_signal<size_t> r_tgt_trdid; |
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189 | sc_signal<size_t> r_tgt_plen; |
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190 | sc_signal<bool> r_tgt_icache_req; |
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191 | sc_signal<bool> r_tgt_dcache_req; |
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192 | sc_signal<bool> r_tgt_icache_rsp; |
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193 | sc_signal<bool> r_tgt_dcache_rsp; |
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194 | |
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195 | WriteBuffer<addr_t> r_wbuf; |
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196 | GenericCache<addr_t> r_icache; |
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197 | GenericCache<addr_t> r_dcache; |
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198 | |
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199 | // Activity counters |
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200 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
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201 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
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202 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
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203 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
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204 | |
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205 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
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206 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
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207 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
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208 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
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209 | |
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210 | uint32_t m_cpt_cc_update; // number of coherence update packets |
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211 | uint32_t m_cpt_cc_inval; // number of coherence inval packets |
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212 | |
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213 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
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214 | uint32_t m_cpt_total_cycles; // total number of cycles |
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215 | |
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216 | uint32_t m_cpt_read; // total number of read instructions |
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217 | uint32_t m_cpt_write; // total number of write instructions |
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218 | uint32_t m_cpt_data_miss; // number of read miss |
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219 | uint32_t m_cpt_ins_miss; // number of instruction miss |
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220 | uint32_t m_cpt_unc_read; // number of read uncached |
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221 | uint32_t m_cpt_write_cached; // number of cached write |
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222 | |
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223 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
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224 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
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225 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
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226 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
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227 | |
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228 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
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229 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
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230 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
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231 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
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232 | |
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233 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
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234 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
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235 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
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236 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
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237 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
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238 | |
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239 | protected: |
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240 | SC_HAS_PROCESS(VciCcXcacheWrapper); |
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241 | |
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242 | public: |
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243 | |
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244 | VciCcXcacheWrapper( |
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245 | sc_module_name insname, |
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246 | int proc_id, |
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247 | const soclib::common::MappingTable &mtp, |
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248 | const soclib::common::MappingTable &mtc, |
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249 | const soclib::common::IntTab &initiator_index, |
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250 | const soclib::common::IntTab &target_index, |
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251 | size_t icache_ways, |
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252 | size_t icache_sets, |
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253 | size_t icache_words, |
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254 | size_t dcache_ways, |
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255 | size_t dcache_sets, |
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256 | size_t dcache_words, |
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257 | addr_t cleanup_offset ); |
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258 | |
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259 | ~VciCcXcacheWrapper(); |
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260 | |
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261 | void print_cpi(); |
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262 | void print_stats(); |
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263 | |
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264 | private: |
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265 | |
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266 | void transition(); |
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267 | void genMoore(); |
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268 | |
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269 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
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270 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
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271 | }; |
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272 | |
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273 | }} |
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274 | |
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275 | #endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_H */ |
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276 | |
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277 | // Local Variables: |
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278 | // tab-width: 4 |
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279 | // c-basic-offset: 4 |
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280 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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281 | // indent-tabs-mode: nil |
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282 | // End: |
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283 | |
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284 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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285 | |
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286 | |
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287 | |
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