1 | /* -*- c++ -*- |
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2 | * File : vci_mem_cache.h |
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3 | * Date : 26/10/2008 |
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4 | * Copyright : UPMC / LIP6 |
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5 | * Authors : Alain Greiner / Eric Guthmuller |
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6 | * |
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7 | * SOCLIB_LGPL_HEADER_BEGIN |
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8 | * |
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9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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10 | * |
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11 | * SoCLib is free software; you can redistribute it and/or modify it |
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12 | * under the terms of the GNU Lesser General Public License as published |
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13 | * by the Free Software Foundation; version 2.1 of the License. |
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14 | * |
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15 | * SoCLib is distributed in the hope that it will be useful, but |
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16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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18 | * Lesser General Public License for more details. |
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19 | * |
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20 | * You should have received a copy of the GNU Lesser General Public |
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21 | * License along with SoCLib; if not, write to the Free Software |
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22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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23 | * 02110-1301 USA |
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24 | * |
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25 | * SOCLIB_LGPL_HEADER_END |
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26 | * |
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27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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28 | */ |
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29 | |
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30 | #ifndef SOCLIB_CABA_MEM_CACHE_H |
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31 | #define SOCLIB_CABA_MEM_CACHE_H |
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32 | |
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33 | #include <inttypes.h> |
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34 | #include <systemc> |
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35 | #include <list> |
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36 | #include <cassert> |
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37 | #include "arithmetics.h" |
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38 | #include "alloc_elems.h" |
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39 | #include "caba_base_module.h" |
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40 | #include "vci_target.h" |
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41 | #include "vci_initiator.h" |
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42 | #include "generic_fifo.h" |
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43 | #include "mapping_table.h" |
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44 | #include "int_tab.h" |
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45 | #include "mem_cache_directory.h" |
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46 | #include "xram_transaction.h" |
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47 | #include "update_tab.h" |
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48 | #include "atomic_tab.h" |
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49 | |
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50 | #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab |
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51 | #define UPDATE_TAB_LINES 4 // Number of lines in the update tab |
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52 | |
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53 | namespace soclib { namespace caba { |
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54 | using namespace sc_core; |
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55 | |
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56 | template<typename vci_param> |
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57 | class VciMemCache |
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58 | : public soclib::caba::BaseModule |
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59 | { |
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60 | typedef uint32_t addr_t; |
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61 | typedef uint32_t data_t; |
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62 | typedef uint32_t tag_t; |
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63 | typedef uint32_t size_t; |
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64 | typedef uint32_t be_t; |
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65 | typedef uint32_t copy_t; |
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66 | |
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67 | /* States of the TGT_CMD fsm */ |
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68 | enum tgt_cmd_fsm_state_e{ |
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69 | TGT_CMD_IDLE, |
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70 | TGT_CMD_READ, |
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71 | TGT_CMD_READ_EOP, |
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72 | TGT_CMD_WRITE, |
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73 | TGT_CMD_ATOMIC, |
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74 | TGT_CMD_CLEANUP, |
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75 | }; |
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76 | |
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77 | /* States of the TGT_RSP fsm */ |
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78 | enum tgt_rsp_fsm_state_e{ |
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79 | TGT_RSP_READ_IDLE, |
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80 | TGT_RSP_WRITE_IDLE, |
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81 | TGT_RSP_LLSC_IDLE, |
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82 | TGT_RSP_CLEANUP_IDLE, |
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83 | TGT_RSP_XRAM_IDLE, |
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84 | TGT_RSP_INIT_IDLE, |
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85 | TGT_RSP_READ_TEST, |
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86 | TGT_RSP_READ_WORD, |
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87 | TGT_RSP_READ_LINE, |
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88 | TGT_RSP_WRITE, |
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89 | TGT_RSP_LLSC, |
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90 | TGT_RSP_CLEANUP, |
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91 | TGT_RSP_XRAM_TEST, |
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92 | TGT_RSP_XRAM_WORD, |
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93 | TGT_RSP_XRAM_LINE, |
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94 | TGT_RSP_INIT, |
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95 | }; |
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96 | |
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97 | /* States of the INIT_CMD fsm */ |
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98 | enum init_cmd_fsm_state_e{ |
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99 | INIT_CMD_INVAL_IDLE, |
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100 | INIT_CMD_INVAL_SEL, |
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101 | INIT_CMD_INVAL_NLINE, |
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102 | INIT_CMD_UPDT_IDLE, |
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103 | INIT_CMD_UPDT_SEL, |
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104 | INIT_CMD_UPDT_NLINE, |
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105 | INIT_CMD_UPDT_INDEX, |
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106 | INIT_CMD_UPDT_DATA, |
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107 | }; |
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108 | |
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109 | /* States of the INIT_RSP fsm */ |
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110 | enum init_rsp_fsm_state_e{ |
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111 | INIT_RSP_IDLE, |
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112 | INIT_RSP_UPT_LOCK, |
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113 | INIT_RSP_UPT_CLEAR, |
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114 | INIT_RSP_END, |
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115 | }; |
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116 | |
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117 | /* States of the READ fsm */ |
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118 | enum read_fsm_state_e{ |
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119 | READ_IDLE, |
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120 | READ_DIR_LOCK, |
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121 | READ_DIR_HIT, |
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122 | READ_RSP, |
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123 | READ_TRT_LOCK, |
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124 | READ_TRT_SET, |
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125 | READ_XRAM_REQ, |
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126 | }; |
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127 | |
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128 | /* States of the WRITE fsm */ |
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129 | enum write_fsm_state_e{ |
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130 | WRITE_IDLE, |
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131 | WRITE_NEXT, |
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132 | WRITE_DIR_LOCK, |
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133 | WRITE_DIR_HIT_READ, |
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134 | WRITE_DIR_HIT, |
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135 | WRITE_UPT_LOCK, |
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136 | WRITE_WAIT_UPT, |
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137 | WRITE_UPDATE, |
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138 | WRITE_RSP, |
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139 | WRITE_TRT_LOCK, |
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140 | WRITE_TRT_DATA, |
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141 | WRITE_TRT_SET, |
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142 | WRITE_WAIT_TRT, |
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143 | WRITE_XRAM_REQ, |
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144 | }; |
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145 | |
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146 | /* States of the IXR_RSP fsm */ |
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147 | enum ixr_rsp_fsm_state_e{ |
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148 | IXR_RSP_IDLE, |
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149 | IXR_RSP_ACK, |
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150 | IXR_RSP_TRT_ERASE, |
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151 | IXR_RSP_TRT_READ, |
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152 | }; |
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153 | |
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154 | /* States of the XRAM_RSP fsm */ |
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155 | enum xram_rsp_fsm_state_e{ |
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156 | XRAM_RSP_IDLE, |
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157 | XRAM_RSP_TRT_COPY, |
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158 | XRAM_RSP_TRT_DIRTY, |
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159 | XRAM_RSP_DIR_LOCK, |
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160 | XRAM_RSP_DIR_UPDT, |
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161 | XRAM_RSP_DIR_RSP, |
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162 | XRAM_RSP_UPT_LOCK, |
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163 | XRAM_RSP_WAIT, |
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164 | XRAM_RSP_INVAL, |
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165 | XRAM_RSP_WRITE_DIRTY, |
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166 | }; |
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167 | |
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168 | /* States of the XRAM_CMD fsm */ |
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169 | enum xram_cmd_fsm_state_e{ |
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170 | XRAM_CMD_READ_IDLE, |
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171 | XRAM_CMD_WRITE_IDLE, |
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172 | XRAM_CMD_LLSC_IDLE, |
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173 | XRAM_CMD_XRAM_IDLE, |
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174 | XRAM_CMD_READ_NLINE, |
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175 | XRAM_CMD_WRITE_NLINE, |
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176 | XRAM_CMD_LLSC_NLINE, |
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177 | XRAM_CMD_XRAM_DATA, |
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178 | }; |
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179 | |
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180 | /* States of the LLSC fsm */ |
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181 | enum llsc_fsm_state_e{ |
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182 | LLSC_IDLE, |
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183 | LL_DIR_LOCK, |
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184 | LL_DIR_HIT, |
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185 | LL_RSP, |
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186 | SC_DIR_LOCK, |
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187 | SC_DIR_HIT, |
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188 | SC_RSP_FALSE, |
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189 | SC_RSP_TRUE, |
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190 | LLSC_TRT_LOCK, |
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191 | LLSC_TRT_SET, |
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192 | LLSC_XRAM_REQ, |
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193 | }; |
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194 | |
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195 | /* States of the CLEANUP fsm */ |
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196 | enum cleanup_fsm_state_e{ |
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197 | CLEANUP_IDLE, |
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198 | CLEANUP_DIR_LOCK, |
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199 | CLEANUP_DIR_WRITE, |
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200 | CLEANUP_RSP, |
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201 | }; |
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202 | |
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203 | /* States of the ALLOC_DIR fsm */ |
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204 | enum alloc_dir_fsm_state_e{ |
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205 | ALLOC_DIR_READ, |
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206 | ALLOC_DIR_WRITE, |
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207 | ALLOC_DIR_LLSC, |
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208 | ALLOC_DIR_CLEANUP, |
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209 | ALLOC_DIR_XRAM_RSP, |
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210 | }; |
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211 | |
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212 | /* States of the ALLOC_TRT fsm */ |
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213 | enum alloc_trt_fsm_state_e{ |
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214 | ALLOC_TRT_READ, |
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215 | ALLOC_TRT_WRITE, |
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216 | ALLOC_TRT_LLSC, |
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217 | ALLOC_TRT_XRAM_RSP, |
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218 | ALLOC_TRT_IXR_RSP, |
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219 | }; |
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220 | |
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221 | /* States of the ALLOC_UPT fsm */ |
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222 | enum alloc_upt_fsm_state_e{ |
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223 | ALLOC_UPT_WRITE, |
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224 | ALLOC_UPT_XRAM_RSP, |
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225 | ALLOC_UPT_INIT_RSP, |
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226 | }; |
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227 | |
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228 | uint32_t m_cpt_cycles; // Counter of cycles |
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229 | uint32_t m_cpt_read; // Number of READ transactions |
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230 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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231 | uint32_t m_cpt_write; // Number of WRITE transactions |
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232 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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233 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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234 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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235 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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236 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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237 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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238 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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239 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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240 | uint32_t m_cpt_ll; // Number of LL transactions |
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241 | uint32_t m_cpt_sc; // Number of SC transactions |
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242 | |
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243 | protected: |
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244 | |
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245 | SC_HAS_PROCESS(VciMemCache); |
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246 | |
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247 | public: |
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248 | sc_in<bool> p_clk; |
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249 | sc_in<bool> p_resetn; |
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250 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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251 | soclib::caba::VciInitiator<vci_param> p_vci_ini; |
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252 | soclib::caba::VciInitiator<vci_param> p_vci_ixr; |
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253 | |
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254 | VciMemCache( |
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255 | sc_module_name name, // Instance Name |
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256 | const soclib::common::MappingTable &mtp, // Mapping table for primary requets |
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257 | const soclib::common::MappingTable &mtc, // Mapping table for coherence requets |
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258 | const soclib::common::MappingTable &mtx, // Mapping table for XRAM |
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259 | const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) |
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260 | const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) |
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261 | const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) |
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262 | size_t nways, // Number of ways per set |
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263 | size_t nsets, // Number of sets |
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264 | size_t nwords); // Number of words per line |
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265 | |
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266 | ~VciMemCache(); |
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267 | |
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268 | void transition(); |
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269 | |
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270 | void genMoore(); |
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271 | |
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272 | void print_stats(); |
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273 | |
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274 | private: |
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275 | |
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276 | // Component attributes |
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277 | const size_t m_initiators; // Number of initiators |
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278 | const size_t m_ways; // Number of ways in a set |
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279 | const size_t m_sets; // Number of cache sets |
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280 | const size_t m_words; // Number of words in a line |
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281 | const size_t m_srcid_ixr; // Srcid for requests to XRAM |
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282 | const size_t m_srcid_ini; // Srcid for requests to processors |
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283 | //soclib::common::Segment m_mem_segment; // memory cached into the cache |
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284 | std::list<soclib::common::Segment> m_seglist; // memory cached into the cache |
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285 | soclib::common::Segment m_reg_segment; // memory cache mapped registers |
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286 | addr_t *m_coherence_table; // address(srcid) |
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287 | AtomicTab m_atomic_tab; // atomic access table |
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288 | TransactionTab m_transaction_tab; // xram transaction table |
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289 | UpdateTab m_update_tab; // pending update & invalidate |
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290 | CacheDirectory m_cache_directory; // data cache directory |
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291 | |
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292 | data_t ***m_cache_data; // data array[set][way][word] |
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293 | |
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294 | // adress masks |
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295 | const soclib::common::AddressMaskingTable<addr_t> m_x; |
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296 | const soclib::common::AddressMaskingTable<addr_t> m_y; |
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297 | const soclib::common::AddressMaskingTable<addr_t> m_z; |
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298 | const soclib::common::AddressMaskingTable<addr_t> m_nline; |
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299 | |
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300 | ////////////////////////////////////////////////// |
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301 | // Registers controlled by the TGT_CMD fsm |
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302 | ////////////////////////////////////////////////// |
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303 | |
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304 | // Fifo between TGT_CMD fsm and READ fsm |
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305 | GenericFifo<addr_t> m_cmd_read_addr_fifo; |
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306 | GenericFifo<bool> m_cmd_read_word_fifo; |
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307 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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308 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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309 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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310 | |
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311 | // Fifo between TGT_CMD fsm and WRITE fsm |
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312 | GenericFifo<addr_t> m_cmd_write_addr_fifo; |
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313 | GenericFifo<bool> m_cmd_write_eop_fifo; |
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314 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
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315 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
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316 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
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317 | GenericFifo<data_t> m_cmd_write_data_fifo; |
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318 | GenericFifo<be_t> m_cmd_write_be_fifo; |
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319 | |
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320 | // Fifo between TGT_CMD fsm and LLSC fsm |
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321 | GenericFifo<addr_t> m_cmd_llsc_addr_fifo; |
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322 | GenericFifo<bool> m_cmd_llsc_sc_fifo; |
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323 | GenericFifo<size_t> m_cmd_llsc_srcid_fifo; |
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324 | GenericFifo<size_t> m_cmd_llsc_trdid_fifo; |
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325 | GenericFifo<size_t> m_cmd_llsc_pktid_fifo; |
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326 | GenericFifo<data_t> m_cmd_llsc_wdata_fifo; |
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327 | |
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328 | // Fifo between TGT_CMD fsm and CLEANUP fsm |
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329 | GenericFifo<size_t> m_cmd_cleanup_srcid_fifo; |
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330 | GenericFifo<size_t> m_cmd_cleanup_trdid_fifo; |
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331 | GenericFifo<size_t> m_cmd_cleanup_pktid_fifo; |
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332 | GenericFifo<data_t> m_cmd_cleanup_nline_fifo; |
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333 | |
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334 | sc_signal<int> r_tgt_cmd_fsm; |
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335 | |
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336 | sc_signal<size_t> r_index; |
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337 | size_t nseg; |
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338 | soclib::common::Segment **m_seg; |
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339 | /////////////////////////////////////////////////////// |
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340 | // Registers controlled by the READ fsm |
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341 | /////////////////////////////////////////////////////// |
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342 | |
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343 | sc_signal<int> r_read_fsm; // FSM state |
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344 | sc_signal<copy_t> r_read_copies; // bit-vector of copies |
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345 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
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346 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
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347 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
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348 | sc_signal<data_t> *r_read_data; // data (one cache line) |
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349 | sc_signal<bool> r_read_word; // single word read |
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350 | sc_signal<size_t> r_read_way; // associative way (in cache) |
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351 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
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352 | |
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353 | // Buffer between READ fsm and XRAM_CMD fsm (ask a missing cache line to XRAM) |
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354 | sc_signal<bool> r_read_to_xram_cmd_req; // valid request |
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355 | sc_signal<data_t> r_read_to_xram_cmd_nline; // cache line index |
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356 | sc_signal<size_t> r_read_to_xram_cmd_trdid; // index in Transaction Table |
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357 | |
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358 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
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359 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
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360 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
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361 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
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362 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
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363 | sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line) |
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364 | sc_signal<bool> *r_read_to_tgt_rsp_val; // valid bit (for single_word) |
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365 | |
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366 | /////////////////////////////////////////////////////////////// |
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367 | // Registers controlled by the WRITE fsm |
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368 | /////////////////////////////////////////////////////////////// |
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369 | |
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370 | sc_signal<int> r_write_fsm; // FSM state |
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371 | sc_signal<addr_t> r_write_address; // first word address |
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372 | sc_signal<size_t> r_write_word_index; // first word index in line |
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373 | sc_signal<size_t> r_write_word_count; // number of words in line |
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374 | sc_signal<size_t> r_write_srcid; // transaction srcid |
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375 | sc_signal<size_t> r_write_trdid; // transaction trdid |
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376 | sc_signal<size_t> r_write_pktid; // transaction pktid |
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377 | sc_signal<data_t> *r_write_data; // data (one cache line) |
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378 | sc_signal<be_t> *r_write_be; // one byte enable per word |
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379 | sc_signal<bool> r_write_byte; // is it a byte write |
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380 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
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381 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
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382 | sc_signal<copy_t> r_write_copies; // bit vector of copies |
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383 | sc_signal<size_t> r_write_nb_copies; // number of copies |
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384 | sc_signal<size_t> r_write_way; // way of the line |
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385 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
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386 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
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387 | |
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388 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
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389 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
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390 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
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391 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
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392 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
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393 | |
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394 | // Buffer between WRITE fsm and XRAM_CMD fsm (ask a missing cache line to XRAM) |
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395 | sc_signal<bool> r_write_to_xram_cmd_req; // valid request |
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396 | sc_signal<data_t> r_write_to_xram_cmd_nline; // cache line index |
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397 | sc_signal<size_t> r_write_to_xram_cmd_trdid; // index in Transaction Table |
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398 | |
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399 | // Buffer between WRITE fsm and INIT_CMD fsm (Update L1 caches) |
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400 | sc_signal<bool> r_write_to_init_cmd_req; // valid request |
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401 | sc_signal<data_t> r_write_to_init_cmd_nline; // cache line index |
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402 | sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table |
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403 | sc_signal<copy_t> r_write_to_init_cmd_copies; // bit_vector of L1 to update |
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404 | sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line) |
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405 | sc_signal<bool> *r_write_to_init_cmd_we; // word enable |
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406 | sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line |
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407 | sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line |
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408 | |
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409 | ///////////////////////////////////////////////////////// |
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410 | // Registers controlled by INIT_RSP fsm |
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411 | ////////////////////////////////////////////////////////// |
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412 | |
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413 | sc_signal<int> r_init_rsp_fsm; // FSM state |
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414 | sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table |
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415 | sc_signal<size_t> r_init_rsp_srcid; // pending write srcid |
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416 | sc_signal<size_t> r_init_rsp_trdid; // pending write trdid |
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417 | sc_signal<size_t> r_init_rsp_pktid; // pending write pktid |
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418 | |
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419 | // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) |
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420 | sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request |
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421 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid |
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422 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid |
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423 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid |
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424 | |
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425 | /////////////////////////////////////////////////////// |
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426 | // Registers controlled by CLEANUP fsm |
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427 | /////////////////////////////////////////////////////// |
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428 | |
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429 | sc_signal<int> r_cleanup_fsm; // FSM state |
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430 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
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431 | sc_signal<size_t> r_cleanup_trdid; // transaction trdid |
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432 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
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433 | sc_signal<data_t> r_cleanup_nline; // cache line index |
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434 | |
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435 | sc_signal<copy_t> r_cleanup_copies; // bit-vector of copies |
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436 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
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437 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
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438 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
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439 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
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440 | |
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441 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a cleanup command from L1) |
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442 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
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443 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
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444 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
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445 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
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446 | |
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447 | /////////////////////////////////////////////////////// |
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448 | // Registers controlled by LLSC fsm |
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449 | /////////////////////////////////////////////////////// |
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450 | |
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451 | sc_signal<int> r_llsc_fsm; // FSM state |
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452 | sc_signal<data_t> r_llsc_data; // read data word |
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453 | sc_signal<copy_t> r_llsc_copies; // bit_vector of copies |
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454 | sc_signal<bool> r_llsc_dirty; // dirty bit (in directory) |
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455 | sc_signal<size_t> r_llsc_way; // way in directory |
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456 | sc_signal<size_t> r_llsc_set; // set in directory |
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457 | sc_signal<data_t> r_llsc_tag; // cache line tag (in directory) |
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458 | sc_signal<size_t> r_llsc_trt_index; // Transaction Table index |
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459 | |
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460 | // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read) |
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461 | sc_signal<bool> r_llsc_to_xram_cmd_req; // valid request |
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462 | sc_signal<data_t> r_llsc_to_xram_cmd_nline; // cache line index |
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463 | sc_signal<size_t> r_llsc_to_xram_cmd_trdid; // index in Transaction Table |
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464 | |
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465 | // Buffer between LLSC fsm and TGT_RSP fsm |
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466 | sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request |
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467 | sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word |
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468 | sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid |
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469 | sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid |
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470 | sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid |
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471 | |
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472 | //////////////////////////////////////////////////// |
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473 | // Registers controlled by the IXR_RSP fsm |
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474 | //////////////////////////////////////////////////// |
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475 | |
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476 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
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477 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
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478 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
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479 | |
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480 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
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481 | sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
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482 | |
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483 | //////////////////////////////////////////////////// |
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484 | // Registers controlled by the XRAM_RSP fsm |
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485 | //////////////////////////////////////////////////// |
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486 | |
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487 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
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488 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
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489 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
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490 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
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491 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
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492 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
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493 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
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494 | sc_signal<data_t> r_xram_rsp_victim_nline; // victim line index |
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495 | sc_signal<copy_t> r_xram_rsp_victim_copies; // victim line copies |
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496 | sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data |
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497 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
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498 | |
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499 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
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500 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
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501 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
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502 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
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503 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
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504 | sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
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505 | sc_signal<bool> *r_xram_rsp_to_tgt_rsp_val; // valid bit (for single word) |
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506 | |
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507 | // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) |
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508 | sc_signal<bool> r_xram_rsp_to_init_cmd_req; // Valid request |
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509 | sc_signal<data_t> r_xram_rsp_to_init_cmd_nline; // cache line index; |
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510 | sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry |
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511 | sc_signal<copy_t> r_xram_rsp_to_init_cmd_copies; // bit_vector of copies |
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512 | |
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513 | // Buffer between XRAM_RSP fsm and XRAM_CMD fsm (XRAM write) |
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514 | sc_signal<bool> r_xram_rsp_to_xram_cmd_req; // Valid request |
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515 | sc_signal<data_t> r_xram_rsp_to_xram_cmd_nline; // cache line index |
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516 | sc_signal<data_t> *r_xram_rsp_to_xram_cmd_data; // cache line data |
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517 | sc_signal<size_t> r_xram_rsp_to_xram_cmd_trdid; // index in transaction table |
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518 | |
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519 | //////////////////////////////////////////////////// |
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520 | // Registers controlled by the XRAM_CMD fsm |
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521 | //////////////////////////////////////////////////// |
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522 | |
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523 | sc_signal<int> r_xram_cmd_fsm; |
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524 | sc_signal<size_t> r_xram_cmd_cpt; |
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525 | |
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526 | //////////////////////////////////////////////////// |
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527 | // Registers controlled by TGT_RSP fsm |
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528 | //////////////////////////////////////////////////// |
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529 | |
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530 | sc_signal<int> r_tgt_rsp_fsm; |
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531 | sc_signal<size_t> r_tgt_rsp_cpt; |
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532 | |
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533 | //////////////////////////////////////////////////// |
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534 | // Registers controlled by INIT_CMD fsm |
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535 | //////////////////////////////////////////////////// |
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536 | |
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537 | sc_signal<int> r_init_cmd_fsm; |
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538 | sc_signal<size_t> r_init_cmd_cpt; |
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539 | sc_signal<size_t> r_init_cmd_target; |
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540 | |
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541 | //////////////////////////////////////////////////// |
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542 | // Registers controlled by ALLOC_DIR fsm |
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543 | //////////////////////////////////////////////////// |
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544 | |
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545 | sc_signal<int> r_alloc_dir_fsm; |
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546 | |
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547 | //////////////////////////////////////////////////// |
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548 | // Registers controlled by ALLOC_TRT fsm |
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549 | //////////////////////////////////////////////////// |
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550 | |
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551 | sc_signal<int> r_alloc_trt_fsm; |
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552 | |
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553 | //////////////////////////////////////////////////// |
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554 | // Registers controlled by ALLOC_UPT fsm |
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555 | //////////////////////////////////////////////////// |
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556 | |
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557 | sc_signal<int> r_alloc_upt_fsm; |
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558 | |
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559 | }; // end class VciMemCache |
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560 | |
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561 | }} |
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562 | |
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563 | #endif |
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