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vci_mem_cache_v3.h @ 890

Last change on this file since 890 was 82, checked in by guthmull, 14 years ago
Add broadcast limitation compatibility, indicate the type of response when possible
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1	/* -- c++ --
2	* File : vci_mem_cache_v3.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	*/
29	/*
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_V3_H
42	#define SOCLIB_CABA_MEM_CACHE_V3_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "mem_cache_directory_v3.h"
57	#include "xram_transaction_v3.h"
58	#include "update_tab_v3.h"
59	#include "atomic_tab_v3.h"
60
61	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
62	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
63
64	namespace soclib { namespace caba {
65	using namespace sc_core;
66
67	template<typename vci_param>
68	class VciMemCacheV3
69	: public soclib::caba::BaseModule
70	{
71	typedef sc_dt::sc_uint<40> addr_t;
72	typedef typename vci_param::fast_addr_t vci_addr_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t size_t;
76	typedef uint32_t be_t;
77	typedef uint32_t copy_t;
78
79	/* States of the TGT_CMD fsm */
80	enum tgt_cmd_fsm_state_e{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_READ_EOP,
84	TGT_CMD_WRITE,
85	TGT_CMD_ATOMIC,
86	};
87
88	/* States of the TGT_RSP fsm */
89	enum tgt_rsp_fsm_state_e{
90	TGT_RSP_READ_IDLE,
91	TGT_RSP_WRITE_IDLE,
92	TGT_RSP_LLSC_IDLE,
93	TGT_RSP_XRAM_IDLE,
94	TGT_RSP_INIT_IDLE,
95	TGT_RSP_CLEANUP_IDLE,
96	TGT_RSP_READ,
97	TGT_RSP_WRITE,
98	TGT_RSP_LLSC,
99	TGT_RSP_XRAM,
100	TGT_RSP_INIT,
101	TGT_RSP_CLEANUP,
102	};
103
104	/* States of the INIT_CMD fsm */
105	enum init_cmd_fsm_state_e{
106	INIT_CMD_INVAL_IDLE,
107	INIT_CMD_INVAL_NLINE,
108	INIT_CMD_XRAM_BRDCAST,
109	INIT_CMD_UPDT_IDLE,
110	INIT_CMD_WRITE_BRDCAST,
111	INIT_CMD_UPDT_NLINE,
112	INIT_CMD_UPDT_INDEX,
113	INIT_CMD_UPDT_DATA,
114	INIT_CMD_SC_UPDT_IDLE,
115	INIT_CMD_SC_BRDCAST,
116	INIT_CMD_SC_UPDT_NLINE,
117	INIT_CMD_SC_UPDT_INDEX,
118	INIT_CMD_SC_UPDT_DATA,
119	};
120
121	/* States of the INIT_RSP fsm */
122	enum init_rsp_fsm_state_e{
123	INIT_RSP_IDLE,
124	INIT_RSP_UPT_LOCK,
125	INIT_RSP_UPT_CLEAR,
126	INIT_RSP_END,
127	};
128
129	/* States of the READ fsm */
130	enum read_fsm_state_e{
131	READ_IDLE,
132	READ_DIR_LOCK,
133	READ_DIR_HIT,
134	READ_HEAP_LOCK,
135	READ_HEAP_WRITE,
136	READ_HEAP_ERASE,
137	READ_HEAP_LAST,
138	READ_RSP,
139	READ_TRT_LOCK,
140	READ_TRT_SET,
141	READ_XRAM_REQ,
142	};
143
144	/* States of the WRITE fsm */
145	enum write_fsm_state_e{
146	WRITE_IDLE,
147	WRITE_NEXT,
148	WRITE_DIR_LOCK,
149	WRITE_DIR_HIT_READ,
150	WRITE_DIR_HIT,
151	WRITE_DIR_HIT_RSP,
152	WRITE_UPT_LOCK,
153	WRITE_HEAP_LOCK,
154	WRITE_UPT_REQ,
155	WRITE_UPDATE,
156	WRITE_UPT_DEC,
157	WRITE_RSP,
158	WRITE_TRT_LOCK,
159	WRITE_TRT_DATA,
160	WRITE_TRT_SET,
161	WRITE_WAIT,
162	WRITE_XRAM_REQ,
163	WRITE_TRT_WRITE_LOCK,
164	WRITE_INVAL_LOCK,
165	WRITE_DIR_INVAL,
166	WRITE_INVAL,
167	WRITE_XRAM_SEND,
168	WRITE_HEAP_ERASE,
169	WRITE_HEAP_LAST,
170	};
171
172	/* States of the IXR_RSP fsm */
173	enum ixr_rsp_fsm_state_e{
174	IXR_RSP_IDLE,
175	IXR_RSP_ACK,
176	IXR_RSP_TRT_ERASE,
177	IXR_RSP_TRT_READ,
178	};
179
180	/* States of the XRAM_RSP fsm */
181	enum xram_rsp_fsm_state_e{
182	XRAM_RSP_IDLE,
183	XRAM_RSP_TRT_COPY,
184	XRAM_RSP_TRT_DIRTY,
185	XRAM_RSP_DIR_LOCK,
186	XRAM_RSP_DIR_UPDT,
187	XRAM_RSP_DIR_RSP,
188	XRAM_RSP_INVAL_LOCK,
189	XRAM_RSP_INVAL_WAIT,
190	XRAM_RSP_INVAL,
191	XRAM_RSP_WRITE_DIRTY,
192	XRAM_RSP_HEAP_ERASE,
193	XRAM_RSP_HEAP_LAST,
194	};
195
196	/* States of the IXR_CMD fsm */
197	enum ixr_cmd_fsm_state_e{
198	IXR_CMD_READ_IDLE,
199	IXR_CMD_WRITE_IDLE,
200	IXR_CMD_LLSC_IDLE,
201	IXR_CMD_XRAM_IDLE,
202	IXR_CMD_READ_NLINE,
203	IXR_CMD_WRITE_NLINE,
204	IXR_CMD_LLSC_NLINE,
205	IXR_CMD_XRAM_DATA,
206	};
207
208	/* States of the LLSC fsm */
209	enum llsc_fsm_state_e{
210	LLSC_IDLE,
211	LL_DIR_LOCK,
212	LL_DIR_HIT,
213	LL_RSP,
214	SC_DIR_LOCK,
215	SC_DIR_HIT,
216	SC_UPT_LOCK,
217	SC_WAIT,
218	SC_HEAP_LOCK,
219	SC_UPT_REQ,
220	SC_UPDATE,
221	SC_TRT_LOCK,
222	SC_INVAL_LOCK,
223	SC_DIR_INVAL,
224	SC_INVAL,
225	SC_XRAM_SEND,
226	SC_HEAP_ERASE,
227	SC_HEAP_LAST,
228	SC_RSP_FALSE,
229	SC_RSP_TRUE,
230	LLSC_TRT_LOCK,
231	LLSC_TRT_SET,
232	LLSC_XRAM_REQ,
233	};
234
235	/* States of the CLEANUP fsm */
236	enum cleanup_fsm_state_e{
237	CLEANUP_IDLE,
238	CLEANUP_DIR_LOCK,
239	CLEANUP_DIR_WRITE,
240	CLEANUP_HEAP_LOCK,
241	CLEANUP_HEAP_SEARCH,
242	CLEANUP_HEAP_CLEAN,
243	CLEANUP_HEAP_FREE,
244	CLEANUP_UPT_LOCK,
245	CLEANUP_UPT_WRITE,
246	CLEANUP_WRITE_RSP,
247	CLEANUP_RSP,
248	};
249
250	/* States of the ALLOC_DIR fsm */
251	enum alloc_dir_fsm_state_e{
252	ALLOC_DIR_READ,
253	ALLOC_DIR_WRITE,
254	ALLOC_DIR_LLSC,
255	ALLOC_DIR_CLEANUP,
256	ALLOC_DIR_XRAM_RSP,
257	};
258
259	/* States of the ALLOC_TRT fsm */
260	enum alloc_trt_fsm_state_e{
261	ALLOC_TRT_READ,
262	ALLOC_TRT_WRITE,
263	ALLOC_TRT_LLSC,
264	ALLOC_TRT_XRAM_RSP,
265	ALLOC_TRT_IXR_RSP,
266	};
267
268	/* States of the ALLOC_UPT fsm */
269	enum alloc_upt_fsm_state_e{
270	ALLOC_UPT_WRITE,
271	ALLOC_UPT_XRAM_RSP,
272	ALLOC_UPT_INIT_RSP,
273	ALLOC_UPT_CLEANUP,
274	ALLOC_UPT_LLSC,
275	};
276
277	/* States of the ALLOC_HEAP fsm */
278	enum alloc_heap_fsm_state_e{
279	ALLOC_HEAP_READ,
280	ALLOC_HEAP_WRITE,
281	ALLOC_HEAP_LLSC,
282	ALLOC_HEAP_CLEANUP,
283	ALLOC_HEAP_XRAM_RSP,
284	};
285
286	uint32_t m_cpt_cycles; // Counter of cycles
287	uint32_t m_cpt_read; // Number of READ transactions
288	uint32_t m_cpt_read_miss; // Number of MISS READ
289	uint32_t m_cpt_write; // Number of WRITE transactions
290	uint32_t m_cpt_write_miss; // Number of MISS WRITE
291	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
292	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
293	uint32_t m_cpt_update; // Number of UPDATE transactions
294	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
295	uint32_t m_cpt_inval; // Number of INVAL transactions
296	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
297	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
298	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
299	uint32_t m_cpt_ll; // Number of LL transactions
300	uint32_t m_cpt_sc; // Number of SC transactions
301
302	protected:
303
304	SC_HAS_PROCESS(VciMemCacheV3);
305
306	public:
307	sc_in<bool> p_clk;
308	sc_in<bool> p_resetn;
309	soclib::caba::VciTarget<vci_param> p_vci_tgt;
310	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
311	soclib::caba::VciInitiator<vci_param> p_vci_ini;
312	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
313
314	VciMemCacheV3(
315	sc_module_name name, // Instance Name
316	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
317	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
318	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
319	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
320	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
321	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
322	const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup
323	size_t nways, // Number of ways per set
324	size_t nsets, // Number of sets
325	size_t nwords, // Number of words per line
326	size_t heap_size=1024); // Size of the heap
327
328	~VciMemCacheV3();
329
330	void transition();
331
332	void genMoore();
333
334	void print_stats();
335
336	private:
337
338	// Component attributes
339	const size_t m_initiators; // Number of initiators
340	const size_t m_heap_size; // Size of the heap
341	const size_t m_ways; // Number of ways in a set
342	const size_t m_sets; // Number of cache sets
343	const size_t m_words; // Number of words in a line
344	const size_t m_srcid_ixr; // Srcid for requests to XRAM
345	const size_t m_srcid_ini; // Srcid for requests to processors
346	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
347	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
348	vci_addr_t *m_coherence_table; // address(srcid)
349	AtomicTab m_atomic_tab; // atomic access table
350	TransactionTab m_transaction_tab; // xram transaction table
351	UpdateTab m_update_tab; // pending update & invalidate
352	CacheDirectory m_cache_directory; // data cache directory
353	HeapDirectory m_heap_directory; // heap directory
354
355	data_t ***m_cache_data; // data array[set][way][word]
356
357	// adress masks
358	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
359	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
360	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
361	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
362
363	// broadcast address
364	vci_addr_t broadcast_addr;
365
366	//////////////////////////////////////////////////
367	// Others registers
368	//////////////////////////////////////////////////
369	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
370
371	//////////////////////////////////////////////////
372	// Registers controlled by the TGT_CMD fsm
373	//////////////////////////////////////////////////
374
375	// Fifo between TGT_CMD fsm and READ fsm
376	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
377	GenericFifo<size_t> m_cmd_read_length_fifo;
378	GenericFifo<size_t> m_cmd_read_srcid_fifo;
379	GenericFifo<size_t> m_cmd_read_trdid_fifo;
380	GenericFifo<size_t> m_cmd_read_pktid_fifo;
381
382	// Fifo between TGT_CMD fsm and WRITE fsm
383	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
384	GenericFifo<bool> m_cmd_write_eop_fifo;
385	GenericFifo<size_t> m_cmd_write_srcid_fifo;
386	GenericFifo<size_t> m_cmd_write_trdid_fifo;
387	GenericFifo<size_t> m_cmd_write_pktid_fifo;
388	GenericFifo<data_t> m_cmd_write_data_fifo;
389	GenericFifo<be_t> m_cmd_write_be_fifo;
390
391	// Fifo between TGT_CMD fsm and LLSC fsm
392	GenericFifo<uint64_t> m_cmd_llsc_addr_fifo;
393	GenericFifo<bool> m_cmd_llsc_sc_fifo;
394	GenericFifo<size_t> m_cmd_llsc_srcid_fifo;
395	GenericFifo<size_t> m_cmd_llsc_trdid_fifo;
396	GenericFifo<size_t> m_cmd_llsc_pktid_fifo;
397	GenericFifo<data_t> m_cmd_llsc_wdata_fifo;
398
399	sc_signal<int> r_tgt_cmd_fsm;
400
401	sc_signal<size_t> r_index;
402	size_t nseg;
403	size_t ncseg;
404	soclib::common::Segment **m_seg;
405	soclib::common::Segment **m_cseg;
406	///////////////////////////////////////////////////////
407	// Registers controlled by the READ fsm
408	///////////////////////////////////////////////////////
409
410	sc_signal<int> r_read_fsm; // FSM state
411	sc_signal<size_t> r_read_copy; // Srcid of the first copy
412	sc_signal<bool> r_read_copy_inst; // Type of the first copy
413	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
414	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
415	sc_signal<bool> r_read_lock; // lock bit (in directory)
416	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
417	sc_signal<bool> r_read_inst; // it is an instruction line
418	sc_signal<size_t> r_read_count; // number of copies
419	sc_signal<size_t> r_read_ptr; // pointer to the heap
420	sc_signal<data_t> *r_read_data; // data (one cache line)
421	sc_signal<size_t> r_read_way; // associative way (in cache)
422	sc_signal<size_t> r_read_trt_index; // Transaction Table index
423	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
424	sc_signal<bool> r_read_last_free; // Last free entry
425
426	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
427	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
428	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
429	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
430
431	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
432	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
433	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
434	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
435	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
436	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
437	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
438	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
439
440	///////////////////////////////////////////////////////////////
441	// Registers controlled by the WRITE fsm
442	///////////////////////////////////////////////////////////////
443
444	sc_signal<int> r_write_fsm; // FSM state
445	sc_signal<addr_t> r_write_address; // first word address
446	sc_signal<size_t> r_write_word_index; // first word index in line
447	sc_signal<size_t> r_write_word_count; // number of words in line
448	sc_signal<size_t> r_write_srcid; // transaction srcid
449	sc_signal<size_t> r_write_trdid; // transaction trdid
450	sc_signal<size_t> r_write_pktid; // transaction pktid
451	sc_signal<data_t> *r_write_data; // data (one cache line)
452	sc_signal<be_t> *r_write_be; // one byte enable per word
453	sc_signal<bool> r_write_byte; // is it a byte write
454	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
455	sc_signal<bool> r_write_lock; // lock bit (in directory)
456	sc_signal<bool> r_write_inst; // instruction bit
457	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
458	sc_signal<size_t> r_write_copy; // first owner of the line
459	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
460	sc_signal<size_t> r_write_count; // number of copies
461	sc_signal<size_t> r_write_ptr; // pointer to the heap
462	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
463	sc_signal<bool> r_write_to_dec; // need to decrement update counter
464	sc_signal<size_t> r_write_way; // way of the line
465	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
466	sc_signal<size_t> r_write_upt_index; // index in Update Table
467
468	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
469	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
470	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
471	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
472	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
473
474	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
475	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
476	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
477	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
478	sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data
479	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
480
481	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
482	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
483	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
484	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
485	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
486	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
487	sc_signal<bool> *r_write_to_init_cmd_we; // word enable
488	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
489	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
490	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
491	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
492
493	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
494	sc_signal<bool> r_write_to_init_rsp_req; // valid request
495	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
496
497	/////////////////////////////////////////////////////////
498	// Registers controlled by INIT_RSP fsm
499	//////////////////////////////////////////////////////////
500
501	sc_signal<int> r_init_rsp_fsm; // FSM state
502	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
503	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
504	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
505	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
506	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
507
508	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
509	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
510	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
511	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
512	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
513
514	///////////////////////////////////////////////////////
515	// Registers controlled by CLEANUP fsm
516	///////////////////////////////////////////////////////
517
518	sc_signal<int> r_cleanup_fsm; // FSM state
519	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
520	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
521	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
522	sc_signal<addr_t> r_cleanup_nline; // cache line index
523
524	sc_signal<copy_t> r_cleanup_copy; // first copy
525	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
526	sc_signal<copy_t> r_cleanup_count; // number of copies
527	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
528	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
529	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
530	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
531	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
532	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
533	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
534	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
535	sc_signal<bool> r_cleanup_inst; // inst bit (in directory)
536	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
537	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
538
539	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
540	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
541	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
542	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
543
544	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
545
546	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
547	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
548	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
549	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
550	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
551
552	///////////////////////////////////////////////////////
553	// Registers controlled by LLSC fsm
554	///////////////////////////////////////////////////////
555
556	sc_signal<int> r_llsc_fsm; // FSM state
557	sc_signal<data_t> r_llsc_data; // read data word
558	sc_signal<copy_t> r_llsc_copy; // Srcid of the first copy
559	sc_signal<bool> r_llsc_copy_inst; // Type of the first copy
560	sc_signal<size_t> r_llsc_count; // number of copies
561	sc_signal<size_t> r_llsc_ptr; // pointer to the heap
562	sc_signal<size_t> r_llsc_next_ptr; // next pointer to the heap
563	sc_signal<bool> r_llsc_is_cnt; // is_cnt bit (in directory)
564	sc_signal<bool> r_llsc_dirty; // dirty bit (in directory)
565	sc_signal<bool> r_llsc_inst; // inst bit
566	sc_signal<size_t> r_llsc_way; // way in directory
567	sc_signal<size_t> r_llsc_set; // set in directory
568	sc_signal<data_t> r_llsc_tag; // cache line tag (in directory)
569	sc_signal<size_t> r_llsc_trt_index; // Transaction Table index
570	sc_signal<size_t> r_llsc_upt_index; // Update Table index
571
572	// Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)
573	sc_signal<bool> r_llsc_to_ixr_cmd_req; // valid request
574	sc_signal<addr_t> r_llsc_to_ixr_cmd_nline; // cache line index
575	sc_signal<size_t> r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
576	sc_signal<bool> r_llsc_to_ixr_cmd_write; // write request
577	sc_signal<data_t> *r_llsc_to_ixr_cmd_data; // cache line data
578
579
580	// Buffer between LLSC fsm and TGT_RSP fsm
581	sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request
582	sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word
583	sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid
584	sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid
585	sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid
586
587	// Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
588	sc_signal<bool> r_llsc_to_init_cmd_multi_req; // valid request
589	sc_signal<bool> r_llsc_to_init_cmd_brdcast_req; // brdcast request
590	sc_signal<addr_t> r_llsc_to_init_cmd_nline; // cache line index
591	sc_signal<size_t> r_llsc_to_init_cmd_trdid; // index in Update Table
592	sc_signal<data_t> r_llsc_to_init_cmd_wdata; // data (one word)
593	sc_signal<size_t> r_llsc_to_init_cmd_index; // index of the word in line
594	GenericFifo<bool> m_llsc_to_init_cmd_inst_fifo; // fifo for the L1 type
595	GenericFifo<size_t> m_llsc_to_init_cmd_srcid_fifo; // fifo for srcids
596
597	// Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
598	sc_signal<bool> r_llsc_to_init_rsp_req; // valid request
599	sc_signal<size_t> r_llsc_to_init_rsp_upt_index; // index in update table
600
601	////////////////////////////////////////////////////
602	// Registers controlled by the IXR_RSP fsm
603	////////////////////////////////////////////////////
604
605	sc_signal<int> r_ixr_rsp_fsm; // FSM state
606	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
607	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
608
609	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
610	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
611
612	////////////////////////////////////////////////////
613	// Registers controlled by the XRAM_RSP fsm
614	////////////////////////////////////////////////////
615
616	sc_signal<int> r_xram_rsp_fsm; // FSM state
617	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
618	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
619	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
620	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
621	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
622	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
623	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
624	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
625	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
626	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
627	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
628	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
629	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
630	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
631	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
632
633	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
634	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
635	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
636	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
637	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
638	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
639	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
640	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response
641
642	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
643	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
644	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
645	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
646	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
647	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
648	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
649
650	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
651	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
652	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
653	sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data
654	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
655
656	////////////////////////////////////////////////////
657	// Registers controlled by the IXR_CMD fsm
658	////////////////////////////////////////////////////
659
660	sc_signal<int> r_ixr_cmd_fsm;
661	sc_signal<size_t> r_ixr_cmd_cpt;
662
663	////////////////////////////////////////////////////
664	// Registers controlled by TGT_RSP fsm
665	////////////////////////////////////////////////////
666
667	sc_signal<int> r_tgt_rsp_fsm;
668	sc_signal<size_t> r_tgt_rsp_cpt;
669
670	////////////////////////////////////////////////////
671	// Registers controlled by INIT_CMD fsm
672	////////////////////////////////////////////////////
673
674	sc_signal<int> r_init_cmd_fsm;
675	sc_signal<size_t> r_init_cmd_cpt;
676	sc_signal<bool> r_init_cmd_inst;
677
678	////////////////////////////////////////////////////
679	// Registers controlled by ALLOC_DIR fsm
680	////////////////////////////////////////////////////
681
682	sc_signal<int> r_alloc_dir_fsm;
683
684	////////////////////////////////////////////////////
685	// Registers controlled by ALLOC_TRT fsm
686	////////////////////////////////////////////////////
687
688	sc_signal<int> r_alloc_trt_fsm;
689
690	////////////////////////////////////////////////////
691	// Registers controlled by ALLOC_UPT fsm
692	////////////////////////////////////////////////////
693
694	sc_signal<int> r_alloc_upt_fsm;
695
696	////////////////////////////////////////////////////
697	// Registers controlled by ALLOC_HEAP fsm
698	////////////////////////////////////////////////////
699
700	sc_signal<int> r_alloc_heap_fsm;
701
702	}; // end class VciMemCacheV3
703
704	}}
705
706	#endif
707
708	// Local Variables:
709	// tab-width: 4
710	// c-basic-offset: 4
711	// c-file-offsets:((innamespace . 0)(inline-open . 0))
712	// indent-tabs-mode: nil
713	// End:
714
715	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
716

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