1 | /* |
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2 | * |
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3 | * SOCLIB_LGPL_HEADER_BEGIN |
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4 | * |
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5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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6 | * |
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7 | * SoCLib is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU Lesser General Public License as published |
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9 | * by the Free Software Foundation; version 2.1 of the License. |
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10 | * |
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11 | * SoCLib is distributed in the hope that it will be useful, but |
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12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with SoCLib; if not, write to the Free Software |
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18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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19 | * 02110-1301 USA |
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20 | * |
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21 | * SOCLIB_LGPL_HEADER_END |
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22 | * |
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23 | * Copyright (c) UPMC, Lip6, Asim |
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24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
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25 | * Christophe Choichillon <choichillon.christophe@gmail.com>, 2011 |
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26 | * |
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27 | * Maintainers: alain, Christophe Choichillon |
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28 | */ |
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29 | |
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30 | ///////////////////////////////////////////////////////////////////////// |
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31 | // This component is a multi-segments Ram controller. |
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32 | // |
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33 | // It supports only the compact VCI packets defined |
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34 | // in the VCI advanced specification: |
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35 | // - A READ burst command packet (such a cache line request) |
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36 | // contains one single flit. |
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37 | // The response packet length is defined by the PLEN field. |
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38 | // The zero value for the PLEN field is not supported. |
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39 | // An ERROR response packets contain one single flit, |
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40 | // - WRITE burst command packets at consecutive addresses are supported. |
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41 | // The zero value for the PLEN field is not supported. |
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42 | // Write response packets contain always one single flit. |
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43 | // - The LL & SC command packets are supported, but the packet |
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44 | // must contain one single flit. |
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45 | // The RAM latency is a parameter, that can have a zero value. |
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46 | //////////////////////////////////////////////////////////////////////// |
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47 | // Implementation note: This component does not contain any FIFO, |
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48 | // and is controlled by a single FSM. |
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49 | // The latency counter is decremented in the IDLE state. |
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50 | // The VCI command is analysed and checked in the CMD_GET state. |
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51 | // - For read, ll or sc commands, the command is acknowledged in |
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52 | // the CMD_STATE. It is executed and the response is sent in the |
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53 | // RSP_READ, RSP_LL or RSP_SC states. |
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54 | // - For write commands, the command is acknowledged in the CMD_STATE, |
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55 | // or in the CMD_WRITE & CMD_ERROR states in case of bursts. |
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56 | // The command is executed in the CMD_WRITE state, or in the RSP_WRITE |
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57 | // state for the last flit of a burst. The response packet is sent |
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58 | // in the RSP_WRITE state. |
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59 | ///////////////////////////////////////////////////////////////////////// |
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60 | |
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61 | #include <iostream> |
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62 | #include <cstring> |
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63 | #include "vci_synthetic_target.h" |
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64 | |
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65 | namespace soclib { |
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66 | namespace caba { |
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67 | |
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68 | using namespace soclib; |
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69 | |
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70 | #define tmpl(x) template<typename vci_param> x VciSyntheticTarget<vci_param> |
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71 | |
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72 | ////////////////////////// |
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73 | tmpl(/**/)::VciSyntheticTarget( |
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74 | sc_module_name insname, |
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75 | const soclib::common::IntTab index, |
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76 | const soclib::common::MappingTable &mt, |
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77 | const soclib::common::Loader &loader, |
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78 | const uint32_t latency) |
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79 | : caba::BaseModule(insname), |
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80 | m_loader(loader), |
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81 | m_seglist(mt.getSegmentList(index)), |
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82 | m_latency(latency), |
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83 | |
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84 | r_llsc_buf((size_t)(1<<vci_param::S)), |
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85 | |
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86 | r_fsm_state("r_fsm_state"), |
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87 | r_flit_count("r_flit_count"), |
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88 | r_seg_index("r_seg_index"), |
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89 | r_address("r_address"), |
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90 | r_wdata("r_wdata"), |
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91 | r_be("r_be"), |
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92 | r_srcid("r_srcid"), |
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93 | r_trdid("r_trdid"), |
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94 | r_pktid("r_pktid"), |
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95 | r_contig("r_contig"), |
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96 | r_latency_count("r_latency_count"), |
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97 | |
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98 | m_nbseg(0), |
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99 | |
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100 | p_resetn("p_resetn"), |
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101 | p_clk("p_clk"), |
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102 | p_vci("p_vci") |
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103 | { |
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104 | SC_METHOD(transition); |
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105 | dont_initialize(); |
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106 | sensitive << p_clk.pos(); |
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107 | |
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108 | SC_METHOD(genMoore); |
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109 | dont_initialize(); |
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110 | sensitive << p_clk.neg(); |
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111 | |
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112 | std::list<soclib::common::Segment>::iterator seg; |
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113 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) m_nbseg++; |
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114 | |
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115 | m_ram = new ram_t*[m_nbseg]; |
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116 | m_seg = new soclib::common::Segment*[m_nbseg]; |
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117 | |
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118 | size_t i = 0; |
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119 | size_t word_size = vci_param::B; // B is VCI's cell size |
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120 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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121 | { |
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122 | m_ram[i] = new ram_t[(seg->size()+word_size-1)/word_size]; |
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123 | m_seg[i] = &(*seg); |
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124 | i++; |
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125 | } |
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126 | } |
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127 | |
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128 | /////////////////////////// |
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129 | tmpl(/**/)::~VciSyntheticTarget() |
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130 | { |
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131 | for (size_t i=0 ; i<m_nbseg ; ++i) delete [] m_ram[i]; |
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132 | delete [] m_ram; |
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133 | delete [] m_seg; |
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134 | } |
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135 | |
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136 | ///////////////////// |
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137 | tmpl(void)::reload() |
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138 | { |
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139 | for ( size_t i=0 ; i<m_nbseg ; ++i ) |
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140 | { |
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141 | m_loader.load(&m_ram[i][0], m_seg[i]->baseAddress(), m_seg[i]->size()); |
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142 | for ( size_t addr = 0 ; addr < m_seg[i]->size()/vci_param::B ; ++addr ) |
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143 | m_ram[i][addr] = le_to_machine(m_ram[i][addr]); |
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144 | } |
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145 | } |
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146 | |
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147 | //////////////////// |
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148 | tmpl(void)::reset() |
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149 | { |
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150 | for ( size_t i=0 ; i<m_nbseg ; ++i ) std::memset(&m_ram[i][0], 0, m_seg[i]->size()); |
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151 | m_cpt_read = 0; |
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152 | m_cpt_write = 0; |
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153 | if (m_latency) { |
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154 | r_fsm_state = FSM_IDLE; |
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155 | r_latency_count = m_latency - 1; |
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156 | } else { |
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157 | r_fsm_state = FSM_CMD_GET; |
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158 | r_latency_count = 0; |
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159 | } |
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160 | r_llsc_buf.clearAll(); |
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161 | } |
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162 | |
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163 | ///////////////////////////////////////////////////////////////////////////// |
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164 | tmpl(bool)::write(size_t seg, vci_addr_t addr, vci_data_t wdata, vci_be_t be) |
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165 | { |
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166 | if ( m_seg[seg]->contains(addr) ) |
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167 | { |
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168 | size_t index = (size_t)((addr - m_seg[seg]->baseAddress()) / vci_param::B); |
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169 | vci_data_t cur = m_ram[seg][index]; |
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170 | vci_data_t mask = vci_param::be2mask(be); |
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171 | m_ram[seg][index] = (cur & ~mask) | (wdata & mask); |
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172 | m_cpt_write++; |
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173 | return true; |
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174 | } |
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175 | return false; |
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176 | } |
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177 | |
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178 | ///////////////////////////////////////////////////////////////// |
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179 | tmpl(bool)::read(size_t seg, vci_addr_t addr, vci_data_t &rdata ) |
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180 | { |
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181 | if ( m_seg[seg]->contains(addr) ) |
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182 | { |
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183 | size_t index = (size_t)((addr - m_seg[seg]->baseAddress()) / vci_param::B); |
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184 | rdata = m_ram[seg][index]; |
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185 | m_cpt_read++; |
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186 | return true; |
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187 | } |
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188 | return false; |
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189 | } |
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190 | |
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191 | ////////////////////////// |
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192 | tmpl(void)::print_trace() |
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193 | { |
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194 | const char* state_str[] = { "IDLE", |
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195 | "CMD_GET", |
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196 | "CMD_WRITE", |
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197 | "CMD_ERROR", |
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198 | "RSP_READ", |
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199 | "RSP_WRITE", |
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200 | "RSP_LL", |
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201 | "RSP_SC", |
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202 | "RSP_ERROR" }; |
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203 | std::cout << "Simple_ram " << name() |
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204 | << " : state = " << state_str[r_fsm_state] |
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205 | << " / latency_count = " << r_latency_count |
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206 | << " / flit_count = " << r_flit_count << std::endl; |
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207 | } |
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208 | |
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209 | ///////////////////////// |
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210 | tmpl(void)::transition() |
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211 | { |
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212 | if (!p_resetn) |
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213 | { |
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214 | reset(); |
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215 | reload(); |
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216 | return; |
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217 | } |
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218 | |
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219 | #ifdef SOCLIB_MODULE_DEBUG |
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220 | std::cout << "Synthetic_target : " << name() << std::endl; |
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221 | std::cout << " fsm_state = " << r_fsm_state |
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222 | << " latency_count = " << r_latency_count << std::endl; |
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223 | #endif |
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224 | |
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225 | switch ( r_fsm_state ) { |
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226 | case FSM_IDLE: // unreachable state if m_latency == 0 |
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227 | { |
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228 | if ( p_vci.cmdval.read() ) |
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229 | { |
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230 | if (r_latency_count.read() == 0) |
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231 | { |
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232 | r_fsm_state = FSM_CMD_GET; |
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233 | r_latency_count = m_latency - 1; |
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234 | } |
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235 | else |
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236 | { |
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237 | r_latency_count = r_latency_count.read() - 1; |
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238 | } |
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239 | } |
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240 | break; |
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241 | } |
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242 | case FSM_CMD_GET: |
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243 | { |
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244 | if ( !p_vci.cmdval.read() ) break; |
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245 | |
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246 | vci_addr_t address = p_vci.address.read(); |
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247 | bool error = true; |
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248 | for ( size_t index = 0 ; index<m_nbseg && error ; ++index) |
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249 | { |
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250 | if(address & 0x3){ |
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251 | error = false; |
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252 | } else { |
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253 | if ( (m_seg[index]->contains(address)) && |
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254 | (m_seg[index]->contains(address + p_vci.plen.read() - vci_param::B)) ) |
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255 | { |
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256 | error = false; |
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257 | r_seg_index = index; |
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258 | } |
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259 | } |
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260 | } |
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261 | |
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262 | r_address = address; |
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263 | r_be = p_vci.be.read(); |
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264 | r_wdata = p_vci.wdata.read(); |
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265 | r_srcid = p_vci.srcid.read(); |
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266 | r_trdid = p_vci.trdid.read(); |
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267 | r_pktid = p_vci.pktid.read(); |
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268 | |
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269 | if ( error ) |
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270 | { |
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271 | if( p_vci.eop.read() ) r_fsm_state = FSM_RSP_ERROR; |
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272 | else r_fsm_state = FSM_CMD_ERROR; |
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273 | } |
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274 | else |
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275 | { |
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276 | assert( (p_vci.plen.read() != 0) && "VCI command packets should have plen != 0"); |
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277 | if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) |
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278 | { |
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279 | r_contig = p_vci.contig.read(); |
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280 | if( p_vci.eop.read() ) r_fsm_state = FSM_RSP_WRITE; |
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281 | else r_fsm_state = FSM_CMD_WRITE; |
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282 | } |
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283 | else if ( p_vci.cmd.read() == vci_param::CMD_READ ) |
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284 | { |
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285 | r_flit_count = p_vci.plen.read()/vci_param::B; |
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286 | r_contig = p_vci.contig.read(); |
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287 | r_fsm_state = FSM_RSP_READ; |
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288 | assert( p_vci.eop.read() && "VCI read command packets should be one flit"); |
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289 | } |
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290 | else if ( p_vci.cmd.read() == vci_param::CMD_STORE_COND ) |
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291 | { |
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292 | r_fsm_state = FSM_RSP_SC; |
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293 | assert( p_vci.eop.read() && "VCI sc command packets should be one flit"); |
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294 | } |
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295 | else if ( p_vci.cmd.read() == vci_param::CMD_LOCKED_READ ) |
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296 | { |
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297 | r_fsm_state = FSM_RSP_LL; |
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298 | assert( p_vci.eop.read() && "VCI ll command packets should be one flit"); |
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299 | } |
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300 | } |
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301 | break; |
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302 | } |
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303 | case FSM_CMD_WRITE: |
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304 | { |
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305 | assert( write (r_seg_index, r_address , r_wdata, r_be ) && "out of bounds access in a write burst" ); |
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306 | if ( p_vci.cmdval.read() ) |
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307 | { |
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308 | vci_addr_t next_address = r_address.read() + (vci_addr_t)vci_param::B; |
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309 | assert( ((r_contig && (next_address == p_vci.address.read())) || |
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310 | (!r_contig && (r_address.read() == p_vci.address.read()))) && |
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311 | "addresses must be contiguous or constant in a VCI write burst" ); |
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312 | r_address = p_vci.address.read(); |
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313 | r_be = p_vci.be.read(); |
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314 | r_wdata = p_vci.wdata.read(); |
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315 | if ( p_vci.eop.read() ) r_fsm_state = FSM_RSP_WRITE; |
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316 | } |
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317 | break; |
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318 | } |
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319 | case FSM_RSP_WRITE: |
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320 | { |
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321 | if (r_address.read() != 0x3) |
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322 | assert( write (r_seg_index, r_address , r_wdata, r_be ) && "out of bounds access in a write burst" ); |
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323 | if( p_vci.rspack.read() ) |
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324 | { |
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325 | if( m_latency ) r_fsm_state = FSM_IDLE; |
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326 | else r_fsm_state = FSM_CMD_GET; |
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327 | } |
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328 | break; |
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329 | } |
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330 | case FSM_RSP_READ: |
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331 | { |
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332 | if ( p_vci.rspack.read() ) |
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333 | { |
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334 | r_flit_count = r_flit_count - 1; |
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335 | if ( r_contig ) r_address = r_address.read() + vci_param::B; |
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336 | if ( r_flit_count == 1) // last flit |
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337 | { |
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338 | if( m_latency ) r_fsm_state = FSM_IDLE; |
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339 | else r_fsm_state = FSM_CMD_GET; |
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340 | } |
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341 | } |
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342 | break; |
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343 | } |
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344 | case FSM_CMD_ERROR: |
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345 | { |
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346 | if ( p_vci.cmdval.read() && p_vci.eop.read() ) |
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347 | { |
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348 | r_fsm_state = FSM_RSP_ERROR; |
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349 | } |
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350 | break; |
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351 | } |
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352 | case FSM_RSP_ERROR: |
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353 | { |
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354 | if ( p_vci.rspack.read() ) |
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355 | { |
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356 | if( m_latency ) r_fsm_state = FSM_IDLE; |
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357 | else r_fsm_state = FSM_CMD_GET; |
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358 | } |
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359 | break; |
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360 | } |
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361 | case FSM_RSP_LL: |
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362 | { |
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363 | if ( p_vci.rspack.read() ) |
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364 | { |
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365 | r_llsc_buf.doLoadLinked(r_address.read(), r_srcid.read()); |
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366 | if( m_latency ) r_fsm_state = FSM_IDLE; |
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367 | else r_fsm_state = FSM_CMD_GET; |
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368 | } |
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369 | break; |
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370 | } |
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371 | case FSM_RSP_SC: |
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372 | { |
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373 | if ( p_vci.rspack.read() ) |
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374 | { |
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375 | if ( r_llsc_buf.isAtomic(r_address.read(), r_srcid.read()) ) |
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376 | { |
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377 | r_llsc_buf.accessDone(r_address.read()); |
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378 | write (r_seg_index, r_address , r_wdata, r_be); |
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379 | } |
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380 | if( m_latency ) r_fsm_state = FSM_IDLE; |
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381 | else r_fsm_state = FSM_CMD_GET; |
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382 | } |
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383 | break; |
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384 | } |
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385 | } // end switch fsm_state |
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386 | |
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387 | } // end transition() |
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388 | |
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389 | /////////////////////// |
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390 | tmpl(void)::genMoore() |
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391 | { |
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392 | switch ( r_fsm_state ) { |
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393 | case FSM_IDLE: |
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394 | { |
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395 | p_vci.cmdack = false; |
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396 | p_vci.rspval = false; |
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397 | p_vci.rdata = 0; |
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398 | p_vci.rsrcid = 0; |
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399 | p_vci.rtrdid = 0; |
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400 | p_vci.rpktid = 0; |
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401 | p_vci.rerror = 0; |
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402 | p_vci.reop = false; |
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403 | break; |
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404 | } |
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405 | case FSM_CMD_GET: |
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406 | case FSM_CMD_WRITE: |
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407 | case FSM_CMD_ERROR: |
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408 | { |
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409 | p_vci.cmdack = true; |
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410 | p_vci.rspval = false; |
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411 | p_vci.rdata = 0; |
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412 | p_vci.rsrcid = 0; |
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413 | p_vci.rtrdid = 0; |
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414 | p_vci.rpktid = 0; |
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415 | p_vci.rerror = 0; |
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416 | p_vci.reop = false; |
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417 | break; |
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418 | } |
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419 | case FSM_RSP_WRITE: |
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420 | { |
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421 | p_vci.cmdack = false; |
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422 | p_vci.rspval = true; |
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423 | p_vci.rdata = 0; |
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424 | p_vci.rsrcid = r_srcid.read(); |
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425 | p_vci.rtrdid = r_trdid.read(); |
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426 | p_vci.rpktid = r_pktid.read(); |
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427 | p_vci.rerror = vci_param::ERR_NORMAL; |
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428 | p_vci.reop = true; |
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429 | break; |
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430 | } |
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431 | case FSM_RSP_READ: |
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432 | { |
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433 | vci_data_t rdata; |
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434 | assert( read(r_seg_index, r_address, rdata) && "out of bounds access in a read burst" ); |
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435 | p_vci.cmdack = false; |
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436 | p_vci.rspval = true; |
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437 | p_vci.rdata = rdata; |
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438 | p_vci.rsrcid = r_srcid.read(); |
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439 | p_vci.rtrdid = r_trdid.read(); |
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440 | p_vci.rpktid = r_pktid.read(); |
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441 | p_vci.rerror = vci_param::ERR_NORMAL; |
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442 | p_vci.reop = (r_flit_count.read() == 1); |
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443 | break; |
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444 | } |
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445 | case FSM_RSP_LL: |
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446 | { |
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447 | vci_data_t rdata; |
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448 | assert( read(r_seg_index, r_address, rdata) && "out of bounds access in a ll access" ); |
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449 | p_vci.cmdack = false; |
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450 | p_vci.rspval = true; |
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451 | p_vci.rdata = rdata; |
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452 | p_vci.rsrcid = r_srcid.read(); |
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453 | p_vci.rtrdid = r_trdid.read(); |
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454 | p_vci.rpktid = r_pktid.read(); |
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455 | p_vci.rerror = vci_param::ERR_NORMAL; |
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456 | p_vci.reop = true; |
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457 | break; |
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458 | } |
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459 | case FSM_RSP_SC: |
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460 | { |
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461 | p_vci.cmdack = false; |
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462 | p_vci.rspval = true; |
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463 | if ( r_llsc_buf.isAtomic(r_address.read(), r_srcid.read()) ) p_vci.rdata = 0; |
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464 | else p_vci.rdata = 1; |
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465 | p_vci.rsrcid = r_srcid.read(); |
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466 | p_vci.rtrdid = r_trdid.read(); |
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467 | p_vci.rpktid = r_pktid.read(); |
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468 | p_vci.rerror = vci_param::ERR_NORMAL; |
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469 | p_vci.reop = true; |
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470 | break; |
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471 | } |
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472 | case FSM_RSP_ERROR: |
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473 | { |
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474 | p_vci.cmdack = false; |
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475 | p_vci.rspval = true; |
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476 | p_vci.rdata = 0; |
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477 | p_vci.rsrcid = r_srcid.read(); |
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478 | p_vci.rtrdid = r_trdid.read(); |
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479 | p_vci.rpktid = r_pktid.read(); |
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480 | p_vci.rerror = vci_param::ERR_GENERAL_DATA_ERROR; |
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481 | p_vci.reop = true; |
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482 | break; |
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483 | } |
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484 | } // end switch fsm_state |
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485 | } // end genMoore() |
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486 | |
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487 | }} |
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488 | |
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489 | |
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