source: branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/segmentation.h @ 459

Last change on this file since 459 was 137, checked in by simerabe, 14 years ago

replacing old ring versions with new one

  • Property svn:eol-style set to native
  • Property svn:executable set to *
  • Property svn:keywords set to "Author Date Id Rev URL Revision"
  • Property svn:mime-type set to text/plain
File size: 1.9 KB
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1
2/////////////////////////////////////////////////////////////////
3//      ADDRESS SPACE SEGMENTATION
4//
5//      This file must be included in the system.cpp file,
6//      for harware configuration : It is used to build
7//      the SOCLIB_SEGMENT_TABLE.
8//
9//      This file can also be used by the ldscript generator,
10//      for embedded software generation.
11//     
12//      It gives the system integrator the garanty
13//      that hardware and software have the same
14//      description of the address space segmentation.
15/////////////////////////////////////////////////////////////////
16
17/////////////////////////////////////////////////////////////////
18//      reset, and exception segments
19//      base address required by MIPS processor
20/////////////////////////////////////////////////////////////////
21//#define MMU
22
23#define RESET_BASE      0xBFC00000
24#define RESET_SIZE      0x00001000
25
26#define EXCEP_BASE      0x80000000
27#define EXCEP_SIZE      0x00001000
28
29#define TEXT_BASE       0x00400000
30#define TEXT_SIZE       0x00100000
31/////////////////////////////////////////////////////////////////
32//      global data segment (initialised)
33/////////////////////////////////////////////////////////////////
34
35#define MC_M_BASE       0x10000000
36#define MC_M_SIZE       0x00100000
37
38//////////////////////////////////////////////////////////
39//      System devices
40///////////////////////////////////////////////////////////
41
42#define TTY_BASE        0xC0200000
43#define TTY_SIZE        0x00010000
44
45#define TIMER_BASE      0xD0200000
46#define TIMER_SIZE      0x00000100
47
48#define LOCKS_BASE      0xE0200000
49#define LOCKS_SIZE      0x00000100
50
51#define C_PROC0_BASE    0x01200000
52#define C_PROC0_SIZE    0x00000010
53
54#define C_PROC1_BASE    0x02200000
55#define C_PROC1_SIZE    0x00000010
56
57#define C_PROC2_BASE    0x03200000
58#define C_PROC2_SIZE    0x00000010
59
60#define C_PROC3_BASE    0x04200000
61#define C_PROC3_SIZE    0x00000010
62
63#define C_MC_M_BASE     0x00200000
64#define C_MC_M_SIZE     0x00000008
65
66#define XRAM_BASE       0xB0200000
67#define XRAM_SIZE       0x00000008
68
69#define MC_R_BASE       0x20200000
70#define MC_R_SIZE       0x00000008
71
72#define CLEANUP_OFFSET  0x20200000
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