| 1 | |
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| 2 | __doc__ = ''' |
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| 3 | This file is a Cluster library. It contains classes implementing the |
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| 4 | netlist of a cluster, for different tsar versions. |
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| 5 | ''' |
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| 6 | |
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| 7 | class Cluster: |
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| 8 | ''' |
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| 9 | A generic netlist of a cluster, which must be subclassed to |
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| 10 | implement caches&dma instanciation |
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| 11 | ''' |
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| 12 | |
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| 13 | def __init__(self, pf, ringp, ringc, mtp, mtc, mtx, proc_count, cluster_no, cluster_base): |
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| 14 | self.pf = pf |
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| 15 | self.ringp = ringp |
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| 16 | self.ringc = ringc |
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| 17 | self.mtp = mtp |
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| 18 | self.mtc = mtc |
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| 19 | self.mtx = mtx |
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| 20 | self.cluster_no = cluster_no |
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| 21 | |
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| 22 | self.generate(proc_count, cluster_base) |
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| 23 | |
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| 24 | def generate(self, proc_count, cluster_base): |
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| 25 | ''' |
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| 26 | The core netlist, where caches and components are created |
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| 27 | ''' |
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| 28 | self.cpu = [] |
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| 29 | for i in range(proc_count): |
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| 30 | c = self.create_cpu(i, |
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| 31 | cluster_base |
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| 32 | + 0x01200000 |
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| 33 | + 0x01000000 * i |
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| 34 | ) |
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| 35 | self.cpu.append(c) |
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| 36 | |
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| 37 | memc, xram = self.create_memcache( segments = [ |
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| 38 | ('reset', 0xbfc00000, 0x00010000), |
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| 39 | ('excep', 0x80000000, 0x00010000), |
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| 40 | ('text', 0x00400000, 0x00050000), |
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| 41 | ('data', 0x10000000, 0x00100000), |
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| 42 | ] ) |
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| 43 | tty = self.create_tty( addr = 0xc0200000, tty_count = 1 ) |
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| 44 | xicu = self.create_xicu( addr = 0xd2200000, pti_count = 1, |
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| 45 | hwi_count = 1, |
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| 46 | wti_count = 4, |
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| 47 | irq_count = 4) |
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| 48 | tty.irq[0] // xicu.hwi[0] |
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| 49 | for i in range(proc_count): |
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| 50 | self.cpu[i].irq[0] // xicu.irq[i] |
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| 51 | |
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| 52 | def create_tty(self, addr, tty_count = 1): |
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| 53 | names = map(lambda x:'tty%d'%x, range(tty_count)) |
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| 54 | name = 'tty%d'%self.cluster_no |
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| 55 | tty = self.pf.create('caba:vci_multi_tty', name, names = names) |
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| 56 | self.ringp.to_target.new() // tty.vci |
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| 57 | tty.addSegment(name, address = addr, size = 0x40, cacheable = False) |
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| 58 | return tty |
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| 59 | |
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| 60 | def create_xicu(self, addr, pti_count, hwi_count, wti_count, irq_count): |
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| 61 | name = 'xicu' |
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| 62 | xicu = self.pf.create('caba:vci_xicu_vhdl', name, pti_count = pti_count, |
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| 63 | hwi_count = hwi_count, |
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| 64 | wti_count = wti_count, |
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| 65 | irq_count = irq_count) |
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| 66 | self.ringp.to_target.new() // xicu.vci |
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| 67 | xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False) |
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| 68 | return xicu |
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| 69 | |
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| 70 | |
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| 71 | class ClusterV3(Cluster): |
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| 72 | ''' |
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| 73 | A TsarV3 implementation, using vci_cc_vcache_wrapper2_v1, |
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| 74 | vci_mem_cache_v3 and vci_dma_tsar_v2. |
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| 75 | ''' |
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| 76 | |
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| 77 | def create_cpu(self, cpuid, addr): |
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| 78 | c = self.pf.create( |
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| 79 | 'caba:vci_cc_xcache_wrapper_v1', |
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| 80 | 'proc_%d_%d' % (self.cluster_no, cpuid), |
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| 81 | iss_t = "common:mips32el", |
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| 82 | proc_id = cpuid, |
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| 83 | icache_ways = 4, |
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| 84 | icache_sets = 64, |
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| 85 | icache_words = 16, |
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| 86 | dcache_ways = 4, |
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| 87 | dcache_sets = 64, |
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| 88 | dcache_words = 16, |
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| 89 | write_buf_size = 16, |
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| 90 | ) |
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| 91 | self.ringc.to_initiator.new() // c.vci_ini_c |
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| 92 | self.ringc.to_target.new() // c.vci_tgt |
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| 93 | self.ringp.to_initiator.new() // c.vci_ini_rw |
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| 94 | |
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| 95 | c.addSegment('proc_%d_%d' % (self.cluster_no, cpuid), |
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| 96 | address = addr, |
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| 97 | size = 0x10, |
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| 98 | cacheable = False, |
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| 99 | ) |
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| 100 | |
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| 101 | return c |
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| 102 | |
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| 103 | def create_memcache(self, segments): |
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| 104 | memc = self.pf.create('caba:vci_mem_cache_v1', 'memc', |
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| 105 | mtx = self.mtx, |
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| 106 | vci_ixr_index = (self.cluster_no,), |
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| 107 | nways = 16, |
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| 108 | nsets = 256, |
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| 109 | nwords = 16, |
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| 110 | ) |
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| 111 | self.ringc.to_target.new() // memc.vci_tgt_cleanup |
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| 112 | self.ringp.to_target.new() // memc.vci_tgt |
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| 113 | self.ringc.to_initiator.new() // memc.vci_ini |
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| 114 | |
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| 115 | xram = self.pf.create('caba:vci_simple_ram', 'xram', |
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| 116 | mt = self.mtx, |
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| 117 | ident = (self.cluster_no,), |
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| 118 | latency = 1, |
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| 119 | ) |
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| 120 | memc.vci_ixr // xram.vci |
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| 121 | |
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| 122 | for name, addr, size in segments: |
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| 123 | # Here DSX knows the only way to address xram is through its |
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| 124 | # vci port. It also knows the only associated mapping_table. |
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| 125 | xram.addSegment('ram_x_'+name, address = addr, size = size, cacheable = True) |
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| 126 | |
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| 127 | # For these segments, there is ambiguity for the mapping_table |
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| 128 | # we are talking about, so we specify mt = ... |
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| 129 | memc.addSegment('ram_p_'+name, address = addr, size = size, cacheable = True, mt = self.mtp) |
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| 130 | memc.addSegment('ram_c_'+name, address = addr, size = size, cacheable = True, mt = self.mtc) |
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| 131 | return memc, xram |
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