1 | #include "tsar_cluster_v1.h" |
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2 | |
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3 | #define DIRECT_TRACE |
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4 | #define COHERENCE_TRACE |
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5 | |
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6 | namespace soclib { |
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7 | namespace caba { |
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8 | |
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9 | template<typename vci_param, size_t cmd_width, size_t rsp_width> |
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10 | TsarClusterV1<vci_param, cmd_width, rsp_width>::TsarClusterV1( |
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11 | sc_module_name nm, |
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12 | |
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13 | // Cluster Index |
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14 | int cluster_idx, |
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15 | |
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16 | // Dspin Routers parameters |
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17 | int infifo_depth, |
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18 | int outfifo_depth, |
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19 | int x_local, |
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20 | int y_local, |
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21 | |
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22 | // Bits for global routing |
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23 | size_t x_width, |
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24 | size_t y_width, |
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25 | |
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26 | // Mapping tables |
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27 | const MappingTable & md, |
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28 | const MappingTable & mc, |
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29 | const MappingTable & mx, |
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30 | |
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31 | // Processor Number |
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32 | size_t nprocs, |
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33 | size_t max_nprocs, |
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34 | |
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35 | // Cache L1 sizes |
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36 | size_t iways, |
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37 | size_t isets, |
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38 | size_t iwords, |
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39 | size_t dways, |
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40 | size_t dsets, |
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41 | size_t dwords, |
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42 | |
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43 | // MemCache sizes |
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44 | size_t mcways, |
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45 | size_t mcsets, |
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46 | size_t mcwords, |
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47 | |
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48 | int is_io, |
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49 | |
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50 | Loader & loader |
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51 | ) : soclib::caba::BaseModule(nm), |
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52 | m_nprocs(nprocs) |
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53 | { |
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54 | std::ostringstream sd; |
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55 | sd << "ringd_" << x_local << "_" << y_local; |
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56 | ringd = new VciSimpleRingFast<vci_param, cmd_width, rsp_width> ( |
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57 | sd.str().c_str(), |
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58 | md, // Direct Mapping Table |
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59 | IntTab(), // Cluster index |
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60 | 2, // Wrapper fifo depth |
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61 | nprocs, // Number of initiators |
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62 | 2 + is_io // Number of targets |
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63 | ); |
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64 | |
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65 | #ifdef DEBUG_TSAR_CLUSTER_V1 |
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66 | std::cout << ringd->name() << " instantiated" << std::endl; |
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67 | #endif |
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68 | |
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69 | std::ostringstream sc; |
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70 | sc << "ringc_" << x_local << "_" << y_local; |
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71 | ringc = new VciSimpleRingFast<vci_param, cmd_width, rsp_width> ( |
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72 | sc.str().c_str(), |
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73 | mc, // Direct Mapping Table |
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74 | IntTab(), // Cluster index |
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75 | 2, // Wrapper fifo depth |
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76 | nprocs + 1, // Number of initiators |
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77 | max_nprocs + 1 // Number of targets |
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78 | ); |
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79 | |
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80 | #ifdef DEBUG_TSAR_CLUSTER_V1 |
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81 | std::cout << ringc->name() << " instantiated" << std::endl; |
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82 | #endif |
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83 | |
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84 | proc_iss::set_loader(loader); |
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85 | procs = new VciCcXCacheWrapperV1<vci_param, proc_iss> * [nprocs]; |
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86 | for(size_t p=0; p < nprocs; p++) { |
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87 | std::ostringstream sp; |
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88 | sp << "proc_" << x_local << "_" << y_local << "_" << p; |
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89 | |
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90 | procs[p] = new VciCcXCacheWrapperV1<vci_param, proc_iss> ( |
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91 | sp.str().c_str(), |
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92 | p + nprocs*cluster_idx, // Processor Id |
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93 | md, mc, // Mapping Tables |
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94 | IntTab(p), // SRCID_D |
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95 | IntTab(p), // SRCID_C |
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96 | IntTab(p), // TGTID_C |
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97 | iways, isets, iwords, // ICache Size |
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98 | dways, dsets, dwords, // DCache Size |
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99 | x_width, y_width, max_nprocs // Coherence Parameters |
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100 | ); |
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101 | |
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102 | #ifdef DEBUG_TSAR_CLUSTER_V1 |
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103 | std::cout << procs[p]->name() << " instantiated" << std::endl; |
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104 | #endif |
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105 | } |
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106 | |
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107 | std::ostringstream sm; |
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108 | sm << "memc_" << x_local << "_" << y_local; |
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109 | memc = new VciMemCacheV1<vci_param> ( |
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110 | sm.str().c_str(), |
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111 | md, mc, mx, // Mapping Tables |
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112 | IntTab(0), // SRCID_X |
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113 | IntTab(max_nprocs), // SRCID_C |
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114 | IntTab(0), // TGTID_D |
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115 | IntTab(max_nprocs), // TGTID_C |
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116 | mcways, mcsets, mcwords // MemCache Size |
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117 | ); |
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118 | |
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119 | #ifdef DEBUG_TSAR_CLUSTER_V1 |
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120 | std::cout << memc->name() << " instantiated" << std::endl; |
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121 | #endif |
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122 | |
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123 | std::ostringstream sx; |
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124 | sx << "xicu_" << x_local << "_" << y_local; |
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125 | xicu = new VciXicu<vci_param> ( |
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126 | sx.str().c_str(), |
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127 | md, |
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128 | IntTab(1), // TGTID_D |
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129 | nprocs, // number of TIMERS |
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130 | is_io, // number of hard IRQs |
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131 | nprocs, // number of soft IRQs |
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132 | nprocs // number of output IRQ lines |
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133 | ); |
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134 | |
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135 | #ifdef DEBUG_TSAR_CLUSTER_V1 |
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136 | std::cout << xicu->name() << " instantiated" << std::endl; |
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137 | #endif |
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138 | |
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139 | std::ostringstream stty; |
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140 | mtty = NULL; |
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141 | if (is_io == 1) { |
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142 | stty << "mtty_" << x_local << "_" << y_local; |
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143 | |
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144 | mtty = new VciMultiTty<vci_param> ( |
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145 | stty.str().c_str(), |
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146 | IntTab(2), |
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147 | md, |
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148 | "tty0", NULL |
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149 | ); |
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150 | |
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151 | #ifdef DEBUG_TSAR_CLUSTER_V1 |
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152 | std::cout << mtty->name() << " instantiated" << std::endl; |
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153 | #endif |
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154 | } |
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155 | |
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156 | ////////////////////////////////////////////////////////////// |
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157 | // Netlist |
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158 | |
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159 | signal_vci_ini_d = alloc_elems<VciSignals<vci_param> >("s_vci_ini_d", nprocs); |
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160 | signal_vci_tgt_d = alloc_elems<VciSignals<vci_param> >("s_vci_tgt_d", 2 + is_io); |
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161 | signal_vci_ini_c = alloc_elems<VciSignals<vci_param> >("s_vci_ini_c", nprocs + 1); |
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162 | signal_vci_tgt_c = alloc_elems<VciSignals<vci_param> >("s_vci_tgt_c", nprocs + 1); |
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163 | |
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164 | signal_proc_irq = new sc_signal<bool>[nprocs]; |
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165 | |
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166 | memc->p_clk (p_clk); |
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167 | memc->p_resetn (p_resetn); |
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168 | memc->p_vci_tgt (signal_vci_tgt_d[0]); |
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169 | memc->p_vci_ini (signal_vci_ini_c[nprocs]); |
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170 | memc->p_vci_tgt_cleanup (signal_vci_tgt_c[max_nprocs]); |
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171 | memc->p_vci_ixr (p_vci_ixr); |
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172 | |
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173 | for ( size_t p = 0 ; p < nprocs ; p++ ) { |
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174 | procs[p]->p_clk (p_clk); |
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175 | procs[p]->p_resetn (p_resetn); |
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176 | procs[p]->p_vci_ini_rw (signal_vci_ini_d[p]); |
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177 | procs[p]->p_vci_ini_c (signal_vci_ini_c[p]); |
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178 | procs[p]->p_vci_tgt (signal_vci_tgt_c[p]); |
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179 | procs[p]->p_irq[0] (signal_proc_irq[p]); |
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180 | |
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181 | for ( size_t j = 1 ; j < 6 ; j++ ) { |
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182 | procs[p]->p_irq[j] (signal_false); |
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183 | } |
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184 | } |
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185 | |
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186 | // XICU |
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187 | xicu->p_clk (p_clk); |
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188 | xicu->p_resetn (p_resetn); |
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189 | xicu->p_vci (signal_vci_tgt_d[1]); |
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190 | |
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191 | if(is_io == 1) { |
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192 | xicu->p_hwi[0] (signal_mtty_irq); |
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193 | |
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194 | mtty->p_clk (p_clk); |
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195 | mtty->p_resetn (p_resetn); |
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196 | mtty->p_vci (signal_vci_tgt_d[2]); |
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197 | mtty->p_irq[0] (signal_mtty_irq); |
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198 | } |
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199 | |
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200 | for ( size_t p = 0 ; p < nprocs ; p++ ) { |
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201 | xicu->p_irq[p] (signal_proc_irq[p]); |
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202 | } |
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203 | |
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204 | // Direct ring |
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205 | ringd->p_clk (p_clk); |
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206 | ringd->p_resetn (p_resetn); |
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207 | |
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208 | for ( size_t p = 0 ; p < nprocs ; p++ ) { |
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209 | ringd->p_to_initiator[p] (signal_vci_ini_d[p]); |
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210 | } |
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211 | |
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212 | for ( int t = 0 ; t < (2 + is_io) ; t++ ) { |
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213 | ringd->p_to_target[t] (signal_vci_tgt_d[t]); |
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214 | } |
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215 | |
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216 | // Coherence ring |
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217 | ringc->p_clk (p_clk); |
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218 | ringc->p_resetn (p_resetn); |
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219 | |
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220 | for ( size_t i = 0 ; i < (nprocs + 1) ; i++ ) { |
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221 | ringc->p_to_initiator[i] (signal_vci_ini_c[i]); |
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222 | } |
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223 | |
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224 | for ( size_t t = 0 ; t < (max_nprocs + 1) ; t++ ) { |
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225 | ringc->p_to_target[t] (signal_vci_tgt_c[t]); |
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226 | } |
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227 | } // End TsarClusterV1 |
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228 | |
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229 | template<typename vci_param, size_t cmd_width, size_t rsp_width> |
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230 | void TsarClusterV1<vci_param, cmd_width, rsp_width>::print_trace() { |
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231 | #ifdef DIRECT_TRACE |
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232 | ringd->print_trace(); |
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233 | #endif |
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234 | #ifdef COHERENCE_TRACE |
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235 | ringc->print_trace(); |
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236 | #endif |
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237 | } |
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238 | |
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239 | template<typename vci_param, size_t cmd_width, size_t rsp_width> |
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240 | TsarClusterV1<vci_param, cmd_width, rsp_width>::~TsarClusterV1() { |
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241 | for(size_t p=0; p < m_nprocs; p++) { |
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242 | delete procs[p]; |
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243 | } |
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244 | delete [] procs; |
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245 | delete ringd; |
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246 | delete ringc; |
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247 | delete memc; |
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248 | delete xicu; |
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249 | |
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250 | if(mtty) { |
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251 | delete mtty; |
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252 | dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_d, 3); |
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253 | } else { |
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254 | dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_d, 2); |
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255 | } |
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256 | |
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257 | dealloc_elems<VciSignals<vci_param> >(signal_vci_ini_d, m_nprocs); |
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258 | dealloc_elems<VciSignals<vci_param> >(signal_vci_ini_c, m_nprocs + 1); |
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259 | dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_c, m_nprocs + 1); |
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260 | delete [] signal_proc_irq; |
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261 | } |
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262 | } |
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263 | } |
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264 | |
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265 | // vim: tabstop=2 : shiftwidth=2 : expandtab |
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