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source: branches/v4/platforms/tsarv4_generic_ring/top.cpp @ 992

Last change on this file since 992 was 155, checked in by alain, 14 years ago
ntroducing the tsarv4_generic_ring platform
File size: 33.7 KB

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1	/////////////////////////////////////////////////////////////////////////
2	// File: tsarv4_generic_ring.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2011
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture without virtual memory,
9	// that can be supported by the GIET.
10	// - It uses vci_local_ring_fast as local interconnect
11	// - It uses the vci_cc_xcache_wrapper_v4
12	// - It uses the vci_mem_cache_v4
13	// - It uses the vci_xicu, with one vci_multi_tty, and one
14	// vci_multi_dma controlers per cluster.
15	// The physical address space is 32 bits.
16	// The number of clusters cannot be larger than 256.
17	// The number of processors per cluster cannot be larger than 4.
18	// The parameters mut be power of 2.
19	// - xmax : number of clusters in a row
20	// - ymax : number of clusters in a column
21	// - nprocs : number of processors per cluster
22	//
23	// The peripherals BDEV, FBUF, and the boot BROM
24	// are in the cluster containing address 0xBFC00000.
25	// - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3]
26	// - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7]
27	// - The IOC IRQ is connected to IRQ_IN[8]
28	//
29	// General policy for 32 bits address decoding in direct space:
30	// All segments base addresses are multiple of 64 Kbytes
31	// Therefore the 16 address MSB bits completely define the target:
32	// The (x_width + y_width) MSB bits (left aligned) define
33	// the cluster index, and the 8 LSB bits define the local index:
34	//
35	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
36	// \|x_width\|y_width\|---\| 8 \| 16 \|
37	//
38	// Half of all clusters being in the protected address space domain
39	// (addresses larger than 0x8000000), software must execute in
40	// kernel mode to access memory if we want to exploit locality,
41	// because some stacks and heaps will be in the protected domain.
42	/////////////////////////////////////////////////////////////////////////
43
44	#include <systemc>
45	#include <sys/time.h>
46	#include <iostream>
47	#include <sstream>
48	#include <cstdlib>
49	#include <cstdarg>
50	#include <stdint.h>
51
52	#include "gdbserver.h"
53	#include "mapping_table.h"
54	#include "tsarv4_cluster_ring.h"
55	#include "alloc_elems.h"
56
57	///////////////////////////////////////////////////
58	// Parallelisation
59	///////////////////////////////////////////////////
60
61	#define USE_OPENMP 0
62	#define OPENMP_THREADS_NR 8
63
64	#if USE_OPENMP
65	#include <omp.h>
66	#endif
67
68
69	// cluster index (computed from x,y coordinates)
70	#define cluster(x,y) (y + ymax*x)
71
72	// flit widths for the DSPIN network
73	#define cmd_width 40
74	#define rsp_width 33
75
76	// VCI format
77	#define cell_width 4
78	#define address_width 32
79	#define plen_width 8
80	#define error_width 2
81	#define clen_width 1
82	#define rflag_width 1
83	#define srcid_width 14
84	#define pktid_width 4
85	#define trdid_width 4
86	#define wrplen_width 1
87
88	///////////////////////////////////////////////////
89	// Parameters default values
90	///////////////////////////////////////////////////
91
92	#define MESH_XMAX 2
93	#define MESH_YMAX 2
94
95	#define NPROCS 4
96	#define XRAM_LATENCY 0
97
98	#define MEMC_WAYS 16
99	#define MEMC_SETS 256
100
101	#define L1_IWAYS 4
102	#define L1_ISETS 64
103
104	#define L1_DWAYS 4
105	#define L1_DSETS 64
106
107	#define FBUF_X_SIZE 128
108	#define FBUF_Y_SIZE 128
109
110	#define BDEV_SECTOR_SIZE 128
111	#define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw"
112
113	#define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft"
114
115	/////////////////////////////////////////////////////////
116	// Segments definition
117	/////////////////////////////////////////////////////////
118	// There is 5 segments replicated in all clusters:
119	// - seg_icu -> ICU / LADR = 0xF0
120	// - seg_tty -> MTTY / LADR = 0xF1
121	// - seg_dma -> CDMA / LADR = 0xF2
122	// - seg_stack -> RAM / LADR = 0x80 to 0x8F
123	// - seg_heap -> RAM / LADR = 0x30 to 0x7F
124	//
125	// There is 3 specific segments in the "IO" cluster
126	// (containing address 0xBF000000)
127	// - seg_reset -> BROM / LADR = 0xC0 to 0xCF
128	// - seg_fbuf -> FBUF / LADR = 0xD0 to OxEF
129	// - seg_bdev -> BDEV / LADR = 0xF3
130	//
131	// There is 3 specific segments in the "kcode" cluster
132	// (containing address 0x80000000)
133	// - seg_kcode -> RAM / LADR = 0x00 to 0x0F
134	// - seg_kdata -> RAM / LADR = 0x10 to 0x1F
135	// - seg_kunc -> RAM / LADR = 0x20 to 0x2F
136	//
137	// There is 2 specific segments in the "code" cluster
138	// (containing address 0x00000000)
139	// - seg_code -> RAM / LADR = 0x00 to Ox0F
140	// - seg_data -> RAM / LADR = 0x10 to 0x1F
141	//
142	// There is one special segment corresponding to
143	// the processors in the coherence address space
144	// - seg_proc -> PROCS / LADR = 0xB0 to 0xBF
145	///////////////////////////////////////////////////
146
147	// specific segments in "kcode" cluster
148
149	#define KCOD_BASE 0x80000000
150	#define KCOD_SIZE 0x00010000
151
152	#define KDAT_BASE 0x80100000
153	#define KDAT_SIZE 0x00010000
154
155	#define KUNC_BASE 0x80200000
156	#define KUNC_SIZE 0x00010000
157
158	// specific segments in "code" cluster
159
160	#define CODE_BASE 0x00000000
161	#define CODE_SIZE 0x00010000
162
163	#define DATA_BASE 0x00100000
164	#define DATA_SIZE 0x00010000
165
166	// specific segments in "IO" cluster
167
168	#define BROM_BASE 0xBFC00000
169	#define BROM_SIZE 0x00010000
170
171	#define FBUF_BASE 0xBFD00000
172	#define FBUF_SIZE 0x00200000
173
174	#define BDEV_BASE 0xBFF30000
175	#define BDEV_SIZE 0x00010000
176
177	// replicated segments
178
179	#define HEAP_BASE 0x00300000
180	#define HEAP_SIZE 0x00500000
181
182	#define STAK_BASE 0x00800000
183	#define STAK_SIZE 0x00100000
184
185	#define XICU_BASE 0x00F00000
186	#define XICU_SIZE 0x00010000
187
188	#define MTTY_BASE 0x00F10000
189	#define MTTY_SIZE 0x00010000
190
191	#define CDMA_BASE 0x00F20000
192	#define CDMA_SIZE 0x00000400
193
194	#define PROC_BASE 0x00B00000
195	#define PROC_SIZE 0x00000010
196
197	////////////////////////////////////////////////////////////////////
198	// TGTID definition in direct space
199	// For all components: global TGTID = global SRCID = cluster_index
200	////////////////////////////////////////////////////////////////////
201
202	#define MEMC_TGTID 0
203	#define XICU_TGTID 1
204	#define MTTY_TGTID 2
205	#define CDMA_TGTID 3
206	#define FBUF_TGTID 4
207	#define BROM_TGTID 5
208	#define BDEV_TGTID 6
209
210	///////////////////////////////////////
211	// service function for signal trace
212	///////////////////////////////////////
213
214	template <typename T>
215	void print_vci_signal(std::string name, T &sig)
216	{
217	if ( sig.cmdval )
218	{
219	std::cout << name << std::hex << " CMD : ";
220	if ( sig.cmd.read() == 1 ) std::cout << "READ ";
221	if ( sig.cmd.read() == 2 ) std::cout << "WRITE ";
222	if ( sig.cmd.read() == 3 ) std::cout << "LL ";
223	if ( sig.cmd.read() == 4 ) std::cout << "SC ";
224	std::cout << " address = " << sig.address
225	<< " \| wdata = " << sig.wdata
226	<< " \| srcid = " << sig.srcid
227	<< " \| trdid = " << sig.trdid
228	<< " \| eop = " << sig.eop << std::endl;
229	}
230	if ( sig.rspval )
231	std::cout << name << std::hex
232	<< " RSP : rerror = " << sig.rerror
233	<< " \| rdata = " << sig.rdata
234	<< " \| rsrcid = " << sig.rsrcid
235	<< " \| rtrdid = " << sig.rtrdid
236	<< " \| reop = " << sig.reop << std::endl;
237	}
238
239	/////////////////////////////////
240	int _main(int argc, char *argv[])
241	{
242	using namespace sc_core;
243	using namespace soclib::caba;
244	using namespace soclib::common;
245
246
247	char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code
248	size_t ncycles = 1000000000; // simulated cycles
249	size_t xmax = MESH_XMAX; // number of clusters in a row
250	size_t ymax = MESH_YMAX; // number of clusters in a column
251	size_t nprocs = NPROCS; // number of processors per cluster
252	size_t xfb = FBUF_X_SIZE; // frameBuffer column number
253	size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number
254	size_t memc_ways = MEMC_WAYS;
255	size_t memc_sets = MEMC_SETS;
256	size_t l1_d_ways = L1_DWAYS;
257	size_t l1_d_sets = L1_DSETS;
258	size_t l1_i_ways = L1_IWAYS;
259	size_t l1_i_sets = L1_ISETS;
260	char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
261	size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes)
262	size_t xram_latency = XRAM_LATENCY; // external RAM latency
263	bool trace_ok = false; // debug activated
264	size_t from_cycle = 0; // debug start cycle
265
266	////////////// command line arguments //////////////////////
267	if (argc > 1)
268	{
269	for( int n=1 ; n<argc ; n=n+2 )
270	{
271	if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
272	{
273	ncycles = atoi(argv[n+1]);
274	}
275	else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
276	{
277	nprocs = atoi(argv[n+1]);
278	assert( ((nprocs == 1) \|\| (nprocs == 2) \|\| (nprocs == 4)) &&
279	"NPROCS must be equal to 1, 2, or 4");
280	}
281	else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
282	{
283	xmax = atoi(argv[n+1]);
284	assert( ((xmax == 1) \|\| (xmax == 2) \|\| (xmax == 4) \|\| (xmax == 8) \|\| (xmax == 16))
285	&& "The XMAX parameter must be 2, 4, 8, or 16" );
286	}
287
288	else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
289	{
290	ymax = atoi(argv[n+1]);
291	assert( ((ymax == 1) \|\| (ymax == 2) \|\| (ymax == 4) \|\| (ymax == 8) \|\| (ymax == 16))
292	&& "The YMAX parameter must be 2, 4, 8, or 16" );
293	}
294	else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) )
295	{
296	xfb = atoi(argv[n+1]);
297	}
298	else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) )
299	{
300	yfb = atoi(argv[n+1]);
301	}
302	else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
303	{
304	strcpy(soft_name, argv[n+1]);
305	}
306	else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
307	{
308	strcpy(disk_name, argv[n+1]);
309	}
310	else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
311	{
312	trace_ok = true;
313	from_cycle = atoi(argv[n+1]);
314	}
315	else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc))
316	{
317	memc_ways = atoi(argv[n+1]);
318	}
319	else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc))
320	{
321	memc_sets = atoi(argv[n+1]);
322	}
323	else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc))
324	{
325	xram_latency = atoi(argv[n+1]);
326	}
327	else
328	{
329	std::cout << " Arguments on the command line are (key,value) couples." << std::endl;
330	std::cout << " The order is not important." << std::endl;
331	std::cout << " Accepted arguments are :" << std::endl << std::endl;
332	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
333	std::cout << " -DISK pathname_for_disk_image" << std::endl;
334	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
335	std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl;
336	std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl;
337	std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl;
338	std::cout << " -TRACE debug_start_cycle" << std::endl;
339	std::cout << " -MCWAYS memory_cache_number_of_ways" << std::endl;
340	std::cout << " -MCSETS memory_cache_number_of_sets" << std::endl;
341	std::cout << " -XLATENCY external_ram_latency_value" << std::endl;
342	std::cout << " -XFB fram_buffer_number_of_pixels" << std::endl;
343	std::cout << " -YFB fram_buffer_number_of_lines" << std::endl;
344	exit(0);
345	}
346	}
347	}
348
349	std::cout << std::endl;
350	std::cout << " - NB_CLUSTERS = " << std::dec << xmax*ymax <<std::endl;
351	std::cout << " - NB_PROCS = " << std::dec << nprocs <<std::endl;
352	std::cout << " - SOFT = " << soft_name << std::endl;
353	std::cout << std::endl;
354
355	#if USE_OPENMP
356	omp_set_dynamic(false);
357	omp_set_num_threads(threads_nr);
358	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
359	#endif
360
361	// Define VCI parameters
362	typedef soclib::caba::VciParams<cell_width,
363	plen_width,
364	address_width,
365	error_width,
366	clen_width,
367	rflag_width,
368	srcid_width,
369	pktid_width,
370	trdid_width,
371	wrplen_width> vci_param;
372
373	size_t cluster_io_index;
374	size_t cluster_code_index;
375	size_t cluster_kcode_index;
376	size_t x_width;
377	size_t y_width;
378
379	if (xmax == 1) x_width = 0;
380	else if (xmax == 2) x_width = 1;
381	else if (xmax <= 4) x_width = 2;
382	else if (xmax <= 8) x_width = 3;
383	else x_width = 4;
384
385	if (ymax == 1) y_width = 0;
386	else if (ymax == 2) y_width = 1;
387	else if (ymax <= 4) y_width = 2;
388	else if (ymax <= 8) y_width = 3;
389	else y_width = 4;
390
391	cluster_io_index = 0xBF >> (8 - x_width - y_width);
392	cluster_kcode_index = 0x80 >> (8 - x_width - y_width);
393	cluster_code_index = 0;
394
395	/////////////////////
396	// Mapping Tables
397	/////////////////////
398
399	// direct network
400	MappingTable maptabd(address_width,
401	IntTab(x_width + y_width, 16 - x_width - y_width),
402	IntTab(x_width + y_width, srcid_width - x_width - y_width),
403	0x00FF0000);
404
405	for ( size_t x = 0 ; x < xmax ; x++)
406	{
407	for ( size_t y = 0 ; y < ymax ; y++)
408	{
409	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
410
411	std::ostringstream sh;
412	sh << "d_seg_heap_" << x << "_" << y;
413	maptabd.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
414
415	std::ostringstream ss;
416	ss << "d_seg_stak_" << x << "_" << y;
417	maptabd.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
418
419	std::ostringstream si;
420	si << "d_seg_xicu_" << x << "_" << y;
421	maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
422
423	std::ostringstream st;
424	st << "d_seg_mtty_" << x << "_" << y;
425	maptabd.add(Segment(st.str(), MTTY_BASE+offset, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
426
427	std::ostringstream sd;
428	sd << "d_seg_cdma_" << x << "_" << y;
429	maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
430
431	if ( cluster(x,y) == cluster_io_index )
432	{
433	maptabd.add(Segment("d_seg_fbuf ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
434	maptabd.add(Segment("d_seg_bdev ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
435	maptabd.add(Segment("d_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
436	}
437	if ( cluster(x,y) == cluster_code_index )
438	{
439	maptabd.add(Segment("d_seg_code ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
440	maptabd.add(Segment("d_seg_data ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
441	}
442	if ( cluster(x,y) == cluster_kcode_index )
443	{
444	maptabd.add(Segment("d_seg_kcod ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
445	maptabd.add(Segment("d_seg_kdat ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
446	maptabd.add(Segment("d_seg_kunc ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
447	}
448	}
449	}
450	std::cout << maptabd << std::endl;
451
452	// coherence network
453	// - tgtid_c_proc = srcid_c_proc = local procid
454	// - tgtid_c_memc = srcid_c_memc = nprocs
455	MappingTable maptabc(address_width,
456	IntTab(x_width + y_width, 16 - x_width - y_width),
457	IntTab(x_width + y_width, srcid_width - x_width - y_width),
458	0x00FF0000);
459
460	for ( size_t x = 0 ; x < xmax ; x++)
461	{
462	for ( size_t y = 0 ; y < ymax ; y++)
463	{
464	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
465
466	// cleanup requests regarding the heap segment must be routed to the memory cache
467	std::ostringstream sh;
468	sh << "c_seg_heap_" << x << "_" << y;
469	maptabc.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y), nprocs), false));
470
471	// cleanup requests regarding the stack segmentmust be routed to the memory cache
472	std::ostringstream ss;
473	ss << "c_seg_stak_" << x << "_" << y;
474	maptabc.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y), nprocs), false));
475
476	// cleanup requests regarding the BROM segment are also be routed to the memory cache
477	if ( cluster(x,y) == cluster_io_index )
478	{
479	maptabc.add(Segment("c_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
480	}
481
482	// cleanup requests regarding the code and data segment musts be send to the memory cache
483	if ( cluster(x,y) == cluster_code_index )
484	{
485	maptabc.add(Segment("c_seg_code ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y), nprocs), false));
486	maptabc.add(Segment("c_seg_data ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y), nprocs), false));
487	}
488	// cleanup requests regarding the kcode, kunc, and kdata segments must be send to the memory cache
489	if ( cluster(x,y) == cluster_kcode_index )
490	{
491	maptabc.add(Segment("c_seg_kcod ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y), nprocs), false));
492	maptabc.add(Segment("c_seg_kdat ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y), nprocs), false));
493	maptabc.add(Segment("c_seg_kunc ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y), nprocs), false));
494	}
495
496	// update & invalidate requests must be routed to the proper processor
497	for ( size_t p = 0 ; p < nprocs ; p++)
498	{
499	std::ostringstream sp;
500	sp << "c_seg_proc_" << x << "_" << y << "_" << p;
501	maptabc.add(Segment(sp.str(), PROC_BASE+offset+(p*0x10000), PROC_SIZE,
502	IntTab(cluster(x,y), p), false, true, IntTab(cluster(x,y), p)));
503	}
504	}
505	}
506	std::cout << maptabc << std::endl;
507
508	// external network
509	MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
510
511	for ( size_t x = 0 ; x < xmax ; x++)
512	{
513	for ( size_t y = 0 ; y < ymax ; y++)
514	{
515
516	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
517
518	std::ostringstream sh;
519	sh << "x_seg_heap_" << x << "_" << y;
520	maptabx.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y)), false));
521
522	std::ostringstream ss;
523	ss << "x_seg_stak_" << x << "_" << y;
524	maptabx.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y)), false));
525
526	if ( cluster(x,y) == cluster_code_index )
527	{
528	maptabx.add(Segment("x_seg_code ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y)), false));
529	maptabx.add(Segment("x_seg_data ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y)), false));
530	}
531	if ( cluster(x,y) == cluster_kcode_index )
532	{
533	maptabx.add(Segment("x_seg_kcod ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y)), false));
534	maptabx.add(Segment("x_seg_kdat ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y)), false));
535	maptabx.add(Segment("x_seg_kunc ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y)), false));
536	}
537	}
538	}
539	std::cout << maptabx << std::endl;
540
541	////////////////////
542	// Signals
543	///////////////////
544
545	sc_clock signal_clk("clk");
546	sc_signal<bool> signal_resetn("resetn");
547
548	// Horizontal inter-clusters DSPIN signals
549	DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
550	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);
551	DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
552	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);
553	DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
554	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);
555	DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
556	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);
557
558	// Vertical inter-clusters DSPIN signals
559	DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
560	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
561	DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
562	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
563	DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
564	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
565	DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
566	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
567
568	// Mesh boundaries DSPIN signals
569	DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
570	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4);
571	DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
572	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);
573	DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
574	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);
575	DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
576	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);
577
578
579	////////////////////////////
580	// Components
581	////////////////////////////
582
583	#if USE_ALMOS
584	soclib::common::Loader loader("bootloader.bin",
585	"arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D",
586	"kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D");
587	#else
588	soclib::common::Loader loader(soft_name);
589	#endif
590
591	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
592	proc_iss::set_loader(loader);
593
594	TsarV4ClusterRing<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax];
595
596	#if USE_OPENMP
597
598	#pragma omp parallel
599	{
600	#pragma omp for
601	for( size_t i = 0 ; i < (xmax * ymax); i++)
602	{
603	size_t x = i / ymax;
604	size_t y = i % ymax;
605
606	#pragma omp critical
607	std::ostringstream sc;
608	sc << "cluster_" << x << "_" << y;
609	clusters[x][y] = new TsarV4ClusterRing<vci_param, proc_iss, cmd_width, rsp_width>
610	(sc.str().c_str(),
611	nprocs,
612	x,
613	y,
614	cluster(x,y),
615	maptabd,
616	maptabc,
617	maptabx,
618	x_width,
619	y_width,
620	MEMC_TGTID,
621	XICU_TGTID,
622	FBUF_TGTID,
623	MTTY_TGTID,
624	BROM_TGTID,
625	BDEV_TGTID,
626	CDMA_TGTID,
627	memc_ways,
628	memc_sets,
629	l1_i_ways,
630	l1_i_sets,
631	l1_d_ways,
632	l1_d_sets,
633	xram_latency,
634	(cluster(x,y) == cluster_io_index),
635	xfb,
636	yfb,
637	disk_name,
638	blk_size,
639	loader);
640	}
641
642	#else // USE_OPENMP
643
644	for( size_t x = 0 ; x < xmax ; x++)
645	{
646	for( size_t y = 0 ; y < ymax ; y++ )
647	{
648
649	std::cout << "building cluster_" << x << "_" << y << std::endl;
650
651	std::ostringstream sc;
652	sc << "cluster_" << x << "_" << y;
653	clusters[x][y] = new TsarV4ClusterRing<vci_param, proc_iss, cmd_width, rsp_width>
654	(sc.str().c_str(),
655	nprocs,
656	x,
657	y,
658	cluster(x,y),
659	maptabd,
660	maptabc,
661	maptabx,
662	x_width,
663	y_width,
664	MEMC_TGTID,
665	XICU_TGTID,
666	FBUF_TGTID,
667	MTTY_TGTID,
668	BROM_TGTID,
669	BDEV_TGTID,
670	CDMA_TGTID,
671	memc_ways,
672	memc_sets,
673	l1_i_ways,
674	l1_i_sets,
675	l1_d_ways,
676	l1_d_sets,
677	xram_latency,
678	(cluster(x,y) == cluster_io_index),
679	xfb,
680	yfb,
681	disk_name,
682	blk_size,
683	loader);
684
685	std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
686
687	}
688	}
689
690	#endif // USE_OPENMP
691
692	///////////////////////////////////////////////////////////////
693	// Net-list
694	///////////////////////////////////////////////////////////////
695
696	// Clock & RESET
697	for ( size_t x = 0 ; x < (xmax) ; x++ )
698	{
699	for ( size_t y = 0 ; y < ymax ; y++ )
700	{
701	clusters[x][y]->p_clk (signal_clk);
702	clusters[x][y]->p_resetn (signal_resetn);
703	}
704	}
705
706	// Inter Clusters horizontal connections
707	if ( xmax > 1 )
708	{
709	for ( size_t x = 0 ; x < (xmax-1) ; x++ )
710	{
711	for ( size_t y = 0 ; y < ymax ; y++ )
712	{
713	for ( size_t k = 0 ; k < 2 ; k++ )
714	{
715	clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]);
716	clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]);
717	clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]);
718	clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]);
719	clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]);
720	clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]);
721	clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]);
722	clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]);
723	}
724	}
725	}
726	}
727	std::cout << "Horizontal connections established" << std::endl;
728
729	// Inter Clusters vertical connections
730	if ( ymax > 1 )
731	{
732	for ( size_t y = 0 ; y < (ymax-1) ; y++ )
733	{
734	for ( size_t x = 0 ; x < xmax ; x++ )
735	{
736	for ( size_t k = 0 ; k < 2 ; k++ )
737	{
738	clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]);
739	clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]);
740	clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]);
741	clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]);
742	clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]);
743	clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]);
744	clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]);
745	clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]);
746	}
747	}
748	}
749	}
750	std::cout << "Vertical connections established" << std::endl;
751
752	// East & West boundary cluster connections
753	for ( size_t y = 0 ; y < ymax ; y++ )
754	{
755	for ( size_t k = 0 ; k < 2 ; k++ )
756	{
757	clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);
758	clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);
759	clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);
760	clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);
761
762	clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);
763	clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);
764	clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);
765	clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);
766	}
767	}
768
769	// North & South boundary clusters connections
770	for ( size_t x = 0 ; x < xmax ; x++ )
771	{
772	for ( size_t k = 0 ; k < 2 ; k++ )
773	{
774	clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
775	clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
776	clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
777	clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
778
779	clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);
780	clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);
781	clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);
782	clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);
783	}
784	}
785
786
787	////////////////////////////////////////////////////////
788	// Simulation
789	///////////////////////////////////////////////////////
790
791	sc_start(sc_core::sc_time(0, SC_NS));
792	signal_resetn = false;
793
794	// network boundaries signals
795	for(size_t x=0; x<xmax ; x++)
796	{
797	for(size_t y=0 ; y<ymax ; y++)
798	{
799	for (size_t k=0; k<2; k++)
800	{
801	for(size_t a=0; a<4; a++)
802	{
803	signal_dspin_false_cmd_in[x][y][k][a].write = false;
804	signal_dspin_false_cmd_in[x][y][k][a].read = true;
805	signal_dspin_false_cmd_out[x][y][k][a].write = false;
806	signal_dspin_false_cmd_out[x][y][k][a].read = true;
807
808	signal_dspin_false_rsp_in[x][y][k][a].write = false;
809	signal_dspin_false_rsp_in[x][y][k][a].read = true;
810	signal_dspin_false_rsp_out[x][y][k][a].write = false;
811	signal_dspin_false_rsp_out[x][y][k][a].read = true;
812	}
813	}
814	}
815	}
816
817	sc_start(sc_core::sc_time(1, SC_NS));
818	signal_resetn = true;
819
820	for ( size_t n=0 ; n<ncycles ; n++)
821	{
822	sc_start(sc_core::sc_time(1, SC_NS));
823	if ( trace_ok && (n > from_cycle) )
824	{
825	std::cout << "****************** cycle " << std::dec << n ;
826	std::cout << " ***********************************" << std::endl;
827
828	clusters[0][0]->proc[0]->print_trace();
829	clusters[0][0]->bdev->print_trace();
830	std::cout << std::endl;
831	print_vci_signal("proc_0_0_0_ini_d", clusters[0][0]->signal_vci_ini_d_proc[0]);
832	print_vci_signal("bdev_tgt", clusters[0][0]->signal_vci_tgt_d_bdev);
833	print_vci_signal("bdev_ini", clusters[0][0]->signal_vci_ini_d_bdev);
834	print_vci_signal("memc_0_0_tgt_d", clusters[0][0]->signal_vci_tgt_d_memc);
835	if ( clusters[0][0]->signal_irq_bdev.read() != 0) std::cout << " IRQ_BDEV" << std::endl;
836	if ( clusters[0][0]->signal_proc_it[0].read() != 0) std::cout << " IRQ_PROC" << std::endl;
837
838	/*
839	clusters[0][0]->memc->print_trace();
840
841
842	print_vci_signal("memc_0_0_ini_c", clusters[0][0]->signal_vci_ini_c_memc);
843
844	print_vci_signal("proc_0_0_0_tgt_c", clusters[0][0]->signal_vci_tgt_c_proc[0]);
845	print_vci_signal("proc_0_0_1_tgt_c", clusters[0][0]->signal_vci_tgt_c_proc[1]);
846	print_vci_signal("proc_1_0_0_tgt_c", clusters[1][0]->signal_vci_tgt_c_proc[0]);
847	print_vci_signal("proc_1_0_1_tgt_c", clusters[1][0]->signal_vci_tgt_c_proc[1]);
848
849	print_vci_signal("memc_0_0_tgt_c", clusters[0][0]->signal_vci_tgt_c_memc);
850
851	print_vci_signal("proc_0_0_0_ini_d", clusters[0][0]->signal_vci_ini_d_proc[0]);
852	print_vci_signal("proc_0_0_1_ini_d", clusters[0][0]->signal_vci_ini_d_proc[1]);
853	print_vci_signal("proc_1_0_0_ini_d", clusters[1][0]->signal_vci_ini_d_proc[0]);
854	print_vci_signal("proc_1_0_1_ini_d", clusters[1][0]->signal_vci_ini_d_proc[1]);
855	print_vci_signal("memc_1_0_tgt_d", clusters[1][0]->signal_vci_tgt_d_memc);
856	print_vci_signal("bdev_tgt", clusters[1][0]->signal_vci_tgt_d_bdev);
857	print_vci_signal("bdev_ini", clusters[1][0]->signal_vci_ini_d_bdev);
858
859	if ( clusters[0][0]->signal_irq_mdma[0].read() != 0) std::cout << " IRQ_DMA_0_0" << std::endl;
860	if ( clusters[0][0]->signal_irq_mdma[1].read() != 0) std::cout << " IRQ_DMA_0_1" << std::endl;
861	if ( clusters[1][0]->signal_irq_mdma[0].read() != 0) std::cout << " IRQ_DMA_1_0" << std::endl;
862	if ( clusters[1][0]->signal_irq_mdma[1].read() != 0) std::cout << " IRQ_DMA_1_1" << std::endl;
863	*/
864	}
865	}
866	return EXIT_SUCCESS;
867	}
868
869	int sc_main (int argc, char *argv[])
870	{
871	try {
872	return _main(argc, argv);
873	} catch (std::exception &e) {
874	std::cout << e.what() << std::endl;
875	} catch (...) {
876	std::cout << "Unknown exception occured" << std::endl;
877	throw;
878	}
879	return 1;
880	}

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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