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top.cpp @ 546

Last change on this file since 546 was 247, checked in by cfuguet, 13 years ago

Introducing new CLEANUP transaction address specification in the components:

vci_cc_vcache_wrapper_v4
vci_mem_cache_v4

The new specification uses the VCI WDATA and the VCI BE to send the cleanup
nline. The VCI ADDRESS is like follows:

NLINE MSb | Memory Cache local ID | 00....00

The platforms:

tsarv4_mono_mmu
tsarv4_generic_mmu

has been modified to use the modified components and the mapping table for the coherence
address space has been updated.

Property svn:executable set to *

File size: 11.9 KB

Line
1
2	#include <systemc>
3	#include <sys/time.h>
4	#include <iostream>
5	#include <cstdlib>
6	#include <cstdarg>
7
8	#ifdef _OPENMP
9	#include <omp.h>
10	#endif
11
12	#include "mapping_table.h"
13	#include "mips32.h"
14	#include "vci_simple_ram.h"
15	#include "vci_multi_tty.h"
16	#include "vci_vgmn.h"
17	#include "vci_mem_cache_v4.h"
18	#include "vci_cc_vcache_wrapper_v4.h"
19	#include "vci_xicu.h"
20	#include "vci_simhelper.h"
21	#include "vci_multi_dma.h"
22
23	// VCI format
24
25	#define cell_width 4
26	#define address_width 32
27	#define plen_width 8
28	#define error_width 2
29	#define clen_width 1
30	#define rflag_width 1
31	#define srcid_width 14
32	#define pktid_width 4
33	#define trdid_width 4
34	#define wrplen_width 1
35
36	// segments definition in direct space
37
38	#define XICU_BASE 0xd8200000
39	#define XICU_SIZE 0x00001000
40
41	#define MDMA_BASE 0xe8000000
42	#define MDMA_SIZE 0x00000014
43
44	#define MTTY_BASE 0xd0200000
45	#define MTTY_SIZE 0x00000010
46
47	#define EXIT_BASE 0xe0000000
48	#define EXIT_SIZE 0x00000010
49
50	#define BOOT_BASE 0xbfc00000
51	#define BOOT_SIZE 0x00040000
52
53	#define MEMC_BASE 0x00000000
54	#define MEMC_SIZE 0x02000000
55
56	/////////////////////////////////
57	int _main(int argc, char *argv[])
58	{
59
60	using namespace sc_core;
61	using namespace soclib::common;
62	using namespace soclib::caba;
63
64	#ifdef _OPENMP
65	omp_set_dynamic(false);
66	omp_set_num_threads(1);
67	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
68	#endif
69
70	char soft_name[256] = "test.elf"; // pathname to binary code
71	size_t ncycles = 1000000000; // max number of simulation cycles
72	bool trace_ok = false;
73	size_t from_cycle = 0; // debug start cycle
74	size_t max_frozen = 1000; // max number of frozen cycles
75	size_t nprocs = 1;
76
77	/////////////// command line arguments ////////////////
78	if (argc > 1)
79	{
80	for( int n=1 ; n<argc ; n=n+2 )
81	{
82	if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
83	{
84	ncycles = atoi(argv[n+1]);
85	}
86	else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
87	{
88	strcpy(soft_name, argv[n+1]);
89	}
90	else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
91	{
92	trace_ok = true;
93	from_cycle = atoi(argv[n+1]);
94	}
95	else if( (strcmp(argv[n],"-MAXFROZEN") == 0) && (n+1<argc) )
96	{
97	max_frozen = atoi(argv[n+1]);
98	}
99	else
100	{
101	std::cout << " Arguments on the command line are (key,value) couples." << std::endl;
102	std::cout << " The order is not important." << std::endl;
103	std::cout << " Accepted arguments are :" << std::endl << std::endl;
104	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
105	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
106	std::cout << " -TRACE debug_start_cycle" << std::endl;
107	exit(0);
108	}
109	}
110	}
111
112	// Define VCI parameters
113	typedef VciParams<cell_width,
114	plen_width,
115	address_width,
116	error_width,
117	clen_width,
118	rflag_width,
119	srcid_width,
120	pktid_width,
121	trdid_width,
122	wrplen_width> vci_param;
123
124	// Define processor type
125	typedef soclib::common::Mips32ElIss proc_iss;
126
127	// Mapping table for direct network
128	soclib::common::MappingTable maptabd(32, IntTab(6), IntTab(6), 0xF0000000);
129	maptabd.add(Segment("memc_d" , MEMC_BASE , MEMC_SIZE , IntTab(0), true));
130	maptabd.add(Segment("boot_d" , BOOT_BASE , BOOT_SIZE , IntTab(1), true));
131	maptabd.add(Segment("exit_d" , EXIT_BASE , EXIT_SIZE , IntTab(2), false));
132	maptabd.add(Segment("mtty_d" , MTTY_BASE , MTTY_SIZE , IntTab(3), false));
133	maptabd.add(Segment("xicu_d" , XICU_BASE , XICU_SIZE , IntTab(4), false));
134	maptabd.add(Segment("mdma_d" , MDMA_BASE , MDMA_SIZE , IntTab(5), false));
135	std::cout << maptabd << std::endl;
136
137	// Mapping table for coherence network
138	soclib::common::MappingTable maptabc(32, IntTab(srcid_width), IntTab(srcid_width), 0xF0000000);
139	maptabc.add(
140	Segment( "proc_c"
141	, 0x0000000
142	, 0x10
143	, IntTab(0)
144	, false
145	)
146	);
147
148	maptabc.add(
149	Segment( "memc_c"
150	, nprocs << (address_width - srcid_width)
151	, 0x10
152	, IntTab(nprocs)
153	, false
154	)
155	);
156	std::cout << maptabc << std::endl;
157
158	// Signals
159
160	sc_clock signal_clk ("signal_clk");
161	sc_signal<bool> signal_resetn ("isgnal_resetn");
162
163	sc_signal<bool> signal_mdma_irq ("signal_mdma_irq");
164	sc_signal<bool> signal_mtty_irq ("signal_mtty_irq");
165	sc_signal<bool> signal_proc_irq ("signal_proc_irq");
166	sc_signal<bool> signal_false ("signal_false");
167
168	VciSignals<vci_param> signal_vci_ini_d_proc ("vci_ini_d_proc");
169	VciSignals<vci_param> signal_vci_ini_c_proc ("vci_ini_c_proc");
170	VciSignals<vci_param> signal_vci_tgt_c_proc ("vci_tgt_c_proc");
171
172	VciSignals<vci_param> signal_vci_tgt_d_mtty ("signal_vci_tgt_d_mtty");
173
174	VciSignals<vci_param> signal_vci_tgt_d_exit ("signal_vci_tgt_d_exit");
175
176	VciSignals<vci_param> signal_vci_tgt_d_xicu ("signal_vci_tgt_d_xicu");
177
178	VciSignals<vci_param> signal_vci_ini_d_mdma ("signal_vci_ini_d_mdma");
179	VciSignals<vci_param> signal_vci_tgt_d_mdma ("signal_vci_tgt_d_mdma");
180
181	VciSignals<vci_param> signal_vci_tgt_d_brom ("signal_vci_tgt_d_brom");
182
183
184	VciSignals<vci_param> signal_vci_ini_c_memc ("signal_vci_ini_c_memc");
185	VciSignals<vci_param> signal_vci_tgt_d_memc ("signal_vci_tgt_d_memc");
186	VciSignals<vci_param> signal_vci_tgt_c_memc ("signal_vci_tgt_c_memc");
187
188	VciSignals<vci_param> signal_vci_xram ("signal_vci_xram");
189
190	// Components
191
192	soclib::common::Loader loader(soft_name);
193
194	VciCcVCacheWrapperV4<vci_param, proc_iss >
195	proc("proc",
196	0, // proc_id
197	maptabd, // direct space
198	maptabc, // coherence space
199	IntTab(0), // srcid_d
200	IntTab(0), // srcid_c
201	IntTab(0), // tgtid_c
202	8,8, // itlb size
203	8,8, // dtlb size
204	4,64,16, // icache size
205	4,64,16, // dcache size
206	4, 4, // wbuf size
207	0, 0, // x, y Width
208	nprocs, // memory cache local id
209	max_frozen, // max frozen cycles
210	from_cycle, trace_ok);
211
212	VciSimpleRam<vci_param>
213	rom("rom",
214	IntTab(1), // tgtid_d
215	maptabd,
216	loader);
217
218	VciSimpleRam<vci_param>
219	xram("xram",
220	IntTab(0), // tgtid_d(RAM) = tgtid_d(MEMC)
221	maptabd,
222	loader);
223
224	VciMemCacheV4<vci_param>
225	memc("memc",
226	maptabd,
227	maptabc,
228	maptabd,
229	IntTab(0), // srcid_x
230	IntTab(1), // srcid_c
231	IntTab(0), // tgtid_d
232	IntTab(1), // tgtid_c
233	16,256,16, // cache size
234	1024, // HEAP size
235	4, // TRT size
236	4, // UPT size
237	from_cycle, trace_ok);
238
239	VciSimhelper<vci_param>
240	vciexit("vciexit",
241	IntTab(2), // tgtid_d
242	maptabd);
243
244	VciXicu<vci_param>
245	xicu("xicu",
246	maptabd,
247	IntTab(4), // tgtid_d
248	1, // number of timers
249	2, // number of hard interrupts
250	0, // number of soft interrupts
251	1); // number of output IRQs
252
253	VciMultiTty<vci_param>
254	mtty("mtty",
255	IntTab(3), // tgtid_d
256	maptabd,
257	"mtty0", NULL);
258
259	VciMultiDma<vci_param>
260	mdma("mdma",
261	maptabd,
262	IntTab(1), // srcid_d
263	IntTab(5), // tgtid_d
264	64, // burst size
265	1); // number of channels
266
267	VciVgmn<vci_param>
268	ringd("ringd",
269	maptabd,
270	2, // number of initiators
271	6, // number of targets
272	2,
273	8);
274
275	VciVgmn<vci_param>
276	ringc("ringc",
277	maptabc,
278	2, // number of initiators
279	2, // number of targets
280	2,
281	8);
282
283	// net-list
284	proc.p_clk(signal_clk);
285	proc.p_resetn (signal_resetn);
286	proc.p_irq[0] (signal_proc_irq);
287	proc.p_irq[1] (signal_false);
288	proc.p_irq[2] (signal_false);
289	proc.p_irq[3] (signal_false);
290	proc.p_irq[4] (signal_false);
291	proc.p_irq[5] (signal_false);
292	proc.p_vci_ini_d (signal_vci_ini_d_proc);
293	proc.p_vci_ini_c (signal_vci_ini_c_proc);
294	proc.p_vci_tgt_c (signal_vci_tgt_c_proc);
295
296	rom.p_clk (signal_clk);
297	rom.p_resetn (signal_resetn);
298	rom.p_vci (signal_vci_tgt_d_brom);
299
300	xicu.p_resetn (signal_resetn);
301	xicu.p_clk (signal_clk);
302	xicu.p_vci (signal_vci_tgt_d_xicu);
303	xicu.p_hwi[0] (signal_mtty_irq);
304	xicu.p_hwi[1] (signal_mdma_irq);
305	xicu.p_irq[0] (signal_proc_irq);
306
307	mdma.p_clk (signal_clk);
308	mdma.p_resetn (signal_resetn);
309	mdma.p_vci_target (signal_vci_tgt_d_mdma);
310	mdma.p_vci_initiator (signal_vci_ini_d_mdma);
311	mdma.p_irq[0] (signal_mdma_irq);
312
313	mtty.p_clk (signal_clk);
314	mtty.p_resetn (signal_resetn);
315	mtty.p_vci (signal_vci_tgt_d_mtty);
316	mtty.p_irq[0] (signal_mtty_irq);
317
318	vciexit.p_clk (signal_clk);
319	vciexit.p_resetn (signal_resetn);
320	vciexit.p_vci (signal_vci_tgt_d_exit);
321
322	memc.p_clk (signal_clk);
323	memc.p_resetn (signal_resetn);
324	memc.p_vci_tgt (signal_vci_tgt_d_memc);
325	memc.p_vci_tgt_cleanup (signal_vci_tgt_c_memc);
326	memc.p_vci_ini (signal_vci_ini_c_memc);
327	memc.p_vci_ixr (signal_vci_xram);
328
329	xram.p_clk (signal_clk);
330	xram.p_resetn (signal_resetn);
331	xram.p_vci (signal_vci_xram);
332
333	ringc.p_clk (signal_clk);
334	ringc.p_resetn (signal_resetn);
335	ringc.p_to_initiator[0] (signal_vci_ini_c_proc);
336	ringc.p_to_initiator[1] (signal_vci_ini_c_memc);
337	ringc.p_to_target[0] (signal_vci_tgt_c_proc);
338	ringc.p_to_target[1] (signal_vci_tgt_c_memc);
339
340	ringd.p_clk (signal_clk);
341	ringd.p_resetn (signal_resetn);
342	ringd.p_to_initiator[0] (signal_vci_ini_d_proc);
343	ringd.p_to_initiator[1] (signal_vci_ini_d_mdma);
344	ringd.p_to_target[0] (signal_vci_tgt_d_memc);
345	ringd.p_to_target[1] (signal_vci_tgt_d_brom);
346	ringd.p_to_target[2] (signal_vci_tgt_d_exit);
347	ringd.p_to_target[3] (signal_vci_tgt_d_mtty);
348	ringd.p_to_target[4] (signal_vci_tgt_d_xicu);
349	ringd.p_to_target[5] (signal_vci_tgt_d_mdma);
350
351	// simulation loop
352
353	sc_start(sc_core::sc_time(0, SC_NS));
354	signal_resetn = false;
355
356	sc_start(sc_core::sc_time(1, SC_NS));
357	signal_resetn = true;
358
359	signal_false = false;
360
361	for ( size_t n=1 ; n<ncycles ; n++ )
362	{
363	if ( trace_ok and (n > from_cycle) )
364	{
365	std::cout << "****************** cycle " << std::dec << n
366	<< " ************************************************" << std::endl;
367	proc.print_trace();
368	memc.print_trace();
369	signal_vci_ini_d_proc.print_trace("proc_ini_d");
370	signal_vci_tgt_c_proc.print_trace("proc_tgt_c");
371	signal_vci_ini_c_proc.print_trace("proc_ini_c");
372	signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
373	signal_vci_tgt_c_memc.print_trace("memc_tgt_c");
374	signal_vci_ini_c_memc.print_trace("memc_ini_c");
375	if ( signal_proc_irq.read() ) std::cout << "---- IRQ ----" << std::endl;
376	}
377	sc_start(sc_core::sc_time(1, SC_NS));
378	}
379	return EXIT_SUCCESS;
380	}
381
382	int sc_main (int argc, char *argv[])
383	{
384	try {
385	return _main(argc, argv);
386	} catch (std::exception &e) {
387	std::cout << e.what() << std::endl;
388	} catch (...) {
389	std::cout << "Unknown exception occured" << std::endl;
390	throw;
391	}
392	return 1;
393	}

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