# -*- python -*-

__id__ = "$Id: dspin_simple_ring_fast.sd 1141 2009-06-04 14:02:48Z abdelmalek.si-merabet@lip6.fr $"
__version__ = "$Revision: 1141 $"

Module('caba:dspin_simple_ring_fast_c',
	classname = 'soclib::caba::DspinSimpleRingFastC',
	tmpl_parameters = [
                parameter.Module('vci_param', default = 'caba:vci_param'),
                parameter.Int('ring_cmd_data_size'),
                parameter.Int('ring_rsp_data_size'),	    
	],
	header_files = ['../source/include/dspin_simple_ring_fast_c.h',
                        '../source/include/dspin_simple_ring_initiator_fast_c.h',
                        '../source/include/dspin_simple_ring_target_fast_c.h',
        ],
	implementation_files = ['../source/src/dspin_simple_ring_fast_c.cpp',],
	ports = [
            Port('caba:dspin_output', 'p_cmd_out', dspin_data_size = parameter.Reference('ring_cmd_data_size')),
            Port('caba:dspin_input',  'p_rsp_in',  dspin_data_size = parameter.Reference('ring_rsp_data_size')),
            Port('caba:dspin_input',  'p_cmd_in',  dspin_data_size = parameter.Reference('ring_cmd_data_size')),
            Port('caba:dspin_output', 'p_rsp_out', dspin_data_size = parameter.Reference('ring_rsp_data_size')),
	    # FIXME: Ports vci
	    Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
	    Port('caba:clock_in', 'p_clk', auto = 'clock'),
	],
	instance_parameters = [
		parameter.Module('mt', 'common:mapping_table'),
	        parameter.IntTab('ringid'),
                parameter.Int('wrapper_fifo_depth'),
                parameter.Int('nb_attached_initiator'),
                parameter.Int('nb_attached_target'),
                parameter.Int('x_width'),
                parameter.Int('y_width'),
	],
	uses = [
	    Uses('caba:base_module'),
	    Uses('common:mapping_table'),
	    Uses('caba:ring_signals_fast'),
	    Uses('caba:generic_fifo'),
	],
	   extensions = [
	'dsx:interconnect=root',
	'dsx:mapping_type=interconnect',
	'dsx:obtain_ident_method=port',
	],
        
)