Context Navigation

source: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 355

Last change on this file since 355 was 355, checked in by joannou, 11 years ago

In vci_cc_vcache_wrapper v5

added check for p_dspin_in.write in CC_RECEIVE FSM states
removed invalid assert
removed some traces

File size: 228.5 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 1
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using namespace soclib::common;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	const int proc_id,
170	const MappingTable &mtd,
171	const IntTab &srcid,
172	const size_t cc_global_id,
173	const size_t itlb_ways,
174	const size_t itlb_sets,
175	const size_t dtlb_ways,
176	const size_t dtlb_sets,
177	const size_t icache_ways,
178	const size_t icache_sets,
179	const size_t icache_words,
180	const size_t dcache_ways,
181	const size_t dcache_sets,
182	const size_t dcache_words,
183	const size_t wbuf_nlines,
184	const size_t wbuf_nwords,
185	const size_t x_width,
186	const size_t y_width,
187	const uint32_t max_frozen_cycles,
188	const uint32_t debug_start_cycle,
189	const bool debug_ok )
190	: soclib::caba::BaseModule(name),
191
192	p_clk("p_clk"),
193	p_resetn("p_resetn"),
194	p_vci("p_vci"),
195	p_dspin_in("p_dspin_in"),
196	p_dspin_out("p_dspin_out"),
197
198	m_cacheability_table( mtd.getCacheabilityTable() ),
199	m_srcid( mtd.indexForId(srcid) ),
200	m_cc_global_id( cc_global_id ),
201	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
202	m_itlb_ways( itlb_ways ),
203	m_itlb_sets( itlb_sets ),
204	m_dtlb_ways( dtlb_ways ),
205	m_dtlb_sets( dtlb_sets ),
206	m_icache_ways( icache_ways ),
207	m_icache_sets( icache_sets ),
208	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
209	m_icache_words( icache_words ),
210	m_dcache_ways( dcache_ways ),
211	m_dcache_sets( dcache_sets ),
212	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
213	m_dcache_words( dcache_words ),
214	m_x_width( x_width ),
215	m_y_width( y_width ),
216	m_proc_id( proc_id ),
217	m_max_frozen_cycles( max_frozen_cycles ),
218	m_paddr_nbits( vci_param::N ),
219	m_debug_start_cycle( debug_start_cycle ),
220	m_debug_ok( debug_ok ),
221
222	r_mmu_ptpr("r_mmu_ptpr"),
223	r_mmu_mode("r_mmu_mode"),
224	r_mmu_word_lo("r_mmu_word_lo"),
225	r_mmu_word_hi("r_mmu_word_hi"),
226	r_mmu_ibvar("r_mmu_ibvar"),
227	r_mmu_dbvar("r_mmu_dbvar"),
228	r_mmu_ietr("r_mmu_ietr"),
229	r_mmu_detr("r_mmu_detr"),
230
231	r_icache_fsm("r_icache_fsm"),
232	r_icache_fsm_save("r_icache_fsm_save"),
233	r_icache_vci_paddr("r_icache_vci_paddr"),
234	r_icache_vaddr_save("r_icache_vaddr_save"),
235
236	r_icache_miss_way("r_icache_miss_way"),
237	r_icache_miss_set("r_icache_miss_set"),
238	r_icache_miss_word("r_icache_miss_word"),
239	r_icache_miss_inval("r_icache_miss_inval"),
240	r_icache_miss_clack("r_icache_miss_clack"),
241
242	r_icache_cc_way("r_icache_cc_way"),
243	r_icache_cc_set("r_icache_cc_set"),
244	r_icache_cc_word("r_icache_cc_word"),
245	r_icache_cc_need_write("r_icache_cc_need_write"),
246
247	r_icache_flush_count("r_icache_flush_count"),
248
249	r_icache_miss_req("r_icache_miss_req"),
250	r_icache_unc_req("r_icache_unc_req"),
251
252	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
253	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
254
255	r_icache_cc_send_req("r_icache_cc_send_req"),
256	r_icache_cc_send_type("r_icache_cc_send_type"),
257	r_icache_cc_send_nline("r_icache_cc_send_nline"),
258	r_icache_cc_send_way("r_icache_cc_send_way"),
259	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
260
261	r_dcache_fsm("r_dcache_fsm"),
262	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
263	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
264
265	r_dcache_wbuf_req("r_dcache_wbuf_req"),
266	r_dcache_updt_req("r_dcache_updt_req"),
267	r_dcache_save_vaddr("r_dcache_save_vaddr"),
268	r_dcache_save_wdata("r_dcache_save_wdata"),
269	r_dcache_save_be("r_dcache_save_be"),
270	r_dcache_save_paddr("r_dcache_save_paddr"),
271	r_dcache_save_cacheable("r_dcache_save_cacheable"),
272	r_dcache_save_cache_way("r_dcache_save_cache_way"),
273	r_dcache_save_cache_set("r_dcache_save_cache_set"),
274	r_dcache_save_cache_word("r_dcache_save_cache_word"),
275
276	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
277	r_dcache_dirty_way("r_dcache_dirty_way"),
278	r_dcache_dirty_set("r_dcache_dirty_set"),
279
280	r_dcache_vci_paddr("r_dcache_vci_paddr"),
281	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
282	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
283	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
284	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
285	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
286	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
287	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
288	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
289	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
290
291	r_dcache_xtn_way("r_dcache_xtn_way"),
292	r_dcache_xtn_set("r_dcache_xtn_set"),
293
294	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
295
296	r_dcache_miss_type("r_dcache_miss_type"),
297	r_dcache_miss_word("r_dcache_miss_word"),
298	r_dcache_miss_way("r_dcache_miss_way"),
299	r_dcache_miss_set("r_dcache_miss_set"),
300	r_dcache_miss_inval("r_dcache_miss_inval"),
301
302	r_dcache_cc_way("r_dcache_cc_way"),
303	r_dcache_cc_set("r_dcache_cc_set"),
304	r_dcache_cc_word("r_dcache_cc_word"),
305	r_dcache_cc_need_write("r_dcache_cc_need_write"),
306
307	r_dcache_flush_count("r_dcache_flush_count"),
308
309	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
310
311	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
312	r_dcache_tlb_ins("r_dcache_tlb_ins"),
313	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
314	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
315	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
316	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
317	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
318	r_dcache_tlb_way("r_dcache_tlb_way"),
319	r_dcache_tlb_set("r_dcache_tlb_set"),
320
321	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
322	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
323
324	r_dcache_xtn_req("r_dcache_xtn_req"),
325	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
326
327	r_dcache_cc_send_req("r_dcache_cc_send_req"),
328	r_dcache_cc_send_type("r_dcache_cc_send_type"),
329	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
330	r_dcache_cc_send_way("r_dcache_cc_send_way"),
331	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
332
333	r_vci_cmd_fsm("r_vci_cmd_fsm"),
334	r_vci_cmd_min("r_vci_cmd_min"),
335	r_vci_cmd_max("r_vci_cmd_max"),
336	r_vci_cmd_cpt("r_vci_cmd_cpt"),
337	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
338
339	r_vci_rsp_fsm("r_vci_rsp_fsm"),
340	r_vci_rsp_cpt("r_vci_rsp_cpt"),
341	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
342	r_vci_rsp_data_error("r_vci_rsp_data_error"),
343	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
344	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
345
346	r_cc_send_fsm("r_cc_send_fsm"),
347	r_cc_send_last_client("r_cc_send_last_client"),
348
349	r_cc_receive_fsm("r_cc_receive_fsm"),
350	r_cc_receive_data_ins("r_cc_receive_data_ins"),
351	r_cc_receive_word_idx("r_cc_receive_word_idx"),
352	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
353	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
354	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
355
356	r_cc_receive_icache_req("r_cc_receive_icache_req"),
357	r_cc_receive_icache_type("r_cc_receive_icache_type"),
358	r_cc_receive_icache_way("r_cc_receive_icache_way"),
359	r_cc_receive_icache_set("r_cc_receive_icache_set"),
360	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
361	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
362
363	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
364	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
365	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
366	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
367	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
368	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
369
370	r_iss(this->name(), proc_id),
371	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
372	r_icache("icache", icache_ways, icache_sets, icache_words),
373	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
374	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
375	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
376	{
377	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
378	"Need more PLEN bits.");
379
380	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
381	"Need more TRDID bits.");
382
383	assert( (icache_words == dcache_words) and
384	"icache_words and dcache_words parameters must be equal");
385
386	assert( (itlb_sets == dtlb_sets) and
387	"itlb_sets and dtlb_sets parameters must be etqual");
388
389	assert( (itlb_ways == dtlb_ways) and
390	"itlb_ways and dtlb_ways parameters must be etqual");
391
392	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
393	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
394	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
395	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
396	(uint32_log2(m_icache_words<<2));
397
398	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
399
400	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
401	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
402
403	SC_METHOD(transition);
404	dont_initialize();
405	sensitive << p_clk.pos();
406
407	SC_METHOD(genMoore);
408	dont_initialize();
409	sensitive << p_clk.neg();
410
411	typename iss_t::CacheInfo cache_info;
412	cache_info.has_mmu = true;
413	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
414	cache_info.icache_assoc = icache_ways;
415	cache_info.icache_n_lines = icache_sets;
416	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
417	cache_info.dcache_assoc = dcache_ways;
418	cache_info.dcache_n_lines = dcache_sets;
419	r_iss.setCacheInfo(cache_info);
420	}
421
422	/////////////////////////////////////
423	tmpl(/**/)::~VciCcVCacheWrapper()
424	/////////////////////////////////////
425	{
426	delete [] r_dcache_in_tlb;
427	delete [] r_dcache_contains_ptd;
428	}
429
430	////////////////////////
431	tmpl(void)::print_cpi()
432	////////////////////////
433	{
434	std::cout << name() << " CPI = "
435	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
436	}
437
438	////////////////////////////////////
439	tmpl(void)::print_trace(size_t mode)
440	////////////////////////////////////
441	{
442	// b0 : write buffer trace
443	// b1 : write buffer verbose
444	// b2 : dcache trace
445	// b3 : icache trace
446	// b4 : dtlb trace
447	// b5 : itlb trace
448
449	std::cout << std::dec << "PROC " << name() << std::endl;
450
451	std::cout << " " << m_ireq << std::endl;
452	std::cout << " " << m_irsp << std::endl;
453	std::cout << " " << m_dreq << std::endl;
454	std::cout << " " << m_drsp << std::endl;
455
456	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
457	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
458	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
459	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
460	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
461	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
462	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
463	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
464	std::cout << std::endl;
465
466	if(mode & 0x01)
467	{
468	r_wbuf.printTrace((mode>>1)&1);
469	}
470	if(mode & 0x04)
471	{
472	std::cout << " Data Cache" << std::endl;
473	r_dcache.printTrace();
474	}
475	if(mode & 0x08)
476	{
477	std::cout << " Instruction Cache" << std::endl;
478	r_icache.printTrace();
479	}
480	if(mode & 0x10)
481	{
482	std::cout << " Data TLB" << std::endl;
483	r_dtlb.printTrace();
484	}
485	if(mode & 0x20)
486	{
487	std::cout << " Instruction TLB" << std::endl;
488	r_itlb.printTrace();
489	}
490	}
491
492	//////////////////////////////////////////
493	tmpl(void)::cache_monitor( paddr_t addr )
494	//////////////////////////////////////////
495	{
496	size_t cache_way;
497	size_t cache_set;
498	size_t cache_word;
499	uint32_t cache_rdata;
500	bool cache_hit = r_dcache.read_neutral( addr,
501	&cache_rdata,
502	&cache_way,
503	&cache_set,
504	&cache_word );
505	bool icache_hit = r_icache.read_neutral( addr,
506	&cache_rdata,
507	&cache_way,
508	&cache_set,
509	&cache_word );
510	if ( cache_hit != m_debug_previous_hit )
511	{
512	std::cout << "PROC " << name()
513	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
514	<< " for adresse " << std::hex << addr
515	<< " / HIT = " << std::dec << cache_hit << std::endl;
516	m_debug_previous_hit = cache_hit;
517	}
518	if ( icache_hit != m_idebug_previous_hit )
519	{
520	std::cout << "PROC " << name()
521	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
522	<< " for adresse " << std::hex << addr
523	<< " / HIT = " << icache_hit << std::endl;
524	m_idebug_previous_hit = icache_hit;
525	}
526	}
527
528	/*
529	////////////////////////
530	tmpl(void)::print_stats()
531	////////////////////////
532	{
533	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
534	std::cout << name() << std::endl
535	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
536	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
537	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
538	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
539	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
540	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
541	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
542	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
543	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
544	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
545	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
546	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
547	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
548	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
549	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
550	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
551	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
552	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
553	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
554	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
555	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
556	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
557	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
558	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
559	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
560	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
561	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
562	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
563	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
564	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
565	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
566	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
567	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
568	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
569	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
570	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
571	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
572	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
573	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
574	}
575
576	////////////////////////
577	tmpl(void)::clear_stats()
578	////////////////////////
579	{
580	m_cpt_dcache_data_read = 0;
581	m_cpt_dcache_data_write = 0;
582	m_cpt_dcache_dir_read = 0;
583	m_cpt_dcache_dir_write = 0;
584	m_cpt_icache_data_read = 0;
585	m_cpt_icache_data_write = 0;
586	m_cpt_icache_dir_read = 0;
587	m_cpt_icache_dir_write = 0;
588
589	m_cpt_frz_cycles = 0;
590	m_cpt_dcache_frz_cycles = 0;
591	m_cpt_total_cycles = 0;
592
593	m_cpt_read = 0;
594	m_cpt_write = 0;
595	m_cpt_data_miss = 0;
596	m_cpt_ins_miss = 0;
597	m_cpt_unc_read = 0;
598	m_cpt_write_cached = 0;
599	m_cpt_ins_read = 0;
600
601	m_cost_write_frz = 0;
602	m_cost_data_miss_frz = 0;
603	m_cost_unc_read_frz = 0;
604	m_cost_ins_miss_frz = 0;
605
606	m_cpt_imiss_transaction = 0;
607	m_cpt_dmiss_transaction = 0;
608	m_cpt_unc_transaction = 0;
609	m_cpt_write_transaction = 0;
610	m_cpt_icache_unc_transaction = 0;
611
612	m_cost_imiss_transaction = 0;
613	m_cost_dmiss_transaction = 0;
614	m_cost_unc_transaction = 0;
615	m_cost_write_transaction = 0;
616	m_cost_icache_unc_transaction = 0;
617	m_length_write_transaction = 0;
618
619	m_cpt_ins_tlb_read = 0;
620	m_cpt_ins_tlb_miss = 0;
621	m_cpt_ins_tlb_update_acc = 0;
622
623	m_cpt_data_tlb_read = 0;
624	m_cpt_data_tlb_miss = 0;
625	m_cpt_data_tlb_update_acc = 0;
626	m_cpt_data_tlb_update_dirty = 0;
627	m_cpt_ins_tlb_hit_dcache = 0;
628	m_cpt_data_tlb_hit_dcache = 0;
629	m_cpt_ins_tlb_occup_cache = 0;
630	m_cpt_data_tlb_occup_cache = 0;
631
632	m_cost_ins_tlb_miss_frz = 0;
633	m_cost_data_tlb_miss_frz = 0;
634	m_cost_ins_tlb_update_acc_frz = 0;
635	m_cost_data_tlb_update_acc_frz = 0;
636	m_cost_data_tlb_update_dirty_frz = 0;
637	m_cost_ins_tlb_occup_cache_frz = 0;
638	m_cost_data_tlb_occup_cache_frz = 0;
639
640	m_cpt_itlbmiss_transaction = 0;
641	m_cpt_itlb_ll_transaction = 0;
642	m_cpt_itlb_sc_transaction = 0;
643	m_cpt_dtlbmiss_transaction = 0;
644	m_cpt_dtlb_ll_transaction = 0;
645	m_cpt_dtlb_sc_transaction = 0;
646	m_cpt_dtlb_ll_dirty_transaction = 0;
647	m_cpt_dtlb_sc_dirty_transaction = 0;
648
649	m_cost_itlbmiss_transaction = 0;
650	m_cost_itlb_ll_transaction = 0;
651	m_cost_itlb_sc_transaction = 0;
652	m_cost_dtlbmiss_transaction = 0;
653	m_cost_dtlb_ll_transaction = 0;
654	m_cost_dtlb_sc_transaction = 0;
655	m_cost_dtlb_ll_dirty_transaction = 0;
656	m_cost_dtlb_sc_dirty_transaction = 0;
657
658	m_cpt_cc_update_data = 0;
659	m_cpt_cc_inval_ins = 0;
660	m_cpt_cc_inval_data = 0;
661	m_cpt_cc_broadcast = 0;
662
663	m_cost_updt_data_frz = 0;
664	m_cost_inval_ins_frz = 0;
665	m_cost_inval_data_frz = 0;
666	m_cost_broadcast_frz = 0;
667
668	m_cpt_cc_cleanup_data = 0;
669	m_cpt_cc_cleanup_ins = 0;
670	}
671
672	*/
673
674	/////////////////////////
675	tmpl(void)::transition()
676	/////////////////////////
677	{
678	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
679	if ( not p_resetn.read() )
680	{
681	r_iss.reset();
682	r_wbuf.reset();
683	r_icache.reset();
684	r_dcache.reset();
685	r_itlb.reset();
686	r_dtlb.reset();
687
688	r_dcache_fsm = DCACHE_IDLE;
689	r_icache_fsm = ICACHE_IDLE;
690	r_vci_cmd_fsm = CMD_IDLE;
691	r_vci_rsp_fsm = RSP_IDLE;
692	r_cc_receive_fsm = CC_RECEIVE_IDLE;
693	r_cc_send_fsm = CC_SEND_IDLE;
694
695	// reset dcache directory extension
696	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
697	{
698	r_dcache_in_tlb[i] = false;
699	r_dcache_contains_ptd[i] = false;
700	}
701
702	// Response FIFOs and cleanup buffer
703	r_vci_rsp_fifo_icache.init();
704	r_vci_rsp_fifo_dcache.init();
705
706	// ICACHE & DCACHE activated
707	r_mmu_mode = 0x3;
708
709	// No request from ICACHE FSM to CMD FSM
710	r_icache_miss_req = false;
711	r_icache_unc_req = false;
712
713	// No request from ICACHE_FSM to DCACHE FSM
714	r_icache_tlb_miss_req = false;
715
716	// No request from ICACHE_FSM to CC_SEND FSM
717	r_icache_cc_send_req = false;
718
719	// No pending write in pipeline
720	r_dcache_wbuf_req = false;
721	r_dcache_updt_req = false;
722
723	// No request from DCACHE_FSM to CMD_FSM
724	r_dcache_vci_miss_req = false;
725	r_dcache_vci_unc_req = false;
726	r_dcache_vci_cas_req = false;
727	r_dcache_vci_ll_req = false;
728	r_dcache_vci_sc_req = false;
729
730	// No uncacheable write pending
731	r_dcache_pending_unc_write = false;
732
733	// No processor XTN request pending
734	r_dcache_xtn_req = false;
735
736	// No request from DCACHE FSM to CC_SEND FSM
737	r_dcache_cc_send_req = false;
738
739	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
740	r_cc_receive_icache_req = false;
741	r_cc_receive_dcache_req = false;
742
743	// last cc_send client was dcache
744	r_cc_send_last_client = false;
745
746	// No pending cleanup after a replacement
747	r_icache_miss_clack = false;
748	r_dcache_miss_clack = false;
749
750	// No signalisation of a coherence request matching a pending miss
751	r_icache_miss_inval = false;
752	r_dcache_miss_inval = false;
753
754	// No signalisation of errors
755	r_vci_rsp_ins_error = false;
756	r_vci_rsp_data_error = false;
757
758	// Debug variables
759	m_debug_previous_hit = false;
760	m_idebug_previous_hit = false;
761	m_debug_dcache_fsm = false;
762	m_debug_icache_fsm = false;
763
764	// activity counters
765	m_cpt_dcache_data_read = 0;
766	m_cpt_dcache_data_write = 0;
767	m_cpt_dcache_dir_read = 0;
768	m_cpt_dcache_dir_write = 0;
769	m_cpt_icache_data_read = 0;
770	m_cpt_icache_data_write = 0;
771	m_cpt_icache_dir_read = 0;
772	m_cpt_icache_dir_write = 0;
773
774	m_cpt_frz_cycles = 0;
775	m_cpt_total_cycles = 0;
776	m_cpt_stop_simulation = 0;
777
778	m_cpt_data_miss = 0;
779	m_cpt_ins_miss = 0;
780	m_cpt_unc_read = 0;
781	m_cpt_write_cached = 0;
782	m_cpt_ins_read = 0;
783
784	m_cost_write_frz = 0;
785	m_cost_data_miss_frz = 0;
786	m_cost_unc_read_frz = 0;
787	m_cost_ins_miss_frz = 0;
788
789	m_cpt_imiss_transaction = 0;
790	m_cpt_dmiss_transaction = 0;
791	m_cpt_unc_transaction = 0;
792	m_cpt_write_transaction = 0;
793	m_cpt_icache_unc_transaction = 0;
794
795	m_cost_imiss_transaction = 0;
796	m_cost_dmiss_transaction = 0;
797	m_cost_unc_transaction = 0;
798	m_cost_write_transaction = 0;
799	m_cost_icache_unc_transaction = 0;
800	m_length_write_transaction = 0;
801
802	m_cpt_ins_tlb_read = 0;
803	m_cpt_ins_tlb_miss = 0;
804	m_cpt_ins_tlb_update_acc = 0;
805
806	m_cpt_data_tlb_read = 0;
807	m_cpt_data_tlb_miss = 0;
808	m_cpt_data_tlb_update_acc = 0;
809	m_cpt_data_tlb_update_dirty = 0;
810	m_cpt_ins_tlb_hit_dcache = 0;
811	m_cpt_data_tlb_hit_dcache = 0;
812	m_cpt_ins_tlb_occup_cache = 0;
813	m_cpt_data_tlb_occup_cache = 0;
814
815	m_cost_ins_tlb_miss_frz = 0;
816	m_cost_data_tlb_miss_frz = 0;
817	m_cost_ins_tlb_update_acc_frz = 0;
818	m_cost_data_tlb_update_acc_frz = 0;
819	m_cost_data_tlb_update_dirty_frz = 0;
820	m_cost_ins_tlb_occup_cache_frz = 0;
821	m_cost_data_tlb_occup_cache_frz = 0;
822
823	m_cpt_ins_tlb_inval = 0;
824	m_cpt_data_tlb_inval = 0;
825	m_cost_ins_tlb_inval_frz = 0;
826	m_cost_data_tlb_inval_frz = 0;
827
828	m_cpt_cc_broadcast = 0;
829
830	m_cost_updt_data_frz = 0;
831	m_cost_inval_ins_frz = 0;
832	m_cost_inval_data_frz = 0;
833	m_cost_broadcast_frz = 0;
834
835	m_cpt_cc_cleanup_data = 0;
836	m_cpt_cc_cleanup_ins = 0;
837
838	m_cpt_itlbmiss_transaction = 0;
839	m_cpt_itlb_ll_transaction = 0;
840	m_cpt_itlb_sc_transaction = 0;
841	m_cpt_dtlbmiss_transaction = 0;
842	m_cpt_dtlb_ll_transaction = 0;
843	m_cpt_dtlb_sc_transaction = 0;
844	m_cpt_dtlb_ll_dirty_transaction = 0;
845	m_cpt_dtlb_sc_dirty_transaction = 0;
846
847	m_cost_itlbmiss_transaction = 0;
848	m_cost_itlb_ll_transaction = 0;
849	m_cost_itlb_sc_transaction = 0;
850	m_cost_dtlbmiss_transaction = 0;
851	m_cost_dtlb_ll_transaction = 0;
852	m_cost_dtlb_sc_transaction = 0;
853	m_cost_dtlb_ll_dirty_transaction = 0;
854	m_cost_dtlb_sc_dirty_transaction = 0;
855	/*
856	m_cpt_dcache_frz_cycles = 0;
857	m_cpt_read = 0;
858	m_cpt_write = 0;
859	m_cpt_cc_update_data = 0;
860	m_cpt_cc_inval_ins = 0;
861	m_cpt_cc_inval_data = 0;
862	*/
863
864	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
865	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
866	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
867	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
868
869	// init the llsc reservation buffer
870	r_dcache_llsc_valid = false;
871
872	return;
873	}
874
875	// Response FIFOs default values
876	bool vci_rsp_fifo_icache_get = false;
877	bool vci_rsp_fifo_icache_put = false;
878	uint32_t vci_rsp_fifo_icache_data = 0;
879
880	bool vci_rsp_fifo_dcache_get = false;
881	bool vci_rsp_fifo_dcache_put = false;
882	uint32_t vci_rsp_fifo_dcache_data = 0;
883
884	// updt fifo
885	bool cc_receive_updt_fifo_get = false;
886	bool cc_receive_updt_fifo_put = false;
887	uint32_t cc_receive_updt_fifo_be = 0;
888	uint32_t cc_receive_updt_fifo_data = 0;
889	bool cc_receive_updt_fifo_eop = false;
890
891	#ifdef INSTRUMENTATION
892	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
893	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
894	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
895	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
896	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
897	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
898	#endif
899
900	m_cpt_total_cycles++;
901
902	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
903	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
904
905	/////////////////////////////////////////////////////////////////////
906	// Get data and instruction requests from processor
907	///////////////////////////////////////////////////////////////////////
908
909	r_iss.getRequests(m_ireq, m_dreq);
910
911	////////////////////////////////////////////////////////////////////////////////////
912	// ICACHE_FSM
913	//
914	// 1/ Coherence operations
915	// They are handled as interrupts generated by the CC_RECEIVE FSM.
916	// - There is a coherence request when r_tgt_icache_req is set.
917	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
918	// - There is a cleanup ack request when r_cleanup_icache_req is set.
919	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
920	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
921	// - For both types of requests, actions associated to the pre-empted state
922	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
923	// or CC_CLACK) to execute the requested coherence operation, and returns
924	// to the pre-empted state.
925	//
926	// 2/ Processor requests
927	// They are taken in IDLE state only. In case of cache miss, or uncacheable
928	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
929	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
930	// flip-flops are reset when the transaction starts.
931	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
932	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
933	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
934	// The availability of the missing cache line is signaled by the response fifo,
935	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
936	// and ICACHE_MISS_DIR_UPDT states.
937	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
938	// to wait the response from the RSP FSM, through the response fifo.
939	// The missing instruction is directly returned to processor in this state.
940	//
941	// 3/ TLB miss
942	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
943	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
944	// register, and goes to the ICACHE_TLB_WAIT state.
945	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
946	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
947	// to signal the completion.
948	//
949	// 4/ XTN requests
950	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
951	// using the r_dcache_xtn_req flip-flop.
952	// The request opcode and the address to be invalidated are transmitted
953	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
954	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
955	// is completed.
956	//
957	// 5/ Error Handling
958	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
959	// in a cache miss or uncacheable read VCI transaction. Nothing is written
960	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
961	////////////////////////////////////////////////////////////////////////////////////////
962
963	// default value for m_irsp
964	m_irsp.valid = false;
965	m_irsp.error = false;
966	m_irsp.instruction = 0;
967
968	switch( r_icache_fsm.read() )
969	{
970	/////////////////
971	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
972	// and coherence requests with a fixed priority:
973	// 1/ Coherence requests => ICACHE_CC_CHECK
974	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
975	// 3/ tlb miss => ICACHE_TLB_WAIT
976	// 4/ cacheable read miss => ICACHE_MISS_SELECT
977	// 5/ uncacheable read miss => ICACHE_UNC_REQ
978	{
979	// coherence interrupt
980	if ( r_cc_receive_icache_req.read() )
981	{
982	r_icache_fsm = ICACHE_CC_CHECK;
983	r_icache_fsm_save = r_icache_fsm.read();
984	break;
985	}
986
987	// XTN requests sent by DCACHE FSM
988	// These request are not executed in this IDLE state, because
989	// they require access to icache or itlb, that are already accessed
990	if ( r_dcache_xtn_req.read() )
991	{
992	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
993	{
994	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
995	}
996	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
997	{
998	r_icache_flush_count = 0;
999	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1000	}
1001	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1002	{
1003	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1004	}
1005	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1006	{
1007	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1008	}
1009	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1010	{
1011	if (sizeof(paddr_t) <= 32)
1012	{
1013	assert(r_mmu_word_hi.read() == 0 &&
1014	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1015	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1016	}
1017	else
1018	{
1019	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1020	(paddr_t)r_mmu_word_lo.read();
1021	}
1022	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1023	}
1024	else
1025	{
1026	assert( false and
1027	"undefined XTN request received by ICACHE FSM");
1028	}
1029	break;
1030	} // end if xtn_req
1031
1032	// processor request
1033	if ( m_ireq.valid )
1034	{
1035	bool cacheable;
1036	paddr_t paddr;
1037	bool tlb_hit = false;
1038	pte_info_t tlb_flags;
1039	size_t tlb_way;
1040	size_t tlb_set;
1041	paddr_t tlb_nline;
1042	uint32_t cache_inst = 0;
1043	size_t cache_way;
1044	size_t cache_set;
1045	size_t cache_word;
1046	int cache_state = CACHE_SLOT_STATE_EMPTY;
1047
1048	// We register processor request
1049	r_icache_vaddr_save = m_ireq.addr;
1050
1051	// sytematic itlb access (if activated)
1052	if ( r_mmu_mode.read() & INS_TLB_MASK )
1053	{
1054
1055	#ifdef INSTRUMENTATION
1056	m_cpt_itlb_read++;
1057	#endif
1058	tlb_hit = r_itlb.translate( m_ireq.addr,
1059	&paddr,
1060	&tlb_flags,
1061	&tlb_nline, // unused
1062	&tlb_way, // unused
1063	&tlb_set ); // unused
1064	}
1065	else
1066	{
1067	paddr = (paddr_t)m_ireq.addr;
1068	}
1069
1070	// systematic icache access (if activated)
1071	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1072	{
1073
1074
1075	#ifdef INSTRUMENTATION
1076	m_cpt_icache_data_read++;
1077	m_cpt_icache_dir_read++;
1078	#endif
1079	r_icache.read( paddr,
1080	&cache_inst,
1081	&cache_way,
1082	&cache_set,
1083	&cache_word,
1084	&cache_state );
1085	}
1086
1087	// We compute cacheability and check access rights:
1088	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1089	// and the access rights are defined by the U and X bits in the PTE.
1090	// - If MMU not activated : cacheability is defined by the segment table,
1091	// and there is no access rights checking
1092
1093	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1094	{
1095	// cacheability
1096	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1097	else cacheable = m_cacheability_table[m_ireq.addr];
1098	}
1099	else // itlb activated
1100	{
1101	if ( tlb_hit ) // ITLB hit
1102	{
1103	// cacheability
1104	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1105	else cacheable = tlb_flags.c;
1106
1107	// access rights checking
1108	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1109	{
1110	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1111	r_mmu_ibvar = m_ireq.addr;
1112	m_irsp.valid = true;
1113	m_irsp.error = true;
1114	m_irsp.instruction = 0;
1115	break;
1116	}
1117	else if ( not tlb_flags.x )
1118	{
1119	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1120	r_mmu_ibvar = m_ireq.addr;
1121	m_irsp.valid = true;
1122	m_irsp.error = true;
1123	m_irsp.instruction = 0;
1124	break;
1125	}
1126	}
1127	else // ITLB miss
1128	{
1129
1130	#ifdef INSTRUMENTATION
1131	m_cpt_itlb_miss++;
1132	#endif
1133	r_icache_fsm = ICACHE_TLB_WAIT;
1134	r_icache_tlb_miss_req = true;
1135	break;
1136	}
1137	} // end if itlb activated
1138
1139	// physical address registration
1140	r_icache_vci_paddr = paddr;
1141
1142	// Finally, we send the response to processor, and compute next state
1143	if ( cacheable )
1144	{
1145	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1146	{
1147
1148	#ifdef INSTRUMENTATION
1149	m_cpt_icache_miss++;
1150	#endif
1151	// we request a VCI transaction
1152	r_icache_fsm = ICACHE_MISS_SELECT;
1153	r_icache_miss_req = true;
1154	}
1155	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1156	{
1157	// stalled until cleanup is acknowledged
1158	r_icache_fsm = ICACHE_IDLE;
1159	}
1160	else // cache hit
1161	{
1162
1163	#ifdef INSTRUMENTATION
1164	m_cpt_ins_read++;
1165	#endif
1166	// return instruction to processor
1167	m_irsp.valid = true;
1168	m_irsp.instruction = cache_inst;
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	}
1172	else // non cacheable read
1173	{
1174	r_icache_unc_req = true;
1175	r_icache_fsm = ICACHE_UNC_WAIT;
1176	}
1177	} // end if m_ireq.valid
1178	break;
1179	}
1180	/////////////////////
1181	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1182	// the itlb is udated by the DCACHE FSM, as well as the
1183	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1184	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1185	// reset the r_icache_tlb_miss_req flip-flop
1186	// external coherence request are accepted in this state.
1187	{
1188	// coherence interrupt
1189	if ( r_cc_receive_icache_req.read() )
1190	{
1191	r_icache_fsm = ICACHE_CC_CHECK;
1192	r_icache_fsm_save = r_icache_fsm.read();
1193	break;
1194	}
1195
1196	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1197
1198	// DCACHE FSM signals response by reseting the request flip-flop
1199	if ( not r_icache_tlb_miss_req.read() )
1200	{
1201	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1202	{
1203	r_icache_tlb_rsp_error = false;
1204	m_irsp.error = true;
1205	m_irsp.valid = true;
1206	r_icache_fsm = ICACHE_IDLE;
1207	}
1208	else // tlb updated : return to IDLE state
1209	{
1210	r_icache_fsm = ICACHE_IDLE;
1211	}
1212	}
1213	break;
1214	}
1215	//////////////////////////
1216	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1217	{
1218	r_itlb.flush();
1219	r_dcache_xtn_req = false;
1220	r_icache_fsm = ICACHE_IDLE;
1221	break;
1222	}
1223	////////////////////////////
1224	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1225	// r_icache_flush_count as a slot counter,
1226	// looping in this state until all slots are visited.
1227	// It can require two cycles per slot:
1228	// We test here the slot state, and make the actual inval
1229	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1230	// A cleanup request is generated for each valid line
1231	{
1232	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1233	{
1234	int state;
1235	uint32_t tag;
1236	size_t way = r_icache_flush_count.read()/m_icache_sets;
1237	size_t set = r_icache_flush_count.read()%m_icache_sets;
1238
1239	#ifdef INSTRUMENTATION
1240	m_cpt_icache_dir_read++;
1241	#endif
1242	r_icache.read_dir( way,
1243	set,
1244	&tag,
1245	&state );
1246
1247	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1248	{
1249	// request cleanup
1250	r_icache_cc_send_req = true;
1251	r_icache_cc_send_nline = tag * m_icache_sets;
1252	r_icache_cc_send_way = way;
1253	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1254
1255	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1256	r_icache_miss_way = way;
1257	r_icache_miss_set = set;
1258	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1259	}
1260	else if ( r_icache_flush_count.read() ==
1261	(m_icache_sets*m_icache_ways - 1) ) // last slot
1262	{
1263	r_dcache_xtn_req = false;
1264	m_drsp.valid = true;
1265	r_icache_fsm = ICACHE_IDLE;
1266	}
1267
1268	// saturation counter, to have the same last slot condition
1269	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1270	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1271	{
1272	r_icache_flush_count = r_icache_flush_count.read() + 1;
1273	}
1274	}
1275	break;
1276	}
1277	///////////////////////////////
1278	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1279	{
1280	size_t way = r_icache_miss_way.read();
1281	size_t set = r_icache_miss_set.read();
1282
1283	#ifdef INSTRUMENTATION
1284	m_cpt_icache_dir_write++;
1285	#endif
1286
1287	r_icache.write_dir( 0,
1288	way,
1289	set,
1290	CACHE_SLOT_STATE_ZOMBI );
1291
1292	if ( r_icache_flush_count.read() ==
1293	(m_icache_sets*m_icache_ways - 1) ) // last slot
1294	{
1295	r_dcache_xtn_req = false;
1296	m_drsp.valid = true;
1297	r_icache_fsm = ICACHE_IDLE;
1298	}
1299	else
1300	{
1301	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1302	}
1303	break;
1304	}
1305
1306	//////////////////////////
1307	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1308	// stored in the r_dcache_save_wdata register
1309	{
1310	r_itlb.inval(r_dcache_save_wdata.read());
1311	r_dcache_xtn_req = false;
1312	r_icache_fsm = ICACHE_IDLE;
1313	break;
1314	}
1315	///////////////////////////////
1316	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1317	// requires 3 cycles (in case of hit on itlb and icache).
1318	// In this state, access TLB to translate virtual address
1319	// stored in the r_dcache_save_wdata register.
1320	{
1321	paddr_t paddr;
1322	bool hit;
1323
1324	// read physical address in TLB when MMU activated
1325	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1326	{
1327
1328	#ifdef INSTRUMENTATION
1329	m_cpt_itlb_read++;
1330	#endif
1331	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1332	&paddr);
1333	}
1334	else // itlb not activated
1335	{
1336	paddr = (paddr_t)r_dcache_save_wdata.read();
1337	hit = true;
1338	}
1339
1340	if ( hit ) // continue the selective inval process
1341	{
1342	r_icache_vci_paddr = paddr;
1343	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1344	}
1345	else // miss : send a request to DCACHE FSM
1346	{
1347
1348	#ifdef INSTRUMENTATION
1349	m_cpt_itlb_miss++;
1350	#endif
1351	r_icache_tlb_miss_req = true;
1352	r_icache_vaddr_save = r_dcache_save_wdata.read();
1353	r_icache_fsm = ICACHE_TLB_WAIT;
1354	}
1355	break;
1356	}
1357	///////////////////////////////
1358	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1359	// require 2 cycles. In this state, we read directory
1360	// with address stored in r_icache_vci_paddr register.
1361	{
1362	int state;
1363	size_t way;
1364	size_t set;
1365	size_t word;
1366
1367	#ifdef INSTRUMENTATION
1368	m_cpt_icache_dir_read++;
1369	#endif
1370	r_icache.read_dir(r_icache_vci_paddr.read(),
1371	&state,
1372	&way,
1373	&set,
1374	&word);
1375
1376	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1377	{
1378	r_icache_miss_way = way;
1379	r_icache_miss_set = set;
1380	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1381	}
1382	else // miss : acknowlege the XTN request and return
1383	{
1384	r_dcache_xtn_req = false;
1385	r_icache_fsm = ICACHE_IDLE;
1386	}
1387	break;
1388	}
1389	///////////////////////////////
1390	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1391	{
1392	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1393	{
1394
1395	#ifdef INSTRUMENTATION
1396	m_cpt_icache_dir_write++;
1397	#endif
1398	r_icache.write_dir( 0,
1399	r_icache_miss_way.read(),
1400	r_icache_miss_set.read(),
1401	CACHE_SLOT_STATE_ZOMBI );
1402
1403	// request cleanup
1404	r_icache_cc_send_req = true;
1405	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1406	r_icache_cc_send_way = r_icache_miss_way.read();
1407	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1408
1409	// acknowledge the XTN request and return
1410	r_dcache_xtn_req = false;
1411	r_icache_fsm = ICACHE_IDLE;
1412	}
1413	break;
1414	}
1415	////////////////////////
1416	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1417	// if previous cleanup has been sent.
1418	// Waiting in this state if no slot available.
1419	// Set the r_icache_cleanup_req flip-flop
1420	// and the r_icache_miss_clack flip-flop,
1421	// when a cleanup is required
1422	{
1423	if (m_ireq.valid) m_cost_ins_miss_frz++;
1424
1425	// coherence interrupt
1426	if ( r_cc_receive_icache_req.read() )
1427	{
1428	r_icache_fsm = ICACHE_CC_CHECK;
1429	r_icache_fsm_save = r_icache_fsm.read();
1430	break;
1431	}
1432
1433	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1434	{
1435	bool found;
1436	bool cleanup;
1437	size_t way;
1438	size_t set;
1439	paddr_t victim;
1440
1441	#ifdef INSTRUMENTATION
1442	m_cpt_icache_dir_read++;
1443	#endif
1444	r_icache.read_select(r_icache_vci_paddr.read(),
1445	&victim,
1446	&way,
1447	&set,
1448	&found,
1449	&cleanup );
1450	if ( found )
1451	{
1452	r_icache_miss_way = way;
1453	r_icache_miss_set = set;
1454
1455	if ( cleanup )
1456	{
1457	r_icache_fsm = ICACHE_MISS_CLEAN;
1458	r_icache_miss_clack = true;
1459	// request cleanup
1460	r_icache_cc_send_req = true;
1461	r_icache_cc_send_nline = victim;
1462	r_icache_cc_send_way = way;
1463	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1464	}
1465	else
1466	{
1467	r_icache_fsm = ICACHE_MISS_WAIT;
1468	}
1469
1470	#if DEBUG_ICACHE
1471	if ( m_debug_dcache_fsm )
1472	{
1473	std::cout << " <PROC " << name()
1474	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1475	<< " / WAY = " << way
1476	<< " / SET = " << set;
1477	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1478	else std::cout << std::endl;
1479	}
1480	#endif
1481	}
1482	}
1483	break;
1484	}
1485	///////////////////////
1486	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1487	{
1488	if (m_ireq.valid) m_cost_ins_miss_frz++;
1489
1490	#ifdef INSTRUMENTATION
1491	m_cpt_icache_dir_write++;
1492	#endif
1493	r_icache.write_dir( 0,
1494	r_icache_miss_way.read(),
1495	r_icache_miss_set.read(),
1496	CACHE_SLOT_STATE_ZOMBI);
1497	#if DEBUG_ICACHE
1498	if ( m_debug_dcache_fsm )
1499	{
1500	std::cout << " <PROC " << name()
1501	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1502	<< " / WAY = " << r_icache_miss_way.read()
1503	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1504	}
1505	#endif
1506
1507	r_icache_fsm = ICACHE_MISS_WAIT;
1508	break;
1509	}
1510	//////////////////////
1511	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1512	{
1513	if (m_ireq.valid) m_cost_ins_miss_frz++;
1514
1515	// coherence interrupt
1516	if ( r_cc_receive_icache_req.read() )
1517	{
1518	r_icache_fsm = ICACHE_CC_CHECK;
1519	r_icache_fsm_save = r_icache_fsm.read();
1520	break;
1521	}
1522
1523	if ( r_vci_rsp_ins_error.read() ) // bus error
1524	{
1525	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1526	r_mmu_ibvar = r_icache_vaddr_save.read();
1527	m_irsp.valid = true;
1528	m_irsp.error = true;
1529	r_vci_rsp_ins_error = false;
1530	r_icache_fsm = ICACHE_IDLE;
1531	}
1532	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1533	{
1534	r_icache_miss_word = 0;
1535	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1536	}
1537	break;
1538	}
1539	///////////////////////////
1540	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1541	{
1542	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1543
1544	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1545	{
1546
1547	#ifdef INSTRUMENTATION
1548	m_cpt_icache_data_write++;
1549	#endif
1550	r_icache.write( r_icache_miss_way.read(),
1551	r_icache_miss_set.read(),
1552	r_icache_miss_word.read(),
1553	r_vci_rsp_fifo_icache.read() );
1554	#if DEBUG_ICACHE
1555	if ( m_debug_icache_fsm )
1556	{
1557	std::cout << " <PROC " << name()
1558	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1559	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1560	<< " WAY = " << r_icache_miss_way.read()
1561	<< " SET = " << r_icache_miss_set.read()
1562	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1563	}
1564	#endif
1565	vci_rsp_fifo_icache_get = true;
1566	r_icache_miss_word = r_icache_miss_word.read() + 1;
1567
1568	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1569	{
1570	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1571	}
1572	}
1573	break;
1574	}
1575	//////////////////////////
1576	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1577	// and the cleanup ack has not been received,
1578	// as indicated by r_icache_miss_clack.
1579	// - If no matching coherence request (r_icache_miss_inval)
1580	// switch directory slot to VALID state.
1581	// - If matching coherence request, switch directory slot
1582	// to ZOMBI state, and send a cleanup request.
1583	{
1584	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1585
1586	// coherence interrupt
1587	if ( r_cc_receive_icache_req.read() )
1588	{
1589	r_icache_fsm = ICACHE_CC_CHECK;
1590	r_icache_fsm_save = r_icache_fsm.read();
1591	break;
1592	}
1593
1594	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1595	{
1596	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1597	{
1598	if ( not r_icache_cc_send_req.read() )
1599	{
1600	r_icache_miss_inval = false;
1601	// request cleanup
1602	r_icache_cc_send_req = true;
1603	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1604	r_icache_cc_send_way = r_icache_miss_way.read();
1605	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1606
1607	#ifdef INSTRUMENTATION
1608	m_cpt_icache_dir_write++;
1609	#endif
1610	r_icache.write_dir( r_icache_vci_paddr.read(),
1611	r_icache_miss_way.read(),
1612	r_icache_miss_set.read(),
1613	CACHE_SLOT_STATE_ZOMBI );
1614	#if DEBUG_ICACHE
1615	if ( m_debug_icache_fsm )
1616	{
1617	std::cout << " <PROC " << name()
1618	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1619	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1620	<< " WAY = " << std::dec << r_icache_miss_way.read()
1621	<< " SET = " << r_icache_miss_set.read() << std::endl;
1622	}
1623	#endif
1624	}
1625	else
1626	break;
1627	}
1628	else // Switch slot to VALID state
1629	{
1630
1631	#ifdef INSTRUMENTATION
1632	m_cpt_icache_dir_write++;
1633	#endif
1634	r_icache.write_dir( r_icache_vci_paddr.read(),
1635	r_icache_miss_way.read(),
1636	r_icache_miss_set.read(),
1637	CACHE_SLOT_STATE_VALID );
1638	#if DEBUG_ICACHE
1639	if ( m_debug_icache_fsm )
1640	{
1641	std::cout << " <PROC " << name()
1642	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1643	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1644	<< " WAY = " << std::dec << r_icache_miss_way.read()
1645	<< " SET = " << r_icache_miss_set.read() << std::endl;
1646	}
1647	#endif
1648	}
1649
1650	r_icache_fsm = ICACHE_IDLE;
1651	}
1652	break;
1653	}
1654	////////////////////
1655	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1656	{
1657	// coherence interrupt
1658	if ( r_cc_receive_icache_req.read() )
1659	{
1660	r_icache_fsm = ICACHE_CC_CHECK;
1661	r_icache_fsm_save = r_icache_fsm.read();
1662	break;
1663	}
1664
1665	if ( r_vci_rsp_ins_error.read() ) // bus error
1666	{
1667	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1668	r_mmu_ibvar = m_ireq.addr;
1669	r_vci_rsp_ins_error = false;
1670	m_irsp.valid = true;
1671	m_irsp.error = true;
1672	r_icache_fsm = ICACHE_IDLE;
1673	}
1674	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1675	{
1676	vci_rsp_fifo_icache_get = true;
1677	r_icache_fsm = ICACHE_IDLE;
1678	if ( m_ireq.valid and
1679	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1680	{
1681	m_irsp.valid = true;
1682	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1683	}
1684	}
1685	break;
1686	}
1687	/////////////////////
1688	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1689	// handling coherence requests.
1690	// if there is a matching pending miss, it is
1691	// signaled in the r_icache_miss_inval flip-flop.
1692	// The return state is defined in r_icache_fsm_save.
1693	{
1694	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1695	paddr_t mask = ~((m_icache_words<<2)-1);
1696
1697	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1698	// We switch the directory slot to EMPTY state
1699	// and reset r_icache_miss_clack if the cleanup ack
1700	// is matching a pending miss
1701	{
1702
1703	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1704
1705	#ifdef INSTRUMENTATION
1706	m_cpt_icache_dir_write++;
1707	#endif
1708	r_icache.write_dir( 0,
1709	r_cc_receive_icache_way.read(),
1710	r_cc_receive_icache_set.read(),
1711	CACHE_SLOT_STATE_EMPTY);
1712
1713	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1714	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1715	r_icache_miss_clack = false;
1716
1717	r_icache_fsm = r_icache_fsm_save.read() ;
1718	r_cc_receive_icache_req = false;
1719
1720	#if DEBUG_ICACHE
1721	if ( m_debug_icache_fsm )
1722	{
1723	std::cout << " <PROC " << name()
1724	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1725	<< " set = " << r_cc_receive_icache_set.read()
1726	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1727	}
1728	#endif
1729	}
1730	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1731	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1732	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1733	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1734	{
1735	// signaling the matching
1736	r_icache_miss_inval = true;
1737
1738	// in case of update, go to CC_UPDT
1739	// JUST TO POP THE FIFO
1740	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1741	{
1742	r_icache_fsm = ICACHE_CC_UPDT;
1743	r_icache_cc_word = r_cc_receive_word_idx.read();
1744	// just pop the fifo , don't write in icache
1745	r_icache_cc_need_write = false;
1746	}
1747	// the request is dealt with
1748	else
1749	{
1750	r_cc_receive_icache_req = false;
1751	r_icache_fsm = r_icache_fsm_save.read();
1752	}
1753	#if DEBUG_ICACHE
1754	if ( m_debug_icache_fsm )
1755	{
1756	std::cout << " <PROC " << name()
1757	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1758	<< " PADDR = " << std::hex << paddr << std::endl;
1759	}
1760	#endif
1761	}
1762	else // no match
1763	{
1764	int state;
1765	size_t way;
1766	size_t set;
1767	size_t word;
1768
1769	#ifdef INSTRUMENTATION
1770	m_cpt_icache_dir_read++;
1771	#endif
1772	r_icache.read_dir(paddr,
1773	&state,
1774	&way,
1775	&set,
1776	&word);
1777
1778	r_icache_cc_way = way;
1779	r_icache_cc_set = set;
1780
1781	if ( state == CACHE_SLOT_STATE_VALID) // hit
1782	{
1783	// need to update the cache state
1784	r_icache_cc_need_write = true;
1785	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1786	{
1787	r_icache_fsm = ICACHE_CC_UPDT;
1788	r_icache_cc_word = r_cc_receive_word_idx.read();
1789	}
1790	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1791	{
1792	r_icache_fsm = ICACHE_CC_INVAL;
1793	}
1794	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1795	{
1796	r_icache_fsm = ICACHE_CC_BROADCAST;
1797	}
1798	}
1799	else // miss
1800	{
1801	// multicast acknowledgement required in case of update
1802	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1803	{
1804	r_icache_fsm = ICACHE_CC_UPDT;
1805	r_icache_cc_word = r_cc_receive_word_idx.read();
1806	// just pop the fifo , don't write in icache
1807	r_icache_cc_need_write = false;
1808	}
1809	else // No response needed
1810	{
1811	r_cc_receive_icache_req = false;
1812	r_icache_fsm = r_icache_fsm_save.read();
1813	}
1814	}
1815	}
1816	break;
1817	}
1818	/////////////////////
1819	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1820	{
1821
1822	#if DEBUG_ICACHE
1823	if ( m_debug_icache_fsm )
1824	{
1825	std::cout << " <PROC " << name()
1826	<< " ICACHE_CC_INVAL> slot returns to empty state"
1827	<< " set = " << r_icache_cc_set.read()
1828	<< " / way = " << r_icache_cc_way.read() << std::endl;
1829	}
1830	#endif
1831
1832	#ifdef INSTRUMENTATION
1833	m_cpt_icache_dir_read++;
1834	#endif
1835	if (r_icache_cc_need_write.read())
1836	{
1837	r_icache.write_dir( 0,
1838	r_icache_cc_way.read(),
1839	r_icache_cc_set.read(),
1840	CACHE_SLOT_STATE_EMPTY );
1841	// no need to write in the cache anymore
1842	r_icache_cc_need_write = false;
1843	}
1844
1845	// multicast acknowledgement
1846	// send a request to cc_send_fsm
1847	if(not r_icache_cc_send_req.read()) // cc_send is available
1848	{
1849	// coherence request completed
1850	r_cc_receive_icache_req = false;
1851	// request multicast acknowledgement
1852	r_icache_cc_send_req = true;
1853	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1854	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1855
1856	r_icache_fsm = r_icache_fsm_save.read();
1857	}
1858	//else wait for previous cc_send request to be sent
1859	break;
1860	}
1861	////////////////////
1862	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1863	{
1864
1865	#if DEBUG_ICACHE
1866	if ( m_debug_icache_fsm )
1867	{
1868	std::cout << " <PROC " << name()
1869	<< " ICACHE_CC_UPDT> Write one word "
1870	<< " set = " << r_icache_cc_set.read()
1871	<< " / way = " << r_icache_cc_way.read()
1872	<< " / word = " << r_icache_cc_word.read() << std::endl;
1873	}
1874	#endif
1875
1876	#ifdef INSTRUMENTATION
1877	m_cpt_icache_data_write++;
1878	#endif
1879	size_t word = r_icache_cc_word.read();
1880	size_t way = r_icache_cc_way.read();
1881	size_t set = r_icache_cc_set.read();
1882
1883	if (r_cc_receive_updt_fifo_be.rok())
1884	{
1885	if (r_icache_cc_need_write.read())
1886	{
1887	r_icache.write( way,
1888	set,
1889	word,
1890	r_cc_receive_updt_fifo_data.read(),
1891	r_cc_receive_updt_fifo_be.read() );
1892
1893	r_icache_cc_word = word+1;
1894	}
1895	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1896	{
1897	// no need to write in the cache anymore
1898	r_icache_cc_need_write = false;
1899	// wait to send a request to cc_send_fsm
1900	if(not r_icache_cc_send_req.read()) // cc_send is available
1901	{
1902	//consume last flit
1903	cc_receive_updt_fifo_get = true;
1904	// coherence request completed
1905	r_cc_receive_icache_req = false;
1906	// request multicast acknowledgement
1907	r_icache_cc_send_req = true;
1908	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1909	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1910
1911	r_icache_fsm = r_icache_fsm_save.read();
1912	}
1913	}
1914	else
1915	{
1916	//consume fifo if not eop
1917	cc_receive_updt_fifo_get = true;
1918	}
1919	}
1920	break;
1921	}
1922	/////////////////////////
1923	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1924	// and request a cleanup
1925	{
1926
1927	#if DEBUG_ICACHE
1928	if ( m_debug_icache_fsm )
1929	{
1930	std::cout << " <PROC " << name()
1931	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1932	<< " set = " << r_icache_cc_set.read()
1933	<< " / way = " << r_icache_cc_way.read() << std::endl;
1934	}
1935	#endif
1936
1937	#ifdef INSTRUMENTATION
1938	m_cpt_icache_dir_write++;
1939	#endif
1940	if (r_icache_cc_need_write.read())
1941	{
1942	r_icache.write_dir( 0,
1943	r_icache_cc_way.read(),
1944	r_icache_cc_set.read(),
1945	CACHE_SLOT_STATE_ZOMBI );
1946	// no need to write in the cache anymore
1947	r_icache_cc_need_write = false;
1948	}
1949
1950	// cleanup
1951	// send a request to cc_send_fsm
1952	if(not r_icache_cc_send_req.read()) // cc_send is available
1953	{
1954	// coherence request completed
1955	r_cc_receive_icache_req = false;
1956	// request cleanup
1957	r_icache_cc_send_req = true;
1958	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1959	r_icache_cc_send_way = r_icache_cc_way.read();
1960	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1961
1962	r_icache_fsm = r_icache_fsm_save.read();
1963	}
1964	//else wait for previous cc_send request to be sent
1965	break;
1966	}
1967	} // end switch r_icache_fsm
1968
1969	////////////////////////////////////////////////////////////////////////////////////
1970	// DCACHE FSM
1971	//
1972	// 1/ Coherence operations
1973	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1974	// - There is a coherence request when r_tgt_dcache_req is set.
1975	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1976	// and SC_WAIT states.
1977	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1978	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1979	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1980	// - For both types of requests, actions associated to the pre-empted state
1981	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1982	// or CC_CLACK) to execute the requested coherence operation, and returns
1983	// to the pre-empted state.
1984	//
1985	// 2/ TLB miss
1986	// The page tables are generally cacheable.
1987	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1988	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1989	// this sub-fsm implement the table-walk...
1990	//
1991	// 3/ processor requests
1992	// Processor requests are taken in IDLE state only.
1993	// The IDLE state implements a two stages pipe-line to handle write bursts:
1994	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
1995	// - The registration in wbuf and the dcache update is done in stage P1
1996	// (if the processor request is a write).
1997	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
1998	// the operations that must be done in P1 stage, and the access type
1999	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2000	// READ requests are delayed if a cache update is requested.
2001	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2002	// that is done (before handling the processor request) by a dedicated sub-fsm.
2003	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2004	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2005	//
2006	// 4/ Atomic instructions LL/SC
2007	// The LL/SC address are non cacheable (systematic access to memory).
2008	// The llsc buffer contains a registration for an active LL/SC operation
2009	// (with an address, a registration key, an aging counter and a valid bit).
2010	// - LL requests from the processor are transmitted as a one flit VCI command
2011	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2012	// be 8 as the response is 2 flits long (data and registration key)
2013	// - SC requests from the processor are systematically transmitted to the
2014	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2015	// as PKTID value). The first flit contains the registration key, the second
2016	// flit contains the data to write in case of success.
2017	// The cache is not updated, as this is done in case of success by the
2018	// coherence transaction.
2019	//
2020	// 5/ Non cacheable access:
2021	// This component implement a strong order between non cacheable access
2022	// (read or write) : A new non cacheable VCI transaction starts only when
2023	// the previous non cacheable transaction is completed. Both cacheable and
2024	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2025	// a non cacheable write transaction posted in the write buffer by setting the
2026	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2027	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2028	// pending non cacheable write transaction completes).
2029	//
2030	// 6/ Error handling:
2031	// When the MMU is not activated, Read Bus Errors are synchronous events,
2032	// but Write Bus Errors are asynchronous events (processor is not frozen).
2033	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2034	// r_vci_rsp_data_error flip-flop, without writing any data in the
2035	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2036	// by the DCACHE FSM.
2037	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2038	// the asynchronous error using the setWriteBerr() method.
2039	// When the MMU is activated bus error are rare events, as the MMU
2040	// checks the physical address before the VCI transaction starts.
2041	////////////////////////////////////////////////////////////////////////////////////////
2042
2043	// default value for m_drsp
2044	m_drsp.valid = false;
2045	m_drsp.error = false;
2046	m_drsp.rdata = 0;
2047
2048	switch ( r_dcache_fsm.read() )
2049	{
2050	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2051	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2052	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2053	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2054	// 4) XTN request (processor) => DCACHE_XTN_*
2055	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2056	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2057	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2058	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2059	// 9) LL access (processor) => DCACHE_LL_WAIT
2060	// 10) SC access (processor) => DCACHE_SC_WAIT
2061	//
2062	// There is a fixed priority to handle requests to DCACHE:
2063	// 1/ the ITLB/DTLB invalidate requests
2064	// 2/ the coherence requests,
2065	// 3/ the processor requests (including DTLB miss),
2066	// 4/ the ITLB miss requests,
2067	// The address space processor request are handled as follows:
2068	// - WRITE request is blocked if the Dirty bit mus be set.
2069	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2070	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2071	// - READ request generate a simultaneouss access to DCACHE.DATA
2072	// and DCACHE.DIR, but is delayed if DCACHE update required.
2073	//
2074	// There is 4 configurations defining the access type to
2075	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2076	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2077	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2078	// 0 / 0 / NOP / NOP / NOP /
2079	// 0 / 1 / NOP / NOP / WRITE /
2080	// 1 / 0 / READ / READ / NOP /
2081	// 1 / 1 / READ / READ / WRITE /
2082	// Those two registers are set at each cycle from the 3 signals
2083	// updt_request, wbuf_request, wbuf_write_miss.
2084	{
2085	paddr_t paddr; // physical address
2086	pte_info_t tlb_flags;
2087	size_t tlb_way;
2088	size_t tlb_set;
2089	paddr_t tlb_nline;
2090	size_t cache_way;
2091	size_t cache_set;
2092	size_t cache_word;
2093	uint32_t cache_rdata = 0;
2094	bool tlb_hit = false;
2095	int cache_state = CACHE_SLOT_STATE_EMPTY;
2096
2097	bool tlb_inval_required = false; // request TLB inval after cache update
2098	bool wbuf_write_miss = false; // miss a WBUF write request
2099	bool updt_request = false; // request DCACHE update in P1 stage
2100	bool wbuf_request = false; // request WBUF write in P1 stage
2101
2102	// physical address computation : systematic DTLB access if activated)
2103	if ( m_dreq.valid )
2104	{
2105	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2106	{
2107	tlb_hit = r_dtlb.translate( m_dreq.addr,
2108	&paddr,
2109	&tlb_flags,
2110	&tlb_nline,
2111	&tlb_way,
2112	&tlb_set );
2113	#ifdef INSTRUMENTATION
2114	m_cpt_dtlb_read++;
2115	#endif
2116	}
2117	else // identity mapping
2118	{
2119	paddr = (paddr_t)m_dreq.addr;
2120	}
2121	} // end physical address computation
2122
2123	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2124	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2125	{
2126	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2127	{
2128	r_dcache.read_dir( paddr,
2129	&cache_state,
2130	&cache_way,
2131	&cache_set,
2132	&cache_word );
2133
2134	r_dcache.write( r_dcache_save_cache_way.read(),
2135	r_dcache_save_cache_set.read(),
2136	r_dcache_save_cache_word.read(),
2137	r_dcache_save_wdata.read(),
2138	r_dcache_save_be.read() );
2139	#ifdef INSTRUMENTATION
2140	m_cpt_dcache_dir_read++;
2141	m_cpt_dcache_data_write++;
2142	#endif
2143	}
2144	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2145	{
2146	r_dcache.read( paddr,
2147	&cache_rdata,
2148	&cache_way,
2149	&cache_set,
2150	&cache_word,
2151	&cache_state );
2152	#ifdef INSTRUMENTATION
2153	m_cpt_dcache_dir_read++;
2154	m_cpt_dcache_data_read++;
2155	#endif
2156	}
2157	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2158	{
2159	r_dcache.write( r_dcache_save_cache_way.read(),
2160	r_dcache_save_cache_set.read(),
2161	r_dcache_save_cache_word.read(),
2162	r_dcache_save_wdata.read(),
2163	r_dcache_save_be.read() );
2164	#ifdef INSTRUMENTATION
2165	m_cpt_dcache_data_write++;
2166	#endif
2167	}
2168	} // end dcache access
2169
2170	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2171	if ( r_dcache_updt_req.read() )
2172	{
2173	size_t way = r_dcache_save_cache_way.read();
2174	size_t set = r_dcache_save_cache_set.read();
2175
2176	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2177	{
2178	tlb_inval_required = true;
2179	r_dcache_tlb_inval_set = 0;
2180	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2181	(uint32_log2(m_dcache_words<<2));
2182	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2183	}
2184	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2185	{
2186	r_itlb.reset();
2187	r_dtlb.reset();
2188	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2189	}
2190
2191	#if DEBUG_DCACHE
2192	if ( m_debug_dcache_fsm )
2193	{
2194	std::cout << " <PROC " << name()
2195	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2196	<< " / WAY = " << r_dcache_save_cache_way.read()
2197	<< " / SET = " << r_dcache_save_cache_set.read()
2198	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2199	<< " / DATA = " << r_dcache_save_wdata.read()
2200	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2201	}
2202	#endif
2203	} // end test TLB inval
2204
2205	// Try WBUF update in P1 stage
2206	// Miss if the write request is non cacheable, and there is a pending
2207	// non cacheable write, or if the write buffer is full.
2208	if ( r_dcache_wbuf_req.read() )
2209	{
2210	// miss if write not cacheable, and previous non cacheable write registered
2211	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2212	{
2213	wbuf_write_miss = true;
2214	}
2215	else // try a registration into write buffer
2216	{
2217	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2218	r_dcache_save_be.read(),
2219	r_dcache_save_wdata.read(),
2220	r_dcache_save_cacheable.read() );
2221	#ifdef INSTRUMENTATION
2222	m_cpt_wbuf_write++;
2223	#endif
2224	if ( not wok ) // miss if write buffer full
2225	{
2226	wbuf_write_miss = true;
2227	}
2228	else // update the write_buffer state extension
2229	{
2230	if(not r_dcache_pending_unc_write.read())
2231	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2232	}
2233	}
2234	} // end WBUF update
2235
2236	// Computing the response to processor,
2237	// and the next value for r_dcache_fsm
2238
2239	// itlb/dtlb invalidation self-request
2240	if ( tlb_inval_required )
2241	{
2242	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2243	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2244	}
2245
2246	// coherence request (from CC_RECEIVE FSM)
2247	else if ( r_cc_receive_dcache_req.read() )
2248	{
2249	r_dcache_fsm = DCACHE_CC_CHECK;
2250	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2251	}
2252
2253	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2254	// we don't take the processor request, and registers
2255	// are frozen in case of wbuf_write_miss
2256	else if ( m_dreq.valid and not wbuf_write_miss )
2257	{
2258	// register processor request and DCACHE response
2259	r_dcache_save_vaddr = m_dreq.addr;
2260	r_dcache_save_be = m_dreq.be;
2261	r_dcache_save_wdata = m_dreq.wdata;
2262	r_dcache_save_paddr = paddr;
2263	r_dcache_save_cache_way = cache_way;
2264	r_dcache_save_cache_set = cache_set;
2265	r_dcache_save_cache_word = cache_word;
2266
2267	// READ XTN requests from processor
2268	// They are executed in this DCACHE_IDLE state.
2269	// The processor must not be in user mode
2270	if (m_dreq.type == iss_t::XTN_READ)
2271	{
2272	int xtn_opcode = (int)m_dreq.addr/4;
2273
2274	// checking processor mode:
2275	if (m_dreq.mode == iss_t::MODE_USER)
2276	{
2277	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2278	r_mmu_dbvar = m_dreq.addr;
2279	m_drsp.valid = true;
2280	m_drsp.error = true;
2281	m_drsp.rdata = 0;
2282	r_dcache_fsm = DCACHE_IDLE;
2283	}
2284	else
2285	{
2286	switch( xtn_opcode )
2287	{
2288	case iss_t::XTN_INS_ERROR_TYPE:
2289	m_drsp.rdata = r_mmu_ietr.read();
2290	m_drsp.valid = true;
2291	m_drsp.error = false;
2292	break;
2293
2294	case iss_t::XTN_DATA_ERROR_TYPE:
2295	m_drsp.rdata = r_mmu_detr.read();
2296	m_drsp.valid = true;
2297	m_drsp.error = false;
2298	break;
2299
2300	case iss_t::XTN_INS_BAD_VADDR:
2301	m_drsp.rdata = r_mmu_ibvar.read();
2302	m_drsp.valid = true;
2303	m_drsp.error = false;
2304	break;
2305
2306	case iss_t::XTN_DATA_BAD_VADDR:
2307	m_drsp.rdata = r_mmu_dbvar.read();
2308	m_drsp.valid = true;
2309	m_drsp.error = false;
2310	break;
2311
2312	case iss_t::XTN_PTPR:
2313	m_drsp.rdata = r_mmu_ptpr.read();
2314	m_drsp.valid = true;
2315	m_drsp.error = false;
2316	break;
2317
2318	case iss_t::XTN_TLB_MODE:
2319	m_drsp.rdata = r_mmu_mode.read();
2320	m_drsp.valid = true;
2321	m_drsp.error = false;
2322	break;
2323
2324	case iss_t::XTN_MMU_PARAMS:
2325	m_drsp.rdata = r_mmu_params;
2326	m_drsp.valid = true;
2327	m_drsp.error = false;
2328	break;
2329
2330	case iss_t::XTN_MMU_RELEASE:
2331	m_drsp.rdata = r_mmu_release;
2332	m_drsp.valid = true;
2333	m_drsp.error = false;
2334	break;
2335
2336	case iss_t::XTN_MMU_WORD_LO:
2337	m_drsp.rdata = r_mmu_word_lo.read();
2338	m_drsp.valid = true;
2339	m_drsp.error = false;
2340	break;
2341
2342	case iss_t::XTN_MMU_WORD_HI:
2343	m_drsp.rdata = r_mmu_word_hi.read();
2344	m_drsp.valid = true;
2345	m_drsp.error = false;
2346	break;
2347
2348	default:
2349	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2350	r_mmu_dbvar = m_dreq.addr;
2351	m_drsp.valid = true;
2352	m_drsp.error = true;
2353	m_drsp.rdata = 0;
2354	break;
2355	} // end switch xtn_opcode
2356	} // end else
2357	} // end if XTN_READ
2358
2359	// Handling WRITE XTN requests from processor.
2360	// They are not executed in this DCACHE_IDLE state
2361	// if they require access to the caches or the TLBs
2362	// that are already accessed.
2363	// Caches can be invalidated or flushed in user mode,
2364	// and the sync instruction can be executed in user mode
2365	else if (m_dreq.type == iss_t::XTN_WRITE)
2366	{
2367	int xtn_opcode = (int)m_dreq.addr/4;
2368	r_dcache_xtn_opcode = xtn_opcode;
2369
2370	// checking processor mode:
2371	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2372	(xtn_opcode != iss_t:: XTN_SYNC) &&
2373	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2374	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2375	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2376	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2377	{
2378	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2379	r_mmu_dbvar = m_dreq.addr;
2380	m_drsp.valid = true;
2381	m_drsp.error = true;
2382	m_drsp.rdata = 0;
2383	r_dcache_fsm = DCACHE_IDLE;
2384	}
2385	else
2386	{
2387	switch( xtn_opcode )
2388	{
2389	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2390	r_dcache_xtn_req = true;
2391	r_dcache_fsm = DCACHE_XTN_SWITCH;
2392	break;
2393
2394	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2395	r_mmu_mode = m_dreq.wdata;
2396	m_drsp.valid = true;
2397	r_dcache_fsm = DCACHE_IDLE;
2398	break;
2399
2400	case iss_t::XTN_DTLB_INVAL: // dtlb access
2401	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2402	break;
2403
2404	case iss_t::XTN_ITLB_INVAL: // itlb access
2405	r_dcache_xtn_req = true;
2406	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2407	break;
2408
2409	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2410	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2411	break;
2412
2413	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2414	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2415	if (sizeof(paddr_t) <= 32)
2416	{
2417	assert(r_mmu_word_hi.read() == 0 &&
2418	"high bits should be 0 for 32bit paddr");
2419	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2420	}
2421	else
2422	{
2423	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2424	(paddr_t)r_mmu_word_lo.read();
2425	}
2426	break;
2427
2428	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2429	r_dcache_flush_count = 0;
2430	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2431	break;
2432
2433	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2434	r_dcache_xtn_req = true;
2435	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2436	break;
2437
2438	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2439	r_dcache_xtn_req = true;
2440	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2441	break;
2442
2443	case iss_t::XTN_ICACHE_FLUSH: // icache access
2444	r_dcache_xtn_req = true;
2445	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2446	break;
2447
2448	case iss_t::XTN_SYNC: // wait until write buffer empty
2449	r_dcache_fsm = DCACHE_XTN_SYNC;
2450	break;
2451
2452	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2453	r_mmu_word_lo = m_dreq.wdata;
2454	m_drsp.valid = true;
2455	r_dcache_fsm = DCACHE_IDLE;
2456	break;
2457
2458	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2459	r_mmu_word_hi = m_dreq.wdata;
2460	m_drsp.valid = true;
2461	r_dcache_fsm = DCACHE_IDLE;
2462	break;
2463
2464	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2465	r_dcache_llsc_valid = false;
2466	m_drsp.valid = true;
2467	r_dcache_fsm = DCACHE_IDLE;
2468	break;
2469
2470	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2471	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2472	m_drsp.valid = true;
2473	r_dcache_fsm = DCACHE_IDLE;
2474	break;
2475
2476	default:
2477	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2478	r_mmu_dbvar = m_dreq.addr;
2479	m_drsp.valid = true;
2480	m_drsp.error = true;
2481	r_dcache_fsm = DCACHE_IDLE;
2482	break;
2483	} // end switch xtn_opcode
2484	} // end else
2485	} // end if XTN_WRITE
2486
2487	// Handling processor requests to address space (READ/WRITE/LL/SC)
2488	// The dtlb and dcache can be activated or not.
2489	// We compute the cacheability, and check processor request validity:
2490	// - If DTLB not activated : cacheability is defined by the segment table,
2491	// and there is no access rights checking.
2492	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2493	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2494	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2495	else
2496	{
2497	bool valid_req;
2498	bool cacheable;
2499
2500	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2501	{
2502	valid_req = true;
2503
2504	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2505	else cacheable = m_cacheability_table[m_dreq.addr];
2506	}
2507	else // dtlb activated
2508	{
2509	if ( tlb_hit ) // tlb hit
2510	{
2511	// cacheability
2512	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2513	else cacheable = tlb_flags.c;
2514
2515	// access rights checking
2516	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2517	{
2518	if ( (m_dreq.type == iss_t::DATA_READ) or
2519	(m_dreq.type == iss_t::DATA_LL) )
2520	{
2521	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2522	}
2523	else
2524	{
2525	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2526	}
2527	valid_req = false;
2528	r_mmu_dbvar = m_dreq.addr;
2529	m_drsp.valid = true;
2530	m_drsp.error = true;
2531	m_drsp.rdata = 0;
2532	#if DEBUG_DCACHE
2533	if ( m_debug_dcache_fsm )
2534	{
2535	std::cout << " <PROC " << name()
2536	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2537	}
2538	#endif
2539	}
2540	else if ( not tlb_flags.w and
2541	((m_dreq.type == iss_t::DATA_WRITE) or
2542	(m_dreq.type == iss_t::DATA_SC)) )
2543	{
2544	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2545	valid_req = false;
2546	r_mmu_dbvar = m_dreq.addr;
2547	m_drsp.valid = true;
2548	m_drsp.error = true;
2549	m_drsp.rdata = 0;
2550	#if DEBUG_DCACHE
2551	if ( m_debug_dcache_fsm )
2552	{
2553	std::cout << " <PROC " << name()
2554	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2555	}
2556	#endif
2557	}
2558	else
2559	{
2560	valid_req = true;
2561	}
2562	}
2563	else // tlb miss
2564	{
2565	valid_req = false;
2566	r_dcache_tlb_vaddr = m_dreq.addr;
2567	r_dcache_tlb_ins = false;
2568	r_dcache_fsm = DCACHE_TLB_MISS;
2569	}
2570	} // end DTLB activated
2571
2572	if ( valid_req ) // processor request is valid after TLB check
2573	{
2574	r_dcache_save_cacheable = cacheable;
2575
2576	// READ request
2577	// The read requests are taken only if there is no cache update.
2578	// We request a VCI transaction to CMD FSM if miss or uncachable
2579	if ( ((m_dreq.type == iss_t::DATA_READ))
2580	and not r_dcache_updt_req.read() )
2581	{
2582	if ( cacheable ) // cacheable read
2583	{
2584	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2585	{
2586	#ifdef INSTRUMENTATION
2587	m_cpt_dcache_miss++;
2588	#endif
2589	// request a VCI DMISS transaction
2590	r_dcache_vci_paddr = paddr;
2591	r_dcache_vci_miss_req = true;
2592	r_dcache_miss_type = PROC_MISS;
2593	r_dcache_fsm = DCACHE_MISS_SELECT;
2594	#if DEBUG_DCACHE
2595	if ( m_debug_dcache_fsm )
2596	{
2597	std::cout << " <PROC " << name()
2598	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2599	}
2600	#endif
2601	}
2602	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2603	{
2604	// stalled until cleanup is acknowledged
2605	r_dcache_fsm = DCACHE_IDLE;
2606	}
2607	else // cache hit
2608	{
2609	#ifdef INSTRUMENTATION
2610	m_cpt_data_read++;
2611	#endif
2612	// returns data to processor
2613	m_drsp.valid = true;
2614	m_drsp.error = false;
2615	m_drsp.rdata = cache_rdata;
2616	#if DEBUG_DCACHE
2617	if ( m_debug_dcache_fsm )
2618	{
2619	std::cout << " <PROC " << name()
2620	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2621	}
2622	#endif
2623	}
2624	}
2625	else // uncacheable read
2626	{
2627	r_dcache_vci_paddr = paddr;
2628	r_dcache_vci_unc_be = m_dreq.be;
2629	r_dcache_vci_unc_req = true;
2630	r_dcache_fsm = DCACHE_UNC_WAIT;
2631	#if DEBUG_DCACHE
2632	if ( m_debug_dcache_fsm )
2633	{
2634	std::cout << " <PROC " << name()
2635	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2636	}
2637	#endif
2638	}
2639	} // end READ
2640
2641	// LL request (non cachable)
2642	// We request a VCI LL transaction to CMD FSM and register
2643	// the LL/SC operation in llsc buffer.
2644	else if (m_dreq.type == iss_t::DATA_LL)
2645	{
2646	// register paddr in LLSC buffer
2647	r_dcache_llsc_paddr = paddr;
2648	r_dcache_llsc_count = LLSC_TIMEOUT;
2649	r_dcache_llsc_valid = true;
2650
2651	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2652	r_dcache_vci_ll_req = true;
2653	r_dcache_vci_paddr = paddr;
2654	r_dcache_ll_rsp_count = 0;
2655	r_dcache_fsm = DCACHE_LL_WAIT;
2656
2657	}// end LL
2658
2659	// WRITE request:
2660	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2661	// the processor and set the Dirty bit before handling the write request,
2662	// going to the DCACHE_DIRTY_GT_PTE state.
2663	// If we don't need to set the Dirty bit, we can acknowledge
2664	// the processor request, as the write arguments (including the
2665	// physical address) are registered in r_dcache_save registers,
2666	// and the write will be done in the P1 pipeline stage.
2667	else if ( m_dreq.type == iss_t::DATA_WRITE )
2668	{
2669	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2670	and not tlb_flags.d ) // Dirty bit must be set
2671	{
2672	// The PTE physical address is obtained from the nline value (dtlb),
2673	// and from the virtual address (word index)
2674	if ( tlb_flags.b ) // PTE1
2675	{
2676	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2677	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2678	}
2679	else // PTE2
2680	{
2681	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2682	(paddr_t)((m_dreq.addr>>9) & 0x38);
2683	}
2684	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2685	}
2686	else // Write request accepted
2687	{
2688	#ifdef INSTRUMENTATION
2689	m_cpt_data_write++;
2690	#endif
2691	// cleaning llsc buffer if address matching
2692	if ( paddr == r_dcache_llsc_paddr.read() )
2693	r_dcache_llsc_valid = false;
2694
2695	// response to processor
2696	m_drsp.valid = true;
2697
2698	// activating P1 stage
2699	wbuf_request = true;
2700	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2701	}
2702	} // end WRITE
2703
2704	// SC request:
2705	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2706	// the processor and set the Dirty bit before handling the write request,
2707	// going to the DCACHE_DIRTY_GT_PTE state.
2708	// If we don't need to set the Dirty bit, we test the llsc buffer:
2709	// If failure, we send a negative response to processor.
2710	// If success, we request a SC transaction to CMD FSM and go
2711	// to DCACHE_SC_WAIT state.
2712	// We don't check a possible write hit in dcache, as the cache update
2713	// is done by the coherence transaction induced by the SC...
2714	else if ( m_dreq.type == iss_t::DATA_SC )
2715	{
2716	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2717	and not tlb_flags.d ) // Dirty bit must be set
2718	{
2719	// The PTE physical address is obtained from the nline value (dtlb),
2720	// and the word index (virtual address)
2721	if ( tlb_flags.b ) // PTE1
2722	{
2723	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2724	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2725	}
2726	else // PTE2
2727	{
2728	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2729	(paddr_t)((m_dreq.addr>>9) & 0x38);
2730	}
2731	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2732	m_drsp.valid = false;
2733	m_drsp.error = false;
2734	m_drsp.rdata = 0;
2735	}
2736	else // SC request accepted
2737	{
2738	#ifdef INSTRUMENTATION
2739	m_cpt_data_sc++;
2740	#endif
2741	// checking local success
2742	if( r_dcache_llsc_valid.read() and
2743	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2744	{
2745	// request an SC CMD and go to DCACHE_SC_WAIT state
2746	r_dcache_vci_paddr = paddr;
2747	r_dcache_vci_sc_req = true;
2748	r_dcache_vci_sc_data = m_dreq.wdata;
2749	r_dcache_fsm = DCACHE_SC_WAIT;
2750	}
2751	else // local fail
2752	{
2753	m_drsp.valid = true;
2754	m_drsp.error = false;
2755	m_drsp.rdata = 0x1;
2756	}
2757	}
2758	} // end SC
2759	} // end valid_req
2760	} // end if read/write/ll/sc request
2761	} // end processor request
2762
2763	// itlb miss request
2764	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2765	{
2766	r_dcache_tlb_ins = true;
2767	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2768	r_dcache_fsm = DCACHE_TLB_MISS;
2769	}
2770
2771	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2772	r_dcache_updt_req = updt_request;
2773	r_dcache_wbuf_req = wbuf_request or
2774	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2775	break;
2776	}
2777	/////////////////////
2778	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2779	// Input arguments are:
2780	// - r_dcache_tlb_vaddr
2781	// - r_dcache_tlb_ins (true when itlb miss)
2782	// The sub-fsm access the dcache to find the missing TLB entry,
2783	// and activates the cache miss procedure in case of miss.
2784	// It bypass the first level page table access if possible.
2785	// It uses atomic access to update the R/L access bits
2786	// in the page table if required.
2787	// It directly updates the itlb or dtlb, and writes into the
2788	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2789	{
2790	uint32_t ptba = 0;
2791	bool bypass;
2792	paddr_t pte_paddr;
2793
2794	// evaluate bypass in order to skip first level page table access
2795	if ( r_dcache_tlb_ins.read() ) // itlb miss
2796	{
2797	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2798	}
2799	else // dtlb miss
2800	{
2801	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2802	}
2803
2804	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2805	{
2806	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2807	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2808	r_dcache_tlb_paddr = pte_paddr;
2809	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2810	}
2811	else // Try to read PTE2 in dcache
2812	{
2813	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2814	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2815	r_dcache_tlb_paddr = pte_paddr;
2816	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2817	}
2818
2819	#if DEBUG_DCACHE
2820	if ( m_debug_dcache_fsm )
2821	{
2822	if ( r_dcache_tlb_ins.read() )
2823	{
2824	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2825	}
2826	else
2827	{
2828	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2829	}
2830	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2831	<< " / BYPASS = " << bypass
2832	<< " / PTE_ADR = " << pte_paddr << std::endl;
2833	}
2834	#endif
2835
2836	break;
2837	}
2838	/////////////////////////
2839	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2840	{
2841	// coherence request (from CC_RECEIVE FSM)
2842	if ( r_cc_receive_dcache_req.read() )
2843	{
2844	r_dcache_fsm = DCACHE_CC_CHECK;
2845	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2846	break;
2847	}
2848
2849	uint32_t entry;
2850	size_t way;
2851	size_t set;
2852	size_t word;
2853	int cache_state;
2854	r_dcache.read( r_dcache_tlb_paddr.read(),
2855	&entry,
2856	&way,
2857	&set,
2858	&word,
2859	&cache_state );
2860	#ifdef INSTRUMENTATION
2861	m_cpt_dcache_data_read++;
2862	m_cpt_dcache_dir_read++;
2863	#endif
2864	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2865	{
2866	if ( not (entry & PTE_V_MASK) ) // unmapped
2867	{
2868	if ( r_dcache_tlb_ins.read() )
2869	{
2870	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2871	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2872	r_icache_tlb_miss_req = false;
2873	r_icache_tlb_rsp_error = true;
2874	}
2875	else
2876	{
2877	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2878	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2879	m_drsp.valid = true;
2880	m_drsp.error = true;
2881	}
2882	r_dcache_fsm = DCACHE_IDLE;
2883
2884	#if DEBUG_DCACHE
2885	if ( m_debug_dcache_fsm )
2886	{
2887	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2888	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2889	<< std::dec << " / way = " << way
2890	<< std::dec << " / set = " << set
2891	<< std::dec << " / word = " << word
2892	<< std::hex << " / PTE1 = " << entry << std::endl;
2893	}
2894	#endif
2895
2896	}
2897	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2898	{
2899	// mark the cache line ac containing a PTD
2900	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2901
2902	// register bypass
2903	if ( r_dcache_tlb_ins.read() ) // itlb
2904	{
2905	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2906	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2907	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2908	}
2909	else // dtlb
2910	{
2911	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2912	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2913	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2914	}
2915	r_dcache_tlb_paddr =
2916	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2917	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2918	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2919
2920	#if DEBUG_DCACHE
2921	if ( m_debug_dcache_fsm )
2922	{
2923	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2924	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2925	<< std::dec << " / way = " << way
2926	<< std::dec << " / set = " << set
2927	<< std::dec << " / word = " << word
2928	<< std::hex << " / PTD = " << entry << std::endl;
2929	}
2930	#endif
2931	}
2932	else // PTE1 : we must update the TLB
2933	{
2934	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2935	r_dcache_tlb_pte_flags = entry;
2936	r_dcache_tlb_cache_way = way;
2937	r_dcache_tlb_cache_set = set;
2938	r_dcache_tlb_cache_word = word;
2939	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2940
2941	#if DEBUG_DCACHE
2942	if ( m_debug_dcache_fsm )
2943	{
2944	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2945	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2946	<< std::dec << " / way = " << way
2947	<< std::dec << " / set = " << set
2948	<< std::dec << " / word = " << word
2949	<< std::hex << " / PTE1 = " << entry << std::endl;
2950	}
2951	#endif
2952	}
2953	}
2954	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2955	{
2956	// stalled until cleanup is acknowledged
2957	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2958	}
2959	else // we must load the missing cache line in dcache
2960	{
2961	r_dcache_vci_miss_req = true;
2962	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2963	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2964	r_dcache_miss_type = PTE1_MISS;
2965	r_dcache_fsm = DCACHE_MISS_SELECT;
2966
2967	#if DEBUG_DCACHE
2968	if ( m_debug_dcache_fsm )
2969	{
2970	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2971	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2972	}
2973	#endif
2974	}
2975	break;
2976	}
2977	////////////////////////////
2978	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2979	{
2980	size_t way;
2981	size_t set;
2982
2983	if ( r_dcache_tlb_ins.read() )
2984	{
2985	r_itlb.select( r_dcache_tlb_vaddr.read(),
2986	true, // PTE1
2987	&way,
2988	&set );
2989	#ifdef INSTRUMENTATION
2990	m_cpt_itlb_read++;
2991	#endif
2992	}
2993	else
2994	{
2995	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2996	true, // PTE1
2997	&way,
2998	&set );
2999	#ifdef INSTRUMENTATION
3000	m_cpt_dtlb_read++;
3001	#endif
3002	}
3003	r_dcache_tlb_way = way;
3004	r_dcache_tlb_set = set;
3005	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3006
3007	#if DEBUG_DCACHE
3008	if ( m_debug_dcache_fsm )
3009	{
3010	if ( r_dcache_tlb_ins.read() )
3011	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3012	else
3013	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3014	std::cout << " way = " << std::dec << way
3015	<< " / set = " << set << std::endl;
3016	}
3017	#endif
3018	break;
3019	}
3020	//////////////////////////
3021	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3022	// - if L/R bit already set, exit the sub-fsm.
3023	// - if not, we update the page table but we dont write
3024	// neither in DCACHE, nor in TLB, as this will be done by
3025	// the coherence mechanism.
3026	{
3027	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3028	uint32_t pte = r_dcache_tlb_pte_flags.read();
3029	bool pt_updt = false;
3030	bool local = true;
3031
3032	// We should compute the access locality:
3033	// The PPN MSB bits define the destination cluster index.
3034	// The m_srcid MSB bits define the source cluster index.
3035	// The number of bits to compare depends on the number of clusters,
3036	// and can be obtained in the mapping table.
3037	// As long as this computation is not done, all access are local.
3038
3039	if ( local ) // local access
3040	{
3041	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3042	{
3043	pt_updt = true;
3044	r_dcache_vci_cas_old = pte;
3045	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3046	pte = pte \| PTE_L_MASK;
3047	r_dcache_tlb_pte_flags = pte;
3048	}
3049	}
3050	else // remote access
3051	{
3052	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3053	{
3054	pt_updt = true;
3055	r_dcache_vci_cas_old = pte;
3056	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3057	pte = pte \| PTE_R_MASK;
3058	r_dcache_tlb_pte_flags = pte;
3059	}
3060	}
3061
3062	if ( not pt_updt ) // update TLB and return
3063	{
3064	if ( r_dcache_tlb_ins.read() )
3065	{
3066	r_itlb.write( true, // 2M page
3067	pte,
3068	0, // argument unused for a PTE1
3069	r_dcache_tlb_vaddr.read(),
3070	r_dcache_tlb_way.read(),
3071	r_dcache_tlb_set.read(),
3072	nline );
3073	#ifdef INSTRUMENTATION
3074	m_cpt_itlb_write++;
3075	#endif
3076
3077	#if DEBUG_DCACHE
3078	if ( m_debug_dcache_fsm )
3079	{
3080	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3081	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3082	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3083	r_itlb.printTrace();
3084	}
3085	#endif
3086	}
3087	else
3088	{
3089	r_dtlb.write( true, // 2M page
3090	pte,
3091	0, // argument unused for a PTE1
3092	r_dcache_tlb_vaddr.read(),
3093	r_dcache_tlb_way.read(),
3094	r_dcache_tlb_set.read(),
3095	nline );
3096	#ifdef INSTRUMENTATION
3097	m_cpt_dtlb_write++;
3098	#endif
3099
3100	#if DEBUG_DCACHE
3101	if ( m_debug_dcache_fsm )
3102	{
3103	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3104	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3105	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3106	r_dtlb.printTrace();
3107	}
3108	#endif
3109	}
3110	r_dcache_fsm = DCACHE_TLB_RETURN;
3111	}
3112	else // update page table but not TLB
3113	{
3114	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3115
3116	#if DEBUG_DCACHE
3117	if ( m_debug_dcache_fsm )
3118	{
3119	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3120	<< std::endl;
3121	}
3122	#endif
3123	}
3124	break;
3125	}
3126	/////////////////////////
3127	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3128	{
3129	// coherence request (from CC_RECEIVE FSM)
3130	if ( r_cc_receive_dcache_req.read() )
3131	{
3132	r_dcache_fsm = DCACHE_CC_CHECK;
3133	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3134	break;
3135	}
3136
3137	uint32_t pte_flags;
3138	uint32_t pte_ppn;
3139	size_t way;
3140	size_t set;
3141	size_t word;
3142	int cache_state;
3143
3144	r_dcache.read( r_dcache_tlb_paddr.read(),
3145	&pte_flags,
3146	&pte_ppn,
3147	&way,
3148	&set,
3149	&word,
3150	&cache_state );
3151	#ifdef INSTRUMENTATION
3152	m_cpt_dcache_data_read++;
3153	m_cpt_dcache_dir_read++;
3154	#endif
3155	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3156	{
3157	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3158	{
3159	if ( r_dcache_tlb_ins.read() )
3160	{
3161	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3162	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3163	r_icache_tlb_miss_req = false;
3164	r_icache_tlb_rsp_error = true;
3165	}
3166	else
3167	{
3168	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3169	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3170	m_drsp.valid = true;
3171	m_drsp.error = true;
3172	}
3173	r_dcache_fsm = DCACHE_IDLE;
3174
3175	#if DEBUG_DCACHE
3176	if ( m_debug_dcache_fsm )
3177	{
3178	std::cout << " <PROC " << name()
3179	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3180	<< " PTE_FLAGS = " << std::hex << pte_flags
3181	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3182	}
3183	#endif
3184	}
3185	else // mapped : we must update the TLB
3186	{
3187	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3188	r_dcache_tlb_pte_flags = pte_flags;
3189	r_dcache_tlb_pte_ppn = pte_ppn;
3190	r_dcache_tlb_cache_way = way;
3191	r_dcache_tlb_cache_set = set;
3192	r_dcache_tlb_cache_word = word;
3193	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3194
3195	#if DEBUG_DCACHE
3196	if ( m_debug_dcache_fsm )
3197	{
3198	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3199	<< " PTE_FLAGS = " << std::hex << pte_flags
3200	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3201	}
3202	#endif
3203	}
3204	}
3205	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3206	{
3207	// stalled until cleanup is acknowledged
3208	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3209	}
3210	else // we must load the missing cache line in dcache
3211	{
3212	r_dcache_fsm = DCACHE_MISS_SELECT;
3213	r_dcache_vci_miss_req = true;
3214	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3215	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3216	r_dcache_miss_type = PTE2_MISS;
3217
3218	#if DEBUG_DCACHE
3219	if ( m_debug_dcache_fsm )
3220	{
3221	std::cout << " <PROC " << name()
3222	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3223	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3224	}
3225	#endif
3226	}
3227	break;
3228	}
3229	////////////////////////////
3230	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3231	{
3232	size_t way;
3233	size_t set;
3234
3235	if ( r_dcache_tlb_ins.read() )
3236	{
3237	r_itlb.select( r_dcache_tlb_vaddr.read(),
3238	false, // PTE2
3239	&way,
3240	&set );
3241	#ifdef INSTRUMENTATION
3242	m_cpt_itlb_read++;
3243	#endif
3244	}
3245	else
3246	{
3247	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3248	false, // PTE2
3249	&way,
3250	&set );
3251	#ifdef INSTRUMENTATION
3252	m_cpt_dtlb_read++;
3253	#endif
3254	}
3255
3256	#if DEBUG_DCACHE
3257	if ( m_debug_dcache_fsm )
3258	{
3259	if ( r_dcache_tlb_ins.read() )
3260	std::cout << " <PROC " << name()
3261	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3262	else
3263	std::cout << " <PROC " << name()
3264	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3265	std::cout << " way = " << std::dec << way
3266	<< " / set = " << set << std::endl;
3267	}
3268	#endif
3269	r_dcache_tlb_way = way;
3270	r_dcache_tlb_set = set;
3271	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3272	break;
3273	}
3274	//////////////////////////
3275	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3276	// - if L/R bit already set, exit the sub-fsm.
3277	// - if not, we update the page table but we dont write
3278	// neither in DCACHE, nor in TLB, as this will be done by
3279	// the coherence mechanism.
3280	{
3281	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3282	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3283	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3284	bool pt_updt = false;
3285	bool local = true;
3286
3287	// We should compute the access locality:
3288	// The PPN MSB bits define the destination cluster index.
3289	// The m_srcid MSB bits define the source cluster index.
3290	// The number of bits to compare depends on the number of clusters,
3291	// and can be obtained in the mapping table.
3292	// As long as this computation is not done, all access are local.
3293
3294	if ( local ) // local access
3295	{
3296	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3297	{
3298	pt_updt = true;
3299	r_dcache_vci_cas_old = pte_flags;
3300	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3301	pte_flags = pte_flags \| PTE_L_MASK;
3302	r_dcache_tlb_pte_flags = pte_flags;
3303	}
3304	}
3305	else // remote access
3306	{
3307	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3308	{
3309	pt_updt = true;
3310	r_dcache_vci_cas_old = pte_flags;
3311	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3312	pte_flags = pte_flags \| PTE_R_MASK;
3313	r_dcache_tlb_pte_flags = pte_flags;
3314	}
3315	}
3316
3317	if ( not pt_updt ) // update TLB
3318	{
3319	if ( r_dcache_tlb_ins.read() )
3320	{
3321	r_itlb.write( false, // 4K page
3322	pte_flags,
3323	pte_ppn,
3324	r_dcache_tlb_vaddr.read(),
3325	r_dcache_tlb_way.read(),
3326	r_dcache_tlb_set.read(),
3327	nline );
3328	#ifdef INSTRUMENTATION
3329	m_cpt_itlb_write++;
3330	#endif
3331
3332	#if DEBUG_DCACHE
3333	if ( m_debug_dcache_fsm )
3334	{
3335	std::cout << " <PROC " << name()
3336	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3337	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3338	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3339	r_itlb.printTrace();
3340	}
3341	#endif
3342	}
3343	else
3344	{
3345	r_dtlb.write( false, // 4K page
3346	pte_flags,
3347	pte_ppn,
3348	r_dcache_tlb_vaddr.read(),
3349	r_dcache_tlb_way.read(),
3350	r_dcache_tlb_set.read(),
3351	nline );
3352	#ifdef INSTRUMENTATION
3353	m_cpt_dtlb_write++;
3354	#endif
3355
3356	#if DEBUG_DCACHE
3357	if ( m_debug_dcache_fsm )
3358	{
3359	std::cout << " <PROC " << name()
3360	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3361	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3362	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3363	r_dtlb.printTrace();
3364	}
3365	#endif
3366
3367	}
3368	r_dcache_fsm = DCACHE_TLB_RETURN;
3369	}
3370	else // update page table but not TLB
3371	{
3372	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3373
3374	#if DEBUG_DCACHE
3375	if ( m_debug_dcache_fsm )
3376	{
3377	std::cout << " <PROC " << name()
3378	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3379	}
3380	#endif
3381	}
3382	break;
3383	}
3384	////////////////////////
3385	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3386	{
3387	#if DEBUG_DCACHE
3388	if ( m_debug_dcache_fsm )
3389	{
3390	std::cout << " <PROC " << name()
3391	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3392	}
3393	#endif
3394	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3395	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3396
3397	// checking llsc reservation buffer
3398	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3399	r_dcache_llsc_valid = false;
3400
3401	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3402	r_dcache_vci_cas_req = true;
3403	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3404	break;
3405	}
3406	////////////////////////
3407	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3408	// We consume the response in rsp FIFO,
3409	// and exit the sub-fsm, but we don't
3410	// analyse the response, because we don't
3411	// care if the L/R bit update is not done.
3412	// We must take the coherence requests because
3413	// there is a risk of dead-lock
3414
3415	{
3416	// coherence request (from CC_RECEIVE FSM)
3417	if ( r_cc_receive_dcache_req.read() )
3418	{
3419	r_dcache_fsm = DCACHE_CC_CHECK;
3420	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3421	break;
3422	}
3423
3424	if ( r_vci_rsp_data_error.read() ) // bus error
3425	{
3426	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3427	std::cout << "This should not happen in this state" << std::endl;
3428	exit(0);
3429	}
3430	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3431	{
3432	#if DEBUG_DCACHE
3433	if ( m_debug_dcache_fsm )
3434	{
3435	std::cout << " <PROC " << name()
3436	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3437	}
3438	#endif
3439	vci_rsp_fifo_dcache_get = true;
3440	r_dcache_fsm = DCACHE_TLB_RETURN;
3441	}
3442	break;
3443	}
3444	///////////////////////
3445	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3446	{
3447	#if DEBUG_DCACHE
3448	if ( m_debug_dcache_fsm )
3449	{
3450	std::cout << " <PROC " << name()
3451	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3452	}
3453	#endif
3454	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3455	r_dcache_fsm = DCACHE_IDLE;
3456	break;
3457	}
3458	///////////////////////
3459	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3460	// and both itlb and dtlb must be flushed.
3461	// Caution : the itlb miss requests must be taken
3462	// to avoid dead-lock in case of simultaneous ITLB miss
3463	{
3464	// itlb miss request
3465	if ( r_icache_tlb_miss_req.read() )
3466	{
3467	r_dcache_tlb_ins = true;
3468	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3469	r_dcache_fsm = DCACHE_TLB_MISS;
3470	break;
3471	}
3472
3473	if ( not r_dcache_xtn_req.read() )
3474	{
3475	r_dtlb.flush();
3476	r_mmu_ptpr = m_dreq.wdata;
3477	r_dcache_fsm = DCACHE_IDLE;
3478	m_drsp.valid = true;
3479	}
3480	break;
3481	}
3482	/////////////////////
3483	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3484	// The coherence request must be taken
3485	// as there is a risk of dead-lock
3486	{
3487	// coherence request (from CC_RECEIVE FSM)
3488	if ( r_cc_receive_dcache_req.read() )
3489	{
3490	r_dcache_fsm = DCACHE_CC_CHECK;
3491	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3492	}
3493
3494	if ( r_wbuf.empty() )
3495	{
3496	m_drsp.valid = true;
3497	r_dcache_fsm = DCACHE_IDLE;
3498	}
3499	break;
3500	}
3501	////////////////////////
3502	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3503	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3504	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3505	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3506	// and because it can exist a simultaneous ITLB miss
3507	{
3508	// coherence request (from CC_RECEIVE FSM)
3509	if ( r_cc_receive_dcache_req.read() )
3510	{
3511	r_dcache_fsm = DCACHE_CC_CHECK;
3512	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3513	break;
3514	}
3515
3516	// itlb miss request
3517	if ( r_icache_tlb_miss_req.read() )
3518	{
3519	r_dcache_tlb_ins = true;
3520	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3521	r_dcache_fsm = DCACHE_TLB_MISS;
3522	break;
3523	}
3524
3525	// test if XTN request to icache completed
3526	if ( not r_dcache_xtn_req.read() )
3527	{
3528	r_dcache_fsm = DCACHE_IDLE;
3529	m_drsp.valid = true;
3530	}
3531	break;
3532	}
3533	/////////////////////////
3534	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3535	// r_dcache_flush_count as a slot counter,
3536	// looping in this state until all slots have been visited.
3537	// It can require two cycles per slot:
3538	// We test here the slot state, and make the actual inval
3539	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3540	// A cleanup request is generated for each valid line.
3541	// returns to IDLE and flush TLBs when last slot
3542	{
3543	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3544	{
3545	int state;
3546	uint32_t tag;
3547	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3548	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3549
3550	#ifdef INSTRUMENTATION
3551	m_cpt_dcache_dir_read++;
3552	#endif
3553	r_dcache.read_dir( way,
3554	set,
3555	&tag,
3556	&state );
3557
3558	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3559	{
3560	// request cleanup
3561	r_dcache_cc_send_req = true;
3562	r_dcache_cc_send_nline = tag * m_dcache_sets;
3563	r_dcache_cc_send_way = way;
3564	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3565
3566	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3567	r_dcache_miss_way = way;
3568	r_dcache_miss_set = set;
3569	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3570	}
3571	else if ( r_dcache_flush_count.read() ==
3572	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3573	{
3574	r_dtlb.reset();
3575	r_itlb.reset();
3576	r_dcache_fsm = DCACHE_IDLE;
3577	m_drsp.valid = true;
3578	}
3579
3580	// saturation counter
3581	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3582	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3583	}
3584	break;
3585	}
3586	////////////////////////////
3587	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3588	// and reset directory extension.
3589	// returns to IDLE and flush TLBs when last slot
3590	{
3591	size_t way = r_dcache_miss_way.read();
3592	size_t set = r_dcache_miss_set.read();
3593
3594	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3595	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3596
3597	#ifdef INSTRUMENTATION
3598	m_cpt_dcache_dir_write++;
3599	#endif
3600	r_dcache.write_dir( 0,
3601	way,
3602	set,
3603	CACHE_SLOT_STATE_ZOMBI );
3604
3605	if ( r_dcache_flush_count.read() ==
3606	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3607	{
3608	r_dtlb.reset();
3609	r_itlb.reset();
3610	r_dcache_fsm = DCACHE_IDLE;
3611	m_drsp.valid = true;
3612	}
3613	else
3614	{
3615	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3616	}
3617	break;
3618	}
3619	/////////////////////////
3620	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3621	{
3622	r_dtlb.inval(r_dcache_save_wdata.read());
3623	r_dcache_fsm = DCACHE_IDLE;
3624	m_drsp.valid = true;
3625	break;
3626	}
3627	////////////////////////////
3628	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3629	// requires 3 cycles: access tlb, read cache, inval cache
3630	// we compute the physical address in this state
3631	{
3632	paddr_t paddr;
3633	bool hit;
3634
3635	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3636	{
3637
3638	#ifdef INSTRUMENTATION
3639	m_cpt_dtlb_read++;
3640	#endif
3641	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3642	&paddr );
3643	}
3644	else // dtlb not activated
3645	{
3646	paddr = (paddr_t)r_dcache_save_wdata.read();
3647	hit = true;
3648	}
3649
3650	if ( hit ) // tlb hit
3651	{
3652	r_dcache_save_paddr = paddr;
3653	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3654	}
3655	else // tlb miss
3656	{
3657
3658	#ifdef INSTRUMENTATION
3659	m_cpt_dtlb_miss++;
3660	#endif
3661	r_dcache_tlb_ins = false; // dtlb
3662	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3663	r_dcache_fsm = DCACHE_TLB_MISS;
3664	}
3665
3666	#if DEBUG_DCACHE
3667	if ( m_debug_dcache_fsm )
3668	{
3669	std::cout << " <PROC " << name()
3670	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3671	<< " / VADDR = " << r_dcache_save_wdata.read()
3672	<< " / PADDR = " << paddr << std::endl;
3673	}
3674	#endif
3675
3676	break;
3677	}
3678	////////////////////////////
3679	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3680	// requires 2 cycles: read cache / inval cache
3681	// In this state we read dcache.
3682	{
3683	size_t way;
3684	size_t set;
3685	size_t word;
3686	int state;
3687
3688	#ifdef INSTRUMENTATION
3689	m_cpt_dcache_dir_read++;
3690	#endif
3691	r_dcache.read_dir( r_dcache_save_paddr.read(),
3692	&state,
3693	&way,
3694	&set,
3695	&word );
3696
3697	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3698	{
3699	r_dcache_xtn_way = way;
3700	r_dcache_xtn_set = set;
3701	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3702	}
3703	else // miss : nothing to do
3704	{
3705	r_dcache_fsm = DCACHE_IDLE;
3706	m_drsp.valid = true;
3707	}
3708
3709	#if DEBUG_DCACHE
3710	if ( m_debug_dcache_fsm )
3711	{
3712	std::cout << " <PROC " << name()
3713	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3714	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3715	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3716	<< " / SET = " << set
3717	<< " / WAY = " << way << std::endl;
3718	}
3719	#endif
3720	break;
3721	}
3722	////////////////////////////
3723	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3724	// Blocked if previous cleanup not completed
3725	// Test if itlb or dtlb inval is required
3726	{
3727	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3728	{
3729	size_t way = r_dcache_xtn_way.read();
3730	size_t set = r_dcache_xtn_set.read();
3731	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3732
3733	#ifdef INSTRUMENTATION
3734	m_cpt_dcache_dir_write++;
3735	#endif
3736	r_dcache.write_dir( 0,
3737	way,
3738	set,
3739	CACHE_SLOT_STATE_EMPTY );
3740
3741	// request cleanup
3742	r_dcache_cc_send_req = true;
3743	r_dcache_cc_send_nline = nline;
3744	r_dcache_cc_send_way = way;
3745	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3746
3747	// possible itlb & dtlb invalidate
3748	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3749	{
3750	r_dcache_tlb_inval_line = nline;
3751	r_dcache_tlb_inval_set = 0;
3752	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3753	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3754	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3755	}
3756	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3757	{
3758	r_itlb.reset();
3759	r_dtlb.reset();
3760	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3761	r_dcache_fsm = DCACHE_IDLE;
3762	m_drsp.valid = true;
3763	}
3764	else
3765	{
3766	r_dcache_fsm = DCACHE_IDLE;
3767	m_drsp.valid = true;
3768	}
3769
3770	#if DEBUG_DCACHE
3771	if ( m_debug_dcache_fsm )
3772	{
3773	std::cout << " <PROC " << name()
3774	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3775	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3776	}
3777	#endif
3778	}
3779	break;
3780	}
3781	//////////////////////////////
3782	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3783	{
3784	r_dcache_fsm = DCACHE_IDLE;
3785	m_drsp.valid = true;
3786	break;
3787	}
3788	////////////////////////
3789	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3790	// if previous cleanup has been sent.
3791	// Waiting in this state if no slot available
3792	// Set the r_dcache_cleanup_req flip-flop
3793	// and the r_dcache_miss_clack flip-flop
3794	// when a cleanup is required
3795	{
3796	if ( m_dreq.valid) m_cost_data_miss_frz++;
3797
3798	// coherence request (from CC_RECEIVE FSM)
3799	if ( r_cc_receive_dcache_req.read() )
3800	{
3801	r_dcache_fsm = DCACHE_CC_CHECK;
3802	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3803	break;
3804	}
3805
3806	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3807	{
3808	bool found;
3809	bool cleanup;
3810	size_t way;
3811	size_t set;
3812	paddr_t victim;
3813
3814	#ifdef INSTRUMENTATION
3815	m_cpt_dcache_dir_read++;
3816	#endif
3817	r_dcache.read_select( r_dcache_save_paddr.read(),
3818	&victim,
3819	&way,
3820	&set,
3821	&found,
3822	&cleanup );
3823
3824	if ( found )
3825	{
3826	r_dcache_miss_way = way;
3827	r_dcache_miss_set = set;
3828
3829	if ( cleanup )
3830	{
3831	r_dcache_miss_clack = true;
3832	r_dcache_fsm = DCACHE_MISS_CLEAN;
3833	// request cleanup
3834	r_dcache_cc_send_req = true;
3835	r_dcache_cc_send_nline = victim;
3836	r_dcache_cc_send_way = way;
3837	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3838	}
3839	else
3840	{
3841	r_dcache_fsm = DCACHE_MISS_WAIT;
3842	}
3843
3844	#if DEBUG_DCACHE
3845	if ( m_debug_dcache_fsm )
3846	{
3847	std::cout << " <PROC " << name()
3848	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3849	<< " / WAY = " << way
3850	<< " / SET = " << set
3851	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3852	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3853	else std::cout << std::endl;
3854	}
3855	#endif
3856	} // end found
3857	}
3858	break;
3859	}
3860	///////////////////////
3861	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3862	// and possibly request itlb or dtlb invalidate
3863	{
3864	if ( m_dreq.valid) m_cost_data_miss_frz++;
3865
3866	size_t way = r_dcache_miss_way.read();
3867	size_t set = r_dcache_miss_set.read();
3868	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3869
3870	#ifdef INSTRUMENTATION
3871	m_cpt_dcache_dir_read++;
3872	#endif
3873	r_dcache.write_dir( 0,
3874	way,
3875	set,
3876	CACHE_SLOT_STATE_ZOMBI );
3877	#if DEBUG_DCACHE
3878	if ( m_debug_dcache_fsm )
3879	{
3880	std::cout << " <PROC " << name()
3881	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3882	<< " / way = " << way
3883	<< " / set = " << set << std::endl;
3884	}
3885	#endif
3886	// if selective itlb & dtlb invalidate are required
3887	// the miss response is not handled before invalidate completed
3888	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3889	{
3890	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3891	r_dcache_tlb_inval_line = nline;
3892	r_dcache_tlb_inval_set = 0;
3893	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3894	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3895	}
3896	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3897	{
3898	r_itlb.reset();
3899	r_dtlb.reset();
3900	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3901	r_dcache_fsm = DCACHE_MISS_WAIT;
3902	}
3903	else
3904	{
3905	r_dcache_fsm = DCACHE_MISS_WAIT;
3906	}
3907	break;
3908	}
3909	//////////////////////
3910	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3911	// This state is in charge of error signaling
3912	// There is 5 types of error depending on the requester
3913	{
3914	if ( m_dreq.valid) m_cost_data_miss_frz++;
3915
3916	// coherence request (from CC_RECEIVE FSM)
3917	if ( r_cc_receive_dcache_req.read() )
3918	{
3919	r_dcache_fsm = DCACHE_CC_CHECK;
3920	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3921	break;
3922	}
3923
3924	if ( r_vci_rsp_data_error.read() ) // bus error
3925	{
3926	switch ( r_dcache_miss_type.read() )
3927	{
3928	case PROC_MISS:
3929	{
3930	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3931	r_mmu_dbvar = r_dcache_save_vaddr.read();
3932	m_drsp.valid = true;
3933	m_drsp.error = true;
3934	r_dcache_fsm = DCACHE_IDLE;
3935	break;
3936	}
3937	case PTE1_MISS:
3938	{
3939	if ( r_dcache_tlb_ins.read() )
3940	{
3941	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3942	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3943	r_icache_tlb_miss_req = false;
3944	r_icache_tlb_rsp_error = true;
3945	}
3946	else
3947	{
3948	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3949	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3950	m_drsp.valid = true;
3951	m_drsp.error = true;
3952	}
3953	r_dcache_fsm = DCACHE_IDLE;
3954	break;
3955	}
3956	case PTE2_MISS:
3957	{
3958	if ( r_dcache_tlb_ins.read() )
3959	{
3960	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3961	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3962	r_icache_tlb_miss_req = false;
3963	r_icache_tlb_rsp_error = true;
3964	}
3965	else
3966	{
3967	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3968	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3969	m_drsp.valid = true;
3970	m_drsp.error = true;
3971	}
3972	r_dcache_fsm = DCACHE_IDLE;
3973	break;
3974	}
3975	} // end switch type
3976	r_vci_rsp_data_error = false;
3977	}
3978	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3979	{
3980	r_dcache_miss_word = 0;
3981	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3982	}
3983	break;
3984	}
3985	//////////////////////////
3986	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
3987	{
3988	if ( m_dreq.valid) m_cost_data_miss_frz++;
3989
3990	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3991	{
3992	#ifdef INSTRUMENTATION
3993	m_cpt_dcache_data_write++;
3994	#endif
3995	r_dcache.write( r_dcache_miss_way.read(),
3996	r_dcache_miss_set.read(),
3997	r_dcache_miss_word.read(),
3998	r_vci_rsp_fifo_dcache.read() );
3999	#if DEBUG_DCACHE
4000	if ( m_debug_dcache_fsm )
4001	{
4002	std::cout << " <PROC " << name()
4003	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4004	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4005	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4006	<< " / SET = " << r_dcache_miss_set.read()
4007	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4008	}
4009	#endif
4010	vci_rsp_fifo_dcache_get = true;
4011	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4012
4013	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4014	{
4015	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4016	}
4017	}
4018	break;
4019	}
4020	//////////////////////////
4021	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4022	// and the cleanup ack has not been received,
4023	// as indicated by the r_dcache_miss clack.
4024	// - If no matching coherence request (r_dcache_inval_miss)
4025	// switch directory slot to VALID state.
4026	// - If matching coherence request, switch directory slot
4027	// to ZOMBI state, and send a cleanup request.
4028	{
4029	if ( m_dreq.valid) m_cost_data_miss_frz++;
4030
4031	// coherence request (from CC_RECEIVE FSM)
4032	if ( r_cc_receive_dcache_req.read() )
4033	{
4034	r_dcache_fsm = DCACHE_CC_CHECK;
4035	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4036	break;
4037	}
4038
4039	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4040	{
4041	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4042	{
4043	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4044	{
4045	r_dcache_miss_inval = false;
4046	// request cleanup
4047	r_dcache_cc_send_req = true;
4048	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4049	r_dcache_cc_send_way = r_dcache_miss_way.read();
4050	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4051
4052	#ifdef INSTRUMENTATION
4053	m_cpt_dcache_dir_write++;
4054	#endif
4055	r_dcache.write_dir( r_dcache_save_paddr.read(),
4056	r_dcache_miss_way.read(),
4057	r_dcache_miss_set.read(),
4058	CACHE_SLOT_STATE_ZOMBI );
4059	#if DEBUG_DCACHE
4060	if ( m_debug_dcache_fsm )
4061	{
4062	std::cout << " <PROC " << name()
4063	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4064	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4065	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4066	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4067	}
4068	#endif
4069	}
4070	else
4071	break;
4072	}
4073	else // switch slot to VALID state
4074	{
4075
4076	#ifdef INSTRUMENTATION
4077	m_cpt_dcache_dir_write++;
4078	#endif
4079	r_dcache.write_dir( r_dcache_save_paddr.read(),
4080	r_dcache_miss_way.read(),
4081	r_dcache_miss_set.read(),
4082	CACHE_SLOT_STATE_VALID );
4083
4084	#if DEBUG_DCACHE
4085	if ( m_debug_dcache_fsm )
4086	{
4087	std::cout << " <PROC " << name()
4088	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4089	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4090	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4091	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4092
4093	r_dcache.printTrace();
4094
4095
4096	}
4097	#endif
4098	// reset directory extension
4099	size_t way = r_dcache_miss_way.read();
4100	size_t set = r_dcache_miss_set.read();
4101	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4102	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4103	}
4104	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4105	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4106	else r_dcache_fsm = DCACHE_IDLE;
4107	}
4108	break;
4109	}
4110	/////////////////////
4111	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4112	{
4113	// coherence request (from CC_RECEIVE FSM)
4114	if ( r_cc_receive_dcache_req.read() )
4115	{
4116	r_dcache_fsm = DCACHE_CC_CHECK;
4117	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4118	break;
4119	}
4120
4121	if ( r_vci_rsp_data_error.read() ) // bus error
4122	{
4123	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4124	r_mmu_dbvar = m_dreq.addr;
4125	r_vci_rsp_data_error = false;
4126	m_drsp.error = true;
4127	m_drsp.valid = true;
4128	r_dcache_fsm = DCACHE_IDLE;
4129	break;
4130	}
4131	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4132	{
4133	// consume data
4134	vci_rsp_fifo_dcache_get = true;
4135	r_dcache_fsm = DCACHE_IDLE;
4136
4137	// acknowledge the processor request if it has not been modified
4138	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4139	{
4140	m_drsp.valid = true;
4141	m_drsp.error = false;
4142	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4143	}
4144	}
4145	break;
4146	}
4147	/////////////////////
4148	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4149	{
4150	// coherence request (from CC_RECEIVE FSM)
4151	if ( r_cc_receive_dcache_req.read() )
4152	{
4153	r_dcache_fsm = DCACHE_CC_CHECK;
4154	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4155	break;
4156	}
4157
4158	if ( r_vci_rsp_data_error.read() ) // bus error
4159	{
4160	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4161	r_mmu_dbvar = m_dreq.addr;
4162	r_vci_rsp_data_error = false;
4163	m_drsp.error = true;
4164	m_drsp.valid = true;
4165	r_dcache_fsm = DCACHE_IDLE;
4166	break;
4167	}
4168	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4169	{
4170	// consume data
4171	vci_rsp_fifo_dcache_get = true;
4172
4173	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4174	{
4175	// set key value in llsc reservation buffer
4176	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4177	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4178	}
4179	else // last flit
4180	{
4181	// acknowledge the processor request if it has not been modified
4182	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4183	{
4184	m_drsp.valid = true;
4185	m_drsp.error = false;
4186	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4187	}
4188	r_dcache_fsm = DCACHE_IDLE;
4189	}
4190	}
4191	break;
4192	}
4193	////////////////////
4194	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4195	{
4196	// coherence request (from CC_RECEIVE FSM)
4197	if ( r_cc_receive_dcache_req.read() )
4198	{
4199	r_dcache_fsm = DCACHE_CC_CHECK;
4200	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4201	break;
4202	}
4203
4204	if ( r_vci_rsp_data_error.read() ) // bus error
4205	{
4206	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4207	r_mmu_dbvar = m_dreq.addr;
4208	r_vci_rsp_data_error = false;
4209	m_drsp.error = true;
4210	m_drsp.valid = true;
4211	r_dcache_fsm = DCACHE_IDLE;
4212	break;
4213	}
4214	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4215	{
4216	// consume response
4217	vci_rsp_fifo_dcache_get = true;
4218	m_drsp.valid = true;
4219	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4220	r_dcache_fsm = DCACHE_IDLE;
4221	}
4222	break;
4223	}
4224	//////////////////////////
4225	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4226	// before handling a processor WRITE or SC request
4227	// Input argument is r_dcache_dirty_paddr
4228	// In this first state, we get PTE value in dcache
4229	// and post a CAS request to CMD FSM
4230	{
4231	// get PTE in dcache
4232	uint32_t pte;
4233	size_t way;
4234	size_t set;
4235	size_t word; // unused
4236	int state;
4237
4238	#ifdef INSTRUMENTATION
4239	m_cpt_dcache_data_read++;
4240	m_cpt_dcache_dir_read++;
4241	#endif
4242	r_dcache.read( r_dcache_dirty_paddr.read(),
4243	&pte,
4244	&way,
4245	&set,
4246	&word,
4247	&state );
4248
4249	assert( (state == CACHE_SLOT_STATE_VALID) and
4250	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4251
4252	// request CAS transaction to CMD_FSM
4253	r_dcache_dirty_way = way;
4254	r_dcache_dirty_set = set;
4255
4256	// check llsc reservation buffer
4257	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4258	r_dcache_llsc_valid = false;
4259
4260	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4261	r_dcache_vci_cas_req = true;
4262	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4263	r_dcache_vci_cas_old = pte;
4264	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4265	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4266
4267	#if DEBUG_DCACHE
4268	if ( m_debug_dcache_fsm )
4269	{
4270	std::cout << " <PROC " << name()
4271	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4272	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4273	<< " / PTE_VALUE = " << pte << std::dec
4274	<< " / SET = " << set
4275	<< " / WAY = " << way << std::endl;
4276	}
4277	#endif
4278	break;
4279	}
4280	///////////////////////
4281	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4282	// and return to IDLE state when response is received.
4283	// we don't care if the CAS is a failure:
4284	// - if the CAS is a success, the coherence mechanism
4285	// updates the local copy.
4286	// - if the CAS is a failure, we just retry the write.
4287	{
4288	// coherence request (from CC_RECEIVE FSM)
4289	if ( r_cc_receive_dcache_req.read() )
4290	{
4291	r_dcache_fsm = DCACHE_CC_CHECK;
4292	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4293	break;
4294	}
4295
4296	if ( r_vci_rsp_data_error.read() ) // bus error
4297	{
4298	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4299	std::cout << "This should not happen in this state" << std::endl;
4300	exit(0);
4301	}
4302	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4303	{
4304	vci_rsp_fifo_dcache_get = true;
4305	r_dcache_fsm = DCACHE_IDLE;
4306
4307	#if DEBUG_DCACHE
4308	if ( m_debug_dcache_fsm )
4309	{
4310	std::cout << " <PROC " << name()
4311	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4312	}
4313	#endif
4314	}
4315	break;
4316	}
4317	/////////////////////
4318	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4319	// handling coherence requests for DCACHE.
4320	// If there is a matching pending miss on the modified cache
4321	// line this is signaled in the r_dcache_miss inval flip-flop.
4322	// If the updated (or invalidated) cache line has copies in TLBs
4323	// these TLB copies are invalidated.
4324	// The return state is defined in r_dcache_fsm_cc_save
4325	{
4326	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4327	paddr_t mask = ~((m_dcache_words<<2)-1);
4328
4329	#if DEBUG_DCACHE
4330	if ( m_debug_dcache_fsm )
4331	{
4332	std::cout << " <PROC " << name()
4333	<< " DCACHE_CC_CHECK> paddr = " << paddr
4334	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4335	<< " mask = " << mask
4336	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4337	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4338	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4339	<<std::endl;
4340	}
4341	#endif
4342
4343	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4344	// We switch the directory slot to EMPTY state
4345	// and reset r_icache_miss_clack if the cleanup ack
4346	// is matching a pending miss.
4347	{
4348
4349	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4350
4351	#ifdef INSTRUMENTATION
4352	m_cpt_dcache_dir_write++;
4353	#endif
4354	r_dcache.write_dir( 0,
4355	r_cc_receive_dcache_way.read(),
4356	r_cc_receive_dcache_set.read(),
4357	CACHE_SLOT_STATE_EMPTY);
4358
4359	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4360	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4361	r_dcache_miss_clack = false;
4362
4363	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4364	r_cc_receive_dcache_req = false;
4365	#if DEBUG_DCACHE
4366	if ( m_debug_dcache_fsm )
4367	{
4368	std::cout << " <PROC " << name()
4369	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4370	<< " set = " << r_cc_receive_dcache_set.read()
4371	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4372	}
4373	#endif
4374	}
4375	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4376	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4377	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4378	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4379	{
4380	// signaling matching
4381	r_dcache_miss_inval = true;
4382
4383	// in case of update, go to CC_UPDT
4384	// JUST TO POP THE FIFO
4385	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4386	{
4387	r_dcache_fsm = DCACHE_CC_UPDT;
4388	r_dcache_cc_word = r_cc_receive_word_idx.read();
4389	// just pop the fifo , don't write in icache
4390	r_dcache_cc_need_write = false;
4391	}
4392	// the request is dealt with
4393	else
4394	{
4395	r_cc_receive_dcache_req = false;
4396	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4397	}
4398
4399	#if DEBUG_DCACHE
4400	if ( m_debug_dcache_fsm )
4401	{
4402	std::cout << " <PROC " << name()
4403	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4404	<< " PADDR = " << std::hex << paddr << std::endl;
4405	}
4406	#endif
4407
4408	}
4409	else // no match
4410	{
4411	int state;
4412	size_t way;
4413	size_t set;
4414	size_t word;
4415
4416	#ifdef INSTRUMENTATION
4417	m_cpt_dcache_dir_read++;
4418	#endif
4419	r_dcache.read_dir( paddr,
4420	&state,
4421	&way,
4422	&set,
4423	&word ); // unused
4424
4425	r_dcache_cc_way = way;
4426	r_dcache_cc_set = set;
4427
4428	if ( state == CACHE_SLOT_STATE_VALID) // hit
4429	{
4430	// need to update the cache state
4431	r_dcache_cc_need_write = true;
4432	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4433	{
4434	r_dcache_fsm = DCACHE_CC_UPDT;
4435	r_dcache_cc_word = r_cc_receive_word_idx.read();
4436	}
4437	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4438	{
4439	r_dcache_fsm = DCACHE_CC_INVAL;
4440	}
4441	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4442	{
4443	r_dcache_fsm = DCACHE_CC_BROADCAST;
4444	}
4445	}
4446	else // miss
4447	{
4448	// multicast acknowledgement required in case of update
4449	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4450	{
4451	r_dcache_fsm = DCACHE_CC_UPDT;
4452	r_dcache_cc_word = r_cc_receive_word_idx.read();
4453	// just pop the fifo , don't write in icache
4454	r_dcache_cc_need_write = false;
4455	}
4456	else // No response needed
4457	{
4458	r_cc_receive_dcache_req = false;
4459	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4460	}
4461	}
4462
4463	#if DEBUG_DCACHE
4464	if ( m_debug_dcache_fsm )
4465	{
4466	std::cout << " <PROC " << name()
4467	<< " DCACHE_CC_CHECK> Coherence request received:"
4468	<< " PADDR = " << std::hex << paddr
4469	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4470	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4471	}
4472	#endif
4473	}
4474	break;
4475	}
4476	/////////////////////
4477	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4478	// after possible invalidation of copies in TLBs
4479	{
4480	size_t way = r_dcache_cc_way.read();
4481	size_t set = r_dcache_cc_set.read();
4482
4483	if (r_dcache_cc_need_write.read())
4484	{
4485	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4486	{
4487	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4488	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4489	r_dcache_tlb_inval_set = 0;
4490	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4491	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4492	break;
4493	}
4494	else
4495	{
4496	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4497	{
4498	r_itlb.reset();
4499	r_dtlb.reset();
4500	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4501
4502	#if DEBUG_DCACHE
4503	if ( m_debug_dcache_fsm )
4504	{
4505	std::cout << " <PROC " << name()
4506	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4507	}
4508	#endif
4509	}
4510
4511	r_dcache.write_dir( 0,
4512	way,
4513	set,
4514	CACHE_SLOT_STATE_EMPTY );
4515
4516	r_dcache_cc_need_write = false;
4517
4518	#if DEBUG_DCACHE
4519	if ( m_debug_dcache_fsm )
4520	{
4521	std::cout << " <PROC " << name()
4522	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4523	<< " / WAY = " << way
4524	<< " / SET = " << set << std::endl;
4525	}
4526	#endif
4527	}
4528	}
4529	// multicast acknowledgement
4530	// send a request to cc_send_fsm
4531	if(not r_dcache_cc_send_req.read()) // cc_send is available
4532	{
4533	// coherence request completed
4534	r_cc_receive_dcache_req = false;
4535	// request multicast acknowledgement
4536	r_dcache_cc_send_req = true;
4537	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4538	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4539
4540	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4541	}
4542	//else wait for previous cc_send request to be sent
4543	break;
4544	}
4545	///////////////////
4546	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4547	// after possible invalidation of copies in TLBs
4548	{
4549	size_t word = r_dcache_cc_word.read();
4550	size_t way = r_dcache_cc_way.read();
4551	size_t set = r_dcache_cc_set.read();
4552
4553	if (r_cc_receive_updt_fifo_be.rok())
4554	{
4555	if (r_dcache_cc_need_write.read())
4556	{
4557	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4558	{
4559	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4560	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4561	r_dcache_tlb_inval_set = 0;
4562	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4563	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4564	break;
4565	}
4566
4567	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4568	{
4569	r_itlb.reset();
4570	r_dtlb.reset();
4571	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4572
4573	#if DEBUG_DCACHE
4574	if ( m_debug_dcache_fsm )
4575	{
4576	std::cout << " <PROC " << name()
4577	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4578	}
4579	#endif
4580	}
4581
4582	#ifdef INSTRUMENTATION
4583	m_cpt_dcache_data_write++;
4584	#endif
4585	r_dcache.write( way,
4586	set,
4587	word,
4588	r_cc_receive_updt_fifo_data.read(),
4589	r_cc_receive_updt_fifo_be.read() );
4590
4591	r_dcache_cc_word = word + 1;
4592
4593	#if DEBUG_DCACHE
4594	if ( m_debug_dcache_fsm )
4595	{
4596	std::cout << " <PROC " << name()
4597	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4598	<< " / WAY = " << way
4599	<< " / SET = " << set
4600	<< " / WORD = " << word
4601	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4602	}
4603	#endif
4604	}
4605
4606	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4607	{
4608	// no need to write in the cache anymore
4609	r_dcache_cc_need_write = false;
4610
4611	// wait to send a request to cc_send_fsm
4612	if(not r_icache_cc_send_req.read())
4613	// cc_send is available
4614	{
4615	//consume last fifo flit if eop and request to cc_send possible
4616	cc_receive_updt_fifo_get = true;
4617
4618	// coherence request completed
4619	r_cc_receive_dcache_req = false;
4620
4621	// request multicast acknowledgement
4622	r_dcache_cc_send_req = true;
4623	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4624	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4625
4626	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4627	}
4628	}
4629	else
4630	{
4631	//consume fifo if not eop
4632	cc_receive_updt_fifo_get = true;
4633	}
4634	}
4635	break;
4636	}
4637	/////////////////////////
4638	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4639	// and request a cleanup, after possible
4640	// invalidation of copies in TLBs
4641	{
4642	size_t way = r_dcache_cc_way.read();
4643	size_t set = r_dcache_cc_set.read();
4644	paddr_t nline = r_cc_receive_dcache_nline.read();
4645
4646	if (r_dcache_cc_need_write.read())
4647	{
4648	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4649	{
4650	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4651	r_dcache_tlb_inval_line = nline;
4652	r_dcache_tlb_inval_set = 0;
4653	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4654	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4655	break;
4656	}
4657	else
4658	{
4659	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4660	{
4661	r_itlb.reset();
4662	r_dtlb.reset();
4663	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4664
4665	#if DEBUG_DCACHE
4666	if ( m_debug_dcache_fsm )
4667	{
4668	std::cout << " <PROC " << name()
4669	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4670	}
4671	#endif
4672	}
4673
4674	#ifdef INSTRUMENTATION
4675	m_cpt_dcache_dir_write++;
4676	#endif
4677	r_dcache.write_dir( 0,
4678	way,
4679	set,
4680	CACHE_SLOT_STATE_ZOMBI );
4681
4682	r_dcache_cc_need_write = false;
4683	#if DEBUG_DCACHE
4684	if ( m_debug_dcache_fsm )
4685	{
4686	std::cout << " <PROC " << name()
4687	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4688	<< " SET = " << set
4689	<< " / WAY = " << way << std::endl;
4690	}
4691	#endif
4692	}
4693	}
4694	// cleanup
4695	// send a request to cc_send_fsm
4696	if(not r_dcache_cc_send_req.read()) // cc_send is available
4697	{
4698	// coherence request completed
4699	r_cc_receive_dcache_req = false;
4700	// request cleanup
4701	r_dcache_cc_send_req = true;
4702	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4703	r_dcache_cc_send_way = r_dcache_cc_way.read();
4704	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4705
4706	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4707	}
4708	//else wait for previous cc_send request to be sent
4709	break;
4710	}
4711	///////////////////////////
4712	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4713	// It makes assumption: m_itlb_sets == m_dtlb_sets
4714	// All ways are handled in parallel.
4715	// We enter this state when a DCACHE line is modified,
4716	// and there is a copy in itlb or dtlb.
4717	// It can be caused by:
4718	// - a coherence inval or updt transaction,
4719	// - a line inval caused by a cache miss
4720	// - a processor XTN inval request,
4721	// - a WRITE hit,
4722	// - a Dirty bit update
4723	// Input arguments are:
4724	// - r_dcache_tlb_inval_line
4725	// - r_dcache_tlb_inval_set
4726	// - r_dcache_fsm_scan_save
4727	{
4728	paddr_t line = r_dcache_tlb_inval_line.read();
4729	size_t set = r_dcache_tlb_inval_set.read();
4730	size_t way;
4731	bool ok;
4732
4733	for ( way = 0 ; way < m_itlb_ways ; way++ )
4734	{
4735	ok = r_itlb.inval( line, way, set );
4736
4737	#if DEBUG_DCACHE
4738	if ( m_debug_dcache_fsm and ok )
4739	{
4740	std::cout << " <PROC " << name()
4741	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4742	<< " line = " << line << std::dec
4743	<< " / set = " << set
4744	<< " / way = " << way << std::endl;
4745	}
4746	#endif
4747	}
4748
4749	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4750	{
4751	ok = r_dtlb.inval( line, way, set );
4752
4753	#if DEBUG_DCACHE
4754	if ( m_debug_dcache_fsm and ok )
4755	{
4756	std::cout << " <PROC " << name()
4757	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4758	<< " line = " << line << std::dec
4759	<< " / set = " << set
4760	<< " / way = " << way << std::endl;
4761	}
4762	#endif
4763	}
4764
4765	// return to the calling state when TLB inval completed
4766	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4767	{
4768	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4769	}
4770	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4771	break;
4772	}
4773	} // end switch r_dcache_fsm
4774
4775	///////////////// wbuf update ///////////////////////////////////////////////////////
4776	r_wbuf.update();
4777
4778	///////////////// llsc update ///////////////////////////////////////////////////////
4779	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4780	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4781
4782	//////////////// test processor frozen //////////////////////////////////////////////
4783	// The simulation exit if the number of consecutive frozen cycles
4784	// is larger than the m_max_frozen_cycles (constructor parameter)
4785	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4786	{
4787	m_cpt_frz_cycles++; // used for instrumentation
4788	m_cpt_stop_simulation++; // used for debug
4789	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4790	{
4791	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4792	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4793	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4794	<< std::endl;
4795	r_iss.dump();
4796	exit(1);
4797	}
4798	}
4799	else
4800	{
4801	m_cpt_stop_simulation = 0;
4802	}
4803
4804	/////////// execute one iss cycle /////////////////////////////////
4805	{
4806	uint32_t it = 0;
4807	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4808	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4809	}
4810
4811	////////////////////////////////////////////////////////////////////////////
4812	// The VCI_CMD FSM controls the following ressources:
4813	// - r_vci_cmd_fsm
4814	// - r_vci_cmd_min
4815	// - r_vci_cmd_max
4816	// - r_vci_cmd_cpt
4817	// - r_vci_cmd_imiss_prio
4818	// - wbuf (reset)
4819	// - r_icache_miss_req (reset)
4820	// - r_icache_unc_req (reset)
4821	// - r_dcache_vci_miss_req (reset)
4822	// - r_dcache_vci_unc_req (reset)
4823	// - r_dcache_vci_ll_req (reset)
4824	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4825	// - r_dcache_vci_cas_req (reset)
4826	//
4827	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4828	// There are 8 request types, with the following priorities :
4829	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4830	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4831	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4832	// 4 - Instruction Uncachable : r_icache_unc_req
4833	// 5 - Data Write : r_wbuf.rok()
4834	// 6 - Data Linked Load : r_dcache_vci_ll_req
4835	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4836	// 8 - Compare And Swap : r_dcache_vci_cas_req
4837	//
4838	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4839	// and the VCI_RSP_FSM are fully desynchronized.
4840	//
4841	// VCI formats:
4842	// According to the VCI advanced specification, all read requests packets
4843	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4844	// are one word packets.
4845	// For write burst packets, all words are in the same cache line,
4846	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4847	// The sc command packet implements actually a compare-and-swap mechanism
4848	// and the packet contains two flits.
4849	////////////////////////////////////////////////////////////////////////////////////
4850
4851	switch ( r_vci_cmd_fsm.read() )
4852	{
4853	//////////////
4854	case CMD_IDLE:
4855	{
4856	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4857	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4858	// to check a possible pending write on the same cache line.
4859	// As there is only one possible access per cycle to write buffer, we implement
4860	// a round-robin priority between DCACHE and ICACHE for this access,
4861	// using the r_vci_cmd_imiss_prio flip-flop.
4862
4863	size_t wbuf_min;
4864	size_t wbuf_max;
4865
4866	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4867	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4868
4869	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4870	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4871
4872	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4873	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4874
4875	bool icache_miss_req = r_icache_miss_req.read() and
4876	( not (r_dcache_vci_miss_req.read() or
4877	r_dcache_vci_ll_req.read() or
4878	r_dcache_vci_unc_req.read())
4879	or r_vci_cmd_imiss_prio.read() ) ;
4880
4881	// 1 - Data Read Miss
4882	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4883	{
4884	r_vci_cmd_fsm = CMD_DATA_MISS;
4885	r_dcache_vci_miss_req = false;
4886	r_vci_cmd_imiss_prio = true;
4887	// m_cpt_dmiss_transaction++;
4888	}
4889	// 2 - Data Read Uncachable
4890	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4891	{
4892	r_vci_cmd_fsm = CMD_DATA_UNC;
4893	r_dcache_vci_unc_req = false;
4894	// m_cpt_dunc_transaction++;
4895	}
4896	// 3 - Data Linked Load
4897	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4898	{
4899	r_dcache_vci_ll_req = false;
4900	r_vci_cmd_fsm = CMD_DATA_LL;
4901	// m_cpt_ll_transaction++;
4902	}
4903	// 4 - Instruction Miss
4904	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4905	{
4906	r_vci_cmd_fsm = CMD_INS_MISS;
4907	r_icache_miss_req = false;
4908	r_vci_cmd_imiss_prio = false;
4909	// m_cpt_imiss_transaction++;
4910	}
4911	// 5 - Instruction Uncachable
4912	else if ( r_icache_unc_req.read() )
4913	{
4914	r_vci_cmd_fsm = CMD_INS_UNC;
4915	r_icache_unc_req = false;
4916	// m_cpt_iunc_transaction++;
4917	}
4918	// 6 - Data Write
4919	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4920	{
4921	r_vci_cmd_fsm = CMD_DATA_WRITE;
4922	r_vci_cmd_cpt = wbuf_min;
4923	r_vci_cmd_min = wbuf_min;
4924	r_vci_cmd_max = wbuf_max;
4925	// m_cpt_write_transaction++;
4926	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4927	}
4928	// 7 - Data Store Conditionnal
4929	else if ( r_dcache_vci_sc_req.read() )
4930	{
4931	r_dcache_vci_sc_req = false;
4932	r_vci_cmd_cpt = 0;
4933	r_vci_cmd_fsm = CMD_DATA_SC;
4934	// m_cpt_sc_transaction++;
4935	}
4936	// 8 - Compare And Swap
4937	else if ( r_dcache_vci_cas_req.read() )
4938	{
4939	r_vci_cmd_fsm = CMD_DATA_CAS;
4940	r_dcache_vci_cas_req = false;
4941	r_vci_cmd_cpt = 0;
4942	// m_cpt_cas_transaction++;
4943	}
4944	break;
4945	}
4946	////////////////////
4947	case CMD_DATA_WRITE:
4948	{
4949	if ( p_vci.cmdack.read() )
4950	{
4951	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4952	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4953	{
4954	r_vci_cmd_fsm = CMD_IDLE ;
4955	r_wbuf.sent() ;
4956	}
4957	}
4958	break;
4959	}
4960	/////////////////
4961	case CMD_DATA_SC:
4962	case CMD_DATA_CAS:
4963	{
4964	// The CAS and SC VCI commands contain two flits
4965	if ( p_vci.cmdack.read() )
4966	{
4967	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4968	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4969	}
4970	break;
4971	}
4972	//////////////////
4973	case CMD_INS_MISS:
4974	case CMD_INS_UNC:
4975	case CMD_DATA_MISS:
4976	case CMD_DATA_UNC:
4977	case CMD_DATA_LL:
4978	{
4979	// all read VCI commands contain one single flit
4980	if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4981	break;
4982	}
4983
4984	} // end switch r_vci_cmd_fsm
4985
4986	//////////////////////////////////////////////////////////////////////////
4987	// The VCI_RSP FSM controls the following ressources:
4988	// - r_vci_rsp_fsm:
4989	// - r_vci_rsp_fifo_icache (push)
4990	// - r_vci_rsp_fifo_dcache (push)
4991	// - r_vci_rsp_data_error (set)
4992	// - r_vci_rsp_ins_error (set)
4993	// - r_vci_rsp_cpt
4994	// - r_dcache_vci_sc_req (reset when SC response recieved)
4995	//
4996	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4997	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
4998	// to identify the transactions.
4999	//
5000	// VCI vormat:
5001	// This component checks the response packet length and accepts only
5002	// single word packets for write response packets.
5003	//
5004	// Error handling:
5005	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5006	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5007	// flip_flop and the error is signaled by the DCACHE FSM.
5008	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5009	// flip_flop and the error is signaled by the ICACHE FSM.
5010	// In case of Cleanup Error, the simulation stops with an error message...
5011	//////////////////////////////////////////////////////////////////////////
5012
5013	switch ( r_vci_rsp_fsm.read() )
5014	{
5015	//////////////
5016	case RSP_IDLE:
5017	{
5018	if ( p_vci.rspval.read() )
5019	{
5020	r_vci_rsp_cpt = 0;
5021
5022	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5023	{
5024	r_vci_rsp_fsm = RSP_DATA_UNC;
5025	}
5026	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5027	{
5028	r_vci_rsp_fsm = RSP_DATA_MISS;
5029	}
5030	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5031	{
5032	r_vci_rsp_fsm = RSP_INS_UNC;
5033	}
5034	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5035	{
5036	r_vci_rsp_fsm = RSP_INS_MISS;
5037	}
5038	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5039	{
5040	r_vci_rsp_fsm = RSP_DATA_WRITE;
5041	}
5042	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5043	{
5044	r_vci_rsp_fsm = RSP_DATA_UNC;
5045	}
5046	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5047	{
5048	r_vci_rsp_fsm = RSP_DATA_LL;
5049	}
5050	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5051	{
5052	r_vci_rsp_fsm = RSP_DATA_UNC;
5053	}
5054	else
5055	{
5056	assert(false and "Unexpected VCI response");
5057	}
5058	}
5059	break;
5060	}
5061	//////////////////
5062	case RSP_INS_MISS:
5063	{
5064	if ( p_vci.rspval.read() )
5065	{
5066	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5067	{
5068	r_vci_rsp_ins_error = true;
5069	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5070	}
5071	else // no error reported
5072	{
5073	if ( r_vci_rsp_fifo_icache.wok() )
5074	{
5075	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5076	"The VCI response packet for instruction miss is too long" );
5077
5078	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5079	vci_rsp_fifo_icache_put = true,
5080	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5081	if ( p_vci.reop.read() )
5082	{
5083	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5084	"The VCI response packet for instruction miss is too short");
5085
5086	r_vci_rsp_fsm = RSP_IDLE;
5087	}
5088	}
5089	}
5090	}
5091	break;
5092	}
5093	/////////////////
5094	case RSP_INS_UNC:
5095	{
5096	if (p_vci.rspval.read() )
5097	{
5098	assert( p_vci.reop.read() and
5099	"illegal VCI response packet for uncachable instruction");
5100
5101	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5102	{
5103	r_vci_rsp_ins_error = true;
5104	r_vci_rsp_fsm = RSP_IDLE;
5105	}
5106	else // no error reported
5107	{
5108	if ( r_vci_rsp_fifo_icache.wok())
5109	{
5110	vci_rsp_fifo_icache_put = true;
5111	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5112	r_vci_rsp_fsm = RSP_IDLE;
5113	}
5114	}
5115	}
5116	break;
5117	}
5118	///////////////////
5119	case RSP_DATA_MISS:
5120	{
5121	if ( p_vci.rspval.read() )
5122	{
5123	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5124	{
5125	r_vci_rsp_data_error = true;
5126	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5127	}
5128	else // no error reported
5129	{
5130	if ( r_vci_rsp_fifo_dcache.wok() )
5131	{
5132	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5133	"The VCI response packet for data miss is too long");
5134
5135	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5136	vci_rsp_fifo_dcache_put = true,
5137	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5138	if ( p_vci.reop.read() )
5139	{
5140	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5141	"The VCI response packet for data miss is too short");
5142
5143	r_vci_rsp_fsm = RSP_IDLE;
5144	}
5145	}
5146	}
5147	}
5148	break;
5149	}
5150	//////////////////
5151	case RSP_DATA_UNC:
5152	{
5153	if (p_vci.rspval.read() )
5154	{
5155	assert( p_vci.reop.read() and
5156	"illegal VCI response packet for uncachable read data");
5157
5158	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5159	{
5160	r_vci_rsp_data_error = true;
5161	r_vci_rsp_fsm = RSP_IDLE;
5162	}
5163	else // no error reported
5164	{
5165	if ( r_vci_rsp_fifo_dcache.wok())
5166	{
5167	vci_rsp_fifo_dcache_put = true;
5168	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5169	r_vci_rsp_fsm = RSP_IDLE;
5170	}
5171	}
5172	}
5173	break;
5174	}
5175	////////////////////
5176	case RSP_DATA_LL:
5177	{
5178	if ( p_vci.rspval.read() )
5179	{
5180	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5181	{
5182	r_vci_rsp_data_error = true;
5183	r_vci_rsp_fsm = RSP_IDLE;
5184	}
5185	if (r_vci_rsp_cpt.read() == 0) //first flit
5186	{
5187	if(r_vci_rsp_fifo_dcache.wok())
5188	{
5189	assert(!p_vci.reop.read() &&
5190	"illegal VCI response packet for LL");
5191	vci_rsp_fifo_dcache_put = true;
5192	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5193	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5194	}
5195	break;
5196	}
5197	else // last flit
5198	{
5199	if(r_vci_rsp_fifo_dcache.wok())
5200	{
5201	assert(p_vci.reop.read() &&
5202	"illegal VCI response packet for LL");
5203	vci_rsp_fifo_dcache_put = true;
5204	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5205	r_vci_rsp_fsm = RSP_IDLE;
5206	}
5207	break;
5208	}
5209	}
5210	break;
5211	}
5212	////////////////////
5213	case RSP_DATA_WRITE:
5214	{
5215	if (p_vci.rspval.read())
5216	{
5217	assert( p_vci.reop.read() and
5218	"a VCI response packet must contain one flit for a write transaction");
5219
5220	r_vci_rsp_fsm = RSP_IDLE;
5221	uint32_t wbuf_index = p_vci.rtrdid.read();
5222	bool cacheable = r_wbuf.completed(wbuf_index);
5223	if ( not cacheable ) r_dcache_pending_unc_write = false;
5224	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5225	}
5226	break;
5227	}
5228	} // end switch r_vci_rsp_fsm
5229
5230	/////////////////////////////////////////////////////////////////////////////////////
5231	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5232	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5233	// and ICACHE FSM) that are served with a round-robin priority.
5234	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5235	// soon as the request has been sent.
5236	/////////////////////////////////////////////////////////////////////////////////////
5237	switch ( r_cc_send_fsm.read() )
5238	{
5239	///////////////////////////
5240	case CC_SEND_IDLE:
5241	{
5242	///////////////////////////////////////////////////////
5243	// handling round robin between icache and dcache : //
5244	// we first check for the last client and listen for //
5245	// a request of the other, then update the client //
5246	///////////////////////////////////////////////////////
5247	// r_cc_send_last_client : 0 dcache / 1 icache
5248	bool update_last_client = r_cc_send_last_client.read();
5249	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5250	{
5251	if (r_icache_cc_send_req.read()) // request from icache
5252	update_last_client = 1; // update last client to icache
5253	}
5254	else // last client was icache
5255	{
5256	if (r_dcache_cc_send_req.read()) // request from dcache
5257	update_last_client = 0; // update last client to dcache
5258	}
5259	r_cc_send_last_client = update_last_client;
5260
5261	// if there is an actual request
5262	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5263	{
5264	// test if the new client is dcache and has a cleanup request
5265	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5266	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5267	// test if the new client is dcache and has a multi acknowledgement request
5268	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5269	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5270	// test if the new client is icache and has a cleanup request
5271	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5272	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5273	// test if the new client is icache and has a multi acknowledgement request
5274	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5275	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5276	}
5277	break;
5278	}
5279	///////////////////////////
5280	case CC_SEND_CLEANUP_1:
5281	{
5282	// wait for the first flit to be consumed
5283	if (p_dspin_out.read.read())
5284	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5285
5286	break;
5287	}
5288	///////////////////////////
5289	case CC_SEND_CLEANUP_2:
5290	{
5291	// wait for the second flit to be consumed
5292	if (p_dspin_out.read.read())
5293	{
5294	if (r_cc_send_last_client.read() == 0) // dcache active request
5295	r_dcache_cc_send_req = false; // reset dcache request
5296	else // icache active request
5297	r_icache_cc_send_req = false; // reset icache request
5298
5299	// go back to idle state
5300	r_cc_send_fsm = CC_SEND_IDLE;
5301	}
5302	break;
5303	}
5304	///////////////////////////
5305	case CC_SEND_MULTI_ACK:
5306	{
5307	// wait for the flit to be consumed
5308	if(p_dspin_out.read.read())
5309	{
5310	if(r_cc_send_last_client.read() == 0) // dcache active request
5311	r_dcache_cc_send_req = false; // reset dcache request
5312	else // icache active request
5313	r_icache_cc_send_req = false; // reset icache request
5314	// go back to idle state
5315	r_cc_send_fsm = CC_SEND_IDLE;
5316	}
5317	break;
5318	}
5319	} // end switch CC_SEND FSM
5320
5321	///////////////////////////////////////////////////////////////////////////////
5322	// C_RECEIVE FSM
5323	// This FSM receive all coherence packets on a DSPIN40 port.
5324	// There is 4 packet types:
5325	// - CC_DATA_INVAL : DCACHE invalidate request
5326	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5327	// - CC_INST_INVAL : ICACHE invalidate request
5328	// - CC_INST_UPDT : ICACHE update request (multi-words)
5329	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5330	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5331	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5332	//////////////////////////////////////////////////////////////////////////////
5333	switch( r_cc_receive_fsm.read() )
5334	{
5335	/////////////////////
5336	case CC_RECEIVE_IDLE:
5337	{
5338	// a coherence request has arrived
5339	if (p_dspin_in.write.read())
5340	{
5341	// initialize dspin received data
5342	uint64_t receive_data = p_dspin_in.data.read();
5343	// initialize coherence packet type
5344	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5345	// initialize data/ins flip_flop (0 data / 1 ins)
5346	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5347	// test for a broadcast
5348	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5349	{
5350	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5351	}
5352	// test for a CLACK
5353	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5354	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5355	{
5356	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5357	}
5358	// test for a multi updt
5359	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5360	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5361	{
5362	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5363	}
5364	// test for a multi inval
5365	else
5366	{
5367	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5368	}
5369	}
5370	break;
5371	}
5372	//////////////////////
5373	case CC_RECEIVE_CLACK:
5374	{
5375	// initialize dspin received data
5376	uint64_t receive_data = p_dspin_in.data.read();
5377
5378	// for data CLACK, wait for dcache to take the request
5379	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5380	{
5381	// request dcache to handle the CLACK
5382	r_cc_receive_dcache_req = true;
5383	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5384	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5385	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5386	// get back to idle state
5387	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5388	break;
5389	}
5390	// for ins CLACK, wait for icache to take the request
5391	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5392	{
5393	// request icache to handle the CLACK
5394	r_cc_receive_icache_req = true;
5395	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5396	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5397	r_cc_receive_icache_type = CC_TYPE_CLACK;
5398	// get back to idle state
5399	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5400	break;
5401	}
5402	// keep waiting for the correct cache to accept the request
5403	break;
5404	}
5405	///////////////////////////////
5406	case CC_RECEIVE_BRDCAST_HEADER:
5407	{
5408	// no actual data in the HEADER, just skip to second flit
5409	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5410	break;
5411	}
5412	//////////////////////////////
5413	case CC_RECEIVE_BRDCAST_NLINE:
5414	{
5415	// initialize dspin received data
5416	uint64_t receive_data = p_dspin_in.data.read();
5417	// wait for both dcache and icache to take the request
5418	// TODO maybe we need to wait for both only to leave the state, but
5419	// not to actually post a request to an available cache => need a
5420	// flip_flop to check that ?
5421	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5422	{
5423	// request dcache to handle the BROADCAST
5424	r_cc_receive_dcache_req = true;
5425	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5426	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5427	// request icache to handle the BROADCAST
5428	r_cc_receive_icache_req = true;
5429	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5430	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5431	// get back to idle state
5432	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5433	break;
5434	}
5435	// keep waiting for the caches to accept the request
5436	break;
5437	}
5438	/////////////////////////////
5439	case CC_RECEIVE_INVAL_HEADER:
5440	{
5441	// sample updt tab index in the HEADER, then skip to second flit
5442	uint64_t receive_data = p_dspin_in.data.read();
5443	// for data INVAL, wait for dcache to take the request
5444	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5445	{
5446	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5447	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5448	break;
5449	}
5450	// for ins INVAL, wait for icache to take the request
5451	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5452	{
5453	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5454	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5455	break;
5456	}
5457	// keep waiting for the correct cache to accept the request
5458	break;
5459	}
5460	////////////////////////////
5461	case CC_RECEIVE_INVAL_NLINE:
5462	{
5463	// sample nline in the second flit
5464	uint64_t receive_data = p_dspin_in.data.read();
5465	// for data INVAL, wait for dcache to take the request
5466	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5467	{
5468	// request dcache to handle the INVAL
5469	r_cc_receive_dcache_req = true;
5470	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5471	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5472	// get back to idle state
5473	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5474	break;
5475	}
5476	// for ins INVAL, wait for icache to take the request
5477	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5478	{
5479	// request icache to handle the INVAL
5480	r_cc_receive_icache_req = true;
5481	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5482	r_cc_receive_icache_type = CC_TYPE_INVAL;
5483	// get back to idle state
5484	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5485	break;
5486	}
5487	// we should never get there
5488	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5489	}
5490	////////////////////////////
5491	case CC_RECEIVE_UPDT_HEADER:
5492	{
5493	// sample updt tab index in the HEADER, than skip to second flit
5494	uint64_t receive_data = p_dspin_in.data.read();
5495	// for data INVAL, wait for dcache to take the request and fifo to
5496	// be empty
5497	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5498	{
5499	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5500	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5501	break;
5502	}
5503	// for ins INVAL, wait for icache to take the request and fifo to be
5504	// empty
5505	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5506	{
5507	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5508	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5509	break;
5510	}
5511	// keep waiting for the correct cache to accept the request
5512	break;
5513	}
5514	///////////////////////////
5515	case CC_RECEIVE_UPDT_NLINE:
5516	{
5517	// sample nline and word index in the second flit
5518	uint64_t receive_data = p_dspin_in.data.read();
5519	// for data INVAL, wait for dcache to take the request and fifo to
5520	// be empty
5521	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5522	{
5523	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5524	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5525	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5526	// get back to idle state
5527	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5528	break;
5529	}
5530	// for ins INVAL, wait for icache to take the request and fifo to be
5531	// empty
5532	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5533	{
5534	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5535	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5536	r_cc_receive_icache_type = CC_TYPE_UPDT;
5537	// get back to idle state
5538	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5539	break;
5540	}
5541	// we should never get there
5542	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5543	break;
5544	}
5545	//////////////////////////
5546	case CC_RECEIVE_UPDT_DATA:
5547	{
5548	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5549	r_cc_receive_dcache_req = true;
5550	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5551	r_cc_receive_icache_req = true;
5552
5553	// sample data, be and eop
5554	uint64_t receive_data = p_dspin_in.data.read();
5555	// wait for the fifo
5556	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
5557	{
5558	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5559	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5560	// sample eop to test for state exit
5561	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5562	cc_receive_updt_fifo_eop = flit_eop;
5563	cc_receive_updt_fifo_put = true;
5564	if(flit_eop)
5565	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5566	}
5567	break;
5568	}
5569	} // end switch CC_RECEIVE FSM
5570
5571	///////////////// Response FIFOs update //////////////////////
5572	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5573	vci_rsp_fifo_icache_put,
5574	vci_rsp_fifo_icache_data);
5575
5576	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5577	vci_rsp_fifo_dcache_put,
5578	vci_rsp_fifo_dcache_data);
5579
5580	///////////////// updt FIFO update //////////////////////
5581	//TODO check this
5582	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5583	cc_receive_updt_fifo_put,
5584	cc_receive_updt_fifo_be);
5585	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5586	cc_receive_updt_fifo_put,
5587	cc_receive_updt_fifo_data);
5588	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5589	cc_receive_updt_fifo_put,
5590	cc_receive_updt_fifo_eop);
5591
5592	} // end transition()
5593
5594	///////////////////////
5595	tmpl(void)::genMoore()
5596	///////////////////////
5597	{
5598
5599	// VCI initiator command on the direct network
5600	// it depends on the CMD FSM state
5601
5602	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5603	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5604
5605	p_vci.pktid = 0;
5606	p_vci.srcid = m_srcid;
5607	p_vci.cons = is_sc_or_cas;
5608	p_vci.contig = not is_sc_or_cas;
5609	p_vci.wrap = false;
5610	p_vci.clen = 0;
5611	p_vci.cfixed = false;
5612
5613	switch ( r_vci_cmd_fsm.read() ) {
5614
5615	case CMD_IDLE:
5616	p_vci.cmdval = false;
5617	p_vci.address = 0;
5618	p_vci.wdata = 0;
5619	p_vci.be = 0;
5620	p_vci.trdid = 0;
5621	p_vci.pktid = 0;
5622	p_vci.plen = 0;
5623	p_vci.cmd = vci_param::CMD_NOP;
5624	p_vci.eop = false;
5625	break;
5626
5627	case CMD_INS_MISS:
5628	p_vci.cmdval = true;
5629	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5630	p_vci.wdata = 0;
5631	p_vci.be = 0xF;
5632	p_vci.trdid = 0;
5633	p_vci.pktid = TYPE_READ_INS_MISS;
5634	p_vci.plen = m_icache_words<<2;
5635	p_vci.cmd = vci_param::CMD_READ;
5636	p_vci.eop = true;
5637	break;
5638
5639	case CMD_INS_UNC:
5640	p_vci.cmdval = true;
5641	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5642	p_vci.wdata = 0;
5643	p_vci.be = 0xF;
5644	p_vci.trdid = 0;
5645	p_vci.pktid = TYPE_READ_INS_UNC;
5646	p_vci.plen = 4;
5647	p_vci.cmd = vci_param::CMD_READ;
5648	p_vci.eop = true;
5649	break;
5650
5651	case CMD_DATA_MISS:
5652	p_vci.cmdval = true;
5653	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5654	p_vci.wdata = 0;
5655	p_vci.be = 0xF;
5656	p_vci.trdid = 0;
5657	p_vci.pktid = TYPE_READ_DATA_MISS;
5658	p_vci.plen = m_dcache_words << 2;
5659	p_vci.cmd = vci_param::CMD_READ;
5660	p_vci.eop = true;
5661	break;
5662
5663	case CMD_DATA_UNC:
5664	p_vci.cmdval = true;
5665	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5666	p_vci.wdata = 0;
5667	p_vci.be = r_dcache_vci_unc_be.read();
5668	p_vci.trdid = 0;
5669	p_vci.pktid = TYPE_READ_DATA_UNC;
5670	p_vci.plen = 4;
5671	p_vci.cmd = vci_param::CMD_READ;
5672	p_vci.eop = true;
5673	break;
5674
5675	case CMD_DATA_WRITE:
5676	p_vci.cmdval = true;
5677	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5678	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5679	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5680	p_vci.trdid = r_wbuf.getIndex();
5681	p_vci.pktid = TYPE_WRITE;
5682	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5683	p_vci.cmd = vci_param::CMD_WRITE;
5684	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5685	break;
5686
5687	case CMD_DATA_LL:
5688	p_vci.cmdval = true;
5689	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5690	p_vci.wdata = 0;
5691	p_vci.be = 0xF;
5692	p_vci.trdid = 0;
5693	p_vci.pktid = TYPE_LL;
5694	p_vci.plen = 8;
5695	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5696	p_vci.eop = true;
5697	break;
5698
5699	case CMD_DATA_SC:
5700	p_vci.cmdval = true;
5701	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5702	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5703	else p_vci.wdata = r_dcache_vci_sc_data.read();
5704	p_vci.be = 0xF;
5705	p_vci.trdid = 0;
5706	p_vci.pktid = TYPE_SC;
5707	p_vci.plen = 8;
5708	p_vci.cmd = vci_param::CMD_NOP;
5709	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5710	break;
5711
5712	case CMD_DATA_CAS:
5713	p_vci.cmdval = true;
5714	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5715	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5716	else p_vci.wdata = r_dcache_vci_cas_new.read();
5717	p_vci.be = 0xF;
5718	p_vci.trdid = 0;
5719	p_vci.pktid = TYPE_CAS;
5720	p_vci.plen = 8;
5721	p_vci.cmd = vci_param::CMD_NOP;
5722	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5723	break;
5724	} // end switch r_vci_cmd_fsm
5725
5726	// VCI initiator response on the direct network
5727	// it depends on the VCI_RSP FSM
5728
5729	switch (r_vci_rsp_fsm.read() )
5730	{
5731	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5732	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5733	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5734	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5735	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5736	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5737	case RSP_IDLE : p_vci.rspack = false; break;
5738	} // end switch r_vci_rsp_fsm
5739
5740
5741	// Send coherence packets on DSPIN L2M
5742	// it depends on the CC_SEND FSM
5743
5744	uint64_t dspin_send_data = 0;
5745	switch ( r_cc_send_fsm.read() )
5746	{
5747	//////////////////
5748	case CC_SEND_IDLE:
5749	{
5750	p_dspin_out.write = false;
5751	break;
5752	}
5753	///////////////////////
5754	case CC_SEND_CLEANUP_1:
5755	{
5756	// initialize dspin send data
5757	DspinDhccpParam::dspin_set(dspin_send_data,
5758	0,
5759	DspinDhccpParam::FROM_L1_EOP);
5760	DspinDhccpParam::dspin_set(dspin_send_data,
5761	m_cc_global_id,
5762	DspinDhccpParam::CLEANUP_SRCID);
5763	DspinDhccpParam::dspin_set(dspin_send_data,
5764	0,
5765	DspinDhccpParam::FROM_L1_BC);
5766
5767	if(r_cc_send_last_client.read() == 0) // dcache active request
5768	{
5769	uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read()
5770	>> (m_nline_width - m_x_width - m_y_width)
5771	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5772
5773	DspinDhccpParam::dspin_set(dspin_send_data,
5774	dest,
5775	DspinDhccpParam::CLEANUP_DEST);
5776
5777	DspinDhccpParam::dspin_set(dspin_send_data,
5778	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5779	DspinDhccpParam::CLEANUP_NLINE_MSB);
5780
5781	DspinDhccpParam::dspin_set(dspin_send_data,
5782	r_dcache_cc_send_way.read(),
5783	DspinDhccpParam::CLEANUP_WAY_INDEX);
5784
5785	DspinDhccpParam::dspin_set(dspin_send_data,
5786	DspinDhccpParam::TYPE_CLEANUP_DATA,
5787	DspinDhccpParam::FROM_L1_TYPE);
5788	}
5789	else // icache active request
5790	{
5791	uint64_t dest = (uint64_t)r_icache_cc_send_nline.read()
5792	>> (m_nline_width - m_x_width - m_y_width)
5793	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5794
5795	DspinDhccpParam::dspin_set(dspin_send_data,
5796	dest,
5797	DspinDhccpParam::CLEANUP_DEST);
5798
5799	DspinDhccpParam::dspin_set(dspin_send_data,
5800	r_icache_cc_send_nline.read() & 0x300000000ULL,
5801	DspinDhccpParam::CLEANUP_NLINE_MSB);
5802
5803	DspinDhccpParam::dspin_set(dspin_send_data,
5804	r_icache_cc_send_way.read(),
5805	DspinDhccpParam::CLEANUP_WAY_INDEX);
5806
5807	DspinDhccpParam::dspin_set(dspin_send_data,
5808	DspinDhccpParam::TYPE_CLEANUP_INST,
5809	DspinDhccpParam::FROM_L1_TYPE);
5810	}
5811	// send flit
5812	p_dspin_out.data = dspin_send_data;
5813	p_dspin_out.write = true;
5814	break;
5815	}
5816	///////////////////////
5817	case CC_SEND_CLEANUP_2:
5818	{
5819	// initialize dspin send data
5820	DspinDhccpParam::dspin_set(dspin_send_data,
5821	1,
5822	DspinDhccpParam::FROM_L1_EOP);
5823
5824	if(r_cc_send_last_client.read() == 0) // dcache active request
5825	{
5826	DspinDhccpParam::dspin_set(dspin_send_data,
5827	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5828	DspinDhccpParam::CLEANUP_NLINE_LSB);
5829	}
5830	else // icache active request
5831	{
5832	DspinDhccpParam::dspin_set(dspin_send_data,
5833	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5834	DspinDhccpParam::CLEANUP_NLINE_LSB);
5835	}
5836	// send flit
5837	p_dspin_out.data = dspin_send_data;
5838	p_dspin_out.write = true;
5839	break;
5840	}
5841	///////////////////////
5842	case CC_SEND_MULTI_ACK:
5843	{
5844	// initialize dspin send data
5845	DspinDhccpParam::dspin_set(dspin_send_data,
5846	1,
5847	DspinDhccpParam::FROM_L1_EOP);
5848	DspinDhccpParam::dspin_set(dspin_send_data,
5849	0,
5850	DspinDhccpParam::FROM_L1_BC);
5851	DspinDhccpParam::dspin_set(dspin_send_data,
5852	DspinDhccpParam::TYPE_MULTI_ACK,
5853	DspinDhccpParam::FROM_L1_TYPE);
5854
5855	if(r_cc_send_last_client.read() == 0) // dcache active request
5856	{
5857	uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read()
5858	>> (m_nline_width - m_x_width - m_y_width)
5859	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5860
5861	DspinDhccpParam::dspin_set(dspin_send_data,
5862	dest,
5863	DspinDhccpParam::MULTI_ACK_DEST);
5864
5865	DspinDhccpParam::dspin_set(dspin_send_data,
5866	r_dcache_cc_send_updt_tab_idx.read(),
5867	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5868	}
5869	else // icache active request
5870	{
5871	uint64_t dest = (uint64_t)r_icache_cc_send_nline.read()
5872	>> (m_nline_width - m_x_width - m_y_width)
5873	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5874
5875
5876	DspinDhccpParam::dspin_set(dspin_send_data,
5877	dest,
5878	DspinDhccpParam::MULTI_ACK_DEST);
5879
5880	DspinDhccpParam::dspin_set(dspin_send_data,
5881	r_icache_cc_send_updt_tab_idx.read(),
5882	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5883	}
5884	// send flit
5885	p_dspin_out.data = dspin_send_data;
5886	p_dspin_out.write = true;
5887
5888	break;
5889	}
5890	} // end switch CC_SEND FSM
5891
5892	// Receive coherence packets
5893	// It depends on the CC_RECEIVE FSM
5894
5895	switch( r_cc_receive_fsm.read() )
5896	{
5897	/////////////////////
5898	case CC_RECEIVE_IDLE:
5899	{
5900	p_dspin_in.read = false;
5901	break;
5902	}
5903	//////////////////////
5904	case CC_RECEIVE_CLACK:
5905	{
5906	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5907	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5908	p_dspin_in.read = true;
5909	else
5910	p_dspin_in.read = false;
5911	break;
5912	}
5913	///////////////////////////////
5914	case CC_RECEIVE_BRDCAST_HEADER:
5915	{
5916	p_dspin_in.read = true;
5917	break;
5918	}
5919	//////////////////////////////
5920	case CC_RECEIVE_BRDCAST_NLINE:
5921	{
5922	// TODO maybe we need to wait for both only to leave the state, but
5923	// not to actually post a request to an available cache => need a
5924	// flip_flop to check that ?
5925	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5926	p_dspin_in.read = true;
5927	else
5928	p_dspin_in.read = false;
5929	break;
5930	}
5931	/////////////////////////////
5932	case CC_RECEIVE_INVAL_HEADER:
5933	{
5934	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5935	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5936	p_dspin_in.read = true;
5937	else
5938	p_dspin_in.read = false;
5939	break;
5940	}
5941	////////////////////////////
5942	case CC_RECEIVE_INVAL_NLINE:
5943	{
5944	p_dspin_in.read = true;
5945	break;
5946	}
5947	////////////////////////////
5948	case CC_RECEIVE_UPDT_HEADER:
5949	{
5950	if (((r_cc_receive_data_ins.read() == 0) and
5951	not r_cc_receive_dcache_req.read() and
5952	r_cc_receive_updt_fifo_be.empty())
5953	or
5954	((r_cc_receive_data_ins.read() == 1) and
5955	not r_cc_receive_icache_req.read()) and
5956	r_cc_receive_updt_fifo_be.empty())
5957	p_dspin_in.read = true;
5958	else
5959	p_dspin_in.read = false;
5960	break;
5961	}
5962	///////////////////////////
5963	case CC_RECEIVE_UPDT_NLINE:
5964	{
5965	if (((r_cc_receive_data_ins.read() == 0) and
5966	not (r_cc_receive_dcache_req.read()) and
5967	r_cc_receive_updt_fifo_be.empty())
5968	or
5969	((r_cc_receive_data_ins.read() == 1) and
5970	not (r_cc_receive_icache_req.read()) and
5971	r_cc_receive_updt_fifo_be.empty()))
5972	p_dspin_in.read = true;
5973	else
5974	p_dspin_in.read = false;
5975	break;
5976	}
5977	//////////////////////////
5978	case CC_RECEIVE_UPDT_DATA:
5979	{
5980	if (r_cc_receive_updt_fifo_be.wok())
5981	p_dspin_in.read = true;
5982	else
5983	p_dspin_in.read = false;
5984	break;
5985	}
5986	} // end switch CC_RECEIVE FSM
5987
5988	} // end genMoore
5989
5990	}}
5991
5992	// Local Variables:
5993	// tab-width: 4
5994	// c-basic-offset: 4
5995	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5996	// indent-tabs-mode: nil
5997	// End:
5998
5999	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0