1 | /* -*- c++ -*- |
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2 | * File : vci_mem_cache.h |
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3 | * Date : 26/10/2008 |
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4 | * Copyright : UPMC / LIP6 |
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5 | * Authors : Alain Greiner / Eric Guthmuller |
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6 | * |
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7 | * SOCLIB_LGPL_HEADER_BEGIN |
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8 | * |
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9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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10 | * |
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11 | * SoCLib is free software; you can redistribute it and/or modify it |
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12 | * under the terms of the GNU Lesser General Public License as published |
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13 | * by the Free Software Foundation; version 2.1 of the License. |
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14 | * |
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15 | * SoCLib is distributed in the hope that it will be useful, but |
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16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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18 | * Lesser General Public License for more details. |
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19 | * |
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20 | * You should have received a copy of the GNU Lesser General Public |
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21 | * License along with SoCLib; if not, write to the Free Software |
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22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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23 | * 02110-1301 USA |
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24 | * |
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25 | * SOCLIB_LGPL_HEADER_END |
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26 | * |
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27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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28 | * cesar.fuguet-tortolero@lip6.fr |
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29 | * alexandre.joannou@lip6.fr |
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30 | */ |
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31 | |
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32 | #ifndef SOCLIB_CABA_MEM_CACHE_H |
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33 | #define SOCLIB_CABA_MEM_CACHE_H |
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34 | |
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35 | #include <inttypes.h> |
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36 | #include <systemc> |
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37 | #include <list> |
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38 | #include <cassert> |
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39 | #include "arithmetics.h" |
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40 | #include "alloc_elems.h" |
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41 | #include "caba_base_module.h" |
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42 | #include "vci_target.h" |
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43 | #include "vci_initiator.h" |
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44 | #include "generic_fifo.h" |
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45 | #include "mapping_table.h" |
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46 | #include "int_tab.h" |
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47 | #include "generic_llsc_global_table.h" |
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48 | #include "mem_cache_directory.h" |
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49 | #include "xram_transaction.h" |
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50 | #include "update_tab.h" |
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51 | #include "dspin_interface.h" |
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52 | #include "dspin_dhccp_param.h" |
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53 | |
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54 | #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab |
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55 | #define UPDATE_TAB_LINES 4 // Number of lines in the update tab |
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56 | |
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57 | namespace soclib { namespace caba { |
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58 | using namespace sc_core; |
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59 | |
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60 | template<typename vci_param> |
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61 | class VciMemCache |
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62 | : public soclib::caba::BaseModule |
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63 | { |
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64 | typedef sc_dt::sc_uint<40> addr_t; |
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65 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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66 | typedef uint32_t data_t; |
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67 | typedef uint32_t tag_t; |
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68 | typedef uint32_t size_t; |
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69 | typedef uint32_t be_t; |
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70 | typedef uint32_t copy_t; |
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71 | |
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72 | /* States of the TGT_CMD fsm */ |
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73 | enum tgt_cmd_fsm_state_e{ |
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74 | TGT_CMD_IDLE, |
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75 | TGT_CMD_READ, |
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76 | TGT_CMD_WRITE, |
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77 | TGT_CMD_CAS |
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78 | }; |
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79 | |
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80 | /* States of the TGT_RSP fsm */ |
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81 | enum tgt_rsp_fsm_state_e{ |
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82 | TGT_RSP_READ_IDLE, |
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83 | TGT_RSP_WRITE_IDLE, |
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84 | TGT_RSP_CAS_IDLE, |
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85 | TGT_RSP_XRAM_IDLE, |
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86 | TGT_RSP_INIT_IDLE, |
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87 | TGT_RSP_CLEANUP_IDLE, |
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88 | TGT_RSP_READ, |
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89 | TGT_RSP_WRITE, |
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90 | TGT_RSP_CAS, |
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91 | TGT_RSP_XRAM, |
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92 | TGT_RSP_INIT, |
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93 | TGT_RSP_CLEANUP |
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94 | }; |
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95 | |
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96 | /* States of the DSPIN_TGT fsm */ |
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97 | enum cc_receive_fsm_state_e{ |
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98 | CC_RECEIVE_IDLE, |
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99 | CC_RECEIVE_CLEANUP, |
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100 | CC_RECEIVE_MULTI_ACK |
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101 | }; |
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102 | |
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103 | /* States of the CC_SEND fsm */ |
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104 | enum cc_send_fsm_state_e{ |
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105 | CC_SEND_XRAM_RSP_IDLE, |
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106 | CC_SEND_WRITE_IDLE, |
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107 | CC_SEND_CAS_IDLE, |
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108 | CC_SEND_CLEANUP_IDLE, |
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109 | CC_SEND_CLEANUP_ACK, |
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110 | CC_SEND_XRAM_RSP_BRDCAST_HEADER, |
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111 | CC_SEND_XRAM_RSP_BRDCAST_NLINE, |
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112 | CC_SEND_XRAM_RSP_INVAL_HEADER, |
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113 | CC_SEND_XRAM_RSP_INVAL_NLINE, |
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114 | CC_SEND_WRITE_BRDCAST_HEADER, |
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115 | CC_SEND_WRITE_BRDCAST_NLINE, |
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116 | CC_SEND_WRITE_UPDT_HEADER, |
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117 | CC_SEND_WRITE_UPDT_NLINE, |
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118 | CC_SEND_WRITE_UPDT_DATA, |
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119 | CC_SEND_CAS_BRDCAST_HEADER, |
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120 | CC_SEND_CAS_BRDCAST_NLINE, |
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121 | CC_SEND_CAS_UPDT_HEADER, |
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122 | CC_SEND_CAS_UPDT_NLINE, |
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123 | CC_SEND_CAS_UPDT_DATA, |
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124 | CC_SEND_CAS_UPDT_DATA_HIGH |
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125 | }; |
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126 | |
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127 | /* States of the MULTI_ACK fsm */ |
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128 | enum multi_ack_fsm_state_e{ |
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129 | MULTI_ACK_IDLE, |
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130 | MULTI_ACK_UPT_LOCK, |
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131 | MULTI_ACK_UPT_CLEAR, |
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132 | MULTI_ACK_WRITE_RSP |
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133 | }; |
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134 | |
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135 | /* States of the READ fsm */ |
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136 | enum read_fsm_state_e{ |
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137 | READ_IDLE, |
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138 | READ_DIR_REQ, |
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139 | READ_DIR_LOCK, |
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140 | READ_DIR_HIT, |
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141 | READ_HEAP_REQ, |
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142 | READ_HEAP_LOCK, |
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143 | READ_HEAP_WRITE, |
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144 | READ_HEAP_ERASE, |
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145 | READ_HEAP_LAST, |
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146 | READ_RSP, |
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147 | READ_TRT_LOCK, |
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148 | READ_TRT_SET, |
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149 | READ_TRT_REQ |
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150 | }; |
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151 | |
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152 | /* States of the WRITE fsm */ |
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153 | enum write_fsm_state_e{ |
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154 | WRITE_IDLE, |
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155 | WRITE_NEXT, |
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156 | WRITE_DIR_REQ, |
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157 | WRITE_DIR_LOCK, |
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158 | WRITE_DIR_READ, |
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159 | WRITE_DIR_HIT, |
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160 | WRITE_UPT_LOCK, |
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161 | WRITE_UPT_HEAP_LOCK, |
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162 | WRITE_UPT_REQ, |
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163 | WRITE_UPT_NEXT, |
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164 | WRITE_UPT_DEC, |
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165 | WRITE_RSP, |
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166 | WRITE_MISS_TRT_LOCK, |
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167 | WRITE_MISS_TRT_DATA, |
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168 | WRITE_MISS_TRT_SET, |
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169 | WRITE_MISS_XRAM_REQ, |
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170 | WRITE_BC_TRT_LOCK, |
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171 | WRITE_BC_UPT_LOCK, |
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172 | WRITE_BC_DIR_INVAL, |
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173 | WRITE_BC_CC_SEND, |
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174 | WRITE_BC_XRAM_REQ, |
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175 | WRITE_WAIT |
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176 | }; |
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177 | |
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178 | /* States of the IXR_RSP fsm */ |
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179 | enum ixr_rsp_fsm_state_e{ |
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180 | IXR_RSP_IDLE, |
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181 | IXR_RSP_ACK, |
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182 | IXR_RSP_TRT_ERASE, |
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183 | IXR_RSP_TRT_READ |
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184 | }; |
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185 | |
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186 | /* States of the XRAM_RSP fsm */ |
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187 | enum xram_rsp_fsm_state_e{ |
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188 | XRAM_RSP_IDLE, |
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189 | XRAM_RSP_TRT_COPY, |
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190 | XRAM_RSP_TRT_DIRTY, |
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191 | XRAM_RSP_DIR_LOCK, |
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192 | XRAM_RSP_DIR_UPDT, |
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193 | XRAM_RSP_DIR_RSP, |
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194 | XRAM_RSP_INVAL_LOCK, |
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195 | XRAM_RSP_INVAL_WAIT, |
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196 | XRAM_RSP_INVAL, |
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197 | XRAM_RSP_WRITE_DIRTY, |
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198 | XRAM_RSP_HEAP_REQ, |
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199 | XRAM_RSP_HEAP_ERASE, |
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200 | XRAM_RSP_HEAP_LAST, |
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201 | XRAM_RSP_ERROR_ERASE, |
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202 | XRAM_RSP_ERROR_RSP |
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203 | }; |
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204 | |
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205 | /* States of the IXR_CMD fsm */ |
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206 | enum ixr_cmd_fsm_state_e{ |
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207 | IXR_CMD_READ_IDLE, |
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208 | IXR_CMD_WRITE_IDLE, |
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209 | IXR_CMD_CAS_IDLE, |
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210 | IXR_CMD_XRAM_IDLE, |
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211 | IXR_CMD_READ_NLINE, |
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212 | IXR_CMD_WRITE_NLINE, |
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213 | IXR_CMD_CAS_NLINE, |
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214 | IXR_CMD_XRAM_DATA |
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215 | }; |
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216 | |
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217 | /* States of the CAS fsm */ |
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218 | enum cas_fsm_state_e{ |
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219 | CAS_IDLE, |
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220 | CAS_DIR_REQ, |
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221 | CAS_DIR_LOCK, |
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222 | CAS_DIR_HIT_READ, |
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223 | CAS_DIR_HIT_COMPARE, |
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224 | CAS_DIR_HIT_WRITE, |
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225 | CAS_UPT_LOCK, |
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226 | CAS_UPT_HEAP_LOCK, |
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227 | CAS_UPT_REQ, |
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228 | CAS_UPT_NEXT, |
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229 | CAS_BC_TRT_LOCK, |
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230 | CAS_BC_UPT_LOCK, |
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231 | CAS_BC_DIR_INVAL, |
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232 | CAS_BC_CC_SEND, |
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233 | CAS_BC_XRAM_REQ, |
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234 | CAS_RSP_FAIL, |
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235 | CAS_RSP_SUCCESS, |
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236 | CAS_MISS_TRT_LOCK, |
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237 | CAS_MISS_TRT_SET, |
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238 | CAS_MISS_XRAM_REQ, |
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239 | CAS_WAIT |
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240 | }; |
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241 | |
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242 | /* States of the CLEANUP fsm */ |
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243 | enum cleanup_fsm_state_e{ |
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244 | CLEANUP_IDLE, |
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245 | CLEANUP_GET_NLINE, |
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246 | CLEANUP_DIR_REQ, |
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247 | CLEANUP_DIR_LOCK, |
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248 | CLEANUP_DIR_WRITE, |
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249 | CLEANUP_HEAP_REQ, |
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250 | CLEANUP_HEAP_LOCK, |
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251 | CLEANUP_HEAP_SEARCH, |
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252 | CLEANUP_HEAP_CLEAN, |
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253 | CLEANUP_HEAP_FREE, |
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254 | CLEANUP_UPT_LOCK, |
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255 | CLEANUP_UPT_DECREMENT, |
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256 | CLEANUP_UPT_CLEAR, |
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257 | CLEANUP_WRITE_RSP, |
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258 | CLEANUP_SEND_ACK |
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259 | }; |
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260 | |
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261 | /* States of the ALLOC_DIR fsm */ |
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262 | enum alloc_dir_fsm_state_e{ |
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263 | ALLOC_DIR_RESET, |
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264 | ALLOC_DIR_READ, |
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265 | ALLOC_DIR_WRITE, |
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266 | ALLOC_DIR_CAS, |
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267 | ALLOC_DIR_CLEANUP, |
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268 | ALLOC_DIR_XRAM_RSP |
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269 | }; |
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270 | |
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271 | /* States of the ALLOC_TRT fsm */ |
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272 | enum alloc_trt_fsm_state_e{ |
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273 | ALLOC_TRT_READ, |
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274 | ALLOC_TRT_WRITE, |
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275 | ALLOC_TRT_CAS, |
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276 | ALLOC_TRT_XRAM_RSP, |
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277 | ALLOC_TRT_IXR_RSP |
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278 | }; |
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279 | |
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280 | /* States of the ALLOC_UPT fsm */ |
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281 | enum alloc_upt_fsm_state_e{ |
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282 | ALLOC_UPT_WRITE, |
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283 | ALLOC_UPT_XRAM_RSP, |
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284 | ALLOC_UPT_MULTI_ACK, |
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285 | ALLOC_UPT_CLEANUP, |
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286 | ALLOC_UPT_CAS |
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287 | }; |
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288 | |
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289 | /* States of the ALLOC_HEAP fsm */ |
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290 | enum alloc_heap_fsm_state_e{ |
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291 | ALLOC_HEAP_RESET, |
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292 | ALLOC_HEAP_READ, |
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293 | ALLOC_HEAP_WRITE, |
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294 | ALLOC_HEAP_CAS, |
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295 | ALLOC_HEAP_CLEANUP, |
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296 | ALLOC_HEAP_XRAM_RSP |
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297 | }; |
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298 | |
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299 | /* transaction type, pktid field */ |
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300 | enum transaction_type_e |
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301 | { |
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302 | // b3 unused |
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303 | // b2 READ / NOT READ |
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304 | // Si READ |
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305 | // b1 DATA / INS |
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306 | // b0 UNC / MISS |
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307 | // Si NOT READ |
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308 | // b1 accÚs table llsc type SW / other |
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309 | // b2 WRITE/CAS/LL/SC |
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310 | TYPE_READ_DATA_UNC = 0x0, |
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311 | TYPE_READ_DATA_MISS = 0x1, |
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312 | TYPE_READ_INS_UNC = 0x2, |
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313 | TYPE_READ_INS_MISS = 0x3, |
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314 | TYPE_WRITE = 0x4, |
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315 | TYPE_CAS = 0x5, |
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316 | TYPE_LL = 0x6, |
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317 | TYPE_SC = 0x7 |
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318 | }; |
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319 | |
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320 | /* SC return values */ |
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321 | enum sc_status_type_e |
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322 | { |
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323 | SC_SUCCESS = 0x00000000, |
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324 | SC_FAIL = 0x00000001 |
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325 | }; |
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326 | |
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327 | // debug variables (for each FSM) |
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328 | bool m_debug_global; |
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329 | bool m_debug_tgt_cmd_fsm; |
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330 | bool m_debug_tgt_rsp_fsm; |
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331 | bool m_debug_cc_send_fsm; |
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332 | bool m_debug_cc_receive_fsm; |
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333 | bool m_debug_multi_ack_fsm; |
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334 | bool m_debug_read_fsm; |
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335 | bool m_debug_write_fsm; |
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336 | bool m_debug_cas_fsm; |
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337 | bool m_debug_cleanup_fsm; |
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338 | bool m_debug_ixr_cmd_fsm; |
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339 | bool m_debug_ixr_rsp_fsm; |
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340 | bool m_debug_xram_rsp_fsm; |
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341 | bool m_debug_previous_hit; |
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342 | size_t m_debug_previous_count; |
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343 | |
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344 | bool m_monitor_ok; |
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345 | vci_addr_t m_monitor_base; |
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346 | vci_addr_t m_monitor_length; |
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347 | |
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348 | // instrumentation counters |
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349 | uint32_t m_cpt_cycles; // Counter of cycles |
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350 | uint32_t m_cpt_read; // Number of READ transactions |
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351 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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352 | uint32_t m_cpt_write; // Number of WRITE transactions |
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353 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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354 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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355 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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356 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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357 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
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358 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
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359 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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360 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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361 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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362 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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363 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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364 | uint32_t m_cpt_ll; // Number of LL transactions |
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365 | uint32_t m_cpt_sc; // Number of SC transactions |
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366 | uint32_t m_cpt_cas; // Number of CAS transactions |
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367 | |
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368 | size_t m_prev_count; |
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369 | |
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370 | protected: |
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371 | |
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372 | SC_HAS_PROCESS(VciMemCache); |
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373 | |
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374 | public: |
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375 | sc_in<bool> p_clk; |
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376 | sc_in<bool> p_resetn; |
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377 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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378 | soclib::caba::VciInitiator<vci_param> p_vci_ixr; |
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379 | soclib::caba::DspinInput<33> p_dspin_in; |
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380 | soclib::caba::DspinOutput<40> p_dspin_out; |
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381 | |
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382 | VciMemCache( |
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383 | sc_module_name name, // Instance Name |
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384 | const soclib::common::MappingTable &mtp, // Mapping table for direct network |
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385 | const soclib::common::MappingTable &mtx, // Mapping table for external network |
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386 | const soclib::common::IntTab &srcid_x, // global index on external network |
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387 | const soclib::common::IntTab &tgtid_d, // global index on direct network |
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388 | const size_t cc_global_id, // global index on cc network |
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389 | const size_t nways, // Number of ways per set |
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390 | const size_t nsets, // Number of sets |
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391 | const size_t nwords, // Number of words per line |
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392 | const size_t max_copies, // max number of copies in heap |
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393 | const size_t heap_size=1024, // number of heap entries |
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394 | const size_t trt_lines=TRANSACTION_TAB_LINES, |
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395 | const size_t upt_lines=UPDATE_TAB_LINES, |
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396 | const size_t debug_start_cycle=0, |
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397 | const bool debug_ok=false ); |
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398 | |
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399 | ~VciMemCache(); |
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400 | |
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401 | void print_stats(); |
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402 | void print_trace(); |
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403 | void copies_monitor(vci_addr_t addr); |
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404 | void start_monitor(vci_addr_t addr, vci_addr_t length); |
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405 | void stop_monitor(); |
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406 | |
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407 | private: |
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408 | |
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409 | void transition(); |
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410 | void genMoore(); |
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411 | void check_monitor( const char *buf, vci_addr_t addr, data_t data); |
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412 | void check_monitor_read( const char *buf, vci_addr_t addr); |
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413 | |
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414 | // Component attributes |
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415 | std::list<soclib::common::Segment> m_seglist; // segments allocated to memcache |
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416 | size_t m_nseg; // number of segments |
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417 | soclib::common::Segment **m_seg; // array of segments pointers |
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418 | const size_t m_srcid_x; // global index on external network |
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419 | const size_t m_initiators; // Number of initiators |
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420 | const size_t m_heap_size; // Size of the heap |
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421 | const size_t m_ways; // Number of ways in a set |
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422 | const size_t m_sets; // Number of cache sets |
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423 | const size_t m_words; // Number of words in a line |
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424 | const size_t m_cc_global_id; // global_index on cc network |
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425 | size_t m_debug_start_cycle; |
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426 | bool m_debug_ok; |
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427 | uint32_t m_trt_lines; |
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428 | TransactionTab m_trt; // xram transaction table |
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429 | uint32_t m_upt_lines; |
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430 | UpdateTab m_upt; // pending update & invalidate |
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431 | CacheDirectory m_cache_directory; // data cache directory |
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432 | CacheData m_cache_data; // data array[set][way][word] |
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433 | HeapDirectory m_heap; // heap for copies |
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434 | size_t m_max_copies; // max number of copies in heap |
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435 | GenericLLSCGlobalTable |
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436 | < 32 , // number of slots |
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437 | 4096, // number of processors in the system |
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438 | 8000, // registratioçn life span (in # of LL operations) |
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439 | typename vci_param::fast_addr_t > // address type |
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440 | m_llsc_table; // ll/sc global registration table |
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441 | |
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442 | // adress masks |
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443 | const soclib::common::AddressMaskingTable<vci_addr_t> m_x; |
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444 | const soclib::common::AddressMaskingTable<vci_addr_t> m_y; |
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445 | const soclib::common::AddressMaskingTable<vci_addr_t> m_z; |
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446 | const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; |
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447 | |
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448 | // broadcast address |
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449 | uint32_t m_broadcast_address; |
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450 | |
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451 | ////////////////////////////////////////////////// |
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452 | // Registers controlled by the TGT_CMD fsm |
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453 | ////////////////////////////////////////////////// |
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454 | |
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455 | // Fifo between TGT_CMD fsm and READ fsm |
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456 | GenericFifo<uint64_t> m_cmd_read_addr_fifo; |
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457 | GenericFifo<size_t> m_cmd_read_length_fifo; |
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458 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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459 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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460 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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461 | |
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462 | // Fifo between TGT_CMD fsm and WRITE fsm |
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463 | GenericFifo<uint64_t> m_cmd_write_addr_fifo; |
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464 | GenericFifo<bool> m_cmd_write_eop_fifo; |
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465 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
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466 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
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467 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
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468 | GenericFifo<data_t> m_cmd_write_data_fifo; |
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469 | GenericFifo<be_t> m_cmd_write_be_fifo; |
---|
470 | |
---|
471 | // Fifo between TGT_CMD fsm and CAS fsm |
---|
472 | GenericFifo<uint64_t> m_cmd_cas_addr_fifo; |
---|
473 | GenericFifo<bool> m_cmd_cas_eop_fifo; |
---|
474 | GenericFifo<size_t> m_cmd_cas_srcid_fifo; |
---|
475 | GenericFifo<size_t> m_cmd_cas_trdid_fifo; |
---|
476 | GenericFifo<size_t> m_cmd_cas_pktid_fifo; |
---|
477 | GenericFifo<data_t> m_cmd_cas_wdata_fifo; |
---|
478 | |
---|
479 | // Fifo between INIT_RSP fsm and CLEANUP fsm |
---|
480 | GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; |
---|
481 | |
---|
482 | // Fifo between INIT_RSP fsm and MULTI_ACK fsm |
---|
483 | GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; |
---|
484 | |
---|
485 | sc_signal<int> r_tgt_cmd_fsm; |
---|
486 | |
---|
487 | /////////////////////////////////////////////////////// |
---|
488 | // Registers controlled by the READ fsm |
---|
489 | /////////////////////////////////////////////////////// |
---|
490 | |
---|
491 | sc_signal<int> r_read_fsm; // FSM state |
---|
492 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
---|
493 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
---|
494 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
---|
495 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
---|
496 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
---|
497 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
---|
498 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
---|
499 | sc_signal<size_t> r_read_count; // number of copies |
---|
500 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
---|
501 | sc_signal<data_t> * r_read_data; // data (one cache line) |
---|
502 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
503 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
504 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
505 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
506 | sc_signal<typename vci_param::fast_addr_t> |
---|
507 | r_read_ll_key; // LL key returned by the llsc_global_table |
---|
508 | |
---|
509 | // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
510 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
511 | sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index |
---|
512 | sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table |
---|
513 | |
---|
514 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
515 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
516 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
517 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
518 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
519 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
---|
520 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
521 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
522 | sc_signal<typename vci_param::fast_addr_t> |
---|
523 | r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table |
---|
524 | |
---|
525 | /////////////////////////////////////////////////////////////// |
---|
526 | // Registers controlled by the WRITE fsm |
---|
527 | /////////////////////////////////////////////////////////////// |
---|
528 | |
---|
529 | sc_signal<int> r_write_fsm; // FSM state |
---|
530 | sc_signal<addr_t> r_write_address; // first word address |
---|
531 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
532 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
533 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
534 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
535 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
536 | sc_signal<data_t> * r_write_data; // data (one cache line) |
---|
537 | sc_signal<be_t> * r_write_be; // one byte enable per word |
---|
538 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
---|
539 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
540 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
541 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
542 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
543 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
---|
544 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
545 | sc_signal<size_t> r_write_count; // number of copies |
---|
546 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
547 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
548 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
549 | sc_signal<size_t> r_write_way; // way of the line |
---|
550 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
551 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
552 | sc_signal<bool> r_write_sc_fail; // sc command failed |
---|
553 | sc_signal<bool> r_write_pending_sc; // sc command pending |
---|
554 | |
---|
555 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
556 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
557 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
558 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
559 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
560 | sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed |
---|
561 | |
---|
562 | // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
563 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
564 | sc_signal<bool> r_write_to_ixr_cmd_write; // write request |
---|
565 | sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index |
---|
566 | sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data |
---|
567 | sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table |
---|
568 | |
---|
569 | // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
570 | sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request |
---|
571 | sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request |
---|
572 | sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index |
---|
573 | sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table |
---|
574 | sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line) |
---|
575 | sc_signal<be_t> * r_write_to_cc_send_be; // word enable |
---|
576 | sc_signal<size_t> r_write_to_cc_send_count; // number of words in line |
---|
577 | sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line |
---|
578 | GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
579 | GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids |
---|
580 | #if L1_MULTI_CACHE |
---|
581 | GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
582 | #endif |
---|
583 | |
---|
584 | // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) |
---|
585 | sc_signal<bool> r_write_to_multi_ack_req; // valid request |
---|
586 | sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table |
---|
587 | |
---|
588 | ///////////////////////////////////////////////////////// |
---|
589 | // Registers controlled by MULTI_ACK fsm |
---|
590 | ////////////////////////////////////////////////////////// |
---|
591 | |
---|
592 | sc_signal<int> r_multi_ack_fsm; // FSM state |
---|
593 | sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table |
---|
594 | sc_signal<size_t> r_multi_ack_srcid; // pending write srcid |
---|
595 | sc_signal<size_t> r_multi_ack_trdid; // pending write trdid |
---|
596 | sc_signal<size_t> r_multi_ack_pktid; // pending write pktid |
---|
597 | sc_signal<addr_t> r_multi_ack_nline; // pending write nline |
---|
598 | |
---|
599 | // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) |
---|
600 | sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request |
---|
601 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid |
---|
602 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid |
---|
603 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid |
---|
604 | |
---|
605 | /////////////////////////////////////////////////////// |
---|
606 | // Registers controlled by CLEANUP fsm |
---|
607 | /////////////////////////////////////////////////////// |
---|
608 | |
---|
609 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
610 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
611 | sc_signal<bool> r_cleanup_inst; // Instruction or Data ? |
---|
612 | sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index |
---|
613 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
614 | |
---|
615 | #if L1_MULTI_CACHE |
---|
616 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
---|
617 | #endif |
---|
618 | |
---|
619 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
620 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
---|
621 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
622 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
623 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
624 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
625 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
626 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
---|
627 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
628 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
629 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
630 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
631 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
632 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
633 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
634 | |
---|
635 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response |
---|
636 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
637 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
638 | sc_signal<bool> r_cleanup_write_need_rsp;// needs a write rsp |
---|
639 | |
---|
640 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
641 | |
---|
642 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
643 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
644 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
645 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
646 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
647 | |
---|
648 | // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1) |
---|
649 | sc_signal<bool> r_cleanup_to_cc_send_req; // valid request |
---|
650 | sc_signal<size_t> r_cleanup_to_cc_send_srcid; // L1 srcid |
---|
651 | sc_signal<size_t> r_cleanup_to_cc_send_set_index; // L1 set index |
---|
652 | sc_signal<size_t> r_cleanup_to_cc_send_way_index; // L1 way index |
---|
653 | sc_signal<bool> r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack |
---|
654 | |
---|
655 | /////////////////////////////////////////////////////// |
---|
656 | // Registers controlled by CAS fsm |
---|
657 | /////////////////////////////////////////////////////// |
---|
658 | |
---|
659 | sc_signal<int> r_cas_fsm; // FSM state |
---|
660 | sc_signal<data_t> r_cas_wdata; // write data word |
---|
661 | sc_signal<data_t> * r_cas_rdata; // read data word |
---|
662 | sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing |
---|
663 | sc_signal<size_t> r_cas_cpt; // size of command |
---|
664 | sc_signal<copy_t> r_cas_copy; // Srcid of the first copy |
---|
665 | sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy |
---|
666 | sc_signal<bool> r_cas_copy_inst; // Type of the first copy |
---|
667 | sc_signal<size_t> r_cas_count; // number of copies |
---|
668 | sc_signal<size_t> r_cas_ptr; // pointer to the heap |
---|
669 | sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap |
---|
670 | sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) |
---|
671 | sc_signal<bool> r_cas_dirty; // dirty bit (in directory) |
---|
672 | sc_signal<size_t> r_cas_way; // way in directory |
---|
673 | sc_signal<size_t> r_cas_set; // set in directory |
---|
674 | sc_signal<data_t> r_cas_tag; // cache line tag (in directory) |
---|
675 | sc_signal<size_t> r_cas_trt_index; // Transaction Table index |
---|
676 | sc_signal<size_t> r_cas_upt_index; // Update Table index |
---|
677 | sc_signal<data_t> * r_cas_data; // cache line data |
---|
678 | |
---|
679 | // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) |
---|
680 | sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request |
---|
681 | sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index |
---|
682 | sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table |
---|
683 | sc_signal<bool> r_cas_to_ixr_cmd_write; // write request |
---|
684 | sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data |
---|
685 | |
---|
686 | |
---|
687 | // Buffer between CAS fsm and TGT_RSP fsm |
---|
688 | sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request |
---|
689 | sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word |
---|
690 | sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid |
---|
691 | sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid |
---|
692 | sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid |
---|
693 | |
---|
694 | // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
695 | sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request |
---|
696 | sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request |
---|
697 | sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index |
---|
698 | sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table |
---|
699 | sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word) |
---|
700 | sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS |
---|
701 | sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word) |
---|
702 | sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line |
---|
703 | GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
704 | GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids |
---|
705 | #if L1_MULTI_CACHE |
---|
706 | GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
707 | #endif |
---|
708 | |
---|
709 | //////////////////////////////////////////////////// |
---|
710 | // Registers controlled by the IXR_RSP fsm |
---|
711 | //////////////////////////////////////////////////// |
---|
712 | |
---|
713 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
714 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
715 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
716 | |
---|
717 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
718 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
---|
719 | |
---|
720 | //////////////////////////////////////////////////// |
---|
721 | // Registers controlled by the XRAM_RSP fsm |
---|
722 | //////////////////////////////////////////////////// |
---|
723 | |
---|
724 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
725 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
726 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
727 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
728 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
729 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
730 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
731 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
732 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
733 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
734 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
---|
735 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
736 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
737 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
738 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
---|
739 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
---|
740 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
741 | |
---|
742 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
743 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
744 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
745 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
746 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
747 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
748 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
749 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
---|
750 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
---|
751 | sc_signal<typename vci_param::fast_addr_t> |
---|
752 | r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table |
---|
753 | |
---|
754 | // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) |
---|
755 | sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request |
---|
756 | sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request |
---|
757 | sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index; |
---|
758 | sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry |
---|
759 | GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
760 | GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids |
---|
761 | #if L1_MULTI_CACHE |
---|
762 | GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
763 | #endif |
---|
764 | |
---|
765 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) |
---|
766 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
767 | sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index |
---|
768 | sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data |
---|
769 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table |
---|
770 | |
---|
771 | //////////////////////////////////////////////////// |
---|
772 | // Registers controlled by the IXR_CMD fsm |
---|
773 | //////////////////////////////////////////////////// |
---|
774 | |
---|
775 | sc_signal<int> r_ixr_cmd_fsm; |
---|
776 | sc_signal<size_t> r_ixr_cmd_cpt; |
---|
777 | |
---|
778 | //////////////////////////////////////////////////// |
---|
779 | // Registers controlled by TGT_RSP fsm |
---|
780 | //////////////////////////////////////////////////// |
---|
781 | |
---|
782 | sc_signal<int> r_tgt_rsp_fsm; |
---|
783 | sc_signal<size_t> r_tgt_rsp_cpt; |
---|
784 | |
---|
785 | //////////////////////////////////////////////////// |
---|
786 | // Registers controlled by CC_SEND fsm |
---|
787 | //////////////////////////////////////////////////// |
---|
788 | |
---|
789 | sc_signal<int> r_cc_send_fsm; |
---|
790 | sc_signal<size_t> r_cc_send_cpt; |
---|
791 | sc_signal<bool> r_cc_send_inst; |
---|
792 | |
---|
793 | //////////////////////////////////////////////////// |
---|
794 | // Registers controlled by CC_RECEIVE fsm |
---|
795 | //////////////////////////////////////////////////// |
---|
796 | |
---|
797 | sc_signal<int> r_cc_receive_fsm; |
---|
798 | |
---|
799 | //////////////////////////////////////////////////// |
---|
800 | // Registers controlled by ALLOC_DIR fsm |
---|
801 | //////////////////////////////////////////////////// |
---|
802 | |
---|
803 | sc_signal<int> r_alloc_dir_fsm; |
---|
804 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
---|
805 | |
---|
806 | //////////////////////////////////////////////////// |
---|
807 | // Registers controlled by ALLOC_TRT fsm |
---|
808 | //////////////////////////////////////////////////// |
---|
809 | |
---|
810 | sc_signal<int> r_alloc_trt_fsm; |
---|
811 | |
---|
812 | //////////////////////////////////////////////////// |
---|
813 | // Registers controlled by ALLOC_UPT fsm |
---|
814 | //////////////////////////////////////////////////// |
---|
815 | |
---|
816 | sc_signal<int> r_alloc_upt_fsm; |
---|
817 | |
---|
818 | //////////////////////////////////////////////////// |
---|
819 | // Registers controlled by ALLOC_HEAP fsm |
---|
820 | //////////////////////////////////////////////////// |
---|
821 | |
---|
822 | sc_signal<int> r_alloc_heap_fsm; |
---|
823 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
---|
824 | }; // end class VciMemCache |
---|
825 | |
---|
826 | }} |
---|
827 | |
---|
828 | #endif |
---|
829 | |
---|
830 | // Local Variables: |
---|
831 | // tab-width: 2 |
---|
832 | // c-basic-offset: 2 |
---|
833 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
834 | // indent-tabs-mode: nil |
---|
835 | // End: |
---|
836 | |
---|
837 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
---|
838 | |
---|