source: branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h @ 335

Last change on this file since 335 was 331, checked in by joannou, 12 years ago

Renaming all files form vci_cc_vcache_wrapper_dspin_coherence and vci_mem_cache_dspin_coherence
File size: 35.8 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
55#define UPDATE_TAB_LINES      4 // Number of lines in the update tab
56
57namespace soclib {  namespace caba {
58  using namespace sc_core;
59
60  template<typename vci_param>
61    class VciMemCache
62    : public soclib::caba::BaseModule
63    {
64      typedef sc_dt::sc_uint<40> addr_t;
65      typedef typename vci_param::fast_addr_t vci_addr_t;
66      typedef uint32_t data_t;
67      typedef uint32_t tag_t;
68      typedef uint32_t size_t;
69      typedef uint32_t be_t;
70      typedef uint32_t copy_t;
71
72      /* States of the TGT_CMD fsm */
73      enum tgt_cmd_fsm_state_e{
74        TGT_CMD_IDLE,
75        TGT_CMD_READ,
76        TGT_CMD_WRITE,
77        TGT_CMD_CAS
78      };
79
80      /* States of the TGT_RSP fsm */
81      enum tgt_rsp_fsm_state_e{
82        TGT_RSP_READ_IDLE,
83        TGT_RSP_WRITE_IDLE,
84        TGT_RSP_CAS_IDLE,
85        TGT_RSP_XRAM_IDLE,
86        TGT_RSP_INIT_IDLE,
87        TGT_RSP_CLEANUP_IDLE,
88        TGT_RSP_READ,
89        TGT_RSP_WRITE,
90        TGT_RSP_CAS,
91        TGT_RSP_XRAM,
92        TGT_RSP_INIT,
93        TGT_RSP_CLEANUP
94      };
95
96      /* States of the DSPIN_TGT fsm */
97      enum cc_receive_fsm_state_e{
98        CC_RECEIVE_IDLE,
99        CC_RECEIVE_CLEANUP,
100        CC_RECEIVE_MULTI_ACK
101      };
102
103      /* States of the CC_SEND fsm */
104      enum cc_send_fsm_state_e{
105        CC_SEND_XRAM_RSP_IDLE,
106        CC_SEND_WRITE_IDLE,
107        CC_SEND_CAS_IDLE,
108        CC_SEND_CLEANUP_IDLE,
109        CC_SEND_CLEANUP_ACK,
110        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
111        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
112        CC_SEND_XRAM_RSP_INVAL_HEADER,
113        CC_SEND_XRAM_RSP_INVAL_NLINE,
114        CC_SEND_WRITE_BRDCAST_HEADER,
115        CC_SEND_WRITE_BRDCAST_NLINE,
116        CC_SEND_WRITE_UPDT_HEADER,
117        CC_SEND_WRITE_UPDT_NLINE,
118        CC_SEND_WRITE_UPDT_DATA,
119        CC_SEND_CAS_BRDCAST_HEADER,
120        CC_SEND_CAS_BRDCAST_NLINE,
121        CC_SEND_CAS_UPDT_HEADER,
122        CC_SEND_CAS_UPDT_NLINE,
123        CC_SEND_CAS_UPDT_DATA,
124        CC_SEND_CAS_UPDT_DATA_HIGH
125      };
126
127      /* States of the MULTI_ACK fsm */
128      enum multi_ack_fsm_state_e{
129        MULTI_ACK_IDLE,
130        MULTI_ACK_UPT_LOCK,
131        MULTI_ACK_UPT_CLEAR,
132        MULTI_ACK_WRITE_RSP
133      };
134
135      /* States of the READ fsm */
136      enum read_fsm_state_e{
137        READ_IDLE,
138        READ_DIR_REQ,
139        READ_DIR_LOCK,
140        READ_DIR_HIT,
141        READ_HEAP_REQ,
142        READ_HEAP_LOCK,
143        READ_HEAP_WRITE,
144        READ_HEAP_ERASE,
145        READ_HEAP_LAST,
146        READ_RSP,
147        READ_TRT_LOCK,
148        READ_TRT_SET,
149        READ_TRT_REQ
150      };
151
152      /* States of the WRITE fsm */
153      enum write_fsm_state_e{
154        WRITE_IDLE,
155        WRITE_NEXT,
156        WRITE_DIR_REQ,
157        WRITE_DIR_LOCK,
158        WRITE_DIR_READ,
159        WRITE_DIR_HIT,
160        WRITE_UPT_LOCK,
161        WRITE_UPT_HEAP_LOCK,
162        WRITE_UPT_REQ,
163        WRITE_UPT_NEXT,
164        WRITE_UPT_DEC,
165        WRITE_RSP,
166        WRITE_MISS_TRT_LOCK,
167        WRITE_MISS_TRT_DATA,
168        WRITE_MISS_TRT_SET,
169        WRITE_MISS_XRAM_REQ,
170        WRITE_BC_TRT_LOCK,
171        WRITE_BC_UPT_LOCK,
172        WRITE_BC_DIR_INVAL,
173        WRITE_BC_CC_SEND,
174        WRITE_BC_XRAM_REQ,
175        WRITE_WAIT
176      };
177
178      /* States of the IXR_RSP fsm */
179      enum ixr_rsp_fsm_state_e{
180        IXR_RSP_IDLE,
181        IXR_RSP_ACK,
182        IXR_RSP_TRT_ERASE,
183        IXR_RSP_TRT_READ
184      };
185
186      /* States of the XRAM_RSP fsm */
187      enum xram_rsp_fsm_state_e{
188        XRAM_RSP_IDLE,
189        XRAM_RSP_TRT_COPY,
190        XRAM_RSP_TRT_DIRTY,
191        XRAM_RSP_DIR_LOCK,
192        XRAM_RSP_DIR_UPDT,
193        XRAM_RSP_DIR_RSP,
194        XRAM_RSP_INVAL_LOCK,
195        XRAM_RSP_INVAL_WAIT,
196        XRAM_RSP_INVAL,
197        XRAM_RSP_WRITE_DIRTY,
198        XRAM_RSP_HEAP_REQ,
199        XRAM_RSP_HEAP_ERASE,
200        XRAM_RSP_HEAP_LAST,
201        XRAM_RSP_ERROR_ERASE,
202        XRAM_RSP_ERROR_RSP
203      };
204
205      /* States of the IXR_CMD fsm */
206      enum ixr_cmd_fsm_state_e{
207        IXR_CMD_READ_IDLE,
208        IXR_CMD_WRITE_IDLE,
209        IXR_CMD_CAS_IDLE,
210        IXR_CMD_XRAM_IDLE,
211        IXR_CMD_READ_NLINE,
212        IXR_CMD_WRITE_NLINE,
213        IXR_CMD_CAS_NLINE,
214        IXR_CMD_XRAM_DATA
215      };
216
217      /* States of the CAS fsm */
218      enum cas_fsm_state_e{
219        CAS_IDLE,
220        CAS_DIR_REQ,
221        CAS_DIR_LOCK,
222        CAS_DIR_HIT_READ,
223        CAS_DIR_HIT_COMPARE,
224        CAS_DIR_HIT_WRITE,
225        CAS_UPT_LOCK,
226        CAS_UPT_HEAP_LOCK,
227        CAS_UPT_REQ,
228        CAS_UPT_NEXT,
229        CAS_BC_TRT_LOCK,
230        CAS_BC_UPT_LOCK,
231        CAS_BC_DIR_INVAL,
232        CAS_BC_CC_SEND,
233        CAS_BC_XRAM_REQ,
234        CAS_RSP_FAIL,
235        CAS_RSP_SUCCESS,
236        CAS_MISS_TRT_LOCK,
237        CAS_MISS_TRT_SET,
238        CAS_MISS_XRAM_REQ,
239        CAS_WAIT
240      };
241
242      /* States of the CLEANUP fsm */
243      enum cleanup_fsm_state_e{
244        CLEANUP_IDLE,
245        CLEANUP_GET_NLINE,
246        CLEANUP_DIR_REQ,
247        CLEANUP_DIR_LOCK,
248        CLEANUP_DIR_WRITE,
249        CLEANUP_HEAP_REQ,
250        CLEANUP_HEAP_LOCK,
251        CLEANUP_HEAP_SEARCH,
252        CLEANUP_HEAP_CLEAN,
253        CLEANUP_HEAP_FREE,
254        CLEANUP_UPT_LOCK,
255        CLEANUP_UPT_DECREMENT,
256        CLEANUP_UPT_CLEAR,
257        CLEANUP_WRITE_RSP,
258        CLEANUP_SEND_ACK
259      };
260
261      /* States of the ALLOC_DIR fsm */
262      enum alloc_dir_fsm_state_e{
263        ALLOC_DIR_RESET,
264        ALLOC_DIR_READ,
265        ALLOC_DIR_WRITE,
266        ALLOC_DIR_CAS,
267        ALLOC_DIR_CLEANUP,
268        ALLOC_DIR_XRAM_RSP
269      };
270
271      /* States of the ALLOC_TRT fsm */
272      enum alloc_trt_fsm_state_e{
273        ALLOC_TRT_READ,
274        ALLOC_TRT_WRITE,
275        ALLOC_TRT_CAS,
276        ALLOC_TRT_XRAM_RSP,
277        ALLOC_TRT_IXR_RSP
278      };
279
280      /* States of the ALLOC_UPT fsm */
281      enum alloc_upt_fsm_state_e{
282        ALLOC_UPT_WRITE,
283        ALLOC_UPT_XRAM_RSP,
284        ALLOC_UPT_MULTI_ACK,
285        ALLOC_UPT_CLEANUP,
286        ALLOC_UPT_CAS
287      };
288
289      /* States of the ALLOC_HEAP fsm */
290      enum alloc_heap_fsm_state_e{
291        ALLOC_HEAP_RESET,
292        ALLOC_HEAP_READ,
293        ALLOC_HEAP_WRITE,
294        ALLOC_HEAP_CAS,
295        ALLOC_HEAP_CLEANUP,
296        ALLOC_HEAP_XRAM_RSP
297      };
298
299      /* transaction type, pktid field */
300      enum transaction_type_e
301      {
302          // b3 unused
303          // b2 READ / NOT READ
304          // Si READ
305          //  b1 DATA / INS
306          //  b0 UNC / MISS
307          // Si NOT READ
308          //  b1 accÚs table llsc type SW / other
309          //  b2 WRITE/CAS/LL/SC
310          TYPE_READ_DATA_UNC          = 0x0,
311          TYPE_READ_DATA_MISS         = 0x1,
312          TYPE_READ_INS_UNC           = 0x2,
313          TYPE_READ_INS_MISS          = 0x3,
314          TYPE_WRITE                  = 0x4,
315          TYPE_CAS                    = 0x5,
316          TYPE_LL                     = 0x6,
317          TYPE_SC                     = 0x7
318      };
319
320      /* SC return values */
321      enum sc_status_type_e
322      {
323          SC_SUCCESS  =   0x00000000,
324          SC_FAIL     =   0x00000001
325      };
326
327      // debug variables (for each FSM)
328      size_t       m_debug_start_cycle;
329      bool         m_debug_ok;
330      bool         m_debug_global;
331      bool         m_debug_tgt_cmd_fsm;
332      bool         m_debug_tgt_rsp_fsm;
333      bool         m_debug_cc_send_fsm;
334      bool         m_debug_cc_receive_fsm;
335      bool         m_debug_multi_ack_fsm;
336      bool         m_debug_read_fsm;
337      bool         m_debug_write_fsm;
338      bool         m_debug_cas_fsm;
339      bool         m_debug_cleanup_fsm;
340      bool         m_debug_ixr_cmd_fsm;
341      bool         m_debug_ixr_rsp_fsm;
342      bool         m_debug_xram_rsp_fsm;
343      bool         m_debug_previous_hit;
344      size_t       m_debug_previous_count;
345
346      bool         m_monitor_ok;
347      vci_addr_t   m_monitor_base;
348      vci_addr_t   m_monitor_length;
349
350      // instrumentation counters
351      uint32_t     m_cpt_cycles;        // Counter of cycles
352      uint32_t     m_cpt_read;          // Number of READ transactions
353      uint32_t     m_cpt_read_miss;     // Number of MISS READ
354      uint32_t     m_cpt_write;         // Number of WRITE transactions
355      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
356      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
357      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
358      uint32_t     m_cpt_update;        // Number of UPDATE transactions
359      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
360      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
361      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
362      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
363      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
364      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
365      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
366      uint32_t     m_cpt_ll;            // Number of LL transactions
367      uint32_t     m_cpt_sc;            // Number of SC transactions
368      uint32_t     m_cpt_cas;           // Number of CAS transactions
369
370      size_t       m_prev_count;
371
372      protected:
373
374      SC_HAS_PROCESS(VciMemCache);
375
376      public:
377      sc_in<bool>                           p_clk;
378      sc_in<bool>                           p_resetn;
379      soclib::caba::VciTarget<vci_param>    p_vci_tgt;
380      soclib::caba::VciInitiator<vci_param> p_vci_ixr;
381
382      soclib::caba::DspinInput<33>          p_dspin_in;
383      soclib::caba::DspinOutput<40>         p_dspin_out;
384
385      VciMemCache(
386          sc_module_name name,                                // Instance Name
387          const soclib::common::MappingTable &mtp,            // Mapping table for primary requets
388          const soclib::common::MappingTable &mtc,            // Mapping table for coherence requets
389          const soclib::common::MappingTable &mtx,            // Mapping table for XRAM
390          const soclib::common::IntTab &vci_ixr_index,        // VCI port to XRAM (initiator)
391          const soclib::common::IntTab &vci_ini_index,        // VCI port to PROC (initiator)
392          const soclib::common::IntTab &vci_tgt_index,        // VCI port to PROC (target)
393          const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
394          size_t nways,                                       // Number of ways per set
395          size_t nsets,                                       // Number of sets
396          size_t nwords,                                      // Number of words per line
397          size_t heap_size=1024,                              // Size of the heap
398          size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
399          size_t update_tab_lines=UPDATE_TAB_LINES,           // Size of the UPT
400          size_t debug_start_cycle=0,
401          bool   debug_ok=false);
402
403      ~VciMemCache();
404
405      void print_stats();
406      void print_trace();
407      void copies_monitor(vci_addr_t addr);
408      void start_monitor(vci_addr_t addr, vci_addr_t length);
409      void stop_monitor();
410
411      private:
412
413      void transition();
414      void genMoore();
415      void check_monitor( const char *buf, vci_addr_t addr, data_t data);
416      void check_monitor_read( const char *buf, vci_addr_t addr);
417
418      // Component attributes
419      std::list<soclib::common::Segment> m_seglist;  // memory cached into the cache
420      std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
421
422      const size_t    m_initiators; // Number of initiators
423      const size_t    m_heap_size;  // Size of the heap
424      const size_t    m_ways;       // Number of ways in a set
425      const size_t    m_sets;       // Number of cache sets
426      const size_t    m_words;      // Number of words in a line
427      const size_t    m_srcid_ixr;  // Srcid for requests to XRAM
428      const size_t    m_srcid_ini;  // Srcid for requests to processors
429
430      uint32_t        m_transaction_tab_lines;
431      TransactionTab  m_transaction_tab;  // xram transaction table
432      uint32_t        m_update_tab_lines;
433      UpdateTab       m_update_tab;       // pending update & invalidate
434      CacheDirectory  m_cache_directory;  // data cache directory
435      CacheData       m_cache_data;       // data array[set][way][word]
436      HeapDirectory   m_heap;             // heap for copies
437      GenericLLSCGlobalTable
438      <
439        32  ,   // desired number of slots
440        4096,   // number of processors in the system
441        8000,   // registratioçn life span (in # of LL operations)
442        typename vci_param::fast_addr_t // address type
443      >
444      m_llsc_table;       // ll/sc global registration table
445
446      // adress masks
447      const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
448      const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
449      const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
450      const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
451
452      // broadcast address
453      uint32_t m_broadcast_address;
454
455      //////////////////////////////////////////////////
456      // Others registers
457      //////////////////////////////////////////////////
458      sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
459      sc_signal<size_t> xxx_count;
460
461      //////////////////////////////////////////////////
462      // Registers controlled by the TGT_CMD fsm
463      //////////////////////////////////////////////////
464
465      // Fifo between TGT_CMD fsm and READ fsm
466      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
467      GenericFifo<size_t>    m_cmd_read_length_fifo;
468      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
469      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
470      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
471
472      // Fifo between TGT_CMD fsm and WRITE fsm
473      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
474      GenericFifo<bool>      m_cmd_write_eop_fifo;
475      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
476      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
477      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
478      GenericFifo<data_t>    m_cmd_write_data_fifo;
479      GenericFifo<be_t>      m_cmd_write_be_fifo;
480
481      // Fifo between TGT_CMD fsm and CAS fsm
482      GenericFifo<uint64_t>  m_cmd_cas_addr_fifo;
483      GenericFifo<bool>      m_cmd_cas_eop_fifo;
484      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
485      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
486      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
487      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
488
489      // Fifo between INIT_RSP fsm and CLEANUP fsm
490      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
491     
492      // Fifo between INIT_RSP fsm and MULTI_ACK fsm
493      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
494
495      sc_signal<int>         r_tgt_cmd_fsm;
496
497      size_t                   m_nseg;
498      size_t                   m_ncseg;
499      soclib::common::Segment  **m_seg;
500      soclib::common::Segment  **m_cseg;
501      ///////////////////////////////////////////////////////
502      // Registers controlled by the READ fsm
503      ///////////////////////////////////////////////////////
504
505      sc_signal<int>      r_read_fsm;        // FSM state
506      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
507      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
508      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
509      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
510      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
511      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
512      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
513      sc_signal<size_t>   r_read_count;      // number of copies
514      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
515      sc_signal<data_t> * r_read_data;       // data (one cache line)
516      sc_signal<size_t>   r_read_way;        // associative way (in cache)
517      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
518      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
519      sc_signal<bool>     r_read_last_free;  // Last free entry
520      sc_signal<typename vci_param::fast_addr_t>
521                          r_read_ll_key;     // LL key returned by the llsc_global_table
522
523      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
524      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
525      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
526      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
527
528      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
529      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
530      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
531      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
532      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
533      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
534      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
535      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
536      sc_signal<typename vci_param::fast_addr_t>
537                          r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
538
539      ///////////////////////////////////////////////////////////////
540      // Registers controlled by the WRITE fsm
541      ///////////////////////////////////////////////////////////////
542
543      sc_signal<int>      r_write_fsm;        // FSM state
544      sc_signal<addr_t>   r_write_address;    // first word address
545      sc_signal<size_t>   r_write_word_index; // first word index in line
546      sc_signal<size_t>   r_write_word_count; // number of words in line
547      sc_signal<size_t>   r_write_srcid;      // transaction srcid
548      sc_signal<size_t>   r_write_trdid;      // transaction trdid
549      sc_signal<size_t>   r_write_pktid;      // transaction pktid
550      sc_signal<data_t> * r_write_data;       // data (one cache line)
551      sc_signal<be_t>   * r_write_be;         // one byte enable per word
552      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
553      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
554      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
555      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
556      sc_signal<size_t>   r_write_copy;       // first owner of the line
557      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
558      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
559      sc_signal<size_t>   r_write_count;      // number of copies
560      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
561      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
562      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
563      sc_signal<size_t>   r_write_way;        // way of the line
564      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
565      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
566      sc_signal<bool>     r_write_sc_fail;    // sc command failed
567      sc_signal<bool>     r_write_pending_sc; // sc command pending in WRITE fsm
568
569      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
570      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
571      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
572      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
573      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
574      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
575
576      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
577      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
578      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
579      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
580      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
581      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
582
583      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
584      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
585      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
586      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
587      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
588      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
589      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
590      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
591      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
592      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
593      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
594#if L1_MULTI_CACHE
595      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
596#endif
597
598      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
599      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
600      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
601
602      /////////////////////////////////////////////////////////
603      // Registers controlled by MULTI_ACK fsm
604      //////////////////////////////////////////////////////////
605
606      sc_signal<int>      r_multi_ack_fsm;       // FSM state
607      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
608      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
609      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
610      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
611      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
612
613      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
614      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
615      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
616      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
617      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
618
619      ///////////////////////////////////////////////////////
620      // Registers controlled by CLEANUP fsm
621      ///////////////////////////////////////////////////////
622
623      sc_signal<int>      r_cleanup_fsm;           // FSM state
624      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
625      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
626      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
627      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
628
629#if L1_MULTI_CACHE
630      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
631#endif
632
633      sc_signal<copy_t>   r_cleanup_copy;          // first copy
634      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
635      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
636      sc_signal<copy_t>   r_cleanup_count;         // number of copies
637      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
638      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
639      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
640      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
641      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
642      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
643      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
644      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
645      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
646      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
647      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
648
649      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write response
650      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
651      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
652      sc_signal<bool>     r_cleanup_write_need_rsp;// needs a write rsp
653
654      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
655
656      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
657      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
658      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
659      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
660      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
661
662      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
663      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
664      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
665      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
666      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
667      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
668
669      ///////////////////////////////////////////////////////
670      // Registers controlled by CAS fsm
671      ///////////////////////////////////////////////////////
672
673      sc_signal<int>      r_cas_fsm;        // FSM state
674      sc_signal<data_t>   r_cas_wdata;      // write data word
675      sc_signal<data_t> * r_cas_rdata;      // read data word
676      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
677      sc_signal<size_t>   r_cas_cpt;        // size of command
678      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
679      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
680      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
681      sc_signal<size_t>   r_cas_count;      // number of copies
682      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
683      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
684      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
685      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
686      sc_signal<size_t>   r_cas_way;        // way in directory
687      sc_signal<size_t>   r_cas_set;        // set in directory
688      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
689      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
690      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
691      sc_signal<data_t> * r_cas_data;       // cache line data
692
693      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
694      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
695      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
696      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
697      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
698      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
699
700
701      // Buffer between CAS fsm and TGT_RSP fsm
702      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
703      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
704      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
705      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
706      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
707
708      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
709      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
710      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
711      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
712      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
713      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
714      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
715      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
716      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
717      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
718      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
719#if L1_MULTI_CACHE
720      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
721#endif
722
723      ////////////////////////////////////////////////////
724      // Registers controlled by the IXR_RSP fsm
725      ////////////////////////////////////////////////////
726
727      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
728      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
729      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
730
731      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
732      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
733
734      ////////////////////////////////////////////////////
735      // Registers controlled by the XRAM_RSP fsm
736      ////////////////////////////////////////////////////
737
738      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
739      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
740      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
741      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
742      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
743      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
744      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
745      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
746      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
747      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
748      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
749      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
750      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
751      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
752      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
753      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
754      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
755
756      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
757      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
758      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
759      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
760      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
761      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
762      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
763      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
764      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
765      sc_signal<typename vci_param::fast_addr_t>
766                          r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
767
768      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
769      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
770      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
771      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
772      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
773      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
774      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
775#if L1_MULTI_CACHE
776      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
777#endif
778
779      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
780      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
781      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
782      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
783      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
784
785      ////////////////////////////////////////////////////
786      // Registers controlled by the IXR_CMD fsm
787      ////////////////////////////////////////////////////
788
789      sc_signal<int>      r_ixr_cmd_fsm;
790      sc_signal<size_t>   r_ixr_cmd_cpt;
791
792      ////////////////////////////////////////////////////
793      // Registers controlled by TGT_RSP fsm
794      ////////////////////////////////////////////////////
795
796      sc_signal<int>      r_tgt_rsp_fsm;
797      sc_signal<size_t>   r_tgt_rsp_cpt;
798
799      ////////////////////////////////////////////////////
800      // Registers controlled by CC_SEND fsm
801      ////////////////////////////////////////////////////
802
803      sc_signal<int>      r_cc_send_fsm;
804      sc_signal<size_t>   r_cc_send_cpt;
805      sc_signal<bool>     r_cc_send_inst;
806
807      ////////////////////////////////////////////////////
808      // Registers controlled by CC_RECEIVE fsm
809      ////////////////////////////////////////////////////
810
811      sc_signal<int>      r_cc_receive_fsm;
812
813      ////////////////////////////////////////////////////
814      // Registers controlled by ALLOC_DIR fsm
815      ////////////////////////////////////////////////////
816
817      sc_signal<int>      r_alloc_dir_fsm;
818      sc_signal<unsigned> r_alloc_dir_reset_cpt;
819
820      ////////////////////////////////////////////////////
821      // Registers controlled by ALLOC_TRT fsm
822      ////////////////////////////////////////////////////
823
824      sc_signal<int>      r_alloc_trt_fsm;
825
826      ////////////////////////////////////////////////////
827      // Registers controlled by ALLOC_UPT fsm
828      ////////////////////////////////////////////////////
829
830      sc_signal<int>      r_alloc_upt_fsm;
831
832      ////////////////////////////////////////////////////
833      // Registers controlled by ALLOC_HEAP fsm
834      ////////////////////////////////////////////////////
835
836      sc_signal<int>      r_alloc_heap_fsm;
837      sc_signal<unsigned> r_alloc_heap_reset_cpt;
838    }; // end class VciMemCache
839
840}}
841
842#endif
843
844// Local Variables:
845// tab-width: 2
846// c-basic-offset: 2
847// c-file-offsets:((innamespace . 0)(inline-open . 0))
848// indent-tabs-mode: nil
849// End:
850
851// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
852
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