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top.cpp @ 725

Last change on this file since 725 was 351, checked in by joannou, 12 years ago
Got rid of intermediate v5 version. _dspin_coherence versions changed to main version for v5. Changed components names and platforms to fit the new names
File size: 29.9 KB

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1	/////////////////////////////////////////////////////////////////////////
2	// File: top.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : august 2012
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture with virtual memory.
9	// The physical address space is 32 bits.
10	// The number of clusters cannot be larger than 256.
11	// The number of processors per cluster cannot be larger than 8.
12	//
13	// - It uses vci_local_crossbar as local interconnect
14	// - It uses virtual_dspin as global interconnect
15	// - It uses the vci_cc_vcache_wrapper
16	// - It uses the vci_mem_cache
17	// - It contains one vci_xicu and one vci_multi_dma per cluster.
18	//
19	// All clusters are identical, but the cluster containing address
20	// 0xBFC00000 (called io_cluster), that contains 5 extra components:
21	// - the boot rom (BROM)
22	// - the disk controller (BDEV)
23	// - the multi-channel network controller (MNIC)
24	// - the multi-channel tty controller (MTTY)
25	// - the frame buffer controller (FBUF)
26	//
27	// It is build with one single component implementing a cluster:
28	// The TsarClusterMmu component is defined in files
29	// tsar_cluster_mmu.* (with * = cpp, h, sd)
30	//
31	// The IRQs are connected to XICUs as follow:
32	// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
33	// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
34	// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
35	// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
36	//
37	// The main hardware parameters must be defined in the hard_config.h file :
38	// - CLUSTER_X : number of clusters in a row (power of 2)
39	// - CLUSTER_Y : number of clusters in a column (power of 2)
40	// - CLUSTER_SIZE : size of the segment allocated to a cluster
41	// - NB_PROCS_MAX : number of processors per cluster (power of 2)
42	// - NB_DMAS_MAX : number of DMA channels per cluster (< 9)
43	// - NB_TTYS : number of TTY channels in I/O cluster (< 16)
44	// - NB_NICS : number of NIC channels in I/O cluster (< 9)
45	//
46	// Some secondary hardware parameters must be defined in this top.cpp file:
47	// - XRAM_LATENCY : external ram latency
48	// - MEMC_WAYS : L2 cache number of ways
49	// - MEMC_SETS : L2 cache number of sets
50	// - L1_IWAYS
51	// - L1_ISETS
52	// - L1_DWAYS
53	// - L1_DSETS
54	// - FBUF_X_SIZE : width of frame buffer (pixels)
55	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
56	// - BDEV_SECTOR_SIZE : block size for block drvice
57	// - BDEV_IMAGE_NAME : file pathname for block device
58	// - NIC_RX_NAME : file pathname for NIC received packets
59	// - NIC_TX_NAME : file pathname for NIC transmited packets
60	// - NIC_TIMEOUT : max number of cycles before closing a container
61	//
62	// General policy for 32 bits physical address decoding:
63	// All segments base addresses are multiple of 64 Kbytes
64	// Therefore the 16 address MSB bits completely define the target:
65	// The (x_width + y_width) MSB bits (left aligned) define
66	// the cluster index, and the 8 LSB bits define the local index:
67	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
68	// \|x_width\|y_width\|---\| 8 \| 16 \|
69	/////////////////////////////////////////////////////////////////////////
70
71	#include <systemc>
72	#include <sys/time.h>
73	#include <iostream>
74	#include <sstream>
75	#include <cstdlib>
76	#include <cstdarg>
77	#include <stdint.h>
78
79	#include "gdbserver.h"
80	#include "mapping_table.h"
81	#include "tsar_cluster_mmu.h"
82	#include "alloc_elems.h"
83
84	///////////////////////////////////////////////////
85	// OS
86	///////////////////////////////////////////////////
87	#define USE_ALMOS 0
88
89	#define almos_bootloader_pathname "bootloader.bin"
90	#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D"
91	#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D"
92
93	///////////////////////////////////////////////////
94	// Parallelisation
95	///////////////////////////////////////////////////
96	#define USE_OPENMP 0
97
98	#if USE_OPENMP
99	#include <omp.h>
100	#endif
101
102	// cluster index (computed from x,y coordinates)
103	#define cluster(x,y) (y + CLUSTER_Y*x)
104
105	// flit widths for the DSPIN network
106	#define cmd_width 40
107	#define rsp_width 33
108
109	// VCI format
110	#define cell_width 4
111	#define address_width 32
112	#define plen_width 8
113	#define error_width 2
114	#define clen_width 1
115	#define rflag_width 1
116	#define srcid_width 14
117	#define pktid_width 4
118	#define trdid_width 4
119	#define wrplen_width 1
120
121	////////////////////////////////////////////////////////////
122	// Main Hardware Parameters values
123	//////////////////////i/////////////////////////////////////
124
125	// Create a symbolic link to your local giet_vm copy
126	// This directory must contain:
127	// - hard_config.h
128	// - soft.elf
129	// - display/images.raw
130	// - nic/rx_data.txt
131	// - nic/tx_data.txt
132
133	#include "giet_vm/hard_config.h"
134
135	////////////////////////////////////////////////////////////
136	// Secondary Hardware Parameters values
137	//////////////////////i/////////////////////////////////////
138
139	#define XRAM_LATENCY 0
140
141	#define MEMC_WAYS 16
142	#define MEMC_SETS 256
143
144	#define L1_IWAYS 4
145	#define L1_ISETS 64
146
147	#define L1_DWAYS 4
148	#define L1_DSETS 64
149
150	#define FBUF_X_SIZE 128
151	#define FBUF_Y_SIZE 128
152
153	#define BDEV_SECTOR_SIZE 512
154	#define BDEV_IMAGE_NAME "giet_vm/display/images.raw"
155
156	#define NIC_RX_NAME "giet_vm/nic/rx_data.txt"
157	#define NIC_TX_NAME "giet_vm/nic/tx_data.txt"
158	#define NIC_TIMEOUT 10000
159
160	////////////////////////////////////////////////////////////
161	// Software to be loaded in ROM & RAM
162	//////////////////////i/////////////////////////////////////
163
164	#define BOOT_SOFT_NAME "giet_vm/soft.elf"
165
166	////////////////////////////////////////////////////////////
167	// DEBUG Parameters default values
168	//////////////////////i/////////////////////////////////////
169
170	#define MAX_FROZEN_CYCLES 10000
171
172	#define TRACE_MEMC_ID 0
173	#define TRACE_PROC_ID 0
174
175	/////////////////////////////////////////////////////////
176	// Physical segments definition
177	/////////////////////////////////////////////////////////
178	// There is 3 segments replicated in all clusters
179	// and 5 specific segments in the "IO" cluster
180	// (containing address 0xBF000000)
181	/////////////////////////////////////////////////////////
182
183	// specific segments in "IO" cluster : absolute physical address
184
185	#define BROM_BASE 0xBFC00000
186	#define BROM_SIZE 0x00100000 // 1 Mbytes
187
188	#define FBUF_BASE 0xBFD00000
189	#define FBUF_SIZE 0x00200000 // 2 Mbytes
190
191	#define BDEV_BASE 0xBFF10000
192	#define BDEV_SIZE 0x00001000 // 4 Kbytes
193
194	#define MTTY_BASE 0xBFF20000
195	#define MTTY_SIZE 0x00001000 // 4 Kbytes
196
197	#define MNIC_BASE 0xBFF80000
198	#define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes
199
200	// replicated segments : address is incremented by a cluster offset
201	// offset = cluster(x,y) << (address_width-x_width-y_width);
202
203	#define MEMC_BASE 0x00000000
204	#define MEMC_SIZE 0x00C00000 // 12 Mbytes
205
206	#define XICU_BASE 0x00F00000
207	#define XICU_SIZE 0x00001000 // 4 Kbytes
208
209	#define CDMA_BASE 0x00F30000
210	#define CDMA_SIZE 0x00001000 * NB_DMAS_MAX // 4 Kbytes per channel
211
212	////////////////////////////////////////////////////////////////////
213	// TGTID definition in direct space
214	// For all components: global TGTID = global SRCID = cluster_index
215	////////////////////////////////////////////////////////////////////
216
217	#define MEMC_TGTID 0
218	#define XICU_TGTID 1
219	#define CDMA_TGTID 2
220	#define MTTY_TGTID 3
221	#define FBUF_TGTID 4
222	#define BROM_TGTID 5
223	#define BDEV_TGTID 6
224	#define MNIC_TGTID 7
225
226	/////////////////////////////////
227	int _main(int argc, char *argv[])
228	{
229	using namespace sc_core;
230	using namespace soclib::caba;
231	using namespace soclib::common;
232
233
234	char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code
235	size_t ncycles = 1000000000; // simulated cycles
236	char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
237	char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
238	char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
239	ssize_t threads_nr = 1; // simulator's threads number
240	bool debug_ok = false; // trace activated
241	size_t debug_period = 1; // trace period
242	size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id)
243	size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced
244	uint32_t debug_from = 0; // trace start cycle
245	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
246
247	////////////// command line arguments //////////////////////
248	if (argc > 1)
249	{
250	for (int n = 1; n < argc; n = n + 2)
251	{
252	if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
253	{
254	ncycles = atoi(argv[n+1]);
255	}
256	else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
257	{
258	strcpy(soft_name, argv[n+1]);
259	}
260	else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
261	{
262	strcpy(disk_name, argv[n+1]);
263	}
264	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
265	{
266	debug_ok = true;
267	debug_from = atoi(argv[n+1]);
268	}
269	else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
270	{
271	debug_memc_id = atoi(argv[n+1]);
272	assert( (debug_memc_id < (CLUSTER_X*CLUSTER_Y) ) &&
273	"debug_memc_id larger than XMAX * YMAX" );
274	}
275	else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
276	{
277	debug_proc_id = atoi(argv[n+1]);
278	assert( (debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) &&
279	"debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
280	}
281	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
282	{
283	threads_nr = atoi(argv[n+1]);
284	threads_nr = (threads_nr < 1) ? 1 : threads_nr;
285	}
286	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
287	{
288	frozen_cycles = atoi(argv[n+1]);
289	}
290	else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
291	{
292	debug_period = atoi(argv[n+1]);
293	}
294	else
295	{
296	std::cout << " Arguments on the command line are (key,value) couples." << std::endl;
297	std::cout << " The order is not important." << std::endl;
298	std::cout << " Accepted arguments are :" << std::endl << std::endl;
299	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
300	std::cout << " -DISK pathname_for_disk_image" << std::endl;
301	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
302	std::cout << " -DEBUG debug_start_cycle" << std::endl;
303	std::cout << " -THREADS simulator's threads number" << std::endl;
304	std::cout << " -FROZEN max_number_of_lines" << std::endl;
305	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
306	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
307	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
308	exit(0);
309	}
310	}
311	}
312
313	// checking hardware parameters
314	assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or
315	(CLUSTER_X == 8) or (CLUSTER_X == 16) ) and
316	"The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" );
317
318	assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or
319	(CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and
320	"The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" );
321
322	assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
323	(NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
324	"The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
325
326	assert( (NB_DMAS_MAX < 9) and
327	"The NB_DMAS_MAX parameter must be smaller than 9" );
328
329	assert( (NB_TTYS < 15) and
330	"The NB_TTYS parameter must be smaller than 15" );
331
332	assert( (NB_NICS < 9) and
333	"The NB_NICS parameter must be smaller than 9" );
334
335	std::cout << std::endl;
336	std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl;
337	std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl;
338	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
339	std::cout << " - NB_DMAS_MAX = " << NB_DMAS_MAX << std::endl;
340	std::cout << " - NB_TTYS = " << NB_TTYS << std::endl;
341	std::cout << " - NB_NICS = " << NB_NICS << std::endl;
342	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
343	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
344	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
345	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
346
347	std::cout << std::endl;
348
349	#if USE_OPENMP
350	omp_set_dynamic(false);
351	omp_set_num_threads(threads_nr);
352	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
353	#endif
354
355	// Define VCI parameters
356	typedef soclib::caba::VciParams<cell_width,
357	plen_width,
358	address_width,
359	error_width,
360	clen_width,
361	rflag_width,
362	srcid_width,
363	pktid_width,
364	trdid_width,
365	wrplen_width> vci_param;
366
367	// Define parameters depending on mesh size
368	size_t cluster_io_id;
369	size_t x_width;
370	size_t y_width;
371
372	if (CLUSTER_X == 1) x_width = 0;
373	else if (CLUSTER_X == 2) x_width = 1;
374	else if (CLUSTER_X <= 4) x_width = 2;
375	else if (CLUSTER_X <= 8) x_width = 3;
376	else x_width = 4;
377
378	if (CLUSTER_Y == 1) y_width = 0;
379	else if (CLUSTER_Y == 2) y_width = 1;
380	else if (CLUSTER_Y <= 4) y_width = 2;
381	else if (CLUSTER_Y <= 8) y_width = 3;
382	else y_width = 4;
383
384	cluster_io_id = 0xBF >> (8 - x_width - y_width);
385
386	/////////////////////
387	// Mapping Tables
388	/////////////////////
389
390	// direct network
391	MappingTable maptabd(address_width,
392	IntTab(x_width + y_width, 16 - x_width - y_width),
393	IntTab(x_width + y_width, srcid_width - x_width - y_width),
394	0x00FF0000);
395
396	for (size_t x = 0; x < CLUSTER_X; x++)
397	{
398	for (size_t y = 0; y < CLUSTER_Y; y++)
399	{
400	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
401
402	std::ostringstream sh;
403	sh << "d_seg_memc_" << x << "_" << y;
404	maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
405
406	std::ostringstream si;
407	si << "d_seg_xicu_" << x << "_" << y;
408	maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
409
410	std::ostringstream sd;
411	sd << "d_seg_mdma_" << x << "_" << y;
412	maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
413
414	if ( cluster(x,y) == cluster_io_id )
415	{
416	maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
417	maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
418	maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
419	maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false));
420	maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
421	}
422	}
423	}
424	std::cout << maptabd << std::endl;
425
426
427	// external network
428	MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
429
430	for (size_t x = 0; x < CLUSTER_X; x++)
431	{
432	for (size_t y = 0; y < CLUSTER_Y ; y++)
433	{
434	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
435	std::ostringstream sh;
436	sh << "x_seg_memc_" << x << "_" << y;
437	maptabx.add(Segment(sh.str(), MEMC_BASE+offset,
438	MEMC_SIZE, IntTab(cluster(x,y)), false));
439	}
440	}
441	std::cout << maptabx << std::endl;
442
443	////////////////////
444	// Signals
445	///////////////////
446
447	sc_clock signal_clk("clk");
448	sc_signal<bool> signal_resetn("resetn");
449
450	// Horizontal inter-clusters DSPIN signals
451	DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
452	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);
453	DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
454	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);
455	DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
456	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);
457	DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
458	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);
459
460	// Vertical inter-clusters DSPIN signals
461	DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
462	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);
463	DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
464	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);
465	DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
466	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);
467	DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
468	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);
469
470	// Mesh boundaries DSPIN signals
471	DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
472	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);
473	DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
474	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);
475	DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
476	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);
477	DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
478	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);
479
480
481	////////////////////////////
482	// Loader
483	////////////////////////////
484
485	#if USE_ALMOS
486	soclib::common::Loader loader(almos_bootloader_pathname,
487	almos_archinfo_pathname,
488	almos_kernel_pathname);
489	#else
490	soclib::common::Loader loader(soft_name);
491	#endif
492
493	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
494	proc_iss::set_loader(loader);
495
496	////////////////////////////
497	// Clusters construction
498	////////////////////////////
499
500	TsarClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[CLUSTER_X][CLUSTER_Y];
501
502	#if USE_OPENMP
503	#pragma omp parallel
504	{
505	#pragma omp for
506	#endif
507	for(size_t i = 0; i < (CLUSTER_X * CLUSTER_Y); i++)
508	{
509	size_t x = i / CLUSTER_Y;
510	size_t y = i % CLUSTER_Y;
511
512	#if USE_OPENMP
513	#pragma omp critical
514	{
515	#endif
516	std::ostringstream sc;
517	sc << "cluster_" << x << "_" << y;
518	clusters[x][y] = new TsarClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>
519	(
520	sc.str().c_str(),
521	NB_PROCS_MAX,
522	NB_TTYS,
523	NB_DMAS_MAX,
524	x,
525	y,
526	cluster(x,y),
527	maptabd,
528	maptabx,
529	x_width,
530	y_width,
531	4, //local_id_width
532	MEMC_TGTID,
533	XICU_TGTID,
534	CDMA_TGTID,
535	FBUF_TGTID,
536	MTTY_TGTID,
537	BROM_TGTID,
538	MNIC_TGTID,
539	BDEV_TGTID,
540	MEMC_WAYS,
541	MEMC_SETS,
542	L1_IWAYS,
543	L1_ISETS,
544	L1_DWAYS,
545	L1_DSETS,
546	XRAM_LATENCY,
547	(cluster(x,y) == cluster_io_id),
548	FBUF_X_SIZE,
549	FBUF_Y_SIZE,
550	disk_name,
551	BDEV_SECTOR_SIZE,
552	NB_NICS,
553	nic_rx_name,
554	nic_tx_name,
555	NIC_TIMEOUT,
556	loader,
557	frozen_cycles,
558	debug_from,
559	debug_ok and (cluster(x,y) == debug_memc_id),
560	debug_ok and (cluster(x,y) == debug_proc_id)
561	);
562
563	std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
564	#if USE_OPENMP
565	} // end critical
566	#endif
567	} // end for
568	#if USE_OPENMP
569	}
570	#endif
571
572	///////////////////////////////////////////////////////////////
573	// Net-list
574	///////////////////////////////////////////////////////////////
575
576	// Clock & RESET
577	for (size_t x = 0; x < (CLUSTER_X); x++){
578	for (size_t y = 0; y < CLUSTER_Y; y++){
579	clusters[x][y]->p_clk (signal_clk);
580	clusters[x][y]->p_resetn (signal_resetn);
581	}
582	}
583
584	// Inter Clusters horizontal connections
585	if (CLUSTER_X > 1){
586	for (size_t x = 0; x < (CLUSTER_X-1); x++){
587	for (size_t y = 0; y < CLUSTER_Y; y++){
588	for (size_t k = 0; k < 2; k++){
589	clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]);
590	clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]);
591	clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]);
592	clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]);
593	clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]);
594	clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]);
595	clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]);
596	clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]);
597	}
598	}
599	}
600	}
601	std::cout << std::endl << "Horizontal connections established" << std::endl;
602
603	// Inter Clusters vertical connections
604	if (CLUSTER_Y > 1) {
605	for (size_t y = 0; y < (CLUSTER_Y-1); y++){
606	for (size_t x = 0; x < CLUSTER_X; x++){
607	for (size_t k = 0; k < 2; k++){
608	clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]);
609	clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]);
610	clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]);
611	clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]);
612	clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]);
613	clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]);
614	clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]);
615	clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]);
616	}
617	}
618	}
619	}
620	std::cout << "Vertical connections established" << std::endl;
621
622	// East & West boundary cluster connections
623	for (size_t y = 0; y < CLUSTER_Y; y++)
624	{
625	for (size_t k = 0; k < 2; k++)
626	{
627	clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);
628	clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);
629	clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);
630	clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);
631
632	clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]);
633	clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]);
634	clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]);
635	clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]);
636	}
637	}
638
639	// North & South boundary clusters connections
640	for (size_t x = 0; x < CLUSTER_X; x++)
641	{
642	for (size_t k = 0; k < 2; k++)
643	{
644	clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
645	clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
646	clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
647	clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
648
649	clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]);
650	clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]);
651	clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]);
652	clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]);
653	}
654	}
655
656
657	////////////////////////////////////////////////////////
658	// Simulation
659	///////////////////////////////////////////////////////
660
661	sc_start(sc_core::sc_time(0, SC_NS));
662	signal_resetn = false;
663
664	// network boundaries signals
665	for (size_t x = 0; x < CLUSTER_X ; x++){
666	for (size_t y = 0; y < CLUSTER_Y ; y++){
667	for (size_t k = 0; k < 2; k++){
668	for (size_t a = 0; a < 4; a++){
669	signal_dspin_false_cmd_in[x][y][k][a].write = false;
670	signal_dspin_false_cmd_in[x][y][k][a].read = true;
671	signal_dspin_false_cmd_out[x][y][k][a].write = false;
672	signal_dspin_false_cmd_out[x][y][k][a].read = true;
673
674	signal_dspin_false_rsp_in[x][y][k][a].write = false;
675	signal_dspin_false_rsp_in[x][y][k][a].read = true;
676	signal_dspin_false_rsp_out[x][y][k][a].write = false;
677	signal_dspin_false_rsp_out[x][y][k][a].read = true;
678	}
679	}
680	}
681	}
682
683	sc_start(sc_core::sc_time(1, SC_NS));
684	signal_resetn = true;
685
686	//clusters[0][0]->memc->start_monitor(0x19000,0x40);
687	for (size_t n = 1; n < ncycles; n++)
688	{
689
690	if (debug_ok and (n > debug_from) and (n % debug_period == 0))
691	{
692	std::cout << "****************** cycle " << std::dec << n ;
693	std::cout << " ************************************************" << std::endl;
694
695	// clusters[0][0]->proc[0]->print_trace();
696	// clusters[0][0]->proc[1]->print_trace();
697	// clusters[1][0]->proc[2]->print_trace();
698	// clusters[0][0]->proc[3]->print_trace();
699	// clusters[0][0]->memc->print_trace();
700	// trace proc[debug_proc_id]
701	if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) )
702	{
703	size_t proc_x = debug_proc_id / CLUSTER_Y;
704	size_t proc_y = debug_proc_id % CLUSTER_Y;
705
706	clusters[proc_x][proc_y]->proc[0]->print_trace();
707
708	clusters[proc_x][proc_y]->signal_vci_ini_d_proc[0].print_trace("proc_ini_d");
709	clusters[proc_x][proc_y]->signal_dspin_c_from_proc[0].print_trace("from_proc_c");
710	clusters[proc_x][proc_y]->signal_dspin_c_to_proc[0].print_trace("to_proc_c");
711	}
712
713	// trace memc[debug_memc_id]
714	if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) )
715	{
716	size_t memc_x = debug_memc_id / CLUSTER_Y;
717	size_t memc_y = debug_memc_id % CLUSTER_Y;
718
719	clusters[memc_x][memc_y]->memc->print_trace();
720
721	clusters[memc_x][memc_y]->signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
722	clusters[memc_x][memc_y]->signal_dspin_c_from_memc.print_trace("from_memc_c");
723	clusters[memc_x][memc_y]->signal_dspin_c_to_memc.print_trace("to_memc_c");
724	}
725
726	// clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0");
727	// clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1");
728	// clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0");
729	// clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1");
730
731	// if ( clusters[1][1]->signal_irq_mdma[0].read() )
732	// std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl;
733	// if ( clusters[1][1]->signal_proc_it[0].read() )
734	// std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl;
735
736	// trace ioc component
737	// size_t io_x = cluster_io_id / CLUSTER_Y;
738	// size_t io_y = cluster_io_id % CLUSTER_Y;
739	// clusters[io_x][io_y]->bdev->print_trace();
740	// clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d ");
741	// clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d ");
742
743	// clusters[1][1]->mdma->print_trace();
744	// clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d ");
745	// clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d ");
746	}
747
748	sc_start(sc_core::sc_time(1, SC_NS));
749	}
750	return EXIT_SUCCESS;
751	}
752
753	int sc_main (int argc, char *argv[])
754	{
755	try {
756	return _main(argc, argv);
757	} catch (std::exception &e) {
758	std::cout << e.what() << std::endl;
759	} catch (...) {
760	std::cout << "Unknown exception occured" << std::endl;
761	throw;
762	}
763	return 1;
764	}
765
766	// Local Variables:
767	// tab-width: 3
768	// c-basic-offset: 3
769	// c-file-offsets:((innamespace . 0)(inline-open . 0))
770	// indent-tabs-mode: nil
771	// End:
772
773	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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source: branches/v5/platforms/tsar_generic_mmu/top.cpp @ 725

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