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tsar_cluster_mmu.cpp @ 343

Last change on this file since 343 was 343, checked in by cfuguet, 11 years ago
Using the Xicu SOFT IRQs (IPIs). Adding them on the Xicu constructor
File size: 22.6 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_cluster_mmu.c
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses the virtual_dspin_router as distributed global interconnect
10	// - It uses the vci_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster
18	// containing address 0xBFC00000.
19	// - The Multi-TTY component controls up to 15 terminals.
20	// - Each Multi-DMA component controls up to 8 DMA channels.
21	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
22	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
23	// - The BDEV IRQ is connected to IRQ_IN[31]
24	//////////////////////////////////////////////////////////////////////////////////
25
26	#include "../include/tsar_cluster_mmu.h"
27
28	namespace soclib {
29	namespace caba {
30
31	//////////////////////////////////////////////////////////////////////////
32	// Constructor
33	//////////////////////////////////////////////////////////////////////////
34	template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
35	TsarClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarClusterMmu(
36	sc_module_name insname,
37	size_t nb_procs,
38	size_t nb_ttys,
39	size_t nb_dmas,
40	size_t x_id,
41	size_t y_id,
42	size_t cluster_id,
43	const soclib::common::MappingTable &mtd,
44	const soclib::common::MappingTable &mtc,
45	const soclib::common::MappingTable &mtx,
46	size_t x_width,
47	size_t y_width,
48	size_t tgtid_memc,
49	size_t tgtid_xicu,
50	size_t tgtid_mdma,
51	size_t tgtid_fbuf,
52	size_t tgtid_mtty,
53	size_t tgtid_brom,
54	size_t tgtid_mnic,
55	size_t tgtid_bdev,
56	size_t memc_ways,
57	size_t memc_sets,
58	size_t l1_i_ways,
59	size_t l1_i_sets,
60	size_t l1_d_ways,
61	size_t l1_d_sets,
62	size_t xram_latency,
63	bool io,
64	size_t xfb,
65	size_t yfb,
66	char* disk_name,
67	size_t block_size,
68	size_t nic_channels,
69	char* nic_rx_name,
70	char* nic_tx_name,
71	uint32_t nic_timeout,
72	const Loader &loader,
73	uint32_t frozen_cycles,
74	uint32_t debug_start_cycle,
75	bool memc_debug_ok,
76	bool proc_debug_ok)
77	: soclib::caba::BaseModule(insname),
78	p_clk("clk"),
79	p_resetn("resetn")
80
81	{
82	// Vectors of ports definition
83
84	p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
85	p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
86	p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
87	p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
88
89	// Components definition
90
91	// on direct network : local srcid[proc] in [0..nb_procs-1]
92	// on direct network : local srcid[mdma] = nb_procs
93	// on direct network : local srcid[bdev] = nb_procs + 1
94
95	// on coherence network : local srcid[proc] in [0...nb_procs-1]
96	// on coherence network : local srcid[memc] = nb_procs
97
98	std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
99
100	for (size_t p = 0; p < nb_procs; p++)
101	{
102	std::ostringstream sproc;
103	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
104	proc[p] = new VciCcVCacheWrapper<vci_param, iss_t>(
105	sproc.str().c_str(),
106	cluster_id*nb_procs + p,
107	mtd, // Mapping Table Direct
108	mtc, // Mapping Table Coherence
109	IntTab(cluster_id,p), // SRCID_D
110	IntTab(cluster_id,p), // SRCID_C
111	IntTab(cluster_id,p), // TGTID_C
112	8, // ITLB ways
113	8, // ITLB sets
114	8, // DTLB ways
115	8, // DTLB sets
116	l1_i_ways,l1_i_sets,16, // ICACHE size
117	l1_d_ways,l1_d_sets,16, // DCACHE size
118	4, // WBUF nlines
119	4, // WBUF nwords
120	x_width,
121	y_width,
122	nb_procs, // MEMC local index
123	frozen_cycles, // max frozen cycles
124	debug_start_cycle,
125	proc_debug_ok);
126	}
127
128	std::cout << " - building memc_" << x_id << "_" << y_id << std::endl;
129
130	std::ostringstream smemc;
131	smemc << "memc_" << x_id << "_" << y_id;
132	memc = new VciMemCache<vci_param>(
133	smemc.str().c_str(),
134	mtd, mtc, mtx,
135	IntTab(cluster_id), // SRCID_X
136	IntTab(cluster_id, nb_procs), // SRCID_C
137	IntTab(cluster_id, tgtid_memc), // TGTID_D
138	IntTab(cluster_id, nb_procs), // TGTID_C
139	memc_ways, memc_sets, 16, // CACHE SIZE
140	//4096, // HEAP SIZE
141	256, // HEAP SIZE
142	8, // TRANSACTION TABLE DEPTH
143	8, // UPDATE TABLE DEPTH
144	debug_start_cycle,
145	memc_debug_ok);
146
147	std::cout << " - building xram_" << x_id << "_" << y_id << std::endl;
148
149	std::ostringstream sxram;
150	sxram << "xram_" << x_id << "_" << y_id;
151	xram = new VciSimpleRam<vci_param>(
152	sxram.str().c_str(),
153	IntTab(cluster_id),
154	mtx,
155	loader,
156	xram_latency);
157
158	std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl;
159
160	std::ostringstream sicu;
161	sicu << "xicu_" << x_id << "_" << y_id;
162	xicu = new VciXicu<vci_param>(
163	sicu.str().c_str(),
164	mtd, // mapping table
165	IntTab(cluster_id, tgtid_xicu), // TGTID_D
166	nb_procs, // number of timer IRQs
167	32, // number of hard IRQs
168	32, // number of soft IRQs
169	nb_procs); // number of output IRQs
170
171	std::cout << " - building dma_" << x_id << "_" << y_id << std::endl;
172
173	std::ostringstream sdma;
174	sdma << "dma_" << x_id << "_" << y_id;
175	mdma = new VciMultiDma<vci_param>(
176	sdma.str().c_str(),
177	mtd,
178	IntTab(cluster_id, nb_procs), // SRCID
179	IntTab(cluster_id, tgtid_mdma), // TGTID
180	64, // burst size
181	nb_dmas); // number of IRQs
182
183	std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl;
184
185	size_t nb_direct_initiators = nb_procs + 1;
186	size_t nb_direct_targets = 3;
187	if ( io )
188	{
189	nb_direct_initiators = nb_procs + 2;
190	nb_direct_targets = 8;
191	}
192	std::ostringstream sd;
193	sd << "xbard_" << x_id << "_" << y_id;
194	xbard = new VciLocalCrossbar<vci_param>(
195	sd.str().c_str(),
196	mtd,
197	IntTab(cluster_id), // cluster initiator index
198	IntTab(cluster_id), // cluster target index
199	nb_direct_initiators, // number of initiators
200	nb_direct_targets); // number of targets
201
202	std::cout << " - building ringc_" << x_id << "_" << y_id << std::endl;
203
204	std::ostringstream sc;
205	sc << "ringc_" << x_id << "_" << y_id;
206	//ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),mtc, IntTab(cluster_id), 2, 2, 2, nb_procs + 1, x_width, y_width);
207	ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),mtc, IntTab(cluster_id), 2, 2, 1, nb_procs, x_width, y_width);
208
209	std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
210
211	std::ostringstream wid;
212	wid << "iniwrapperd_" << x_id << "_" << y_id;
213	iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
214	wid.str().c_str(),
215	4, // cmd fifo depth
216	4); // rsp fifo depth
217
218	std::ostringstream wtd;
219	wtd << "tgtwrapperd_" << x_id << "_" << y_id;
220	tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
221	wtd.str().c_str(),
222	4, // cmd fifo depth
223	4); // rsp fifo depth
224
225	std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl;
226
227	std::ostringstream scmd;
228	scmd << "cmdrouter_" << x_id << "_" << y_id;
229	cmdrouter = new VirtualDspinRouter<cmd_width>(
230	scmd.str().c_str(),
231	x_id,y_id, // coordinate in the mesh
232	x_width, y_width, // x & y fields width
233	4,4); // input & output fifo depths
234
235	std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl;
236
237	std::ostringstream srsp;
238	srsp << "rsprouter_" << x_id << "_" << y_id;
239	rsprouter = new VirtualDspinRouter<rsp_width>(
240	srsp.str().c_str(),
241	x_id,y_id, // coordinates in mesh
242	x_width, y_width, // x & y fields width
243	4,4); // input & output fifo depths
244
245	// IO cluster components
246	if ( io )
247	{
248	std::cout << " - building brom" << std::endl;
249
250	brom = new VciSimpleRam<vci_param>(
251	"brom",
252	IntTab(cluster_id, tgtid_brom),
253	mtd,
254	loader);
255
256	std::cout << " - building fbuf" << std::endl;
257
258	fbuf = new VciFrameBuffer<vci_param>(
259	"fbuf",
260	IntTab(cluster_id, tgtid_fbuf),
261	mtd,
262	xfb, yfb);
263
264	std::cout << " - building fbuf" << std::endl;
265
266	bdev = new VciBlockDeviceTsarV4<vci_param>(
267	"bdev",
268	mtd,
269	IntTab(cluster_id, nb_procs+1),
270	IntTab(cluster_id, tgtid_bdev),
271	disk_name,
272	block_size,
273	64); // burst size
274
275	std::cout << " - building mnic" << std::endl;
276
277	mnic = new VciMultiNic<vci_param>(
278	"mnic",
279	IntTab(cluster_id, tgtid_mnic),
280	mtd,
281	nic_channels,
282	nic_rx_name,
283	nic_tx_name,
284	0, // default mac address MAC4
285	0 ); // default mac address MAC2
286
287	std::cout << " - building mtty" << std::endl;
288
289	std::vector<std::string> vect_names;
290	for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
291	{
292	std::ostringstream term_name;
293	term_name << "term" << tid;
294	vect_names.push_back(term_name.str().c_str());
295	}
296	mtty = new VciMultiTty<vci_param>(
297	"mtty",
298	IntTab(cluster_id, tgtid_mtty),
299	mtd,
300	vect_names);
301	}
302
303	std::cout << std::endl;
304
305	////////////////////////////////////
306	// Connections are defined here
307	////////////////////////////////////
308
309	// CMDROUTER and RSPROUTER
310	cmdrouter->p_clk (this->p_clk);
311	cmdrouter->p_resetn (this->p_resetn);
312	rsprouter->p_clk (this->p_clk);
313	rsprouter->p_resetn (this->p_resetn);
314	for (int x = 0; x < 2; x++)
315	{
316	for(int y = 0; y < 4; y++)
317	{
318	cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]);
319	cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]);
320	rsprouter->p_out[x][y] (this->p_rsp_out[x][y]);
321	rsprouter->p_in[x][y] (this->p_rsp_in[x][y]);
322	}
323	}
324
325	cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d);
326	cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c);
327	cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d);
328	cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c);
329
330	rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d);
331	rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c);
332	rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d);
333	rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c);
334
335	std::cout << " - CMD & RSP routers connected" << std::endl;
336
337	// VCI/DSPIN WRAPPERS
338	iniwrapperd->p_clk (this->p_clk);
339	iniwrapperd->p_resetn (this->p_resetn);
340	iniwrapperd->p_vci (signal_vci_l2g_d);
341	iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d);
342	iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d);
343
344	tgtwrapperd->p_clk (this->p_clk);
345	tgtwrapperd->p_resetn (this->p_resetn);
346	tgtwrapperd->p_vci (signal_vci_g2l_d);
347	tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d);
348	tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d);
349
350	std::cout << " - VCI/DSPIN wrappers connected" << std::endl;
351
352	// CROSSBAR direct
353	xbard->p_clk (this->p_clk);
354	xbard->p_resetn (this->p_resetn);
355	xbard->p_initiator_to_up (signal_vci_l2g_d);
356	xbard->p_target_to_up (signal_vci_g2l_d);
357
358	xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc);
359	xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu);
360	xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma);
361
362	xbard->p_to_initiator[nb_procs] (signal_vci_ini_d_mdma);
363
364	for (size_t p = 0; p < nb_procs; p++)
365	{
366	xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]);
367	}
368
369	if ( io )
370	{
371	xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty);
372	xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom);
373	xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev);
374	xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf);
375	xbard->p_to_target[tgtid_mnic] (signal_vci_tgt_d_mnic);
376
377	xbard->p_to_initiator[nb_procs+1] (signal_vci_ini_d_bdev);
378	}
379
380	std::cout << " - Direct crossbar connected" << std::endl;
381
382	// RING coherence
383	ringc->p_clk (this->p_clk);
384	ringc->p_resetn (this->p_resetn);
385	//ringc procs
386	for (size_t p = 0; p < nb_procs; p++)
387	{
388	ringc->p_rsp_in[p](signal_dspin_c_from_proc[p]);
389	ringc->p_cmd_out[p](signal_dspin_c_to_proc[p]);
390	}
391	//ringc memc
392	ringc->p_cmd_in[0](signal_dspin_c_from_memc);
393	ringc->p_rsp_out[0](signal_dspin_c_to_memc);
394	//ringc router
395	ringc->p_cmd_in[1](signal_dspin_cmd_g2l_c);
396	ringc->p_rsp_in[nb_procs](signal_dspin_rsp_g2l_c);
397	ringc->p_cmd_out[nb_procs](signal_dspin_cmd_l2g_c);
398	ringc->p_rsp_out[1](signal_dspin_rsp_l2g_c);
399
400	std::cout << " - Coherence ring connected" << std::endl;
401
402	// Processors
403	for (size_t p = 0; p < nb_procs; p++)
404	{
405	proc[p]->p_clk (this->p_clk);
406	proc[p]->p_resetn (this->p_resetn);
407	proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]);
408	proc[p]->p_dspin_in (signal_dspin_c_to_proc[p]);
409	proc[p]->p_dspin_out (signal_dspin_c_from_proc[p]);
410	proc[p]->p_irq[0] (signal_proc_it[p]);
411	for ( size_t j = 1 ; j < 6 ; j++)
412	{
413	proc[p]->p_irq[j] (signal_false);
414	}
415	}
416
417	std::cout << " - Processors connected" << std::endl;
418
419	// XICU
420	xicu->p_clk (this->p_clk);
421	xicu->p_resetn (this->p_resetn);
422	xicu->p_vci (signal_vci_tgt_d_xicu);
423	for ( size_t p=0 ; p<nb_procs ; p++)
424	{
425	xicu->p_irq[p] (signal_proc_it[p]);
426	}
427	for ( size_t i=0 ; i<32 ; i++)
428	{
429	if ( io ) // I/O cluster
430	{
431	if (i < 8) xicu->p_hwi[i] (signal_false);
432	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
433	else if (i < 16) xicu->p_hwi[i] (signal_false);
434	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]);
435	else if (i < 31) xicu->p_hwi[i] (signal_false);
436	else xicu->p_hwi[i] (signal_irq_bdev);
437	}
438	else // other clusters
439	{
440	if (i < 8) xicu->p_hwi[i] (signal_false);
441	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
442	else xicu->p_hwi[i] (signal_false);
443	}
444	}
445
446	std::cout << " - XICU connected" << std::endl;
447
448	// MEMC
449	memc->p_clk (this->p_clk);
450	memc->p_resetn (this->p_resetn);
451	memc->p_vci_ixr (signal_vci_xram);
452	memc->p_vci_tgt (signal_vci_tgt_d_memc);
453	memc->p_dspin_in (signal_dspin_c_to_memc);
454	memc->p_dspin_out (signal_dspin_c_from_memc);
455
456	std::cout << " - MEMC connected" << std::endl;
457
458	// XRAM
459	xram->p_clk (this->p_clk);
460	xram->p_resetn (this->p_resetn);
461	xram->p_vci (signal_vci_xram);
462
463	std::cout << " - XRAM connected" << std::endl;
464
465	// CDMA
466	mdma->p_clk (this->p_clk);
467	mdma->p_resetn (this->p_resetn);
468	mdma->p_vci_target (signal_vci_tgt_d_mdma);
469	mdma->p_vci_initiator (signal_vci_ini_d_mdma);
470	for (size_t i=0 ; i<nb_dmas ; i++)
471	{
472	mdma->p_irq[i] (signal_irq_mdma[i]);
473	}
474
475	std::cout << " - MDMA connected" << std::endl;
476
477	// Components in I/O cluster
478
479	if ( io )
480	{
481	// BDEV
482	bdev->p_clk (this->p_clk);
483	bdev->p_resetn (this->p_resetn);
484	bdev->p_irq (signal_irq_bdev);
485	bdev->p_vci_target (signal_vci_tgt_d_bdev);
486	bdev->p_vci_initiator (signal_vci_ini_d_bdev);
487
488	std::cout << " - BDEV connected" << std::endl;
489
490	// FBUF
491	fbuf->p_clk (this->p_clk);
492	fbuf->p_resetn (this->p_resetn);
493	fbuf->p_vci (signal_vci_tgt_d_fbuf);
494
495	std::cout << " - FBUF connected" << std::endl;
496
497	// MNIC
498	mnic->p_clk (this->p_clk);
499	mnic->p_resetn (this->p_resetn);
500	mnic->p_vci (signal_vci_tgt_d_mnic);
501	for ( size_t i=0 ; i<nic_channels ; i++ )
502	{
503	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
504	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
505	}
506
507	std::cout << " - MNIC connected" << std::endl;
508
509	// BROM
510	brom->p_clk (this->p_clk);
511	brom->p_resetn (this->p_resetn);
512	brom->p_vci (signal_vci_tgt_d_brom);
513
514	std::cout << " - BROM connected" << std::endl;
515
516	// MTTY
517	mtty->p_clk (this->p_clk);
518	mtty->p_resetn (this->p_resetn);
519	mtty->p_vci (signal_vci_tgt_d_mtty);
520	for ( size_t i=0 ; i<nb_ttys ; i++ )
521	{
522	mtty->p_irq[i] (signal_irq_mtty[i]);
523	}
524
525	std::cout << " - MTTY connected" << std::endl;
526	}
527	} // end constructor
528
529	///////////////////////////////////////////////////////////////////////////
530	// destructor
531	///////////////////////////////////////////////////////////////////////////
532	template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
533	TsarClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarClusterMmu() {}
534
535	}
536	}
537
538
539	// Local Variables:
540	// tab-width: 3
541	// c-basic-offset: 3
542	// c-file-offsets:((innamespace . 0)(inline-open . 0))
543	// indent-tabs-mode: nil
544	// End:
545
546	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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source: branches/v5/platforms/tsar_generic_mmu_dspin_coherence/tsar_cluster_mmu/caba/source/src/tsar_cluster_mmu.cpp @ 343

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