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source: branches/v5/platforms/tsar_generic_xbar/top.cpp @ 452

Last change on this file since 452 was 448, checked in by cfuguet, 11 years ago

Modification in branches/v5/platforms/tsar_generic_xbar:

Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

File size: 36.6 KB

Line
1	/////////////////////////////////////////////////////////////////////////
2	// File: top.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : may 2013
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture.
9	// The physical address space is 40 bits.
10	//
11	// The number of clusters cannot be larger than 256.
12	// The number of processors per cluster cannot be larger than 8.
13	//
14	// - It uses four dspin_local_crossbar per cluster as local interconnect
15	// - It uses two virtual_dspin routers per cluster as global interconnect
16	// - It uses the vci_cc_vcache_wrapper
17	// - It uses the vci_mem_cache
18	// - It contains one vci_xicu per cluster.
19	// - It contains one vci_multi_dma per cluster.
20	// - It contains one vci_simple_ram per cluster to model the L3 cache.
21	//
22	// The communication between the MemCache and the Xram is 64 bits.
23	//
24	// All clusters are identical, but the cluster 0 (called io_cluster),
25	// contains 5 extra components:
26	// - the boot rom (BROM)
27	// - the disk controller (BDEV)
28	// - the multi-channel network controller (MNIC)
29	// - the multi-channel tty controller (MTTY)
30	// - the frame buffer controller (FBUF)
31	//
32	// It is build with one single component implementing a cluster,
33	// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd)
34	//
35	// The IRQs are connected to XICUs as follow:
36	// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
37	// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
38	// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
39	// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
40	//
41	// Some hardware parameters are used when compiling the OS, and are used
42	// by this top.cpp file. They must be defined in the hard_config.h file :
43	// - CLUSTER_X : number of clusters in a row (power of 2)
44	// - CLUSTER_Y : number of clusters in a column (power of 2)
45	// - CLUSTER_SIZE : size of the segment allocated to a cluster
46	// - NB_PROCS_MAX : number of processors per cluster (power of 2)
47	// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9)
48	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16)
49	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9)
50	//
51	// Some other hardware parameters are not used when compiling the OS,
52	// and can be directly defined in this top.cpp file:
53	// - XRAM_LATENCY : external ram latency
54	// - MEMC_WAYS : L2 cache number of ways
55	// - MEMC_SETS : L2 cache number of sets
56	// - L1_IWAYS
57	// - L1_ISETS
58	// - L1_DWAYS
59	// - L1_DSETS
60	// - FBUF_X_SIZE : width of frame buffer (pixels)
61	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
62	// - BDEV_SECTOR_SIZE : block size for block drvice
63	// - BDEV_IMAGE_NAME : file pathname for block device
64	// - NIC_RX_NAME : file pathname for NIC received packets
65	// - NIC_TX_NAME : file pathname for NIC transmited packets
66	// - NIC_TIMEOUT : max number of cycles before closing a container
67	/////////////////////////////////////////////////////////////////////////
68	// General policy for 40 bits physical address decoding:
69	// All physical segments base addresses are multiple of 1 Mbytes
70	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
71	// The (x_width + y_width) MSB bits (left aligned) define
72	// the cluster index, and the LADR bits define the local index:
73	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
74	// \|x_width\|y_width\|---\| 8 \| 24 \|
75	/////////////////////////////////////////////////////////////////////////
76	// General policy for 14 bits SRCID decoding:
77	// Each component is identified by (x_id, y_id, l_id) tuple.
78	// \| X_ID \| Y_ID \|---\| L_ID \|
79	// \|x_width\|y_width\|---\| 6 \|
80	/////////////////////////////////////////////////////////////////////////
81
82	#include <systemc>
83	#include <sys/time.h>
84	#include <iostream>
85	#include <sstream>
86	#include <cstdlib>
87	#include <cstdarg>
88	#include <stdint.h>
89
90	#include "gdbserver.h"
91	#include "mapping_table.h"
92	#include "tsar_xbar_cluster.h"
93	#include "alloc_elems.h"
94
95	///////////////////////////////////////////////////
96	// OS
97	///////////////////////////////////////////////////
98	#define USE_ALMOS 0
99
100	#define almos_bootloader_pathname "bootloader.bin"
101	#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D"
102	#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D"
103
104	///////////////////////////////////////////////////
105	// Parallelisation
106	///////////////////////////////////////////////////
107	#define USE_OPENMP 0
108
109	#if USE_OPENMP
110	#include <omp.h>
111	#endif
112
113	// cluster index (computed from x,y coordinates)
114	#define cluster(x,y) (y + YMAX*x)
115
116	///////////////////////////////////////////////////////////
117	// DSPIN parameters
118	///////////////////////////////////////////////////////////
119
120	#define dspin_cmd_width 39
121	#define dspin_rsp_width 32
122
123	///////////////////////////////////////////////////////////
124	// VCI parameters
125	///////////////////////////////////////////////////////////
126
127	#define vci_cell_width_int 4
128	#define vci_cell_width_ext 8
129
130	#define vci_plen_width 8
131	#define vci_address_width 40
132	#define vci_rerror_width 1
133	#define vci_clen_width 1
134	#define vci_rflag_width 1
135	#define vci_srcid_width 14
136	#define vci_pktid_width 4
137	#define vci_trdid_width 4
138	#define vci_wrplen_width 1
139
140	////////////////////////////////////////////////////////////
141	// Main Hardware Parameters values
142	//////////////////////i/////////////////////////////////////
143
144	#include "hard_config.h"
145
146	////////////////////////////////////////////////////////////
147	// Secondary Hardware Parameters
148	//////////////////////i/////////////////////////////////////
149
150	#define XMAX CLUSTER_X
151	#define YMAX CLUSTER_Y
152
153	#define XRAM_LATENCY 0
154
155	#define MEMC_WAYS 16
156	#define MEMC_SETS 256
157
158	#define L1_IWAYS 4
159	#define L1_ISETS 64
160
161	#define L1_DWAYS 4
162	#define L1_DSETS 64
163
164	#define FBUF_X_SIZE 128
165	#define FBUF_Y_SIZE 128
166
167	#define BDEV_SECTOR_SIZE 512
168	#define BDEV_IMAGE_NAME "images.raw"
169
170	#define NIC_RX_NAME "giet_vm/nic/rx_packets.txt"
171	#define NIC_TX_NAME "giet_vm/nic/tx_packets.txt"
172	#define NIC_TIMEOUT 10000
173
174	#define NORTH 0
175	#define SOUTH 1
176	#define EAST 2
177	#define WEST 3
178
179	////////////////////////////////////////////////////////////
180	// Software to be loaded in ROM & RAM
181	//////////////////////i/////////////////////////////////////
182
183	#define SOFT_NAME "soft.elf"
184
185	////////////////////////////////////////////////////////////
186	// DEBUG Parameters default values
187	//////////////////////i/////////////////////////////////////
188
189	#define MAX_FROZEN_CYCLES 10000
190
191	/////////////////////////////////////////////////////////
192	// Physical segments definition
193	/////////////////////////////////////////////////////////
194	// There is 3 segments replicated in all clusters
195	// and 5 specific segments in the "IO" cluster
196	// (containing address 0xBF000000)
197	/////////////////////////////////////////////////////////
198
199	// specific segments in "IO" cluster : absolute physical address
200
201	#define BROM_BASE 0x00BFC00000
202	#define BROM_SIZE 0x0000100000 // 1 Mbytes
203
204	#define FBUF_BASE 0x00B2000000
205	#define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE
206
207	#define BDEV_BASE 0x00B3000000
208	#define BDEV_SIZE 0x0000001000 // 4 Kbytes
209
210	#define MTTY_BASE 0x00B4000000
211	#define MTTY_SIZE 0x0000001000 // 4 Kbytes
212
213	#define MNIC_BASE 0x00B5000000
214	#define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels)
215
216	// replicated segments : address is incremented by a cluster offset
217	// offset = cluster(x,y) << (address_width-x_width-y_width);
218
219	#define MEMC_BASE 0x0000000000
220	#define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster
221
222	#define XICU_BASE 0x00B0000000
223	#define XICU_SIZE 0x0000001000 // 4 Kbytes
224
225	#define MDMA_BASE 0x00B1000000
226	#define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel
227
228	////////////////////////////////////////////////////////////////////
229	// TGTID definition in direct space
230	// For all components: global TGTID = global SRCID = cluster_index
231	////////////////////////////////////////////////////////////////////
232
233	#define MEMC_TGTID 0
234	#define XICU_TGTID 1
235	#define MDMA_TGTID 2
236	#define MTTY_TGTID 3
237	#define FBUF_TGTID 4
238	#define BDEV_TGTID 5
239	#define MNIC_TGTID 6
240	#define BROM_TGTID 7
241
242	/////////////////////////////////
243	int _main(int argc, char *argv[])
244	{
245	using namespace sc_core;
246	using namespace soclib::caba;
247	using namespace soclib::common;
248
249
250	char soft_name[256] = SOFT_NAME; // pathname to binary code
251	uint64_t ncycles = 100000000000; // simulated cycles
252	char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
253	char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
254	char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
255	ssize_t threads_nr = 1; // simulator's threads number
256	bool debug_ok = false; // trace activated
257	size_t debug_period = 1; // trace period
258	size_t debug_memc_id = 0; // index of memc to be traced
259	size_t debug_proc_id = 0; // index of proc to be traced
260	uint32_t debug_from = 0; // trace start cycle
261	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
262	size_t cluster_io_id = 0; // index of cluster containing IOs
263
264	////////////// command line arguments //////////////////////
265	if (argc > 1)
266	{
267	for (int n = 1; n < argc; n = n + 2)
268	{
269	if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
270	{
271	ncycles = atoi(argv[n+1]);
272	}
273	else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
274	{
275	strcpy(soft_name, argv[n+1]);
276	}
277	else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
278	{
279	strcpy(disk_name, argv[n+1]);
280	}
281	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
282	{
283	debug_ok = true;
284	debug_from = atoi(argv[n+1]);
285	}
286	else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
287	{
288	debug_memc_id = atoi(argv[n+1]);
289	assert( (debug_memc_id < (XMAX*YMAX) ) &&
290	"debug_memc_id larger than XMAX * YMAX" );
291	}
292	else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
293	{
294	debug_proc_id = atoi(argv[n+1]);
295	assert( (debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX) ) &&
296	"debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
297	}
298	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
299	{
300	threads_nr = atoi(argv[n+1]);
301	threads_nr = (threads_nr < 1) ? 1 : threads_nr;
302	}
303	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
304	{
305	frozen_cycles = atoi(argv[n+1]);
306	}
307	else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
308	{
309	debug_period = atoi(argv[n+1]);
310	}
311	else
312	{
313	std::cout << " Arguments are (key,value) couples." << std::endl;
314	std::cout << " The order is not important." << std::endl;
315	std::cout << " Accepted arguments are :" << std::endl << std::endl;
316	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
317	std::cout << " -DISK pathname_for_disk_image" << std::endl;
318	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
319	std::cout << " -DEBUG debug_start_cycle" << std::endl;
320	std::cout << " -THREADS simulator's threads number" << std::endl;
321	std::cout << " -FROZEN max_number_of_lines" << std::endl;
322	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
323	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
324	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
325	exit(0);
326	}
327	}
328	}
329
330	// checking hardware parameters
331	assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or
332	(XMAX == 8) or (XMAX == 16) ) and
333	"The XMAX parameter must be 1, 2, 4, 8 or 16" );
334
335	assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or
336	(YMAX == 8) or (YMAX == 16) ) and
337	"The YMAX parameter must be 1, 2, 4, 8 or 16" );
338
339	assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
340	(NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
341	"The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
342
343	assert( (NB_DMA_CHANNELS < 9) and
344	"The NB_DMA_CHANNELS parameter must be smaller than 9" );
345
346	assert( (NB_TTY_CHANNELS < 15) and
347	"The NB_TTY_CHANNELS parameter must be smaller than 15" );
348
349	assert( (NB_NIC_CHANNELS < 9) and
350	"The NB_NIC_CHANNELS parameter must be smaller than 9" );
351
352	assert( (vci_address_width == vci_address_width) and
353	"address widths must be equal on internal & external networks" );
354
355	assert( (vci_address_width == 40) and
356	"VCI address width must be 40 bits" );
357
358	std::cout << std::endl;
359	std::cout << " - XMAX = " << XMAX << std::endl;
360	std::cout << " - YMAX = " << YMAX << std::endl;
361	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
362	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
363	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
364	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
365	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
366	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
367	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
368	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
369
370	std::cout << std::endl;
371
372	// Internal and External VCI parameters definition
373	typedef soclib::caba::VciParams<vci_cell_width_int,
374	vci_plen_width,
375	vci_address_width,
376	vci_rerror_width,
377	vci_clen_width,
378	vci_rflag_width,
379	vci_srcid_width,
380	vci_pktid_width,
381	vci_trdid_width,
382	vci_wrplen_width> vci_param_int;
383
384	typedef soclib::caba::VciParams<vci_cell_width_ext,
385	vci_plen_width,
386	vci_address_width,
387	vci_rerror_width,
388	vci_clen_width,
389	vci_rflag_width,
390	vci_srcid_width,
391	vci_pktid_width,
392	vci_trdid_width,
393	vci_wrplen_width> vci_param_ext;
394
395	#if USE_OPENMP
396	omp_set_dynamic(false);
397	omp_set_num_threads(threads_nr);
398	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
399	#endif
400
401	// Define parameters depending on mesh size
402	size_t x_width;
403	size_t y_width;
404
405	if (XMAX == 1) x_width = 0;
406	else if (XMAX == 2) x_width = 1;
407	else if (XMAX <= 4) x_width = 2;
408	else if (XMAX <= 8) x_width = 3;
409	else x_width = 4;
410
411	if (YMAX == 1) y_width = 0;
412	else if (YMAX == 2) y_width = 1;
413	else if (YMAX <= 4) y_width = 2;
414	else if (YMAX <= 8) y_width = 3;
415	else y_width = 4;
416
417	/////////////////////
418	// Mapping Tables
419	/////////////////////
420
421	// internal network
422	MappingTable maptabd(vci_address_width,
423	IntTab(x_width + y_width, 16 - x_width - y_width),
424	IntTab(x_width + y_width, vci_srcid_width - x_width - y_width),
425	0x00FF000000);
426
427	for (size_t x = 0; x < XMAX; x++)
428	{
429	for (size_t y = 0; y < YMAX; y++)
430	{
431	sc_uint<vci_address_width> offset;
432	offset = (sc_uint<vci_address_width>)cluster(x,y)
433	<< (vci_address_width-x_width-y_width);
434
435	std::ostringstream sh;
436	sh << "seg_memc_" << x << "_" << y;
437	maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE,
438	IntTab(cluster(x,y),MEMC_TGTID), true));
439
440	std::ostringstream si;
441	si << "seg_xicu_" << x << "_" << y;
442	maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE,
443	IntTab(cluster(x,y),XICU_TGTID), false));
444
445	std::ostringstream sd;
446	sd << "seg_mdma_" << x << "_" << y;
447	maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE,
448	IntTab(cluster(x,y),MDMA_TGTID), false));
449
450	if ( cluster(x,y) == cluster_io_id )
451	{
452	maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE,
453	IntTab(cluster(x,y),MTTY_TGTID), false));
454	maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE,
455	IntTab(cluster(x,y),FBUF_TGTID), false));
456	maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE,
457	IntTab(cluster(x,y),BDEV_TGTID), false));
458	maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE,
459	IntTab(cluster(x,y),MNIC_TGTID), false));
460	maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE,
461	IntTab(cluster(x,y),BROM_TGTID), true));
462	}
463	}
464	}
465	std::cout << maptabd << std::endl;
466
467	// external network
468	MappingTable maptabx(vci_address_width,
469	IntTab(x_width+y_width),
470	IntTab(x_width+y_width),
471	0xFFFF000000ULL);
472
473	for (size_t x = 0; x < XMAX; x++)
474	{
475	for (size_t y = 0; y < YMAX ; y++)
476	{
477
478	sc_uint<vci_address_width> offset;
479	offset = (sc_uint<vci_address_width>)cluster(x,y)
480	<< (vci_address_width-x_width-y_width);
481
482	std::ostringstream sh;
483	sh << "x_seg_memc_" << x << "_" << y;
484
485	maptabx.add(Segment(sh.str(), MEMC_BASE+offset,
486	MEMC_SIZE, IntTab(cluster(x,y)), false));
487	}
488	}
489	std::cout << maptabx << std::endl;
490
491	////////////////////
492	// Signals
493	///////////////////
494
495	sc_clock signal_clk("clk");
496	sc_signal<bool> signal_resetn("resetn");
497
498	// Horizontal inter-clusters DSPIN signals
499	DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc =
500	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 2);
501	DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec =
502	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 2);
503	DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc =
504	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2);
505	DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec =
506	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2);
507	DspinSignals<dspin_cmd_width>** signal_dspin_h_clack_inc =
508	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_clack_inc", XMAX-1, YMAX);
509	DspinSignals<dspin_cmd_width>** signal_dspin_h_clack_dec =
510	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_clack_dec", XMAX-1, YMAX);
511
512	// Vertical inter-clusters DSPIN signals
513	DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc =
514	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 2);
515	DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec =
516	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 2);
517	DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc =
518	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2);
519	DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec =
520	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2);
521	DspinSignals<dspin_cmd_width>** signal_dspin_v_clack_inc =
522	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_clack_inc", XMAX, YMAX-1);
523	DspinSignals<dspin_cmd_width>** signal_dspin_v_clack_dec =
524	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_clack_dec", XMAX, YMAX-1);
525
526	// Mesh boundaries DSPIN signals
527	DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in =
528	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", XMAX, YMAX, 2, 4);
529	DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out =
530	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 2, 4);
531	DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in =
532	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", XMAX, YMAX, 2, 4);
533	DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out =
534	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 2, 4);
535	DspinSignals<dspin_cmd_width>*** signal_dspin_false_clack_in =
536	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_clack_in", XMAX, YMAX, 4);
537	DspinSignals<dspin_cmd_width>*** signal_dspin_false_clack_out =
538	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_clack_out", XMAX, YMAX, 4);
539
540
541	////////////////////////////
542	// Loader
543	////////////////////////////
544
545	#if USE_ALMOS
546	soclib::common::Loader loader(almos_bootloader_pathname,
547	almos_archinfo_pathname,
548	almos_kernel_pathname);
549	#else
550	soclib::common::Loader loader(soft_name);
551	#endif
552
553	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
554	proc_iss::set_loader(loader);
555
556	////////////////////////////
557	// Clusters construction
558	////////////////////////////
559
560	TsarXbarCluster<dspin_cmd_width,
561	dspin_rsp_width,
562	vci_param_int,
563	vci_param_ext>* clusters[XMAX][YMAX];
564
565	#if USE_OPENMP
566	#pragma omp parallel
567	{
568	#pragma omp for
569	#endif
570	for(size_t i = 0; i < (XMAX * YMAX); i++)
571	{
572	size_t x = i / YMAX;
573	size_t y = i % YMAX;
574
575	#if USE_OPENMP
576	#pragma omp critical
577	{
578	#endif
579	std::cout << std::endl;
580	std::cout << "Cluster_" << x << "_" << y << std::endl;
581	std::cout << std::endl;
582
583	std::ostringstream sc;
584	sc << "cluster_" << x << "_" << y;
585	clusters[x][y] = new TsarXbarCluster<dspin_cmd_width,
586	dspin_rsp_width,
587	vci_param_int,
588	vci_param_ext>
589	(
590	sc.str().c_str(),
591	NB_PROCS_MAX,
592	NB_TTY_CHANNELS,
593	NB_DMA_CHANNELS,
594	x,
595	y,
596	cluster(x,y),
597	maptabd,
598	maptabx,
599	x_width,
600	y_width,
601	vci_srcid_width - x_width - y_width, // l_id width,
602	MEMC_TGTID,
603	XICU_TGTID,
604	MDMA_TGTID,
605	FBUF_TGTID,
606	MTTY_TGTID,
607	BROM_TGTID,
608	MNIC_TGTID,
609	BDEV_TGTID,
610	MEMC_WAYS,
611	MEMC_SETS,
612	L1_IWAYS,
613	L1_ISETS,
614	L1_DWAYS,
615	L1_DSETS,
616	XRAM_LATENCY,
617	(cluster(x,y) == cluster_io_id),
618	FBUF_X_SIZE,
619	FBUF_Y_SIZE,
620	disk_name,
621	BDEV_SECTOR_SIZE,
622	NB_NIC_CHANNELS,
623	nic_rx_name,
624	nic_tx_name,
625	NIC_TIMEOUT,
626	loader,
627	frozen_cycles,
628	debug_from ,
629	debug_ok and (cluster(x,y) == debug_memc_id),
630	debug_ok and (cluster(x,y) == debug_proc_id)
631	);
632
633	#if USE_OPENMP
634	} // end critical
635	#endif
636	} // end for
637	#if USE_OPENMP
638	}
639	#endif
640
641	///////////////////////////////////////////////////////////////
642	// Net-list
643	///////////////////////////////////////////////////////////////
644
645	// Clock & RESET
646	for (size_t x = 0; x < (XMAX); x++){
647	for (size_t y = 0; y < YMAX; y++){
648	clusters[x][y]->p_clk (signal_clk);
649	clusters[x][y]->p_resetn (signal_resetn);
650	}
651	}
652
653	// Inter Clusters horizontal connections
654	if (XMAX > 1){
655	for (size_t x = 0; x < (XMAX-1); x++){
656	for (size_t y = 0; y < YMAX; y++){
657	for (size_t k = 0; k < 2; k++){
658	clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]);
659	clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]);
660	clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]);
661	clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]);
662	clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]);
663	clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]);
664	clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]);
665	clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]);
666	}
667	clusters[x][y]->p_clack_out[EAST] (signal_dspin_h_clack_inc[x][y]);
668	clusters[x+1][y]->p_clack_in[WEST] (signal_dspin_h_clack_inc[x][y]);
669	clusters[x][y]->p_clack_in[EAST] (signal_dspin_h_clack_dec[x][y]);
670	clusters[x+1][y]->p_clack_out[WEST] (signal_dspin_h_clack_dec[x][y]);
671	}
672	}
673	}
674	std::cout << std::endl << "Horizontal connections established" << std::endl;
675
676	// Inter Clusters vertical connections
677	if (YMAX > 1) {
678	for (size_t y = 0; y < (YMAX-1); y++){
679	for (size_t x = 0; x < XMAX; x++){
680	for (size_t k = 0; k < 2; k++){
681	clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]);
682	clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]);
683	clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]);
684	clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]);
685	clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]);
686	clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]);
687	clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]);
688	clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]);
689	}
690	clusters[x][y]->p_clack_out[NORTH] (signal_dspin_v_clack_inc[x][y]);
691	clusters[x][y+1]->p_clack_in[SOUTH] (signal_dspin_v_clack_inc[x][y]);
692	clusters[x][y]->p_clack_in[NORTH] (signal_dspin_v_clack_dec[x][y]);
693	clusters[x][y+1]->p_clack_out[SOUTH] (signal_dspin_v_clack_dec[x][y]);
694	}
695	}
696	}
697	std::cout << "Vertical connections established" << std::endl;
698
699	// East & West boundary cluster connections
700	for (size_t y = 0; y < YMAX; y++)
701	{
702	for (size_t k = 0; k < 2; k++)
703	{
704	clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);
705	clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);
706	clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);
707	clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);
708
709	clusters[XMAX-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[XMAX-1][y][k][EAST]);
710	clusters[XMAX-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[XMAX-1][y][k][EAST]);
711	clusters[XMAX-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[XMAX-1][y][k][EAST]);
712	clusters[XMAX-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[XMAX-1][y][k][EAST]);
713	}
714
715	clusters[0][y]->p_clack_in[WEST] (signal_dspin_false_clack_in[0][y][WEST]);
716	clusters[0][y]->p_clack_out[WEST] (signal_dspin_false_clack_out[0][y][WEST]);
717
718	clusters[XMAX-1][y]->p_clack_in[EAST] (signal_dspin_false_clack_in[XMAX-1][y][EAST]);
719	clusters[XMAX-1][y]->p_clack_out[EAST] (signal_dspin_false_clack_out[XMAX-1][y][EAST]);
720	}
721
722	// North & South boundary clusters connections
723	for (size_t x = 0; x < XMAX; x++)
724	{
725	for (size_t k = 0; k < 2; k++)
726	{
727	clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
728	clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
729	clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
730	clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
731
732	clusters[x][YMAX-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][YMAX-1][k][NORTH]);
733	clusters[x][YMAX-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][YMAX-1][k][NORTH]);
734	clusters[x][YMAX-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][YMAX-1][k][NORTH]);
735	clusters[x][YMAX-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][YMAX-1][k][NORTH]);
736	}
737
738	clusters[x][0]->p_clack_in[SOUTH] (signal_dspin_false_clack_in[x][0][SOUTH]);
739	clusters[x][0]->p_clack_out[SOUTH] (signal_dspin_false_clack_out[x][0][SOUTH]);
740
741	clusters[x][YMAX-1]->p_clack_in[NORTH] (signal_dspin_false_clack_in[x][YMAX-1][NORTH]);
742	clusters[x][YMAX-1]->p_clack_out[NORTH] (signal_dspin_false_clack_out[x][YMAX-1][NORTH]);
743	}
744	std::cout << "North, South, West, East connections established" << std::endl;
745	std::cout << std::endl;
746
747
748	////////////////////////////////////////////////////////
749	// Simulation
750	///////////////////////////////////////////////////////
751
752	sc_start(sc_core::sc_time(0, SC_NS));
753	signal_resetn = false;
754
755	// network boundaries signals
756	for (size_t x = 0; x < XMAX ; x++){
757	for (size_t y = 0; y < YMAX ; y++){
758	for (size_t k = 0; k < 2; k++){
759	for (size_t a = 0; a < 4; a++){
760	signal_dspin_false_cmd_in [x][y][k][a].write = false;
761	signal_dspin_false_cmd_in [x][y][k][a].read = true;
762	signal_dspin_false_cmd_out[x][y][k][a].write = false;
763	signal_dspin_false_cmd_out[x][y][k][a].read = true;
764
765	signal_dspin_false_rsp_in [x][y][k][a].write = false;
766	signal_dspin_false_rsp_in [x][y][k][a].read = true;
767	signal_dspin_false_rsp_out[x][y][k][a].write = false;
768	signal_dspin_false_rsp_out[x][y][k][a].read = true;
769	}
770	}
771	}
772	}
773	// clack network boundaries signals
774	for (size_t x = 0; x < XMAX ; x++){
775	for (size_t y = 0; y < YMAX ; y++){
776	for (size_t k = 0; k < 4; k++){
777	signal_dspin_false_clack_in [x][y][k].write = false;
778	signal_dspin_false_clack_in [x][y][k].read = true;
779	signal_dspin_false_clack_out[x][y][k].write = false;
780	signal_dspin_false_clack_out[x][y][k].read = true;
781	}
782	}
783	}
784
785	sc_start(sc_core::sc_time(1, SC_NS));
786	signal_resetn = true;
787
788	for (uint64_t n = 1; n < ncycles; n++)
789	{
790	// Monitor a specific address for L1 & L2 caches
791	//clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL);
792	//clusters[1][0]->memc->copies_monitor(0x800002C000ULL);
793
794	if (debug_ok and (n > debug_from) and (n % debug_period == 0))
795	{
796	std::cout << "****************** cycle " << std::dec << n ;
797	std::cout << " ************************************************" << std::endl;
798
799	// trace proc[debug_proc_id]
800	size_t l = debug_proc_id % NB_PROCS_MAX ;
801	size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ;
802	size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ;
803
804	std::ostringstream proc_signame;
805	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
806	std::ostringstream p2m_signame;
807	p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ;
808	std::ostringstream m2p_signame;
809	m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ;
810	std::ostringstream p_cmd_signame;
811	p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ;
812	std::ostringstream p_rsp_signame;
813	p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ;
814
815	clusters[x][y]->proc[l]->print_trace();
816	clusters[x][y]->wi_proc[l]->print_trace();
817	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
818	clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str());
819	clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str());
820	clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str());
821	clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str());
822
823	clusters[x][y]->xbar_rsp_d->print_trace();
824	clusters[x][y]->xbar_cmd_d->print_trace();
825	clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD");
826	clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD");
827	clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP");
828	clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP");
829
830	// trace memc[debug_memc_id]
831	x = debug_memc_id / YMAX;
832	y = debug_memc_id % YMAX;
833
834	std::ostringstream smemc;
835	smemc << "[SIG]MEMC_" << x << "_" << y;
836	std::ostringstream sxram;
837	sxram << "[SIG]XRAM_" << x << "_" << y;
838	std::ostringstream sm2p;
839	sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ;
840	std::ostringstream sp2m;
841	sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ;
842	std::ostringstream m_cmd_signame;
843	m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ;
844	std::ostringstream m_rsp_signame;
845	m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ;
846
847	clusters[x][y]->memc->print_trace();
848	clusters[x][y]->wt_memc->print_trace();
849	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
850	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
851	clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());
852	clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());
853	clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str());
854	clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str());
855
856	// trace replicated peripherals
857	// clusters[1][1]->mdma->print_trace();
858	// clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1");
859	// clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1");
860
861
862	// trace external peripherals
863	size_t io_x = cluster_io_id / YMAX;
864	size_t io_y = cluster_io_id % YMAX;
865
866	clusters[io_x][io_y]->brom->print_trace();
867	clusters[io_x][io_y]->wt_brom->print_trace();
868	clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM");
869	clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD");
870	clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP");
871
872	// clusters[io_x][io_y]->bdev->print_trace();
873	// clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
874	// clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
875	}
876
877	sc_start(sc_core::sc_time(1, SC_NS));
878	}
879	return EXIT_SUCCESS;
880	}
881
882	int sc_main (int argc, char *argv[])
883	{
884	try {
885	return _main(argc, argv);
886	} catch (std::exception &e) {
887	std::cout << e.what() << std::endl;
888	} catch (...) {
889	std::cout << "Unknown exception occured" << std::endl;
890	throw;
891	}
892	return 1;
893	}
894
895
896	// Local Variables:
897	// tab-width: 3
898	// c-basic-offset: 3
899	// c-file-offsets:((innamespace . 0)(inline-open . 0))
900	// indent-tabs-mode: nil
901	// End:
902
903	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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