source: branches/v5/platforms/tsar_mono_mmu/top.cpp

Last change on this file was 351, checked in by joannou, 13 years ago

Got rid of intermediate v5 version. _dspin_coherence versions changed to main version for v5. Changed components names and platforms to fit the new names
File size: 11.8 KB
Line 
1#include <systemc>
2#include <sys/time.h>
3#include <iostream>
4#include <cstdlib>
5#include <cstdarg>
6
7#ifdef _OPENMP
8#include <omp.h>
9#endif
10
11#include "mapping_table.h"
12#include "mips32.h"
13#include "vci_simple_ram.h"
14#include "vci_multi_tty.h"
15#include "vci_vgmn.h"
16#include "vci_mem_cache.h"
17#include "vci_cc_vcache_wrapper.h"
18#include "vci_xicu.h"
19#include "vci_simhelper.h"
20#include "vci_multi_dma.h"
21
22// VCI format
23
24#define cell_width 4
25#define address_width 32
26#define plen_width 8
27#define error_width 2
28#define clen_width 1
29#define rflag_width 1
30#define srcid_width 14
31#define pktid_width 4
32#define trdid_width 4
33#define wrplen_width 1
34
35// segments definition in direct space
36
37#define XICU_BASE 0xd8200000
38#define XICU_SIZE 0x00001000
39
40#define MDMA_BASE 0xe8000000
41#define MDMA_SIZE 0x00000014
42
43#define MTTY_BASE 0xd0200000
44#define MTTY_SIZE 0x00000010
45
46#define EXIT_BASE 0xe0000000
47#define EXIT_SIZE 0x00000010
48
49#define BOOT_BASE 0xbfc00000
50#define BOOT_SIZE 0x00040000
51
52#define MEMC_BASE 0x00000000
53#define MEMC_SIZE 0x02000000
54
55/////////////////////////////////
56int _main(int argc, char *argv[])
57{
58
59using namespace sc_core;
60using namespace soclib::common;
61using namespace soclib::caba;
62
63#ifdef _OPENMP
64 omp_set_dynamic(false);
65 omp_set_num_threads(1);
66 std::cerr << "Built with openmp version " << _OPENMP << std::endl;
67#endif
68
69 char soft_name[256] = "test.elf"; // pathname to binary code
70 size_t ncycles = 1000000000; // max number of simulation cycles
71 bool trace_ok = false;
72 size_t from_cycle = 0; // debug start cycle
73 size_t max_frozen = 100000; // max number of frozen cycles
74 size_t nprocs = 1;
75
76 /////////////// command line arguments ////////////////
77 if (argc > 1)
78 {
79 for( int n=1 ; n<argc ; n=n+2 )
80 {
81 if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
82 {
83 ncycles = atoi(argv[n+1]);
84 }
85 else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
86 {
87 strcpy(soft_name, argv[n+1]);
88 }
89 else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
90 {
91 trace_ok = true;
92 from_cycle = atoi(argv[n+1]);
93 }
94 else if( (strcmp(argv[n],"-MAXFROZEN") == 0) && (n+1<argc) )
95 {
96 max_frozen = atoi(argv[n+1]);
97 }
98 else
99 {
100 std::cout << " Arguments on the command line are (key,value) couples." << std::endl;
101 std::cout << " The order is not important." << std::endl;
102 std::cout << " Accepted arguments are :" << std::endl << std::endl;
103 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
104 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
105 std::cout << " -TRACE debug_start_cycle" << std::endl;
106 exit(0);
107 }
108 }
109 }
110
111 // Define VCI parameters
112 typedef VciParams<cell_width,
113 plen_width,
114 address_width,
115 error_width,
116 clen_width,
117 rflag_width,
118 srcid_width,
119 pktid_width,
120 trdid_width,
121 wrplen_width> vci_param;
122
123 // Define processor type
124 typedef soclib::common::Mips32ElIss proc_iss;
125
126 // Mapping table for direct network
127 soclib::common::MappingTable maptabd(32, IntTab(6), IntTab(6), 0xF0000000);
128 maptabd.add(Segment("memc_d" , MEMC_BASE , MEMC_SIZE , IntTab(0), true));
129 maptabd.add(Segment("boot_d" , BOOT_BASE , BOOT_SIZE , IntTab(1), true));
130 maptabd.add(Segment("exit_d" , EXIT_BASE , EXIT_SIZE , IntTab(2), false));
131 maptabd.add(Segment("mtty_d" , MTTY_BASE , MTTY_SIZE , IntTab(3), false));
132 maptabd.add(Segment("xicu_d" , XICU_BASE , XICU_SIZE , IntTab(4), false));
133 maptabd.add(Segment("mdma_d" , MDMA_BASE , MDMA_SIZE , IntTab(5), false));
134 std::cout << maptabd << std::endl;
135
136 // Mapping table for coherence network
137 soclib::common::MappingTable maptabc(32, IntTab(srcid_width), IntTab(srcid_width), 0xF0000000);
138 maptabc.add(
139 Segment( "proc_c"
140 , 0x0000000
141 , 0x10
142 , IntTab(0)
143 , false
144 )
145 );
146
147 maptabc.add(
148 Segment( "memc_c"
149 , nprocs << (address_width - srcid_width)
150 , 0x10
151 , IntTab(nprocs)
152 , false
153 )
154 );
155 std::cout << maptabc << std::endl;
156
157 // Signals
158
159 sc_clock signal_clk ("signal_clk");
160 sc_signal<bool> signal_resetn ("isgnal_resetn");
161
162 sc_signal<bool> signal_mdma_irq ("signal_mdma_irq");
163 sc_signal<bool> signal_mtty_irq ("signal_mtty_irq");
164 sc_signal<bool> signal_proc_irq ("signal_proc_irq");
165 sc_signal<bool> signal_false ("signal_false");
166
167 VciSignals<vci_param> signal_vci_ini_d_proc ("vci_ini_d_proc");
168 // dspin coherence network
169 DspinSignals<33> signal_dspin_from_proc ("dspin_from_proc");
170 DspinSignals<40> signal_dspin_from_memc ("dspin_from_memc");
171
172 VciSignals<vci_param> signal_vci_tgt_d_mtty ("signal_vci_tgt_d_mtty");
173
174 VciSignals<vci_param> signal_vci_tgt_d_exit ("signal_vci_tgt_d_exit");
175
176 VciSignals<vci_param> signal_vci_tgt_d_xicu ("signal_vci_tgt_d_xicu");
177
178 VciSignals<vci_param> signal_vci_ini_d_mdma ("signal_vci_ini_d_mdma");
179 VciSignals<vci_param> signal_vci_tgt_d_mdma ("signal_vci_tgt_d_mdma");
180
181 VciSignals<vci_param> signal_vci_tgt_d_brom ("signal_vci_tgt_d_brom");
182
183
184 VciSignals<vci_param> signal_vci_ini_c_memc ("signal_vci_ini_c_memc");
185 VciSignals<vci_param> signal_vci_tgt_d_memc ("signal_vci_tgt_d_memc");
186 VciSignals<vci_param> signal_vci_tgt_c_memc ("signal_vci_tgt_c_memc");
187
188 VciSignals<vci_param> signal_vci_xram ("signal_vci_xram");
189
190 // Components
191
192 soclib::common::Loader loader(soft_name);
193
194 VciCcVCacheWrapper<vci_param, proc_iss >
195 proc("proc",
196 0, // proc_id
197 maptabd, // direct space
198 0, // srcid_d
199 0, // id_c
200 8,8, // itlb size
201 8,8, // dtlb size
202 4,64,16, // icache size
203 4,64,16, // dcache size
204 4, 4, // wbuf size
205 0, 0, // x, y Width
206 max_frozen, // max frozen cycles
207 from_cycle, trace_ok);
208
209 VciSimpleRam<vci_param>
210 rom("rom",
211 IntTab(1), // tgtid_d
212 maptabd,
213 loader);
214
215 VciSimpleRam<vci_param>
216 xram("xram",
217 IntTab(0), // tgtid_d(RAM) = tgtid_d(MEMC)
218 maptabd,
219 loader);
220
221 VciMemCache<vci_param>
222 memc("memc",
223 maptabd,
224 maptabd,
225 0, // srcid_x
226 0, // tgtid_d
227 1, // cc_id
228 16,256,16, // cache size
229 3, // MAX NUMBER OF COPIES
230 1024, // HEAP size
231 4, // TRT size
232 4, // UPT size
233 from_cycle, trace_ok);
234
235 VciSimhelper<vci_param>
236 vciexit("vciexit",
237 IntTab(2), // tgtid_d
238 maptabd);
239
240 VciXicu<vci_param>
241 xicu("xicu",
242 maptabd,
243 IntTab(4), // tgtid_d
244 1, // number of timers
245 2, // number of hard interrupts
246 0, // number of soft interrupts
247 1); // number of output IRQs
248
249 VciMultiTty<vci_param>
250 mtty("mtty",
251 IntTab(3), // tgtid_d
252 maptabd,
253 "mtty0", NULL);
254
255 VciMultiDma<vci_param>
256 mdma("mdma",
257 maptabd,
258 IntTab(1), // srcid_d
259 IntTab(5), // tgtid_d
260 64, // burst size
261 1); // number of channels
262
263 VciVgmn<vci_param>
264 ringd("ringd",
265 maptabd,
266 2, // number of initiators
267 6, // number of targets
268 2,
269 8);
270/*
271 VciVgmn<vci_param>
272 ringc("ringc",
273 maptabc,
274 2, // number of initiators
275 2, // number of targets
276 2,
277 8);
278*/
279
280 // net-list
281 proc.p_clk(signal_clk);
282 proc.p_resetn (signal_resetn);
283 proc.p_irq[0] (signal_proc_irq);
284 proc.p_irq[1] (signal_false);
285 proc.p_irq[2] (signal_false);
286 proc.p_irq[3] (signal_false);
287 proc.p_irq[4] (signal_false);
288 proc.p_irq[5] (signal_false);
289 proc.p_vci (signal_vci_ini_d_proc);
290 proc.p_dspin_in (signal_dspin_from_memc);
291 proc.p_dspin_out (signal_dspin_from_proc);
292
293 rom.p_clk (signal_clk);
294 rom.p_resetn (signal_resetn);
295 rom.p_vci (signal_vci_tgt_d_brom);
296
297 xicu.p_resetn (signal_resetn);
298 xicu.p_clk (signal_clk);
299 xicu.p_vci (signal_vci_tgt_d_xicu);
300 xicu.p_hwi[0] (signal_mtty_irq);
301 xicu.p_hwi[1] (signal_mdma_irq);
302 xicu.p_irq[0] (signal_proc_irq);
303
304 mdma.p_clk (signal_clk);
305 mdma.p_resetn (signal_resetn);
306 mdma.p_vci_target (signal_vci_tgt_d_mdma);
307 mdma.p_vci_initiator (signal_vci_ini_d_mdma);
308 mdma.p_irq[0] (signal_mdma_irq);
309
310 mtty.p_clk (signal_clk);
311 mtty.p_resetn (signal_resetn);
312 mtty.p_vci (signal_vci_tgt_d_mtty);
313 mtty.p_irq[0] (signal_mtty_irq);
314
315 vciexit.p_clk (signal_clk);
316 vciexit.p_resetn (signal_resetn);
317 vciexit.p_vci (signal_vci_tgt_d_exit);
318
319 memc.p_clk (signal_clk);
320 memc.p_resetn (signal_resetn);
321 memc.p_vci_tgt (signal_vci_tgt_d_memc);
322 memc.p_dspin_in (signal_dspin_from_proc);
323 memc.p_dspin_out (signal_dspin_from_memc);
324 memc.p_vci_ixr (signal_vci_xram);
325
326 xram.p_clk (signal_clk);
327 xram.p_resetn (signal_resetn);
328 xram.p_vci (signal_vci_xram);
329
330/*
331 ringc.p_clk (signal_clk);
332 ringc.p_resetn (signal_resetn);
333 ringc.p_to_initiator[0] (signal_vci_ini_c_proc);
334 ringc.p_to_initiator[1] (signal_vci_ini_c_memc);
335 ringc.p_to_target[0] (signal_vci_tgt_c_proc);
336 ringc.p_to_target[1] (signal_vci_tgt_c_memc);
337*/
338
339 ringd.p_clk (signal_clk);
340 ringd.p_resetn (signal_resetn);
341 ringd.p_to_initiator[0] (signal_vci_ini_d_proc);
342 ringd.p_to_initiator[1] (signal_vci_ini_d_mdma);
343 ringd.p_to_target[0] (signal_vci_tgt_d_memc);
344 ringd.p_to_target[1] (signal_vci_tgt_d_brom);
345 ringd.p_to_target[2] (signal_vci_tgt_d_exit);
346 ringd.p_to_target[3] (signal_vci_tgt_d_mtty);
347 ringd.p_to_target[4] (signal_vci_tgt_d_xicu);
348 ringd.p_to_target[5] (signal_vci_tgt_d_mdma);
349
350 // simulation loop
351
352 sc_start(sc_core::sc_time(0, SC_NS));
353 signal_resetn = false;
354
355 sc_start(sc_core::sc_time(1, SC_NS));
356 signal_resetn = true;
357
358 signal_false = false;
359
360 for ( size_t n=1 ; n<ncycles ; n++ )
361 {
362 if ( trace_ok and (n > from_cycle) )
363 {
364 std::cout << "****************** cycle " << std::dec << n
365 << " ************************************************" << std::endl;
366 proc.print_trace();
367 memc.print_trace();
368 signal_vci_ini_d_proc.print_trace("proc_ini_d");
369 signal_dspin_from_memc.print_trace("proc_dspin_in_c");
370 signal_dspin_from_proc.print_trace("proc_dspin_out_c");
371 signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
372 signal_vci_tgt_c_memc.print_trace("memc_tgt_c");
373 signal_vci_ini_c_memc.print_trace("memc_ini_c");
374 if ( signal_proc_irq.read() ) std::cout << "---- IRQ ----" << std::endl;
375 }
376 sc_start(sc_core::sc_time(1, SC_NS));
377 }
378 return EXIT_SUCCESS;
379}
380
381int sc_main (int argc, char *argv[])
382{
383 try {
384 return _main(argc, argv);
385 } catch (std::exception &e) {
386 std::cout << e.what() << std::endl;
387 } catch (...) {
388 std::cout << "Unknown exception occured" << std::endl;
389 throw;
390 }
391 return 1;
392}
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