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vci_mem_cache.h @ 295

Last change on this file since 295 was 295, checked in by cfuguet, 12 years ago
Introducing branches/v5/ components directory. This branch will be used to version control of new TSAR V5 which implements the DHCCP new modifications. All components version suffixes is not used anymore
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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	* cesar.fuguet-tortolero@lip6.fr
29	* alexandre.joannou@lip6.fr
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_H
42	#define SOCLIB_CABA_MEM_CACHE_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "generic_llsc_global_table.h"
57	#include "mem_cache_directory.h"
58	#include "xram_transaction.h"
59	#include "update_tab.h"
60
61	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
62	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
63
64	namespace soclib { namespace caba {
65	using namespace sc_core;
66
67	template<typename vci_param>
68	class VciMemCache
69	: public soclib::caba::BaseModule
70	{
71	typedef sc_dt::sc_uint<40> addr_t;
72	typedef typename vci_param::fast_addr_t vci_addr_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t size_t;
76	typedef uint32_t be_t;
77	typedef uint32_t copy_t;
78
79	/* States of the TGT_CMD fsm */
80	enum tgt_cmd_fsm_state_e{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_WRITE,
84	TGT_CMD_CAS
85	};
86
87	/* States of the TGT_RSP fsm */
88	enum tgt_rsp_fsm_state_e{
89	TGT_RSP_READ_IDLE,
90	TGT_RSP_WRITE_IDLE,
91	TGT_RSP_CAS_IDLE,
92	TGT_RSP_XRAM_IDLE,
93	TGT_RSP_INIT_IDLE,
94	TGT_RSP_CLEANUP_IDLE,
95	TGT_RSP_READ,
96	TGT_RSP_WRITE,
97	TGT_RSP_CAS,
98	TGT_RSP_XRAM,
99	TGT_RSP_INIT,
100	TGT_RSP_CLEANUP
101	};
102
103	/* States of the INIT_CMD fsm */
104	enum init_cmd_fsm_state_e{
105	INIT_CMD_INVAL_IDLE,
106	INIT_CMD_INVAL_NLINE,
107	INIT_CMD_XRAM_BRDCAST,
108	INIT_CMD_UPDT_IDLE,
109	INIT_CMD_WRITE_BRDCAST,
110	INIT_CMD_UPDT_NLINE,
111	INIT_CMD_UPDT_INDEX,
112	INIT_CMD_UPDT_DATA,
113	INIT_CMD_CAS_UPDT_IDLE,
114	INIT_CMD_CAS_BRDCAST,
115	INIT_CMD_CAS_UPDT_NLINE,
116	INIT_CMD_CAS_UPDT_INDEX,
117	INIT_CMD_CAS_UPDT_DATA,
118	INIT_CMD_CAS_UPDT_DATA_HIGH
119	};
120
121	/* States of the INIT_RSP fsm */
122	enum init_rsp_fsm_state_e{
123	INIT_RSP_IDLE,
124	INIT_RSP_UPT_LOCK,
125	INIT_RSP_UPT_CLEAR,
126	INIT_RSP_END
127	};
128
129	/* States of the READ fsm */
130	enum read_fsm_state_e{
131	READ_IDLE,
132	READ_DIR_REQ,
133	READ_DIR_LOCK,
134	READ_DIR_HIT,
135	READ_HEAP_REQ,
136	READ_HEAP_LOCK,
137	READ_HEAP_WRITE,
138	READ_HEAP_ERASE,
139	READ_HEAP_LAST,
140	READ_RSP,
141	READ_TRT_LOCK,
142	READ_TRT_SET,
143	READ_TRT_REQ
144	};
145
146	/* States of the WRITE fsm */
147	enum write_fsm_state_e{
148	WRITE_IDLE,
149	WRITE_NEXT,
150	WRITE_DIR_REQ,
151	WRITE_DIR_LOCK,
152	WRITE_DIR_READ,
153	WRITE_DIR_HIT,
154	WRITE_UPT_LOCK,
155	WRITE_UPT_HEAP_LOCK,
156	WRITE_UPT_REQ,
157	WRITE_UPT_NEXT,
158	WRITE_UPT_DEC,
159	WRITE_RSP,
160	WRITE_MISS_TRT_LOCK,
161	WRITE_MISS_TRT_DATA,
162	WRITE_MISS_TRT_SET,
163	WRITE_MISS_XRAM_REQ,
164	WRITE_BC_TRT_LOCK,
165	WRITE_BC_UPT_LOCK,
166	WRITE_BC_DIR_INVAL,
167	WRITE_BC_CC_SEND,
168	WRITE_BC_XRAM_REQ,
169	WRITE_WAIT
170	};
171
172	/* States of the IXR_RSP fsm */
173	enum ixr_rsp_fsm_state_e{
174	IXR_RSP_IDLE,
175	IXR_RSP_ACK,
176	IXR_RSP_TRT_ERASE,
177	IXR_RSP_TRT_READ
178	};
179
180	/* States of the XRAM_RSP fsm */
181	enum xram_rsp_fsm_state_e{
182	XRAM_RSP_IDLE,
183	XRAM_RSP_TRT_COPY,
184	XRAM_RSP_TRT_DIRTY,
185	XRAM_RSP_DIR_LOCK,
186	XRAM_RSP_DIR_UPDT,
187	XRAM_RSP_DIR_RSP,
188	XRAM_RSP_INVAL_LOCK,
189	XRAM_RSP_INVAL_WAIT,
190	XRAM_RSP_INVAL,
191	XRAM_RSP_WRITE_DIRTY,
192	XRAM_RSP_HEAP_REQ,
193	XRAM_RSP_HEAP_ERASE,
194	XRAM_RSP_HEAP_LAST,
195	XRAM_RSP_ERROR_ERASE,
196	XRAM_RSP_ERROR_RSP
197	};
198
199	/* States of the IXR_CMD fsm */
200	enum ixr_cmd_fsm_state_e{
201	IXR_CMD_READ_IDLE,
202	IXR_CMD_WRITE_IDLE,
203	IXR_CMD_CAS_IDLE,
204	IXR_CMD_XRAM_IDLE,
205	IXR_CMD_READ_NLINE,
206	IXR_CMD_WRITE_NLINE,
207	IXR_CMD_CAS_NLINE,
208	IXR_CMD_XRAM_DATA
209	};
210
211	/* States of the CAS fsm */
212	enum cas_fsm_state_e{
213	CAS_IDLE,
214	CAS_DIR_REQ,
215	CAS_DIR_LOCK,
216	CAS_DIR_HIT_READ,
217	CAS_DIR_HIT_WRITE,
218	CAS_UPT_LOCK,
219	CAS_UPT_HEAP_LOCK,
220	CAS_UPT_REQ,
221	CAS_UPT_NEXT,
222	CAS_BC_TRT_LOCK,
223	CAS_BC_UPT_LOCK,
224	CAS_BC_DIR_INVAL,
225	CAS_BC_CC_SEND,
226	CAS_BC_XRAM_REQ,
227	CAS_RSP_FAIL,
228	CAS_RSP_SUCCESS,
229	CAS_MISS_TRT_LOCK,
230	CAS_MISS_TRT_SET,
231	CAS_MISS_XRAM_REQ,
232	CAS_WAIT
233	};
234
235	/* States of the CLEANUP fsm */
236	enum cleanup_fsm_state_e{
237	CLEANUP_IDLE,
238	CLEANUP_DIR_REQ,
239	CLEANUP_DIR_LOCK,
240	CLEANUP_DIR_WRITE,
241	CLEANUP_HEAP_REQ,
242	CLEANUP_HEAP_LOCK,
243	CLEANUP_HEAP_SEARCH,
244	CLEANUP_HEAP_CLEAN,
245	CLEANUP_HEAP_FREE,
246	CLEANUP_UPT_LOCK,
247	CLEANUP_UPT_WRITE,
248	CLEANUP_WRITE_RSP,
249	CLEANUP_RSP
250	};
251
252	/* States of the ALLOC_DIR fsm */
253	enum alloc_dir_fsm_state_e{
254	ALLOC_DIR_RESET,
255	ALLOC_DIR_READ,
256	ALLOC_DIR_WRITE,
257	ALLOC_DIR_CAS,
258	ALLOC_DIR_CLEANUP,
259	ALLOC_DIR_XRAM_RSP
260	};
261
262	/* States of the ALLOC_TRT fsm */
263	enum alloc_trt_fsm_state_e{
264	ALLOC_TRT_READ,
265	ALLOC_TRT_WRITE,
266	ALLOC_TRT_CAS,
267	ALLOC_TRT_XRAM_RSP,
268	ALLOC_TRT_IXR_RSP
269	};
270
271	/* States of the ALLOC_UPT fsm */
272	enum alloc_upt_fsm_state_e{
273	ALLOC_UPT_WRITE,
274	ALLOC_UPT_XRAM_RSP,
275	ALLOC_UPT_INIT_RSP,
276	ALLOC_UPT_CLEANUP,
277	ALLOC_UPT_CAS
278	};
279
280	/* States of the ALLOC_HEAP fsm */
281	enum alloc_heap_fsm_state_e{
282	ALLOC_HEAP_RESET,
283	ALLOC_HEAP_READ,
284	ALLOC_HEAP_WRITE,
285	ALLOC_HEAP_CAS,
286	ALLOC_HEAP_CLEANUP,
287	ALLOC_HEAP_XRAM_RSP
288	};
289
290	/* transaction type, pktid field */
291	enum transaction_type_e
292	{
293	// b3 unused
294	// b2 READ / NOT READ
295	// Si READ
296	// b1 DATA / INS
297	// b0 UNC / MISS
298	// Si NOT READ
299	// b1 accÃšs table llsc type SW / other
300	// b2 WRITE/CAS/LL/SC
301	TYPE_READ_DATA_UNC = 0x0,
302	TYPE_READ_DATA_MISS = 0x1,
303	TYPE_READ_INS_UNC = 0x2,
304	TYPE_READ_INS_MISS = 0x3,
305	TYPE_WRITE = 0x4,
306	TYPE_CAS = 0x5,
307	TYPE_LL = 0x6,
308	TYPE_SC = 0x7
309	};
310
311	/* SC return values */
312	enum sc_status_type_e
313	{
314	SC_SUCCESS = 0x00000000,
315	SC_FAIL = 0x00000001
316	};
317
318	// debug variables (for each FSM)
319	size_t m_debug_start_cycle;
320	bool m_debug_ok;
321	bool m_debug_global;
322	bool m_debug_tgt_cmd_fsm;
323	bool m_debug_tgt_rsp_fsm;
324	bool m_debug_init_cmd_fsm;
325	bool m_debug_init_rsp_fsm;
326	bool m_debug_read_fsm;
327	bool m_debug_write_fsm;
328	bool m_debug_cas_fsm;
329	bool m_debug_cleanup_fsm;
330	bool m_debug_ixr_cmd_fsm;
331	bool m_debug_ixr_rsp_fsm;
332	bool m_debug_xram_rsp_fsm;
333	bool m_debug_previous_hit;
334	size_t m_debug_previous_count;
335
336	bool m_monitor_ok;
337	vci_addr_t m_monitor_base;
338	vci_addr_t m_monitor_length;
339
340	// instrumentation counters
341	uint32_t m_cpt_cycles; // Counter of cycles
342	uint32_t m_cpt_read; // Number of READ transactions
343	uint32_t m_cpt_read_miss; // Number of MISS READ
344	uint32_t m_cpt_write; // Number of WRITE transactions
345	uint32_t m_cpt_write_miss; // Number of MISS WRITE
346	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
347	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
348	uint32_t m_cpt_update; // Number of UPDATE transactions
349	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
350	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
351	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
352	uint32_t m_cpt_inval; // Number of INVAL transactions
353	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
354	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
355	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
356	uint32_t m_cpt_ll; // Number of LL transactions
357	uint32_t m_cpt_sc; // Number of SC transactions
358	uint32_t m_cpt_cas; // Number of CAS transactions
359
360	size_t m_prev_count;
361
362	protected:
363
364	SC_HAS_PROCESS(VciMemCache);
365
366	public:
367	sc_in<bool> p_clk;
368	sc_in<bool> p_resetn;
369	soclib::caba::VciTarget<vci_param> p_vci_tgt;
370	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
371	soclib::caba::VciInitiator<vci_param> p_vci_ini;
372	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
373
374	VciMemCache(
375	sc_module_name name, // Instance Name
376	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
377	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
378	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
379	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
380	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
381	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
382	const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
383	size_t nways, // Number of ways per set
384	size_t nsets, // Number of sets
385	size_t nwords, // Number of words per line
386	size_t heap_size=1024, // Size of the heap
387	size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
388	size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT
389	size_t debug_start_cycle=0,
390	bool debug_ok=false);
391
392	~VciMemCache();
393
394	void print_stats();
395	void print_trace();
396	void copies_monitor(vci_addr_t addr);
397	void start_monitor(vci_addr_t addr, vci_addr_t length);
398	void stop_monitor();
399
400	private:
401
402	void transition();
403	void genMoore();
404	void check_monitor( const char *buf, vci_addr_t addr, data_t data);
405
406	// Component attributes
407	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
408	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
409
410	const size_t m_initiators; // Number of initiators
411	const size_t m_heap_size; // Size of the heap
412	const size_t m_ways; // Number of ways in a set
413	const size_t m_sets; // Number of cache sets
414	const size_t m_words; // Number of words in a line
415	const size_t m_srcid_ixr; // Srcid for requests to XRAM
416	const size_t m_srcid_ini; // Srcid for requests to processors
417
418	uint32_t m_transaction_tab_lines;
419	TransactionTab m_transaction_tab; // xram transaction table
420	uint32_t m_update_tab_lines;
421	UpdateTab m_update_tab; // pending update & invalidate
422	CacheDirectory m_cache_directory; // data cache directory
423	CacheData m_cache_data; // data array[set][way][word]
424	HeapDirectory m_heap; // heap for copies
425	GenericLLSCGlobalTable
426	<
427	32 , // desired number of slots
428	4096, // number of processors in the system
429	8000, // registratioÃ§n life span (in # of LL operations)
430	typename vci_param::fast_addr_t // address type
431	>
432	m_llsc_table; // ll/sc global registration table
433
434	// adress masks
435	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
436	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
437	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
438	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
439
440	// broadcast address
441	vci_addr_t m_broadcast_address;
442
443	//////////////////////////////////////////////////
444	// Others registers
445	//////////////////////////////////////////////////
446	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
447	sc_signal<size_t> xxx_count;
448
449	//////////////////////////////////////////////////
450	// Registers controlled by the TGT_CMD fsm
451	//////////////////////////////////////////////////
452
453	// Fifo between TGT_CMD fsm and READ fsm
454	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
455	GenericFifo<size_t> m_cmd_read_length_fifo;
456	GenericFifo<size_t> m_cmd_read_srcid_fifo;
457	GenericFifo<size_t> m_cmd_read_trdid_fifo;
458	GenericFifo<size_t> m_cmd_read_pktid_fifo;
459
460	// Fifo between TGT_CMD fsm and WRITE fsm
461	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
462	GenericFifo<bool> m_cmd_write_eop_fifo;
463	GenericFifo<size_t> m_cmd_write_srcid_fifo;
464	GenericFifo<size_t> m_cmd_write_trdid_fifo;
465	GenericFifo<size_t> m_cmd_write_pktid_fifo;
466	GenericFifo<data_t> m_cmd_write_data_fifo;
467	GenericFifo<be_t> m_cmd_write_be_fifo;
468
469	// Fifo between TGT_CMD fsm and CAS fsm
470	GenericFifo<uint64_t> m_cmd_cas_addr_fifo;
471	GenericFifo<bool> m_cmd_cas_eop_fifo;
472	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
473	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
474	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
475	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
476
477	sc_signal<int> r_tgt_cmd_fsm;
478
479	size_t m_nseg;
480	size_t m_ncseg;
481	soclib::common::Segment **m_seg;
482	soclib::common::Segment **m_cseg;
483	///////////////////////////////////////////////////////
484	// Registers controlled by the READ fsm
485	///////////////////////////////////////////////////////
486
487	sc_signal<int> r_read_fsm; // FSM state
488	sc_signal<size_t> r_read_copy; // Srcid of the first copy
489	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
490	sc_signal<bool> r_read_copy_inst; // Type of the first copy
491	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
492	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
493	sc_signal<bool> r_read_lock; // lock bit (in directory)
494	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
495	sc_signal<size_t> r_read_count; // number of copies
496	sc_signal<size_t> r_read_ptr; // pointer to the heap
497	sc_signal<data_t> * r_read_data; // data (one cache line)
498	sc_signal<size_t> r_read_way; // associative way (in cache)
499	sc_signal<size_t> r_read_trt_index; // Transaction Table index
500	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
501	sc_signal<bool> r_read_last_free; // Last free entry
502	sc_signal<typename vci_param::fast_addr_t>
503	r_read_ll_key; // LL key returned by the llsc_global_table
504
505	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
506	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
507	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
508	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
509
510	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
511	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
512	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
513	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
514	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
515	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
516	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
517	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
518	sc_signal<typename vci_param::fast_addr_t>
519	r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
520
521	///////////////////////////////////////////////////////////////
522	// Registers controlled by the WRITE fsm
523	///////////////////////////////////////////////////////////////
524
525	sc_signal<int> r_write_fsm; // FSM state
526	sc_signal<addr_t> r_write_address; // first word address
527	sc_signal<size_t> r_write_word_index; // first word index in line
528	sc_signal<size_t> r_write_word_count; // number of words in line
529	sc_signal<size_t> r_write_srcid; // transaction srcid
530	sc_signal<size_t> r_write_trdid; // transaction trdid
531	sc_signal<size_t> r_write_pktid; // transaction pktid
532	sc_signal<data_t> * r_write_data; // data (one cache line)
533	sc_signal<be_t> * r_write_be; // one byte enable per word
534	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
535	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
536	sc_signal<bool> r_write_lock; // lock bit (in directory)
537	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
538	sc_signal<size_t> r_write_copy; // first owner of the line
539	sc_signal<size_t> r_write_copy_cache; // first owner of the line
540	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
541	sc_signal<size_t> r_write_count; // number of copies
542	sc_signal<size_t> r_write_ptr; // pointer to the heap
543	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
544	sc_signal<bool> r_write_to_dec; // need to decrement update counter
545	sc_signal<size_t> r_write_way; // way of the line
546	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
547	sc_signal<size_t> r_write_upt_index; // index in Update Table
548	sc_signal<bool> r_write_sc_fail; // sc command failed
549	sc_signal<bool> r_write_pending_sc; // sc command pending in WRITE fsm
550
551	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
552	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
553	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
554	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
555	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
556	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
557
558	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
559	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
560	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
561	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
562	sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data
563	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
564
565	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
566	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
567	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
568	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
569	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
570	sc_signal<data_t> * r_write_to_init_cmd_data; // data (one cache line)
571	sc_signal<be_t> * r_write_to_init_cmd_be; // word enable
572	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
573	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
574	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
575	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
576	#if L1_MULTI_CACHE
577	GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids
578	#endif
579
580	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
581	sc_signal<bool> r_write_to_init_rsp_req; // valid request
582	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
583
584	/////////////////////////////////////////////////////////
585	// Registers controlled by INIT_RSP fsm
586	//////////////////////////////////////////////////////////
587
588	sc_signal<int> r_init_rsp_fsm; // FSM state
589	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
590	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
591	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
592	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
593	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
594
595	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
596	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
597	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
598	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
599	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
600
601	///////////////////////////////////////////////////////
602	// Registers controlled by CLEANUP fsm
603	///////////////////////////////////////////////////////
604
605	sc_signal<int> r_cleanup_fsm; // FSM state
606	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
607	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
608	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
609	sc_signal<addr_t> r_cleanup_nline; // cache line index
610
611	sc_signal<copy_t> r_cleanup_copy; // first copy
612	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
613	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
614	sc_signal<copy_t> r_cleanup_count; // number of copies
615	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
616	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
617	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
618	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
619	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
620	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
621	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
622	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
623	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
624	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
625	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
626
627	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
628	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
629	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
630	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
631
632	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
633
634	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
635	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
636	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
637	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
638	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
639
640	///////////////////////////////////////////////////////
641	// Registers controlled by CAS fsm
642	///////////////////////////////////////////////////////
643
644	sc_signal<int> r_cas_fsm; // FSM state
645	sc_signal<data_t> r_cas_wdata; // write data word
646	sc_signal<data_t> * r_cas_rdata; // read data word
647	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
648	sc_signal<size_t> r_cas_cpt; // size of command
649	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
650	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
651	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
652	sc_signal<size_t> r_cas_count; // number of copies
653	sc_signal<size_t> r_cas_ptr; // pointer to the heap
654	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
655	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
656	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
657	sc_signal<size_t> r_cas_way; // way in directory
658	sc_signal<size_t> r_cas_set; // set in directory
659	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
660	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
661	sc_signal<size_t> r_cas_upt_index; // Update Table index
662
663	// Buffer between CAS fsm and INIT_CMD fsm (XRAM read)
664	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
665	sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index
666	sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table
667	sc_signal<bool> r_cas_to_ixr_cmd_write; // write request
668	sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data
669
670
671	// Buffer between CAS fsm and TGT_RSP fsm
672	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
673	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
674	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
675	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
676	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
677
678	// Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
679	sc_signal<bool> r_cas_to_init_cmd_multi_req; // valid request
680	sc_signal<bool> r_cas_to_init_cmd_brdcast_req; // brdcast request
681	sc_signal<addr_t> r_cas_to_init_cmd_nline; // cache line index
682	sc_signal<size_t> r_cas_to_init_cmd_trdid; // index in Update Table
683	sc_signal<data_t> r_cas_to_init_cmd_wdata; // data (one word)
684	sc_signal<bool> r_cas_to_init_cmd_is_long; // it is a 64 bits CAS
685	sc_signal<data_t> r_cas_to_init_cmd_wdata_high; // data high (one word)
686	sc_signal<size_t> r_cas_to_init_cmd_index; // index of the word in line
687	GenericFifo<bool> m_cas_to_init_cmd_inst_fifo; // fifo for the L1 type
688	GenericFifo<size_t> m_cas_to_init_cmd_srcid_fifo; // fifo for srcids
689	#if L1_MULTI_CACHE
690	GenericFifo<size_t> m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids
691	#endif
692
693	// Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry)
694	sc_signal<bool> r_cas_to_init_rsp_req; // valid request
695	sc_signal<size_t> r_cas_to_init_rsp_upt_index; // index in update table
696
697	////////////////////////////////////////////////////
698	// Registers controlled by the IXR_RSP fsm
699	////////////////////////////////////////////////////
700
701	sc_signal<int> r_ixr_rsp_fsm; // FSM state
702	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
703	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
704
705	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
706	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
707
708	////////////////////////////////////////////////////
709	// Registers controlled by the XRAM_RSP fsm
710	////////////////////////////////////////////////////
711
712	sc_signal<int> r_xram_rsp_fsm; // FSM state
713	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
714	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
715	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
716	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
717	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
718	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
719	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
720	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
721	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
722	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
723	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
724	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
725	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
726	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
727	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
728	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
729
730	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
731	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
732	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
733	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
734	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
735	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
736	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
737	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
738	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
739	sc_signal<typename vci_param::fast_addr_t>
740	r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
741
742	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
743	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
744	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
745	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
746	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
747	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
748	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
749	#if L1_MULTI_CACHE
750	GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids
751	#endif
752
753	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
754	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
755	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
756	sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data
757	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
758
759	////////////////////////////////////////////////////
760	// Registers controlled by the IXR_CMD fsm
761	////////////////////////////////////////////////////
762
763	sc_signal<int> r_ixr_cmd_fsm;
764	sc_signal<size_t> r_ixr_cmd_cpt;
765
766	////////////////////////////////////////////////////
767	// Registers controlled by TGT_RSP fsm
768	////////////////////////////////////////////////////
769
770	sc_signal<int> r_tgt_rsp_fsm;
771	sc_signal<size_t> r_tgt_rsp_cpt;
772
773	////////////////////////////////////////////////////
774	// Registers controlled by INIT_CMD fsm
775	////////////////////////////////////////////////////
776
777	sc_signal<int> r_init_cmd_fsm;
778	sc_signal<size_t> r_init_cmd_cpt;
779	sc_signal<bool> r_init_cmd_inst;
780
781	////////////////////////////////////////////////////
782	// Registers controlled by ALLOC_DIR fsm
783	////////////////////////////////////////////////////
784
785	sc_signal<int> r_alloc_dir_fsm;
786	sc_signal<unsigned> r_alloc_dir_reset_cpt;
787
788	////////////////////////////////////////////////////
789	// Registers controlled by ALLOC_TRT fsm
790	////////////////////////////////////////////////////
791
792	sc_signal<int> r_alloc_trt_fsm;
793
794	////////////////////////////////////////////////////
795	// Registers controlled by ALLOC_UPT fsm
796	////////////////////////////////////////////////////
797
798	sc_signal<int> r_alloc_upt_fsm;
799
800	////////////////////////////////////////////////////
801	// Registers controlled by ALLOC_HEAP fsm
802	////////////////////////////////////////////////////
803
804	sc_signal<int> r_alloc_heap_fsm;
805	sc_signal<unsigned> r_alloc_heap_reset_cpt;
806	}; // end class VciMemCache
807
808	}}
809
810	#endif
811
812	// Local Variables:
813	// tab-width: 2
814	// c-basic-offset: 2
815	// c-file-offsets:((innamespace . 0)(inline-open . 0))
816	// indent-tabs-mode: nil
817	// End:
818
819	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
820

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