[920] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * File : vci_cc_vcache_wrapper.h |
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| 4 | * Copyright (c) UPMC, Lip6, SoC |
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| 5 | * Authors : Alain GREINER, Yang GAO |
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| 6 | * Date : 27/11/2011 |
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| 7 | * |
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| 8 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 9 | * |
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| 10 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 11 | * |
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| 12 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 13 | * under the terms of the GNU Lesser General Public License as published |
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| 14 | * by the Free Software Foundation; version 2.1 of the License. |
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| 15 | * |
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| 16 | * SoCLib is distributed in the hope that it will be useful, but |
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 19 | * Lesser General Public License for more details. |
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| 20 | * |
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| 21 | * You should have received a copy of the GNU Lesser General Public |
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| 22 | * License along with SoCLib; if not, write to the Free Software |
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| 23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 24 | * 02110-1301 USA |
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| 25 | * |
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| 26 | * SOCLIB_LGPL_HEADER_END |
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| 27 | * |
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| 28 | * Maintainers: cesar.fuguet-tortolero@lip6.fr |
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| 29 | * alexandre.joannou@lip6.fr |
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| 30 | */ |
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| 31 | |
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| 32 | #ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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| 33 | #define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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| 34 | |
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| 35 | #include <inttypes.h> |
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| 36 | #include <systemc> |
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| 37 | #include <set> |
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| 38 | |
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| 39 | #include "caba_base_module.h" |
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| 40 | #include "multi_write_buffer.h" |
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| 41 | #include "generic_fifo.h" |
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| 42 | #include "generic_tlb.h" |
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| 43 | #include "generic_cache.h" |
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| 44 | #include "vci_initiator.h" |
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| 45 | #include "dspin_interface.h" |
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| 46 | #include "dspin_wtidl_param.h" |
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| 47 | #include "mapping_table.h" |
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| 48 | #include "static_assert.h" |
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| 49 | #include "iss2.h" |
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| 50 | |
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| 51 | #define LLSC_TIMEOUT 10000 |
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| 52 | |
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| 53 | namespace soclib { |
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| 54 | namespace caba { |
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| 55 | |
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| 56 | using namespace sc_core; |
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| 57 | |
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| 58 | |
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| 59 | class VcacheUpdate { |
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| 60 | |
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| 61 | public: |
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| 62 | uint64_t m_addr; |
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| 63 | uint32_t m_value; |
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| 64 | uint32_t m_be; |
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| 65 | |
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| 66 | VcacheUpdate(uint64_t ad, uint32_t val, uint32_t b) : |
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| 67 | m_addr(ad), |
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| 68 | m_value(val), |
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| 69 | m_be(b) |
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| 70 | { |
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| 71 | } |
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| 72 | |
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| 73 | ~VcacheUpdate() {} |
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| 74 | |
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| 75 | }; |
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| 76 | |
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| 77 | |
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| 78 | //////////////////////////////////////////// |
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| 79 | template<typename vci_param, |
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| 80 | size_t dspin_in_width, |
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| 81 | size_t dspin_out_width, |
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| 82 | typename iss_t> |
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| 83 | class VciCcVCacheWrapper |
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| 84 | //////////////////////////////////////////// |
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| 85 | : public soclib::caba::BaseModule |
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| 86 | { |
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| 87 | |
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| 88 | typedef typename vci_param::fast_addr_t paddr_t; |
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| 89 | |
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| 90 | enum icache_fsm_state_e |
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| 91 | { |
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| 92 | ICACHE_IDLE, |
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| 93 | // handling XTN processor requests |
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| 94 | ICACHE_XTN_TLB_FLUSH, |
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| 95 | ICACHE_XTN_CACHE_FLUSH, |
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| 96 | ICACHE_XTN_CACHE_FLUSH_GO, |
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| 97 | ICACHE_XTN_TLB_INVAL, |
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| 98 | ICACHE_XTN_CACHE_INVAL_VA, |
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| 99 | ICACHE_XTN_CACHE_INVAL_PA, |
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| 100 | ICACHE_XTN_CACHE_INVAL_GO, |
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| 101 | // handling tlb miss |
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| 102 | ICACHE_TLB_WAIT, |
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| 103 | // handling cache miss |
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| 104 | ICACHE_MISS_SELECT, |
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| 105 | ICACHE_MISS_CLEAN, |
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| 106 | ICACHE_MISS_WAIT, |
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| 107 | ICACHE_MISS_DATA_UPDT, |
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| 108 | ICACHE_MISS_DIR_UPDT, |
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| 109 | // handling unc read |
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| 110 | ICACHE_UNC_WAIT, |
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| 111 | }; |
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| 112 | |
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| 113 | enum dcache_fsm_state_e |
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| 114 | { |
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| 115 | DCACHE_IDLE, |
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| 116 | // handling itlb & dtlb miss |
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| 117 | DCACHE_TLB_MISS, |
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| 118 | DCACHE_TLB_PTE1_GET, |
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| 119 | DCACHE_TLB_PTE1_SELECT, |
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| 120 | DCACHE_TLB_PTE1_UPDT, |
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| 121 | DCACHE_TLB_PTE2_GET, |
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| 122 | DCACHE_TLB_PTE2_SELECT, |
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| 123 | DCACHE_TLB_PTE2_UPDT, |
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| 124 | DCACHE_TLB_LR_UPDT, |
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| 125 | DCACHE_TLB_LR_WAIT, |
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| 126 | DCACHE_TLB_RETURN, |
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| 127 | // handling processor XTN requests |
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| 128 | DCACHE_XTN_SWITCH, |
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| 129 | DCACHE_XTN_SYNC, |
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| 130 | DCACHE_XTN_IC_INVAL_VA, |
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| 131 | DCACHE_XTN_IC_FLUSH, |
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| 132 | DCACHE_XTN_IC_INVAL_PA, |
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| 133 | DCACHE_XTN_IC_PADDR_EXT, |
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| 134 | DCACHE_XTN_IT_INVAL, |
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| 135 | DCACHE_XTN_DC_FLUSH, |
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| 136 | DCACHE_XTN_DC_FLUSH_GO, |
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| 137 | DCACHE_XTN_DC_INVAL_VA, |
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| 138 | DCACHE_XTN_DC_INVAL_PA, |
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| 139 | DCACHE_XTN_DC_INVAL_END, |
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| 140 | DCACHE_XTN_DC_INVAL_GO, |
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| 141 | DCACHE_XTN_DT_INVAL, |
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| 142 | //handling dirty bit update |
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| 143 | DCACHE_DIRTY_GET_PTE, |
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| 144 | DCACHE_DIRTY_WAIT, |
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| 145 | // handling processor miss requests |
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| 146 | DCACHE_MISS_SELECT, |
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| 147 | DCACHE_MISS_VICTIM_CHECK, |
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| 148 | DCACHE_MISS_WAIT, |
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| 149 | DCACHE_MISS_DATA_UPDT, |
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| 150 | DCACHE_MISS_DIR_UPDT, |
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| 151 | // handling processor unc, ll and sc requests |
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| 152 | DCACHE_UNC_WAIT, |
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| 153 | DCACHE_LL_WAIT, |
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| 154 | DCACHE_SC_WAIT, |
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| 155 | // handling TLB inval (after a coherence or XTN request) |
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| 156 | DCACHE_INVAL_TLB_SCAN, |
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| 157 | }; |
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| 158 | |
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| 159 | enum cmd_fsm_state_e |
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| 160 | { |
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| 161 | CMD_IDLE, |
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| 162 | CMD_INS_MISS, |
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| 163 | CMD_INS_UNC, |
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| 164 | CMD_DATA_MISS, |
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| 165 | CMD_DATA_UNC_READ, |
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| 166 | CMD_DATA_UNC_WRITE, |
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| 167 | CMD_DATA_WRITE, |
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| 168 | CMD_DATA_LL, |
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| 169 | CMD_DATA_SC, |
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| 170 | CMD_DATA_CAS, |
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| 171 | }; |
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| 172 | |
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| 173 | enum rsp_fsm_state_e |
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| 174 | { |
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| 175 | RSP_IDLE, |
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| 176 | RSP_INS_MISS, |
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| 177 | RSP_INS_UNC, |
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| 178 | RSP_DATA_MISS, |
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| 179 | RSP_DATA_UNC, |
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| 180 | RSP_DATA_LL, |
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| 181 | RSP_DATA_WRITE, |
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| 182 | }; |
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| 183 | |
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| 184 | /* transaction type, pktid field */ |
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| 185 | enum transaction_type_e |
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| 186 | { |
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| 187 | // b3 unused |
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| 188 | // b2 READ / NOT READ |
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| 189 | // if READ |
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| 190 | // b1 DATA / INS |
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| 191 | // b0 UNC / MISS |
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| 192 | // else |
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| 193 | // b1 accÚs table llsc type SW / other |
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| 194 | // b2 WRITE/CAS/LL/SC |
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| 195 | TYPE_DATA_UNC = 0x0, |
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| 196 | TYPE_READ_DATA_MISS = 0x1, |
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| 197 | TYPE_READ_INS_UNC = 0x2, |
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| 198 | TYPE_READ_INS_MISS = 0x3, |
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| 199 | TYPE_WRITE = 0x4, |
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| 200 | TYPE_CAS = 0x5, |
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| 201 | TYPE_LL = 0x6, |
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| 202 | TYPE_SC = 0x7 |
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| 203 | }; |
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| 204 | |
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| 205 | /* SC return values */ |
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| 206 | enum sc_status_type_e |
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| 207 | { |
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| 208 | SC_SUCCESS = 0x00000000, |
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| 209 | SC_FAIL = 0x00000001 |
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| 210 | }; |
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| 211 | |
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| 212 | // TLB Mode : ITLB / DTLB / ICACHE / DCACHE |
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| 213 | enum |
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| 214 | { |
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| 215 | INS_TLB_MASK = 0x8, |
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| 216 | DATA_TLB_MASK = 0x4, |
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| 217 | INS_CACHE_MASK = 0x2, |
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| 218 | DATA_CACHE_MASK = 0x1, |
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| 219 | }; |
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| 220 | |
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| 221 | // Error Type |
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| 222 | enum mmu_error_type_e |
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| 223 | { |
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| 224 | MMU_NONE = 0x0000, // None |
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| 225 | MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 |
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| 226 | MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 |
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| 227 | MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode |
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| 228 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page |
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| 229 | MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write & undefined external access |
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| 230 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write & Bus Error accessing PT1 |
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| 231 | MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 |
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| 232 | MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access |
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| 233 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 |
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| 234 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 |
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| 235 | MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode |
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| 236 | MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page |
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| 237 | MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access |
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| 238 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 |
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| 239 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 |
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| 240 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access |
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| 241 | }; |
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| 242 | |
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| 243 | // miss types for data cache |
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| 244 | enum dcache_miss_type_e |
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| 245 | { |
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| 246 | PTE1_MISS, |
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| 247 | PTE2_MISS, |
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| 248 | PROC_MISS, |
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| 249 | }; |
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| 250 | |
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| 251 | public: |
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| 252 | sc_in<bool> p_clk; |
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| 253 | sc_in<bool> p_resetn; |
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| 254 | sc_in<bool> p_irq[iss_t::n_irq]; |
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| 255 | soclib::caba::VciInitiator<vci_param> p_vci; |
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| 256 | soclib::caba::DspinInput<dspin_in_width> p_dspin_m2p; |
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| 257 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m; |
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| 258 | soclib::caba::DspinInput<dspin_in_width> p_dspin_clack; |
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| 259 | |
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| 260 | private: |
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| 261 | |
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| 262 | // STRUCTURAL PARAMETERS |
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| 263 | soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table; |
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| 264 | |
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| 265 | const size_t m_srcid; |
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| 266 | const size_t m_cc_global_id; |
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| 267 | const size_t m_nline_width; |
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| 268 | const size_t m_itlb_ways; |
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| 269 | const size_t m_itlb_sets; |
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| 270 | const size_t m_dtlb_ways; |
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| 271 | const size_t m_dtlb_sets; |
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| 272 | const size_t m_icache_ways; |
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| 273 | const size_t m_icache_sets; |
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| 274 | const paddr_t m_icache_yzmask; |
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| 275 | const size_t m_icache_words; |
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| 276 | const size_t m_dcache_ways; |
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| 277 | const size_t m_dcache_sets; |
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| 278 | const paddr_t m_dcache_yzmask; |
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| 279 | const size_t m_dcache_words; |
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| 280 | const size_t m_x_width; |
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| 281 | const size_t m_y_width; |
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| 282 | const size_t m_proc_id; |
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| 283 | const uint32_t m_max_frozen_cycles; |
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| 284 | const size_t m_paddr_nbits; |
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| 285 | uint32_t m_debug_start_cycle; |
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| 286 | bool m_debug_ok; |
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| 287 | |
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| 288 | uint32_t m_dcache_paddr_ext_reset; |
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| 289 | uint32_t m_icache_paddr_ext_reset; |
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| 290 | |
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| 291 | //////////////////////////////////////// |
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| 292 | // Communication with processor ISS |
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| 293 | //////////////////////////////////////// |
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| 294 | typename iss_t::InstructionRequest m_ireq; |
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| 295 | typename iss_t::InstructionResponse m_irsp; |
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| 296 | typename iss_t::DataRequest m_dreq; |
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| 297 | typename iss_t::DataResponse m_drsp; |
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| 298 | |
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| 299 | ///////////////////////////////////////////// |
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| 300 | // debug variables |
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| 301 | ///////////////////////////////////////////// |
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| 302 | bool m_debug_previous_i_hit; |
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| 303 | bool m_debug_previous_d_hit; |
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| 304 | bool m_debug_icache_fsm; |
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| 305 | bool m_debug_dcache_fsm; |
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| 306 | bool m_debug_cmd_fsm; |
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| 307 | uint32_t m_previous_status; |
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| 308 | |
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| 309 | |
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| 310 | /////////////////////////////// |
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| 311 | // Software visible REGISTERS |
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| 312 | /////////////////////////////// |
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| 313 | sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register |
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| 314 | sc_signal<uint32_t> r_mmu_mode; // mmu mode register |
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| 315 | sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low |
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| 316 | sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight |
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| 317 | sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address |
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| 318 | sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address |
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| 319 | sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type |
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| 320 | sc_signal<uint32_t> r_mmu_detr; // mmu data error type |
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| 321 | uint32_t r_mmu_params; // read-only |
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| 322 | uint32_t r_mmu_release; // read_only |
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| 323 | |
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| 324 | |
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| 325 | ////////////////////////////// |
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| 326 | // ICACHE FSM REGISTERS |
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| 327 | ////////////////////////////// |
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| 328 | sc_signal<int> r_icache_fsm; // state register |
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| 329 | sc_signal<int> r_icache_fsm_save; // return state for coherence op |
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| 330 | sc_signal<paddr_t> r_icache_vci_paddr; // physical address |
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| 331 | sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor |
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| 332 | |
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| 333 | // icache miss handling |
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| 334 | sc_signal<size_t> r_icache_miss_way; // selected way for cache update |
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| 335 | sc_signal<size_t> r_icache_miss_set; // selected set for cache update |
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| 336 | sc_signal<size_t> r_icache_miss_word; // word index ( cache update) |
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| 337 | sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge |
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| 338 | |
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| 339 | // icache flush handling |
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| 340 | sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush |
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| 341 | |
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| 342 | // communication between ICACHE FSM and VCI_CMD FSM |
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| 343 | sc_signal<bool> r_icache_miss_req; // cached read miss |
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| 344 | sc_signal<bool> r_icache_unc_req; // uncached read miss |
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| 345 | |
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| 346 | // communication between ICACHE FSM and DCACHE FSM |
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| 347 | sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache) |
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| 348 | sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error |
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| 349 | |
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| 350 | // Physical address extension for data access |
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| 351 | sc_signal<uint32_t> r_icache_paddr_ext; // CP2 register (if vci_address > 32) |
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| 352 | |
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| 353 | /////////////////////////////// |
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| 354 | // DCACHE FSM REGISTERS |
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| 355 | /////////////////////////////// |
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| 356 | sc_signal<int> r_dcache_fsm; // state register |
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| 357 | sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op |
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| 358 | // registers written in P0 stage (used in P1 stage) |
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| 359 | sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage |
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| 360 | sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage |
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| 361 | sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) |
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| 362 | sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) |
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| 363 | sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) |
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| 364 | sc_signal<paddr_t> r_dcache_save_paddr; // physical address |
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| 365 | sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) |
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| 366 | sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) |
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| 367 | sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache) |
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| 368 | // registers used by the Dirty bit sub-fsm |
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| 369 | sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address |
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| 370 | sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache |
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| 371 | sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache |
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| 372 | |
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| 373 | // communication between DCACHE FSM and VCI_CMD FSM |
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| 374 | sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command |
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| 375 | sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command |
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| 376 | sc_signal<bool> r_dcache_vci_miss_req; // read miss request |
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| 377 | sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) |
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| 378 | sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable byte enable |
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| 379 | sc_signal<uint32_t> r_dcache_vci_unc_write; // uncacheable data write request |
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| 380 | sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS |
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| 381 | sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS |
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| 382 | sc_signal<uint32_t> r_dcache_vci_cas_new; // new data value for a CAS |
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| 383 | sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL |
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| 384 | sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC |
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| 385 | sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) |
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| 386 | |
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| 387 | // register used for XTN inval |
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| 388 | sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) |
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| 389 | sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) |
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| 390 | |
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| 391 | // handling dcache miss |
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| 392 | sc_signal<int> r_dcache_miss_type; // depending on the requester |
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| 393 | sc_signal<size_t> r_dcache_miss_word; // word index for cache update |
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| 394 | sc_signal<size_t> r_dcache_miss_way; // selected way for cache update |
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| 395 | sc_signal<size_t> r_dcache_miss_set; // selected set for cache update |
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| 396 | sc_signal<paddr_t> r_dcache_miss_victim; // selected set for cache update |
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| 397 | |
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| 398 | // dcache flush handling |
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| 399 | sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush |
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| 400 | |
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| 401 | // ll response handling |
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| 402 | sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp |
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| 403 | |
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| 404 | // used by the TLB miss sub-fsm |
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| 405 | sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss |
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| 406 | sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) |
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| 407 | sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte |
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| 408 | sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 |
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| 409 | sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 |
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| 410 | sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache |
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| 411 | sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache |
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| 412 | sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache |
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| 413 | sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb |
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| 414 | sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb |
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| 415 | |
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| 416 | // ITLB and DTLB invalidation |
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| 417 | sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index |
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| 418 | sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter |
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| 419 | |
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| 420 | // communication between DCACHE FSM and ICACHE FSM |
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| 421 | sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor) |
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| 422 | sc_signal<int> r_dcache_xtn_opcode; // xtn request type |
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| 423 | |
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| 424 | // dcache directory extension |
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| 425 | bool *r_dcache_in_tlb; // copy exist in dtlb or itlb |
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| 426 | bool *r_dcache_contains_ptd; // cache line contains a PTD |
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| 427 | |
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| 428 | // Physical address extension for data access |
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| 429 | sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32) |
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| 430 | |
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| 431 | /////////////////////////////////// |
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| 432 | // VCI_CMD FSM REGISTERS |
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| 433 | /////////////////////////////////// |
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| 434 | sc_signal<int> r_vci_cmd_fsm; |
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| 435 | sc_signal<size_t> r_vci_cmd_min; // used for write bursts |
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| 436 | sc_signal<size_t> r_vci_cmd_max; // used for write bursts |
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| 437 | sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts |
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| 438 | sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss |
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| 439 | |
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| 440 | /////////////////////////////////// |
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| 441 | // VCI_RSP FSM REGISTERS |
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| 442 | /////////////////////////////////// |
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| 443 | sc_signal<int> r_vci_rsp_fsm; |
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| 444 | sc_signal<size_t> r_vci_rsp_cpt; |
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| 445 | sc_signal<bool> r_vci_rsp_ins_error; |
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| 446 | sc_signal<bool> r_vci_rsp_data_error; |
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| 447 | GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM |
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| 448 | GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM |
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| 449 | |
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| 450 | ////////////////////////////////////////////////////////////////// |
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| 451 | // processor, write buffer, caches , TLBs |
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| 452 | ////////////////////////////////////////////////////////////////// |
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| 453 | |
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| 454 | iss_t r_iss; |
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| 455 | MultiWriteBuffer<paddr_t> r_wbuf; |
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| 456 | GenericCache<paddr_t> r_icache; |
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| 457 | GenericCache<paddr_t> r_dcache; |
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| 458 | GenericTlb<paddr_t> r_itlb; |
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| 459 | GenericTlb<paddr_t> r_dtlb; |
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| 460 | |
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| 461 | ////////////////////////////////////////////////////////////////// |
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| 462 | // llsc registration buffer |
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| 463 | ////////////////////////////////////////////////////////////////// |
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| 464 | |
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| 465 | sc_signal<paddr_t> r_dcache_llsc_paddr; |
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| 466 | sc_signal<uint32_t> r_dcache_llsc_key; |
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| 467 | sc_signal<uint32_t> r_dcache_llsc_count; |
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| 468 | sc_signal<bool> r_dcache_llsc_valid; |
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| 469 | |
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| 470 | //////////////////////////////// |
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| 471 | // Activity counters |
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| 472 | //////////////////////////////// |
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| 473 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
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| 474 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
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| 475 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
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| 476 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
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| 477 | |
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| 478 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
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| 479 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
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| 480 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
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| 481 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
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| 482 | |
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| 483 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
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| 484 | uint32_t m_cpt_total_cycles; // total number of cycles |
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| 485 | |
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| 486 | // Cache activity counters |
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| 487 | uint32_t m_cpt_data_read; // total number of read data |
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| 488 | uint32_t m_cpt_data_write; // total number of write data |
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| 489 | uint32_t m_cpt_data_miss; // number of read miss |
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| 490 | uint32_t m_cpt_ins_miss; // number of instruction miss |
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| 491 | uint32_t m_cpt_unc_read; // number of read uncached |
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| 492 | uint32_t m_cpt_write_cached; // number of cached write |
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| 493 | uint32_t m_cpt_ins_read; // number of instruction read |
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| 494 | uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss |
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| 495 | |
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| 496 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
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| 497 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
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| 498 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
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| 499 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
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| 500 | |
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| 501 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
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| 502 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
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| 503 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
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| 504 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
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| 505 | uint32_t m_cpt_icache_unc_transaction; |
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| 506 | |
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| 507 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
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| 508 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
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| 509 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
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| 510 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
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| 511 | uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions |
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| 512 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
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| 513 | |
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| 514 | // TLB activity counters |
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| 515 | uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read |
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| 516 | uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss |
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| 517 | uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update |
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| 518 | uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line |
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| 519 | uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache |
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| 520 | |
---|
| 521 | uint32_t m_cpt_data_tlb_read; // number of data tlb read |
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| 522 | uint32_t m_cpt_data_tlb_miss; // number of data tlb miss |
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| 523 | uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update |
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| 524 | uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty |
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| 525 | uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache |
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| 526 | uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line |
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| 527 | uint32_t m_cpt_tlb_occup_dcache; |
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| 528 | |
---|
| 529 | uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss |
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| 530 | uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss |
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| 531 | uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc |
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| 532 | uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc |
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| 533 | uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty |
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| 534 | uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache |
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| 535 | uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache |
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| 536 | |
---|
| 537 | uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions |
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| 538 | uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions |
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| 539 | uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions |
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| 540 | uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions |
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| 541 | uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions |
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| 542 | uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions |
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| 543 | uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions |
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| 544 | uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions |
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| 545 | |
---|
| 546 | uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions |
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| 547 | uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions |
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| 548 | uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions |
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| 549 | uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions |
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| 550 | uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions |
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| 551 | uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions |
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| 552 | uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions |
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| 553 | uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions |
---|
| 554 | |
---|
| 555 | // coherence activity counters |
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| 556 | uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands |
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| 557 | uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands |
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| 558 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands |
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| 559 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands |
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| 560 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands |
---|
| 561 | |
---|
| 562 | uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets |
---|
| 563 | uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets |
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| 564 | uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets |
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| 565 | uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets |
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| 566 | |
---|
| 567 | uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets |
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| 568 | uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets |
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| 569 | |
---|
| 570 | uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions |
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| 571 | uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions |
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| 572 | uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions |
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| 573 | uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions |
---|
| 574 | |
---|
| 575 | uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate |
---|
| 576 | uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate |
---|
| 577 | |
---|
| 578 | uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate |
---|
| 579 | uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate |
---|
| 580 | |
---|
| 581 | // FSM activity counters |
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| 582 | uint32_t m_cpt_fsm_icache[64]; |
---|
| 583 | uint32_t m_cpt_fsm_dcache[64]; |
---|
| 584 | uint32_t m_cpt_fsm_cmd[64]; |
---|
| 585 | uint32_t m_cpt_fsm_rsp[64]; |
---|
| 586 | |
---|
| 587 | uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen |
---|
| 588 | bool m_monitor_ok; // used to debug cache output |
---|
| 589 | uint32_t m_monitor_base; |
---|
| 590 | uint32_t m_monitor_length; |
---|
| 591 | |
---|
| 592 | // Members for ideal coherence updates |
---|
| 593 | std::list<VcacheUpdate> m_dpending_updates; |
---|
| 594 | std::list<VcacheUpdate> m_ipending_updates; |
---|
| 595 | |
---|
| 596 | protected: |
---|
| 597 | SC_HAS_PROCESS(VciCcVCacheWrapper); |
---|
| 598 | |
---|
| 599 | public: |
---|
| 600 | VciCcVCacheWrapper( |
---|
| 601 | sc_module_name name, |
---|
| 602 | const int proc_id, |
---|
| 603 | const soclib::common::MappingTable &mtd, |
---|
| 604 | const soclib::common::IntTab &srcid, |
---|
| 605 | const size_t cc_global_id, |
---|
| 606 | const size_t itlb_ways, |
---|
| 607 | const size_t itlb_sets, |
---|
| 608 | const size_t dtlb_ways, |
---|
| 609 | const size_t dtlb_sets, |
---|
| 610 | const size_t icache_ways, |
---|
| 611 | const size_t icache_sets, |
---|
| 612 | const size_t icache_words, |
---|
| 613 | const size_t dcache_ways, |
---|
| 614 | const size_t dcache_sets, |
---|
| 615 | const size_t dcache_words, |
---|
| 616 | const size_t wbuf_nlines, |
---|
| 617 | const size_t wbuf_nwords, |
---|
| 618 | const size_t x_width, |
---|
| 619 | const size_t y_width, |
---|
| 620 | const uint32_t max_frozen_cycles, |
---|
| 621 | const uint32_t debug_start_cycle, |
---|
| 622 | const bool debug_ok); |
---|
| 623 | |
---|
| 624 | ~VciCcVCacheWrapper(); |
---|
| 625 | |
---|
| 626 | void cache_direct_update(uint64_t addr, uint32_t value, uint32_t be, int32_t srcid); |
---|
| 627 | void print_cpi(); |
---|
| 628 | void print_stats(); |
---|
| 629 | void clear_stats(); |
---|
| 630 | void print_trace(size_t mode = 0); |
---|
| 631 | void cache_monitor(paddr_t addr); |
---|
| 632 | void start_monitor(paddr_t,paddr_t); |
---|
| 633 | void stop_monitor(); |
---|
| 634 | inline void iss_set_debug_mask(uint v) |
---|
| 635 | { |
---|
| 636 | r_iss.set_debug_mask(v); |
---|
| 637 | } |
---|
| 638 | |
---|
| 639 | ///////////////////////////////////////////////////////////// |
---|
| 640 | // Set the m_dcache_paddr_ext_reset attribute |
---|
| 641 | // |
---|
| 642 | // The r_dcache_paddr_ext register will be initialized after |
---|
| 643 | // reset with the m_dcache_paddr_ext_reset value |
---|
| 644 | ///////////////////////////////////////////////////////////// |
---|
| 645 | inline void set_dcache_paddr_ext_reset(uint32_t v) |
---|
| 646 | { |
---|
| 647 | m_dcache_paddr_ext_reset = v; |
---|
| 648 | } |
---|
| 649 | |
---|
| 650 | ///////////////////////////////////////////////////////////// |
---|
| 651 | // Set the m_icache_paddr_ext_reset attribute |
---|
| 652 | // |
---|
| 653 | // The r_icache_paddr_ext register will be initialized after |
---|
| 654 | // reset with the m_icache_paddr_ext_reset value |
---|
| 655 | ///////////////////////////////////////////////////////////// |
---|
| 656 | inline void set_icache_paddr_ext_reset(uint32_t v) |
---|
| 657 | { |
---|
| 658 | m_icache_paddr_ext_reset = v; |
---|
| 659 | } |
---|
| 660 | |
---|
| 661 | private: |
---|
| 662 | void transition(); |
---|
| 663 | void genMoore(); |
---|
| 664 | |
---|
| 665 | soclib_static_assert((int) iss_t::SC_ATOMIC == (int) vci_param::STORE_COND_ATOMIC); |
---|
| 666 | soclib_static_assert((int) iss_t::SC_NOT_ATOMIC == (int) vci_param::STORE_COND_NOT_ATOMIC); |
---|
| 667 | }; |
---|
| 668 | |
---|
| 669 | |
---|
| 670 | }} |
---|
| 671 | |
---|
| 672 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */ |
---|
| 673 | |
---|
| 674 | // Local Variables: |
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| 675 | // tab-width: 4 |
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| 676 | // c-basic-offset: 4 |
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| 677 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 678 | // indent-tabs-mode: nil |
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| 679 | // End: |
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| 680 | |
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| 681 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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