1 | /* -*- c++ -*- |
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2 | * File : vci_cc_vcache_wrapper.cpp |
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3 | * Copyright (c) UPMC, Lip6, SoC |
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4 | * Authors : Alain GREINER, Yang GAO |
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5 | * |
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6 | * SOCLIB_LGPL_HEADER_BEGIN |
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7 | * |
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8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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9 | * |
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10 | * SoCLib is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU Lesser General Public License as published |
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12 | * by the Free Software Foundation; version 2.1 of the License. |
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13 | * |
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14 | * SoCLib is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * Lesser General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU Lesser General Public |
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20 | * License along with SoCLib; if not, write to the Free Software |
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21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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22 | * 02110-1301 USA |
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23 | * |
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24 | * SOCLIB_LGPL_HEADER_END |
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25 | * |
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26 | * Maintainers: cesar.fuguet-tortolero@lip6.fr |
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27 | * alexandre.joannou@lip6.fr |
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28 | */ |
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29 | |
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30 | #include <cassert> |
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31 | #include <signal.h> |
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32 | |
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33 | #include "arithmetics.h" |
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34 | #include "../include/vci_cc_vcache_wrapper.h" |
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35 | |
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36 | #define DEBUG_DCACHE 1 |
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37 | #define DEBUG_ICACHE 1 |
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38 | #define DEBUG_CMD 0 |
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39 | |
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40 | namespace soclib { |
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41 | namespace caba { |
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42 | |
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43 | namespace { |
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44 | const char * icache_fsm_state_str[] = { |
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45 | "ICACHE_IDLE", |
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46 | |
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47 | "ICACHE_XTN_TLB_FLUSH", |
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48 | "ICACHE_XTN_CACHE_FLUSH", |
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49 | "ICACHE_XTN_CACHE_FLUSH_GO", |
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50 | "ICACHE_XTN_TLB_INVAL", |
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51 | "ICACHE_XTN_CACHE_INVAL_VA", |
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52 | "ICACHE_XTN_CACHE_INVAL_PA", |
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53 | "ICACHE_XTN_CACHE_INVAL_GO", |
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54 | |
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55 | "ICACHE_TLB_WAIT", |
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56 | |
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57 | "ICACHE_MISS_SELECT", |
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58 | "ICACHE_MISS_CLEAN", |
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59 | "ICACHE_MISS_WAIT", |
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60 | "ICACHE_MISS_DATA_UPDT", |
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61 | "ICACHE_MISS_DIR_UPDT", |
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62 | |
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63 | "ICACHE_UNC_WAIT", |
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64 | }; |
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65 | |
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66 | const char * dcache_fsm_state_str[] = { |
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67 | "DCACHE_IDLE", |
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68 | |
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69 | "DCACHE_TLB_MISS", |
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70 | "DCACHE_TLB_PTE1_GET", |
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71 | "DCACHE_TLB_PTE1_SELECT", |
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72 | "DCACHE_TLB_PTE1_UPDT", |
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73 | "DCACHE_TLB_PTE2_GET", |
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74 | "DCACHE_TLB_PTE2_SELECT", |
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75 | "DCACHE_TLB_PTE2_UPDT", |
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76 | "DCACHE_TLB_LR_UPDT", |
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77 | "DCACHE_TLB_LR_WAIT", |
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78 | "DCACHE_TLB_RETURN", |
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79 | |
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80 | "DCACHE_XTN_SWITCH", |
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81 | "DCACHE_XTN_SYNC", |
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82 | "DCACHE_XTN_IC_INVAL_VA", |
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83 | "DCACHE_XTN_IC_FLUSH", |
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84 | "DCACHE_XTN_IC_INVAL_PA", |
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85 | "DCACHE_XTN_IC_PADDR_EXT", |
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86 | "DCACHE_XTN_IT_INVAL", |
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87 | "DCACHE_XTN_DC_FLUSH", |
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88 | "DCACHE_XTN_DC_FLUSH_GO", |
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89 | "DCACHE_XTN_DC_INVAL_VA", |
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90 | "DCACHE_XTN_DC_INVAL_PA", |
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91 | "DCACHE_XTN_DC_INVAL_END", |
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92 | "DCACHE_XTN_DC_INVAL_GO", |
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93 | "DCACHE_XTN_DT_INVAL", |
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94 | |
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95 | "DCACHE_DIRTY_GET_PTE", |
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96 | "DCACHE_DIRTY_WAIT", |
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97 | |
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98 | "DCACHE_MISS_SELECT", |
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99 | "DCACHE_MISS_VICTIM_CHECK", |
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100 | "DCACHE_MISS_WAIT", |
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101 | "DCACHE_MISS_DATA_UPDT", |
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102 | "DCACHE_MISS_DIR_UPDT", |
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103 | |
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104 | "DCACHE_UNC_WAIT", |
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105 | "DCACHE_LL_WAIT", |
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106 | "DCACHE_SC_WAIT", |
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107 | |
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108 | "DCACHE_INVAL_TLB_SCAN", |
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109 | }; |
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110 | |
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111 | const char * cmd_fsm_state_str[] = { |
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112 | "CMD_IDLE", |
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113 | "CMD_INS_MISS", |
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114 | "CMD_INS_UNC", |
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115 | "CMD_DATA_MISS", |
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116 | "CMD_DATA_UNC_READ", |
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117 | "CMD_DATA_UNC_WRITE", |
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118 | "CMD_DATA_WRITE", |
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119 | "CMD_DATA_LL", |
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120 | "CMD_DATA_SC", |
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121 | "CMD_DATA_CAS", |
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122 | }; |
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123 | |
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124 | const char * vci_pktid_type_str[] = { |
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125 | "TYPE_DATA_UNC", |
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126 | "TYPE_READ_DATA_MISS", |
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127 | "TYPE_READ_INS_UNC", |
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128 | "TYPE_READ_INS_MISS", |
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129 | "TYPE_WRITE", |
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130 | "TYPE_CAS", |
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131 | "TYPE_LL", |
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132 | "TYPE_SC", |
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133 | }; |
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134 | |
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135 | const char * vci_cmd_type_str[] = { |
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136 | "NOP or STORE_COND", |
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137 | "READ", |
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138 | "WRITE", |
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139 | "LOCKED_READ" |
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140 | }; |
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141 | |
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142 | const char * rsp_fsm_state_str[] = { |
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143 | "RSP_IDLE", |
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144 | "RSP_INS_MISS", |
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145 | "RSP_INS_UNC", |
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146 | "RSP_DATA_MISS", |
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147 | "RSP_DATA_UNC", |
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148 | "RSP_DATA_LL", |
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149 | "RSP_DATA_WRITE", |
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150 | }; |
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151 | |
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152 | } |
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153 | |
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154 | #define tmpl(...) \ |
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155 | template<typename vci_param, \ |
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156 | size_t dspin_in_width, \ |
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157 | size_t dspin_out_width, \ |
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158 | typename iss_t> __VA_ARGS__ \ |
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159 | VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t> |
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160 | |
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161 | using namespace soclib::common; |
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162 | |
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163 | ///////////////////////////////// |
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164 | tmpl(/**/)::VciCcVCacheWrapper( |
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165 | sc_module_name name, |
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166 | const int proc_id, |
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167 | const MappingTable &mtd, |
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168 | const IntTab &srcid, |
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169 | const size_t cc_global_id, |
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170 | const size_t itlb_ways, |
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171 | const size_t itlb_sets, |
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172 | const size_t dtlb_ways, |
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173 | const size_t dtlb_sets, |
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174 | const size_t icache_ways, |
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175 | const size_t icache_sets, |
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176 | const size_t icache_words, |
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177 | const size_t dcache_ways, |
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178 | const size_t dcache_sets, |
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179 | const size_t dcache_words, |
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180 | const size_t wbuf_nlines, |
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181 | const size_t wbuf_nwords, |
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182 | const size_t x_width, |
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183 | const size_t y_width, |
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184 | const uint32_t max_frozen_cycles, |
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185 | const uint32_t debug_start_cycle, |
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186 | const bool debug_ok) |
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187 | : soclib::caba::BaseModule(name), |
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188 | |
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189 | p_clk("p_clk"), |
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190 | p_resetn("p_resetn"), |
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191 | p_vci("p_vci"), |
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192 | p_dspin_m2p("p_dspin_m2p"), |
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193 | p_dspin_p2m("p_dspin_p2m"), |
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194 | p_dspin_clack("p_dspin_clack"), |
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195 | |
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196 | m_cacheability_table( mtd.getCacheabilityTable()), |
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197 | m_srcid(mtd.indexForId(srcid)), |
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198 | m_cc_global_id(cc_global_id), |
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199 | m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2), |
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200 | m_itlb_ways(itlb_ways), |
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201 | m_itlb_sets(itlb_sets), |
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202 | m_dtlb_ways(dtlb_ways), |
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203 | m_dtlb_sets(dtlb_sets), |
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204 | m_icache_ways(icache_ways), |
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205 | m_icache_sets(icache_sets), |
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206 | m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)), |
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207 | m_icache_words(icache_words), |
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208 | m_dcache_ways(dcache_ways), |
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209 | m_dcache_sets(dcache_sets), |
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210 | m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)), |
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211 | m_dcache_words(dcache_words), |
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212 | m_x_width(x_width), |
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213 | m_y_width(y_width), |
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214 | m_proc_id(proc_id), |
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215 | m_max_frozen_cycles(max_frozen_cycles), |
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216 | m_paddr_nbits(vci_param::N), |
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217 | m_debug_start_cycle(debug_start_cycle), |
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218 | m_debug_ok(debug_ok), |
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219 | m_dcache_paddr_ext_reset(0), |
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220 | m_icache_paddr_ext_reset(0), |
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221 | |
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222 | r_mmu_ptpr("r_mmu_ptpr"), |
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223 | r_mmu_mode("r_mmu_mode"), |
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224 | r_mmu_word_lo("r_mmu_word_lo"), |
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225 | r_mmu_word_hi("r_mmu_word_hi"), |
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226 | r_mmu_ibvar("r_mmu_ibvar"), |
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227 | r_mmu_dbvar("r_mmu_dbvar"), |
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228 | r_mmu_ietr("r_mmu_ietr"), |
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229 | r_mmu_detr("r_mmu_detr"), |
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230 | |
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231 | r_icache_fsm("r_icache_fsm"), |
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232 | r_icache_fsm_save("r_icache_fsm_save"), |
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233 | r_icache_vci_paddr("r_icache_vci_paddr"), |
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234 | r_icache_vaddr_save("r_icache_vaddr_save"), |
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235 | |
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236 | r_icache_miss_way("r_icache_miss_way"), |
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237 | r_icache_miss_set("r_icache_miss_set"), |
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238 | r_icache_miss_word("r_icache_miss_word"), |
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239 | r_icache_miss_clack("r_icache_miss_clack"), |
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240 | |
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241 | r_icache_flush_count("r_icache_flush_count"), |
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242 | |
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243 | r_icache_miss_req("r_icache_miss_req"), |
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244 | r_icache_unc_req("r_icache_unc_req"), |
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245 | |
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246 | r_icache_tlb_miss_req("r_icache_tlb_read_req"), |
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247 | r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), |
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248 | |
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249 | r_dcache_fsm("r_dcache_fsm"), |
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250 | r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), |
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251 | |
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252 | r_dcache_wbuf_req("r_dcache_wbuf_req"), |
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253 | r_dcache_updt_req("r_dcache_updt_req"), |
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254 | r_dcache_save_vaddr("r_dcache_save_vaddr"), |
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255 | r_dcache_save_wdata("r_dcache_save_wdata"), |
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256 | r_dcache_save_be("r_dcache_save_be"), |
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257 | r_dcache_save_paddr("r_dcache_save_paddr"), |
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258 | r_dcache_save_cache_way("r_dcache_save_cache_way"), |
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259 | r_dcache_save_cache_set("r_dcache_save_cache_set"), |
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260 | r_dcache_save_cache_word("r_dcache_save_cache_word"), |
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261 | |
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262 | r_dcache_dirty_paddr("r_dcache_dirty_paddr"), |
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263 | r_dcache_dirty_way("r_dcache_dirty_way"), |
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264 | r_dcache_dirty_set("r_dcache_dirty_set"), |
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265 | |
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266 | r_dcache_vci_paddr("r_dcache_vci_paddr"), |
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267 | r_dcache_vci_wdata("r_dcache_vci_wdata"), |
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268 | r_dcache_vci_miss_req("r_dcache_vci_miss_req"), |
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269 | r_dcache_vci_unc_req("r_dcache_vci_unc_req"), |
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270 | r_dcache_vci_unc_be("r_dcache_vci_unc_be"), |
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271 | r_dcache_vci_unc_write("r_dcache_vci_unc_write"), |
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272 | r_dcache_vci_cas_req("r_dcache_vci_cas_req"), |
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273 | r_dcache_vci_cas_old("r_dcache_vci_cas_old"), |
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274 | r_dcache_vci_cas_new("r_dcache_vci_cas_new"), |
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275 | r_dcache_vci_ll_req("r_dcache_vci_ll_req"), |
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276 | r_dcache_vci_sc_req("r_dcache_vci_sc_req"), |
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277 | r_dcache_vci_sc_data("r_dcache_vci_sc_data"), |
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278 | |
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279 | r_dcache_xtn_way("r_dcache_xtn_way"), |
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280 | r_dcache_xtn_set("r_dcache_xtn_set"), |
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281 | |
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282 | r_dcache_miss_type("r_dcache_miss_type"), |
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283 | r_dcache_miss_word("r_dcache_miss_word"), |
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284 | r_dcache_miss_way("r_dcache_miss_way"), |
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285 | r_dcache_miss_set("r_dcache_miss_set"), |
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286 | r_dcache_miss_victim("r_dcache_miss_victim"), |
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287 | |
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288 | r_dcache_flush_count("r_dcache_flush_count"), |
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289 | |
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290 | r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"), |
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291 | |
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292 | r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"), |
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293 | r_dcache_tlb_ins("r_dcache_tlb_ins"), |
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294 | r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), |
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295 | r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), |
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296 | r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), |
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297 | r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), |
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298 | r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), |
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299 | r_dcache_tlb_way("r_dcache_tlb_way"), |
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300 | r_dcache_tlb_set("r_dcache_tlb_set"), |
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301 | |
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302 | r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"), |
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303 | r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"), |
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304 | |
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305 | r_dcache_xtn_req("r_dcache_xtn_req"), |
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306 | r_dcache_xtn_opcode("r_dcache_xtn_opcode"), |
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307 | |
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308 | r_vci_cmd_fsm("r_vci_cmd_fsm"), |
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309 | r_vci_cmd_min("r_vci_cmd_min"), |
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310 | r_vci_cmd_max("r_vci_cmd_max"), |
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311 | r_vci_cmd_cpt("r_vci_cmd_cpt"), |
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312 | r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"), |
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313 | |
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314 | r_vci_rsp_fsm("r_vci_rsp_fsm"), |
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315 | r_vci_rsp_cpt("r_vci_rsp_cpt"), |
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316 | r_vci_rsp_ins_error("r_vci_rsp_ins_error"), |
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317 | r_vci_rsp_data_error("r_vci_rsp_data_error"), |
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318 | r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth |
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319 | r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth |
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320 | |
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321 | r_iss(this->name(), proc_id), |
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322 | r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ), |
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323 | r_icache("icache", icache_ways, icache_sets, icache_words), |
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324 | r_dcache("dcache", dcache_ways, dcache_sets, dcache_words), |
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325 | r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N), |
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326 | r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N), |
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327 | |
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328 | m_dpending_updates(), |
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329 | m_ipending_updates() |
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330 | { |
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331 | std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl; |
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332 | |
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333 | assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and |
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334 | "Need more PLEN bits."); |
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335 | |
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336 | assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and |
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337 | "Need more TRDID bits."); |
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338 | |
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339 | assert((icache_words == dcache_words) and |
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340 | "icache_words and dcache_words parameters must be equal"); |
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341 | |
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342 | assert((itlb_sets == dtlb_sets) and |
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343 | "itlb_sets and dtlb_sets parameters must be etqual"); |
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344 | |
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345 | assert((itlb_ways == dtlb_ways) and |
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346 | "itlb_ways and dtlb_ways parameters must be etqual"); |
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347 | |
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348 | r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | |
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349 | (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | |
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350 | (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | |
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351 | (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | |
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352 | (uint32_log2(m_icache_words << 2)); |
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353 | |
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354 | r_mmu_release = (uint32_t) (1 << 16) | 0x1; |
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355 | |
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356 | r_dcache_in_tlb = new bool[dcache_ways * dcache_sets]; |
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357 | r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets]; |
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358 | |
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359 | SC_METHOD(transition); |
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360 | dont_initialize(); |
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361 | sensitive << p_clk.pos(); |
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362 | |
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363 | SC_METHOD(genMoore); |
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364 | dont_initialize(); |
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365 | sensitive << p_clk.neg(); |
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366 | |
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367 | typename iss_t::CacheInfo cache_info; |
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368 | cache_info.has_mmu = true; |
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369 | cache_info.icache_line_size = icache_words * sizeof(uint32_t); |
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370 | cache_info.icache_assoc = icache_ways; |
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371 | cache_info.icache_n_lines = icache_sets; |
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372 | cache_info.dcache_line_size = dcache_words * sizeof(uint32_t); |
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373 | cache_info.dcache_assoc = dcache_ways; |
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374 | cache_info.dcache_n_lines = dcache_sets; |
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375 | r_iss.setCacheInfo(cache_info); |
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376 | } |
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377 | |
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378 | ///////////////////////////////////// |
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379 | tmpl(/**/)::~VciCcVCacheWrapper() |
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380 | ///////////////////////////////////// |
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381 | { |
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382 | delete [] r_dcache_in_tlb; |
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383 | delete [] r_dcache_contains_ptd; |
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384 | } |
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385 | |
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386 | |
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387 | ////////////////////////////////////////////////////////////////////////////////////////// |
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388 | tmpl(void)::cache_direct_update(uint64_t addr, uint32_t value, uint32_t be, int32_t srcid) |
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389 | ////////////////////////////////////////////////////////////////////////////////////////// |
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390 | { |
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391 | |
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392 | bool cache_hit; |
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393 | size_t cache_way = 0; |
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394 | size_t cache_set = 0; |
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395 | size_t cache_word = 0; |
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396 | uint32_t cache_rdata = 0; |
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397 | |
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398 | if (srcid != m_srcid) |
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399 | { |
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400 | // We ignore the update if it was a consequence of a write by the same L1 cache |
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401 | paddr_t mask = ~((m_dcache_words << 2) - 1); |
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402 | |
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403 | // Test if hit in dcache |
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404 | cache_hit = r_dcache.read_neutral(addr, |
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405 | &cache_rdata, |
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406 | &cache_way, |
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407 | &cache_set, |
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408 | &cache_word); |
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409 | |
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410 | if (cache_hit) |
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411 | { |
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412 | r_dcache.write(cache_way, cache_set, cache_word, value, be); |
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413 | #if DEBUG_DCACHE |
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414 | if (m_debug_dcache_fsm) |
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415 | { |
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416 | std::cout << " <DCache " << name() << " Direct Update>" |
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417 | << " ADDR = " << std::hex << addr |
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418 | << " / VALUE = " << value |
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419 | << " / BE = " << be << std::endl; |
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420 | } |
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421 | #endif |
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422 | // DCACHE update can require ITLB / DTLB inval or flush |
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423 | if (r_dcache_contains_ptd[cache_way * m_dcache_sets + cache_set]) |
---|
424 | { |
---|
425 | #if DEBUG_DCACHE |
---|
426 | if (m_debug_dcache_fsm) |
---|
427 | { |
---|
428 | std::cout << " <Cache " << name() << " Reset TLBs>" << std::endl; |
---|
429 | } |
---|
430 | #endif |
---|
431 | r_itlb.reset(); |
---|
432 | r_dtlb.reset(); |
---|
433 | r_dcache_contains_ptd[cache_way * m_dcache_sets + cache_set] = false; |
---|
434 | r_dcache_in_tlb[cache_way * m_dcache_sets + cache_set] = false; |
---|
435 | } |
---|
436 | else if (r_dcache_in_tlb[cache_way * m_dcache_sets + cache_set]) |
---|
437 | { |
---|
438 | #if DEBUG_DCACHE |
---|
439 | if (m_debug_dcache_fsm) |
---|
440 | { |
---|
441 | std::cout << " <Cache " << name() << " Scan TLBs>" << std::endl; |
---|
442 | } |
---|
443 | #endif |
---|
444 | for (uint32_t set = 0; set < m_dcache_sets; set++) |
---|
445 | { |
---|
446 | size_t way; |
---|
447 | paddr_t line = addr / (m_dcache_words << 2); |
---|
448 | for (way = 0; way < m_itlb_ways; way++) |
---|
449 | { |
---|
450 | r_itlb.inval(line, way, set); |
---|
451 | } |
---|
452 | for (way = 0; way < m_dtlb_ways; way++) |
---|
453 | { |
---|
454 | r_dtlb.inval(line, way, set); |
---|
455 | } |
---|
456 | } |
---|
457 | r_dcache_in_tlb[cache_way * m_dcache_sets + cache_set] = false; |
---|
458 | } |
---|
459 | } |
---|
460 | else if ((r_dcache_fsm == DCACHE_MISS_SELECT || |
---|
461 | r_dcache_fsm == DCACHE_MISS_VICTIM_CHECK || |
---|
462 | r_dcache_fsm == DCACHE_MISS_WAIT || |
---|
463 | r_dcache_fsm == DCACHE_MISS_DATA_UPDT || |
---|
464 | r_dcache_fsm == DCACHE_MISS_DIR_UPDT) && |
---|
465 | (addr & mask) == (r_dcache_save_paddr.read() & mask)) |
---|
466 | { |
---|
467 | // Test if there is currently a miss on the line containing the address |
---|
468 | // In case we are in DCACHE_MISS_DIR_UPDT, the transition function has not yet |
---|
469 | // been evaluated, otherwise it would have resulted in a cache_hit |
---|
470 | #if DEBUG_DCACHE |
---|
471 | if (m_debug_dcache_fsm) |
---|
472 | { |
---|
473 | std::cout << " <DCache " << name() << " Direct Update>" |
---|
474 | << " Adding pending update for DCACHE: " << std::hex |
---|
475 | << " ADDR = " << addr |
---|
476 | << " / VALUE = " << value |
---|
477 | << " / BE = " << be |
---|
478 | << " / SAVE_ADDR = " << r_dcache_save_paddr.read() |
---|
479 | << std::dec << std::endl; |
---|
480 | } |
---|
481 | #endif |
---|
482 | VcacheUpdate up(addr, value, be); |
---|
483 | m_dpending_updates.push_back(up); |
---|
484 | } |
---|
485 | |
---|
486 | // Test if hit in icache |
---|
487 | cache_hit = r_icache.read_neutral(addr, |
---|
488 | &cache_rdata, |
---|
489 | &cache_way, |
---|
490 | &cache_set, |
---|
491 | &cache_word); |
---|
492 | |
---|
493 | if (cache_hit) |
---|
494 | { |
---|
495 | r_icache.write(cache_way, cache_set, cache_word, value, be); |
---|
496 | #if DEBUG_ICACHE |
---|
497 | if (m_debug_dcache_fsm) |
---|
498 | { |
---|
499 | std::cout << " <ICache " << name() << " Direct Update>" |
---|
500 | << " ADDR = " << std::hex << addr |
---|
501 | << " / VALUE = " << value |
---|
502 | << " / BE = " << be << std::endl; |
---|
503 | } |
---|
504 | #endif |
---|
505 | } |
---|
506 | else if ((r_icache_fsm == ICACHE_MISS_SELECT || |
---|
507 | r_icache_fsm == ICACHE_MISS_WAIT || |
---|
508 | r_icache_fsm == ICACHE_MISS_DATA_UPDT || |
---|
509 | r_icache_fsm == ICACHE_MISS_DIR_UPDT) && |
---|
510 | (addr & mask) == (r_icache_vci_paddr.read() & mask)) |
---|
511 | { |
---|
512 | #if DEBUG_ICACHE |
---|
513 | if (m_debug_icache_fsm) |
---|
514 | { |
---|
515 | std::cout << " <ICache " << name() << " Direct Update>" |
---|
516 | << " Adding pending update for ICACHE: " << std::hex |
---|
517 | << " ADDR = " << addr |
---|
518 | << " / VALUE = " << value |
---|
519 | << " / BE = " << be << std::endl; |
---|
520 | } |
---|
521 | #endif |
---|
522 | // Test if there is currently a miss on the line containing the address |
---|
523 | // In case we are in ICACHE_MISS_DIR_UPDT, the transition function has not yet |
---|
524 | // been evaluated, otherwise it would have resulted in a cache_hit |
---|
525 | VcacheUpdate up(addr, value, be); |
---|
526 | m_ipending_updates.push_back(up); |
---|
527 | } |
---|
528 | } |
---|
529 | } |
---|
530 | |
---|
531 | |
---|
532 | //////////////////////// |
---|
533 | tmpl(void)::print_cpi() |
---|
534 | //////////////////////// |
---|
535 | { |
---|
536 | std::cout << name() << " CPI = " |
---|
537 | << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl; |
---|
538 | } |
---|
539 | |
---|
540 | //////////////////////////////////// |
---|
541 | tmpl(void)::print_trace(size_t mode) |
---|
542 | //////////////////////////////////// |
---|
543 | { |
---|
544 | // b0 : write buffer trace |
---|
545 | // b1 : dump processor registers |
---|
546 | // b2 : dcache trace |
---|
547 | // b3 : icache trace |
---|
548 | // b4 : dtlb trace |
---|
549 | // b5 : itlb trace |
---|
550 | // b6 : SR (ISS register 32) |
---|
551 | |
---|
552 | std::cout << std::dec << "PROC " << name() << std::endl; |
---|
553 | |
---|
554 | std::cout << " " << m_ireq << std::endl; |
---|
555 | std::cout << " " << m_irsp << std::endl; |
---|
556 | std::cout << " " << m_dreq << std::endl; |
---|
557 | std::cout << " " << m_drsp << std::endl; |
---|
558 | |
---|
559 | std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] |
---|
560 | << " | " << dcache_fsm_state_str[r_dcache_fsm.read()] |
---|
561 | << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()] |
---|
562 | << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] |
---|
563 | << " | MMU = " << r_mmu_mode.read(); |
---|
564 | |
---|
565 | if (r_dcache_updt_req.read()) std::cout << " | P1_UPDT"; |
---|
566 | if (r_dcache_wbuf_req.read()) std::cout << " | P1_WBUF"; |
---|
567 | std::cout << std::endl; |
---|
568 | |
---|
569 | if (mode & 0x01) { |
---|
570 | if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl; |
---|
571 | if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl; |
---|
572 | if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl; |
---|
573 | if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl; |
---|
574 | |
---|
575 | r_wbuf.printTrace((mode >> 1) & 1); |
---|
576 | } |
---|
577 | if (mode & 0x02) { |
---|
578 | r_iss.dump(); |
---|
579 | } |
---|
580 | if (mode & 0x04) { |
---|
581 | std::cout << " Data Cache" << std::endl; |
---|
582 | r_dcache.printTrace(); |
---|
583 | } |
---|
584 | if (mode & 0x08) { |
---|
585 | std::cout << " Instruction Cache" << std::endl; |
---|
586 | r_icache.printTrace(); |
---|
587 | } |
---|
588 | if (mode & 0x10) { |
---|
589 | std::cout << " Data TLB" << std::endl; |
---|
590 | r_dtlb.printTrace(); |
---|
591 | } |
---|
592 | if (mode & 0x20) { |
---|
593 | std::cout << " Instruction TLB" << std::endl; |
---|
594 | r_itlb.printTrace(); |
---|
595 | } |
---|
596 | if (mode & 0x40) { |
---|
597 | uint32_t status = r_iss.debugGetRegisterValue(32); |
---|
598 | std::cout << name(); |
---|
599 | if (status != m_previous_status ) std::cout << " NEW "; |
---|
600 | std::cout << " status = " << std::hex << status << " " << std::endl; |
---|
601 | m_previous_status = status; |
---|
602 | } |
---|
603 | } |
---|
604 | |
---|
605 | ////////////////////////////////////////// |
---|
606 | tmpl(void)::cache_monitor(paddr_t addr) |
---|
607 | ////////////////////////////////////////// |
---|
608 | { |
---|
609 | bool cache_hit; |
---|
610 | size_t cache_way = 0; |
---|
611 | size_t cache_set = 0; |
---|
612 | size_t cache_word = 0; |
---|
613 | uint32_t cache_rdata = 0; |
---|
614 | |
---|
615 | cache_hit = r_dcache.read_neutral(addr, |
---|
616 | &cache_rdata, |
---|
617 | &cache_way, |
---|
618 | &cache_set, |
---|
619 | &cache_word); |
---|
620 | |
---|
621 | if (cache_hit != m_debug_previous_d_hit) { |
---|
622 | std::cout << "Monitor PROC " << name() |
---|
623 | << " DCACHE at cycle " << std::dec << m_cpt_total_cycles |
---|
624 | << " / HIT = " << cache_hit |
---|
625 | << " / PADDR = " << std::hex << addr |
---|
626 | << " / DATA = " << cache_rdata |
---|
627 | << " / WAY = " << cache_way << std::endl; |
---|
628 | m_debug_previous_d_hit = cache_hit; |
---|
629 | } |
---|
630 | |
---|
631 | cache_hit = r_icache.read_neutral(addr, |
---|
632 | &cache_rdata, |
---|
633 | &cache_way, |
---|
634 | &cache_set, |
---|
635 | &cache_word); |
---|
636 | |
---|
637 | if (cache_hit != m_debug_previous_i_hit) { |
---|
638 | std::cout << "Monitor PROC " << name() |
---|
639 | << " ICACHE at cycle " << std::dec << m_cpt_total_cycles |
---|
640 | << " / HIT = " << cache_hit |
---|
641 | << " / PADDR = " << std::hex << addr |
---|
642 | << " / DATA = " << cache_rdata |
---|
643 | << " / WAY = " << cache_way << std::endl; |
---|
644 | m_debug_previous_i_hit = cache_hit; |
---|
645 | } |
---|
646 | } |
---|
647 | |
---|
648 | |
---|
649 | ///////////////////////// |
---|
650 | tmpl(void)::transition() |
---|
651 | ///////////////////////// |
---|
652 | { |
---|
653 | if (not p_resetn.read()) { |
---|
654 | r_iss.reset(); |
---|
655 | r_wbuf.reset(); |
---|
656 | r_icache.reset(); |
---|
657 | r_dcache.reset(); |
---|
658 | r_itlb.reset(); |
---|
659 | r_dtlb.reset(); |
---|
660 | |
---|
661 | r_dcache_fsm = DCACHE_IDLE; |
---|
662 | r_icache_fsm = ICACHE_IDLE; |
---|
663 | r_vci_cmd_fsm = CMD_IDLE; |
---|
664 | r_vci_rsp_fsm = RSP_IDLE; |
---|
665 | |
---|
666 | // reset data physical address extension |
---|
667 | r_dcache_paddr_ext = m_dcache_paddr_ext_reset; |
---|
668 | |
---|
669 | // reset inst physical address extension |
---|
670 | r_icache_paddr_ext = m_icache_paddr_ext_reset; |
---|
671 | |
---|
672 | // reset dcache directory extension |
---|
673 | for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++) { |
---|
674 | r_dcache_in_tlb[i] = false; |
---|
675 | r_dcache_contains_ptd[i] = false; |
---|
676 | } |
---|
677 | |
---|
678 | // Response FIFOs and cleanup buffer |
---|
679 | r_vci_rsp_fifo_icache.init(); |
---|
680 | r_vci_rsp_fifo_dcache.init(); |
---|
681 | |
---|
682 | // ICACHE & DCACHE activated |
---|
683 | // ITLB & DTLB desactivated |
---|
684 | r_mmu_mode = 0x3; |
---|
685 | |
---|
686 | // No request from ICACHE FSM to CMD FSM |
---|
687 | r_icache_miss_req = false; |
---|
688 | r_icache_unc_req = false; |
---|
689 | |
---|
690 | // No request from ICACHE_FSM to DCACHE FSM |
---|
691 | r_icache_tlb_miss_req = false; |
---|
692 | |
---|
693 | // No pending write in pipeline |
---|
694 | r_dcache_wbuf_req = false; |
---|
695 | r_dcache_updt_req = false; |
---|
696 | |
---|
697 | // No request from DCACHE_FSM to CMD_FSM |
---|
698 | r_dcache_vci_miss_req = false; |
---|
699 | r_dcache_vci_unc_req = false; |
---|
700 | r_dcache_vci_cas_req = false; |
---|
701 | r_dcache_vci_ll_req = false; |
---|
702 | r_dcache_vci_sc_req = false; |
---|
703 | |
---|
704 | r_dcache_miss_type = 0; |
---|
705 | r_dcache_miss_word = 0; |
---|
706 | r_dcache_miss_way = 0; |
---|
707 | r_dcache_miss_set = 0; |
---|
708 | r_dcache_miss_victim = 0; |
---|
709 | |
---|
710 | // No processor XTN request pending |
---|
711 | r_dcache_xtn_req = false; |
---|
712 | |
---|
713 | // No signalisation of errors |
---|
714 | r_vci_rsp_ins_error = false; |
---|
715 | r_vci_rsp_data_error = false; |
---|
716 | |
---|
717 | // Debug variables |
---|
718 | m_debug_previous_i_hit = false; |
---|
719 | m_debug_previous_d_hit = false; |
---|
720 | m_debug_icache_fsm = false; |
---|
721 | m_debug_dcache_fsm = false; |
---|
722 | m_debug_cmd_fsm = false; |
---|
723 | |
---|
724 | // activity counters |
---|
725 | m_cpt_dcache_data_read = 0; |
---|
726 | m_cpt_dcache_data_write = 0; |
---|
727 | m_cpt_dcache_dir_read = 0; |
---|
728 | m_cpt_dcache_dir_write = 0; |
---|
729 | m_cpt_icache_data_read = 0; |
---|
730 | m_cpt_icache_data_write = 0; |
---|
731 | m_cpt_icache_dir_read = 0; |
---|
732 | m_cpt_icache_dir_write = 0; |
---|
733 | |
---|
734 | m_cpt_frz_cycles = 0; |
---|
735 | m_cpt_total_cycles = 0; |
---|
736 | m_cpt_stop_simulation = 0; |
---|
737 | |
---|
738 | m_cpt_data_miss = 0; |
---|
739 | m_cpt_ins_miss = 0; |
---|
740 | m_cpt_unc_read = 0; |
---|
741 | m_cpt_write_cached = 0; |
---|
742 | m_cpt_ins_read = 0; |
---|
743 | |
---|
744 | m_cost_write_frz = 0; |
---|
745 | m_cost_data_miss_frz = 0; |
---|
746 | m_cost_unc_read_frz = 0; |
---|
747 | m_cost_ins_miss_frz = 0; |
---|
748 | |
---|
749 | m_cpt_imiss_transaction = 0; |
---|
750 | m_cpt_dmiss_transaction = 0; |
---|
751 | m_cpt_unc_transaction = 0; |
---|
752 | m_cpt_write_transaction = 0; |
---|
753 | m_cpt_icache_unc_transaction = 0; |
---|
754 | |
---|
755 | m_cost_imiss_transaction = 0; |
---|
756 | m_cost_dmiss_transaction = 0; |
---|
757 | m_cost_unc_transaction = 0; |
---|
758 | m_cost_write_transaction = 0; |
---|
759 | m_cost_icache_unc_transaction = 0; |
---|
760 | m_length_write_transaction = 0; |
---|
761 | |
---|
762 | m_cpt_ins_tlb_read = 0; |
---|
763 | m_cpt_ins_tlb_miss = 0; |
---|
764 | m_cpt_ins_tlb_update_acc = 0; |
---|
765 | |
---|
766 | m_cpt_data_tlb_read = 0; |
---|
767 | m_cpt_data_tlb_miss = 0; |
---|
768 | m_cpt_data_tlb_update_acc = 0; |
---|
769 | m_cpt_data_tlb_update_dirty = 0; |
---|
770 | m_cpt_ins_tlb_hit_dcache = 0; |
---|
771 | m_cpt_data_tlb_hit_dcache = 0; |
---|
772 | m_cpt_ins_tlb_occup_cache = 0; |
---|
773 | m_cpt_data_tlb_occup_cache = 0; |
---|
774 | |
---|
775 | m_cost_ins_tlb_miss_frz = 0; |
---|
776 | m_cost_data_tlb_miss_frz = 0; |
---|
777 | m_cost_ins_tlb_update_acc_frz = 0; |
---|
778 | m_cost_data_tlb_update_acc_frz = 0; |
---|
779 | m_cost_data_tlb_update_dirty_frz = 0; |
---|
780 | m_cost_ins_tlb_occup_cache_frz = 0; |
---|
781 | m_cost_data_tlb_occup_cache_frz = 0; |
---|
782 | |
---|
783 | m_cpt_ins_tlb_inval = 0; |
---|
784 | m_cpt_data_tlb_inval = 0; |
---|
785 | m_cost_ins_tlb_inval_frz = 0; |
---|
786 | m_cost_data_tlb_inval_frz = 0; |
---|
787 | |
---|
788 | m_cpt_cc_broadcast = 0; |
---|
789 | |
---|
790 | m_cost_updt_data_frz = 0; |
---|
791 | m_cost_inval_ins_frz = 0; |
---|
792 | m_cost_inval_data_frz = 0; |
---|
793 | m_cost_broadcast_frz = 0; |
---|
794 | |
---|
795 | m_cpt_itlbmiss_transaction = 0; |
---|
796 | m_cpt_itlb_ll_transaction = 0; |
---|
797 | m_cpt_itlb_sc_transaction = 0; |
---|
798 | m_cpt_dtlbmiss_transaction = 0; |
---|
799 | m_cpt_dtlb_ll_transaction = 0; |
---|
800 | m_cpt_dtlb_sc_transaction = 0; |
---|
801 | m_cpt_dtlb_ll_dirty_transaction = 0; |
---|
802 | m_cpt_dtlb_sc_dirty_transaction = 0; |
---|
803 | |
---|
804 | m_cost_itlbmiss_transaction = 0; |
---|
805 | m_cost_itlb_ll_transaction = 0; |
---|
806 | m_cost_itlb_sc_transaction = 0; |
---|
807 | m_cost_dtlbmiss_transaction = 0; |
---|
808 | m_cost_dtlb_ll_transaction = 0; |
---|
809 | m_cost_dtlb_sc_transaction = 0; |
---|
810 | m_cost_dtlb_ll_dirty_transaction = 0; |
---|
811 | m_cost_dtlb_sc_dirty_transaction = 0; |
---|
812 | |
---|
813 | m_dpending_updates.clear(); |
---|
814 | m_ipending_updates.clear(); |
---|
815 | |
---|
816 | for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0; |
---|
817 | for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0; |
---|
818 | for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0; |
---|
819 | for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0; |
---|
820 | |
---|
821 | // init the llsc reservation buffer |
---|
822 | r_dcache_llsc_valid = false; |
---|
823 | m_monitor_ok = false; |
---|
824 | |
---|
825 | return; |
---|
826 | } |
---|
827 | |
---|
828 | // Response FIFOs default values |
---|
829 | bool vci_rsp_fifo_icache_get = false; |
---|
830 | bool vci_rsp_fifo_icache_put = false; |
---|
831 | uint32_t vci_rsp_fifo_icache_data = 0; |
---|
832 | |
---|
833 | bool vci_rsp_fifo_dcache_get = false; |
---|
834 | bool vci_rsp_fifo_dcache_put = false; |
---|
835 | uint32_t vci_rsp_fifo_dcache_data = 0; |
---|
836 | |
---|
837 | #ifdef INSTRUMENTATION |
---|
838 | m_cpt_fsm_dcache[r_dcache_fsm.read()]++; |
---|
839 | m_cpt_fsm_icache[r_icache_fsm.read()]++; |
---|
840 | m_cpt_fsm_cmd[r_vci_cmd_fsm.read()]++; |
---|
841 | m_cpt_fsm_rsp[r_vci_rsp_fsm.read()]++; |
---|
842 | m_cpt_fsm_tgt[r_tgt_fsm.read()]++; |
---|
843 | m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()]++; |
---|
844 | #endif |
---|
845 | |
---|
846 | m_cpt_total_cycles++; |
---|
847 | |
---|
848 | m_debug_icache_fsm = m_debug_icache_fsm || |
---|
849 | ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok); |
---|
850 | m_debug_dcache_fsm = m_debug_dcache_fsm || |
---|
851 | ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok); |
---|
852 | m_debug_cmd_fsm = m_debug_cmd_fsm || |
---|
853 | ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok); |
---|
854 | |
---|
855 | ///////////////////////////////////////////////////////////////////// |
---|
856 | // Get data and instruction requests from processor |
---|
857 | /////////////////////////////////////////////////////////////////////// |
---|
858 | |
---|
859 | r_iss.getRequests(m_ireq, m_dreq); |
---|
860 | |
---|
861 | //////////////////////////////////////////////////////////////////////////////////// |
---|
862 | // ICACHE_FSM |
---|
863 | // |
---|
864 | // 1/ Coherence operations |
---|
865 | // They are handled as interrupts generated by the CC_RECEIVE FSM. |
---|
866 | // - There is a coherence request when r_tgt_icache_req is set. |
---|
867 | // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states. |
---|
868 | // - There is a cleanup ack request when r_cleanup_icache_req is set. |
---|
869 | // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, |
---|
870 | // MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states. |
---|
871 | // - For both types of requests, actions associated to the pre-empted state |
---|
872 | // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK |
---|
873 | // or CC_CLACK) to execute the requested coherence operation, and returns |
---|
874 | // to the pre-empted state. |
---|
875 | // |
---|
876 | // 2/ Processor requests |
---|
877 | // They are taken in IDLE state only. In case of cache miss, or uncacheable |
---|
878 | // instruction, the ICACHE FSM request a VCI transaction to CMD FSM, |
---|
879 | // using the r_icache_miss_req or r_icache_unc_req flip-flops. These |
---|
880 | // flip-flops are reset when the transaction starts. |
---|
881 | // - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state |
---|
882 | // to select a slot and possibly request a cleanup transaction to the CC_SEND FSM. |
---|
883 | // It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM, |
---|
884 | // The availability of the missing cache line is signaled by the response fifo, |
---|
885 | // and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT |
---|
886 | // and ICACHE_MISS_DIR_UPDT states. |
---|
887 | // - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT |
---|
888 | // to wait the response from the RSP FSM, through the response fifo. |
---|
889 | // The missing instruction is directly returned to processor in this state. |
---|
890 | // |
---|
891 | // 3/ TLB miss |
---|
892 | // In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the |
---|
893 | // ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr |
---|
894 | // register, and goes to the ICACHE_TLB_WAIT state. |
---|
895 | // The tlb update is entirely done by the DCACHE FSM (who becomes the owner |
---|
896 | // of ITLB until the update is completed, and reset r_icache_tlb_miss_req |
---|
897 | // to signal the completion. |
---|
898 | // |
---|
899 | // 4/ XTN requests |
---|
900 | // The DCACHE FSM signals XTN processor requests to ICACHE_FSM |
---|
901 | // using the r_dcache_xtn_req flip-flop. |
---|
902 | // The request opcode and the address to be invalidated are transmitted |
---|
903 | // in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively. |
---|
904 | // The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation |
---|
905 | // is completed. |
---|
906 | // |
---|
907 | // 5/ Error Handling |
---|
908 | // The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error |
---|
909 | // in a cache miss or uncacheable read VCI transaction. Nothing is written |
---|
910 | // in the response fifo. This flip-flop is reset by the ICACHE-FSM. |
---|
911 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
912 | |
---|
913 | // default value for m_irsp |
---|
914 | m_irsp.valid = false; |
---|
915 | m_irsp.error = false; |
---|
916 | m_irsp.instruction = 0; |
---|
917 | |
---|
918 | switch (r_icache_fsm.read()) { |
---|
919 | ///////////////// |
---|
920 | case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests, |
---|
921 | // and coherence requests with a fixed priority: |
---|
922 | // 1/ Coherence requests => ICACHE_CC_CHECK |
---|
923 | // 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_* |
---|
924 | // 3/ tlb miss => ICACHE_TLB_WAIT |
---|
925 | // 4/ cacheable read miss => ICACHE_MISS_SELECT |
---|
926 | // 5/ uncacheable read miss => ICACHE_UNC_REQ |
---|
927 | { |
---|
928 | // XTN requests sent by DCACHE FSM |
---|
929 | // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), |
---|
930 | // because they require access to icache or itlb, that are already accessed |
---|
931 | if (r_dcache_xtn_req.read()) { |
---|
932 | if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR ) { |
---|
933 | r_icache_fsm = ICACHE_XTN_TLB_FLUSH; |
---|
934 | } |
---|
935 | else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH) { |
---|
936 | r_icache_flush_count = 0; |
---|
937 | r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; |
---|
938 | } |
---|
939 | else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL) { |
---|
940 | r_icache_fsm = ICACHE_XTN_TLB_INVAL; |
---|
941 | } |
---|
942 | else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL) { |
---|
943 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; |
---|
944 | } |
---|
945 | else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV) { |
---|
946 | if (sizeof(paddr_t) <= 32) { |
---|
947 | assert(r_mmu_word_hi.read() == 0 && |
---|
948 | "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); |
---|
949 | r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read(); |
---|
950 | } |
---|
951 | else { |
---|
952 | r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 | |
---|
953 | (paddr_t) r_mmu_word_lo.read(); |
---|
954 | } |
---|
955 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
956 | } |
---|
957 | else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT) { |
---|
958 | r_icache_paddr_ext = r_dcache_save_wdata.read(); |
---|
959 | r_dcache_xtn_req = false; |
---|
960 | } |
---|
961 | else { |
---|
962 | assert(false and |
---|
963 | "undefined XTN request received by ICACHE FSM"); |
---|
964 | } |
---|
965 | break; |
---|
966 | } // end if xtn_req |
---|
967 | |
---|
968 | // processor request |
---|
969 | if (m_ireq.valid) { |
---|
970 | bool cacheable; |
---|
971 | paddr_t paddr; |
---|
972 | bool tlb_hit = false; |
---|
973 | pte_info_t tlb_flags; |
---|
974 | size_t tlb_way; |
---|
975 | size_t tlb_set; |
---|
976 | paddr_t tlb_nline; |
---|
977 | uint32_t cache_inst = 0; |
---|
978 | size_t cache_way; |
---|
979 | size_t cache_set; |
---|
980 | size_t cache_word; |
---|
981 | int cache_state = CACHE_SLOT_STATE_INVALID; |
---|
982 | |
---|
983 | // We register processor request |
---|
984 | r_icache_vaddr_save = m_ireq.addr; |
---|
985 | paddr = (paddr_t) m_ireq.addr; |
---|
986 | |
---|
987 | // sytematic itlb access (if activated) |
---|
988 | if (r_mmu_mode.read() & INS_TLB_MASK) { |
---|
989 | |
---|
990 | #ifdef INSTRUMENTATION |
---|
991 | m_cpt_itlb_read++; |
---|
992 | #endif |
---|
993 | tlb_hit = r_itlb.translate(m_ireq.addr, |
---|
994 | &paddr, |
---|
995 | &tlb_flags, |
---|
996 | &tlb_nline, // unused |
---|
997 | &tlb_way, // unused |
---|
998 | &tlb_set); // unused |
---|
999 | } |
---|
1000 | else if (vci_param::N > 32) { |
---|
1001 | paddr = paddr | ((paddr_t) r_icache_paddr_ext.read() << 32); |
---|
1002 | } |
---|
1003 | |
---|
1004 | // systematic icache access (if activated) |
---|
1005 | if (r_mmu_mode.read() & INS_CACHE_MASK) { |
---|
1006 | |
---|
1007 | |
---|
1008 | #ifdef INSTRUMENTATION |
---|
1009 | m_cpt_icache_data_read++; |
---|
1010 | m_cpt_icache_dir_read++; |
---|
1011 | #endif |
---|
1012 | r_icache.read(paddr, |
---|
1013 | &cache_inst, |
---|
1014 | &cache_way, |
---|
1015 | &cache_set, |
---|
1016 | &cache_word, |
---|
1017 | &cache_state); |
---|
1018 | } |
---|
1019 | |
---|
1020 | // We compute cacheability and check access rights: |
---|
1021 | // - If MMU activated : cacheability is defined by the C bit in the PTE, |
---|
1022 | // and the access rights are defined by the U and X bits in the PTE. |
---|
1023 | // - If MMU not activated : cacheability is defined by the segment table, |
---|
1024 | // and there is no access rights checking |
---|
1025 | |
---|
1026 | if (not (r_mmu_mode.read() & INS_TLB_MASK)) { |
---|
1027 | // tlb not activated: |
---|
1028 | // cacheability |
---|
1029 | if (not (r_mmu_mode.read() & INS_CACHE_MASK)) { |
---|
1030 | cacheable = false; |
---|
1031 | } |
---|
1032 | else { |
---|
1033 | cacheable = m_cacheability_table[(uint64_t) m_ireq.addr]; |
---|
1034 | } |
---|
1035 | } |
---|
1036 | else |
---|
1037 | { |
---|
1038 | // itlb activated |
---|
1039 | if (tlb_hit) |
---|
1040 | { |
---|
1041 | // ITLB hit |
---|
1042 | // cacheability |
---|
1043 | if (not (r_mmu_mode.read() & INS_CACHE_MASK)) |
---|
1044 | { |
---|
1045 | cacheable = false; |
---|
1046 | } |
---|
1047 | else |
---|
1048 | { |
---|
1049 | cacheable = tlb_flags.c; |
---|
1050 | } |
---|
1051 | |
---|
1052 | // access rights checking |
---|
1053 | if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER)) |
---|
1054 | { |
---|
1055 | r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
1056 | r_mmu_ibvar = m_ireq.addr; |
---|
1057 | m_irsp.valid = true; |
---|
1058 | m_irsp.error = true; |
---|
1059 | m_irsp.instruction = 0; |
---|
1060 | break; |
---|
1061 | } |
---|
1062 | else if (not tlb_flags.x) |
---|
1063 | { |
---|
1064 | r_mmu_ietr = MMU_READ_EXEC_VIOLATION; |
---|
1065 | r_mmu_ibvar = m_ireq.addr; |
---|
1066 | m_irsp.valid = true; |
---|
1067 | m_irsp.error = true; |
---|
1068 | m_irsp.instruction = 0; |
---|
1069 | break; |
---|
1070 | } |
---|
1071 | } |
---|
1072 | else |
---|
1073 | { |
---|
1074 | // ITLB miss |
---|
1075 | |
---|
1076 | #ifdef INSTRUMENTATION |
---|
1077 | m_cpt_itlb_miss++; |
---|
1078 | #endif |
---|
1079 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
1080 | r_icache_tlb_miss_req = true; |
---|
1081 | break; |
---|
1082 | } |
---|
1083 | } // end if itlb activated |
---|
1084 | |
---|
1085 | // physical address registration |
---|
1086 | r_icache_vci_paddr = paddr; |
---|
1087 | |
---|
1088 | // Finally, we send the response to processor, and compute next state |
---|
1089 | if (cacheable) { |
---|
1090 | if (cache_state == CACHE_SLOT_STATE_INVALID) { |
---|
1091 | // cache miss |
---|
1092 | #ifdef INSTRUMENTATION |
---|
1093 | m_cpt_icache_miss++; |
---|
1094 | #endif |
---|
1095 | // we request a VCI transaction |
---|
1096 | r_icache_fsm = ICACHE_MISS_SELECT; |
---|
1097 | #if DEBUG_ICACHE |
---|
1098 | if (m_debug_icache_fsm) { |
---|
1099 | std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" |
---|
1100 | << " : PADDR = " << std::hex << paddr << std::endl; |
---|
1101 | } |
---|
1102 | #endif |
---|
1103 | r_icache_miss_req = true; |
---|
1104 | } |
---|
1105 | else { |
---|
1106 | // cache hit |
---|
1107 | #ifdef INSTRUMENTATION |
---|
1108 | m_cpt_ins_read++; |
---|
1109 | #endif |
---|
1110 | // return instruction to processor |
---|
1111 | m_irsp.valid = true; |
---|
1112 | m_irsp.instruction = cache_inst; |
---|
1113 | r_icache_fsm = ICACHE_IDLE; |
---|
1114 | #if DEBUG_ICACHE |
---|
1115 | if (m_debug_icache_fsm) { |
---|
1116 | std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" |
---|
1117 | << " : PADDR = " << std::hex << paddr |
---|
1118 | << " / INST = " << cache_inst << std::endl; |
---|
1119 | } |
---|
1120 | #endif |
---|
1121 | } |
---|
1122 | } |
---|
1123 | else { |
---|
1124 | // non cacheable read |
---|
1125 | r_icache_unc_req = true; |
---|
1126 | r_icache_fsm = ICACHE_UNC_WAIT; |
---|
1127 | |
---|
1128 | #if DEBUG_ICACHE |
---|
1129 | if (m_debug_icache_fsm) { |
---|
1130 | std::cout << " <PROC " << name() |
---|
1131 | << " ICACHE_IDLE> READ UNCACHEABLE in icache" |
---|
1132 | << " : PADDR = " << std::hex << paddr << std::endl; |
---|
1133 | } |
---|
1134 | #endif |
---|
1135 | } |
---|
1136 | } // end if m_ireq.valid |
---|
1137 | break; |
---|
1138 | } |
---|
1139 | ///////////////////// |
---|
1140 | case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss |
---|
1141 | // the itlb is udated by the DCACHE FSM, as well as the |
---|
1142 | // r_mmu_ietr and r_mmu_ibvar registers in case of error. |
---|
1143 | // the itlb is not accessed by ICACHE FSM until DCACHE FSM |
---|
1144 | // reset the r_icache_tlb_miss_req flip-flop |
---|
1145 | // external coherence request are accepted in this state. |
---|
1146 | { |
---|
1147 | // DCACHE FSM signals response by reseting the request flip-flop |
---|
1148 | if (not r_icache_tlb_miss_req.read()) { |
---|
1149 | if (r_icache_tlb_rsp_error.read()) { |
---|
1150 | // error reported : tlb not updated |
---|
1151 | r_icache_tlb_rsp_error = false; |
---|
1152 | m_irsp.error = true; |
---|
1153 | m_irsp.valid = true; |
---|
1154 | r_icache_fsm = ICACHE_IDLE; |
---|
1155 | } |
---|
1156 | else { |
---|
1157 | // tlb updated : return to IDLE state |
---|
1158 | r_icache_fsm = ICACHE_IDLE; |
---|
1159 | } |
---|
1160 | } |
---|
1161 | break; |
---|
1162 | } |
---|
1163 | ////////////////////////// |
---|
1164 | case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries |
---|
1165 | { |
---|
1166 | r_itlb.flush(); |
---|
1167 | r_dcache_xtn_req = false; |
---|
1168 | r_icache_fsm = ICACHE_IDLE; |
---|
1169 | break; |
---|
1170 | } |
---|
1171 | //////////////////////////// |
---|
1172 | case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using |
---|
1173 | // r_icache_flush_count as a slot counter, |
---|
1174 | // looping in this state until all slots are visited. |
---|
1175 | // It can require two cycles per slot: |
---|
1176 | // We test here the slot state, and make the actual inval |
---|
1177 | // (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state. |
---|
1178 | // A cleanup request is generated for each valid line |
---|
1179 | { |
---|
1180 | int state; |
---|
1181 | paddr_t tag; |
---|
1182 | size_t way = r_icache_flush_count.read() / m_icache_sets; |
---|
1183 | size_t set = r_icache_flush_count.read() % m_icache_sets; |
---|
1184 | |
---|
1185 | r_icache.read_dir(way, |
---|
1186 | set, |
---|
1187 | &tag, |
---|
1188 | &state); |
---|
1189 | |
---|
1190 | if (state == CACHE_SLOT_STATE_VALID) { |
---|
1191 | // goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval |
---|
1192 | r_icache_miss_way = way; |
---|
1193 | r_icache_miss_set = set; |
---|
1194 | r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO; |
---|
1195 | } |
---|
1196 | else if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways - 1)) { |
---|
1197 | // last slot |
---|
1198 | r_dcache_xtn_req = false; |
---|
1199 | m_drsp.valid = true; |
---|
1200 | r_icache_fsm = ICACHE_IDLE; |
---|
1201 | } |
---|
1202 | |
---|
1203 | // saturation counter, to have the same last slot condition |
---|
1204 | // in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states |
---|
1205 | if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1)) { |
---|
1206 | r_icache_flush_count = r_icache_flush_count.read() + 1; |
---|
1207 | } |
---|
1208 | break; |
---|
1209 | } |
---|
1210 | /////////////////////////////// |
---|
1211 | case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush |
---|
1212 | { |
---|
1213 | size_t way = r_icache_miss_way.read(); |
---|
1214 | size_t set = r_icache_miss_set.read(); |
---|
1215 | |
---|
1216 | r_icache.write_dir(way, |
---|
1217 | set, |
---|
1218 | CACHE_SLOT_STATE_INVALID); |
---|
1219 | |
---|
1220 | if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways - 1)) { |
---|
1221 | // last slot |
---|
1222 | r_dcache_xtn_req = false; |
---|
1223 | m_drsp.valid = true; |
---|
1224 | r_icache_fsm = ICACHE_IDLE; |
---|
1225 | } |
---|
1226 | else { |
---|
1227 | r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; |
---|
1228 | } |
---|
1229 | break; |
---|
1230 | } |
---|
1231 | |
---|
1232 | ////////////////////////// |
---|
1233 | case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address |
---|
1234 | // stored in the r_dcache_save_wdata register |
---|
1235 | { |
---|
1236 | r_itlb.inval(r_dcache_save_wdata.read()); |
---|
1237 | r_dcache_xtn_req = false; |
---|
1238 | r_icache_fsm = ICACHE_IDLE; |
---|
1239 | break; |
---|
1240 | } |
---|
1241 | /////////////////////////////// |
---|
1242 | case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address |
---|
1243 | // requires 3 cycles (in case of hit on itlb and icache). |
---|
1244 | // In this state, access TLB to translate virtual address |
---|
1245 | // stored in the r_dcache_save_wdata register. |
---|
1246 | { |
---|
1247 | paddr_t paddr; |
---|
1248 | bool hit; |
---|
1249 | |
---|
1250 | // read physical address in TLB when MMU activated |
---|
1251 | if (r_mmu_mode.read() & INS_TLB_MASK) { |
---|
1252 | // itlb activated |
---|
1253 | hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr); |
---|
1254 | } |
---|
1255 | else { |
---|
1256 | // itlb not activated |
---|
1257 | paddr = (paddr_t) r_dcache_save_wdata.read(); |
---|
1258 | hit = true; |
---|
1259 | } |
---|
1260 | |
---|
1261 | if (hit) { |
---|
1262 | // continue the selective inval process |
---|
1263 | r_icache_vci_paddr = paddr; |
---|
1264 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
1265 | } |
---|
1266 | else { |
---|
1267 | // miss : send a request to DCACHE FSM |
---|
1268 | r_icache_tlb_miss_req = true; |
---|
1269 | r_icache_vaddr_save = r_dcache_save_wdata.read(); |
---|
1270 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
1271 | } |
---|
1272 | break; |
---|
1273 | } |
---|
1274 | /////////////////////////////// |
---|
1275 | case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address |
---|
1276 | // require 2 cycles. In this state, we read directory |
---|
1277 | // with address stored in r_icache_vci_paddr register. |
---|
1278 | { |
---|
1279 | int state; |
---|
1280 | size_t way; |
---|
1281 | size_t set; |
---|
1282 | size_t word; |
---|
1283 | |
---|
1284 | r_icache.read_dir(r_icache_vci_paddr.read(), |
---|
1285 | &state, |
---|
1286 | &way, |
---|
1287 | &set, |
---|
1288 | &word); |
---|
1289 | |
---|
1290 | if (state == CACHE_SLOT_STATE_VALID) { |
---|
1291 | // inval to be done |
---|
1292 | r_icache_miss_way = way; |
---|
1293 | r_icache_miss_set = set; |
---|
1294 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; |
---|
1295 | } |
---|
1296 | else { |
---|
1297 | // miss : acknowlege the XTN request and return |
---|
1298 | r_dcache_xtn_req = false; |
---|
1299 | r_icache_fsm = ICACHE_IDLE; |
---|
1300 | } |
---|
1301 | break; |
---|
1302 | } |
---|
1303 | /////////////////////////////// |
---|
1304 | case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval |
---|
1305 | { |
---|
1306 | r_icache.write_dir(r_icache_miss_way.read(), |
---|
1307 | r_icache_miss_set.read(), |
---|
1308 | CACHE_SLOT_STATE_INVALID); |
---|
1309 | |
---|
1310 | // acknowledge the XTN request and return |
---|
1311 | r_dcache_xtn_req = false; |
---|
1312 | r_icache_fsm = ICACHE_IDLE; |
---|
1313 | break; |
---|
1314 | } |
---|
1315 | //////////////////////// |
---|
1316 | case ICACHE_MISS_SELECT: // Try to select a slot in associative set, |
---|
1317 | // Waiting in this state if no slot available. |
---|
1318 | // If a victim slot has been chosen and the r_icache_cc_send_req is false, |
---|
1319 | // we send the cleanup request in this state. |
---|
1320 | // If not, a r_icache_cleanup_victim_req flip-flop is |
---|
1321 | // utilized for saving this cleanup request, and it will be sent later |
---|
1322 | // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. |
---|
1323 | // The r_icache_miss_clack flip-flop is set |
---|
1324 | // when a cleanup is required |
---|
1325 | { |
---|
1326 | bool found; |
---|
1327 | bool cleanup; |
---|
1328 | size_t way; |
---|
1329 | size_t set; |
---|
1330 | paddr_t victim; |
---|
1331 | |
---|
1332 | r_icache.read_select(r_icache_vci_paddr.read(), |
---|
1333 | &victim, |
---|
1334 | &way, |
---|
1335 | &set, |
---|
1336 | &found, |
---|
1337 | &cleanup); |
---|
1338 | if (not found) |
---|
1339 | { |
---|
1340 | break; |
---|
1341 | } |
---|
1342 | else { |
---|
1343 | r_icache_miss_way = way; |
---|
1344 | r_icache_miss_set = set; |
---|
1345 | |
---|
1346 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
1347 | |
---|
1348 | #if DEBUG_ICACHE |
---|
1349 | if (m_debug_icache_fsm) { |
---|
1350 | std::cout << " <PROC " << name() |
---|
1351 | << " ICACHE_MISS_SELECT> Select a slot:" << std::dec |
---|
1352 | << " / WAY = " << way |
---|
1353 | << " / SET = " << set << std::endl; |
---|
1354 | } |
---|
1355 | #endif |
---|
1356 | } |
---|
1357 | break; |
---|
1358 | } |
---|
1359 | /////////////////////// |
---|
1360 | case ICACHE_MISS_CLEAN: // switch the slot to zombi state |
---|
1361 | { |
---|
1362 | r_icache.write_dir(r_icache_miss_way.read(), |
---|
1363 | r_icache_miss_set.read(), |
---|
1364 | CACHE_SLOT_STATE_INVALID); |
---|
1365 | #if DEBUG_ICACHE |
---|
1366 | if (m_debug_icache_fsm) { |
---|
1367 | std::cout << " <PROC " << name() |
---|
1368 | << " ICACHE_MISS_CLEAN> Switch to EMPTY state" << std::dec |
---|
1369 | << " / WAY = " << r_icache_miss_way.read() |
---|
1370 | << " / SET = " << r_icache_miss_set.read() << std::endl; |
---|
1371 | } |
---|
1372 | #endif |
---|
1373 | |
---|
1374 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
1375 | break; |
---|
1376 | } |
---|
1377 | ////////////////////// |
---|
1378 | case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM |
---|
1379 | { |
---|
1380 | if (r_vci_rsp_ins_error.read()) { |
---|
1381 | // bus error |
---|
1382 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
1383 | r_mmu_ibvar = r_icache_vaddr_save.read(); |
---|
1384 | m_irsp.valid = true; |
---|
1385 | m_irsp.error = true; |
---|
1386 | r_vci_rsp_ins_error = false; |
---|
1387 | r_icache_fsm = ICACHE_IDLE; |
---|
1388 | } |
---|
1389 | else if (r_vci_rsp_fifo_icache.rok()) { |
---|
1390 | // response available |
---|
1391 | r_icache_miss_word = 0; |
---|
1392 | r_icache_fsm = ICACHE_MISS_DATA_UPDT; |
---|
1393 | } |
---|
1394 | break; |
---|
1395 | } |
---|
1396 | /////////////////////////// |
---|
1397 | case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) |
---|
1398 | { |
---|
1399 | if (r_vci_rsp_fifo_icache.rok()) { |
---|
1400 | // response available |
---|
1401 | r_icache.write(r_icache_miss_way.read(), |
---|
1402 | r_icache_miss_set.read(), |
---|
1403 | r_icache_miss_word.read(), |
---|
1404 | r_vci_rsp_fifo_icache.read()); |
---|
1405 | #if DEBUG_ICACHE |
---|
1406 | if (m_debug_icache_fsm) { |
---|
1407 | std::cout << " <PROC " << name() |
---|
1408 | << " ICACHE_MISS_DATA_UPDT> Write one word:" |
---|
1409 | << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() |
---|
1410 | << " WAY = " << r_icache_miss_way.read() |
---|
1411 | << " SET = " << r_icache_miss_set.read() |
---|
1412 | << " WORD = " << r_icache_miss_word.read() << std::endl; |
---|
1413 | } |
---|
1414 | #endif |
---|
1415 | vci_rsp_fifo_icache_get = true; |
---|
1416 | r_icache_miss_word = r_icache_miss_word.read() + 1; |
---|
1417 | |
---|
1418 | if (r_icache_miss_word.read() == m_icache_words - 1) { |
---|
1419 | // last word |
---|
1420 | r_icache_fsm = ICACHE_MISS_DIR_UPDT; |
---|
1421 | } |
---|
1422 | } |
---|
1423 | break; |
---|
1424 | } |
---|
1425 | ////////////////////////// |
---|
1426 | case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted, |
---|
1427 | // and the cleanup ack has not been received, |
---|
1428 | // as indicated by r_icache_miss_clack. |
---|
1429 | // - If no matching coherence request (r_icache_miss_inval) |
---|
1430 | // switch directory slot to VALID state. |
---|
1431 | // - If matching coherence request, switch directory slot |
---|
1432 | // to ZOMBI state, and send a cleanup request. |
---|
1433 | { |
---|
1434 | // Switch slot to VALID state |
---|
1435 | r_icache.write_dir(r_icache_vci_paddr.read(), |
---|
1436 | r_icache_miss_way.read(), |
---|
1437 | r_icache_miss_set.read(), |
---|
1438 | CACHE_SLOT_STATE_VALID); |
---|
1439 | #if DEBUG_ICACHE |
---|
1440 | if (m_debug_icache_fsm) { |
---|
1441 | std::cout << " <PROC " << name() |
---|
1442 | << " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state" |
---|
1443 | << " PADDR = " << std::hex << r_icache_vci_paddr.read() |
---|
1444 | << " WAY = " << std::dec << r_icache_miss_way.read() |
---|
1445 | << " SET = " << r_icache_miss_set.read() << std::endl; |
---|
1446 | } |
---|
1447 | #endif |
---|
1448 | |
---|
1449 | // Immediate coherence test: |
---|
1450 | // If we have received one or several updates on the line during the miss, we have stored them |
---|
1451 | // and we update the values now |
---|
1452 | for (std::list<VcacheUpdate>::iterator it = m_ipending_updates.begin(); it != m_ipending_updates.end(); it++) |
---|
1453 | { |
---|
1454 | bool cache_hit; |
---|
1455 | size_t cache_way = 0; |
---|
1456 | size_t cache_set = 0; |
---|
1457 | size_t cache_word = 0; |
---|
1458 | uint32_t cache_rdata = 0; |
---|
1459 | |
---|
1460 | // Test if hit in dcache |
---|
1461 | cache_hit = r_icache.read_neutral(it->m_addr, |
---|
1462 | &cache_rdata, |
---|
1463 | &cache_way, |
---|
1464 | &cache_set, |
---|
1465 | &cache_word); |
---|
1466 | |
---|
1467 | assert(cache_hit); |
---|
1468 | assert(cache_way == r_icache_miss_way.read()); |
---|
1469 | assert(cache_set == r_icache_miss_set.read()); |
---|
1470 | |
---|
1471 | r_icache.write(cache_way, cache_set, cache_word, it->m_value, it->m_be); |
---|
1472 | #if DEBUG_DCACHE |
---|
1473 | if (m_debug_icache_fsm) { |
---|
1474 | std::cout << " <Cache " << name() |
---|
1475 | << " CACHE_MISS_DIR_UPDT> Updating pending update:" |
---|
1476 | << " ADDR = " << std::hex << it->m_addr |
---|
1477 | << " / WAY = " << std::dec << cache_way |
---|
1478 | << " / SET = " << cache_set |
---|
1479 | << " / VALUE = " << std::hex << it->m_value |
---|
1480 | << " / BE = " << it->m_be << std::endl; |
---|
1481 | } |
---|
1482 | #endif |
---|
1483 | } |
---|
1484 | m_ipending_updates.clear(); |
---|
1485 | |
---|
1486 | r_icache_fsm = ICACHE_IDLE; |
---|
1487 | break; |
---|
1488 | } |
---|
1489 | //////////////////// |
---|
1490 | case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM |
---|
1491 | { |
---|
1492 | if (r_vci_rsp_ins_error.read()) { |
---|
1493 | // bus error |
---|
1494 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
1495 | r_mmu_ibvar = m_ireq.addr; |
---|
1496 | r_vci_rsp_ins_error = false; |
---|
1497 | m_irsp.valid = true; |
---|
1498 | m_irsp.error = true; |
---|
1499 | r_icache_fsm = ICACHE_IDLE; |
---|
1500 | } |
---|
1501 | else if (r_vci_rsp_fifo_icache.rok()) { |
---|
1502 | // instruction available |
---|
1503 | vci_rsp_fifo_icache_get = true; |
---|
1504 | r_icache_fsm = ICACHE_IDLE; |
---|
1505 | if (m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read())) { |
---|
1506 | // request unmodified |
---|
1507 | m_irsp.valid = true; |
---|
1508 | m_irsp.instruction = r_vci_rsp_fifo_icache.read(); |
---|
1509 | } |
---|
1510 | } |
---|
1511 | break; |
---|
1512 | } |
---|
1513 | |
---|
1514 | } // end switch r_icache_fsm |
---|
1515 | |
---|
1516 | //////////////////////////////////////////////////////////////////////////////////// |
---|
1517 | // DCACHE FSM |
---|
1518 | // |
---|
1519 | // 1/ Coherence operations |
---|
1520 | // They are handled as interrupts generated by the CC_RECEIVE FSM. |
---|
1521 | // - There is a coherence request when r_tgt_dcache_req is set. |
---|
1522 | // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT |
---|
1523 | // and SC_WAIT states. |
---|
1524 | // - There is a cleanup acknowledge request when r_cleanup_dcache_req is set. |
---|
1525 | // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT, |
---|
1526 | // MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states. |
---|
1527 | // - For both types of requests, actions associated to the pre-empted state |
---|
1528 | // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK |
---|
1529 | // or CC_CLACK) to execute the requested coherence operation, and returns |
---|
1530 | // to the pre-empted state. |
---|
1531 | // |
---|
1532 | // 2/ TLB miss |
---|
1533 | // The page tables are generally cacheable. |
---|
1534 | // In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated |
---|
1535 | // sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE, |
---|
1536 | // this sub-fsm implement the table-walk... |
---|
1537 | // |
---|
1538 | // 3/ processor requests |
---|
1539 | // Processor requests are taken in IDLE state only. |
---|
1540 | // The IDLE state implements a two stages pipe-line to handle write bursts: |
---|
1541 | // - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid). |
---|
1542 | // - The registration in wbuf and the dcache update is done in stage P1 |
---|
1543 | // (if the processor request is a write). |
---|
1544 | // The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define |
---|
1545 | // the operations that must be done in P1 stage, and the access type |
---|
1546 | // (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req. |
---|
1547 | // READ requests are delayed if a cache update is requested. |
---|
1548 | // WRITE or SC requests can require a PTE Dirty bit update (in memory), |
---|
1549 | // that is done (before handling the processor request) by a dedicated sub-fsm. |
---|
1550 | // If a PTE is modified, both the itlb and dtlb are selectively, but sequencially |
---|
1551 | // cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state). |
---|
1552 | // |
---|
1553 | // 4/ Atomic instructions LL/SC |
---|
1554 | // The LL/SC address are non cacheable (systematic access to memory). |
---|
1555 | // The llsc buffer contains a registration for an active LL/SC operation |
---|
1556 | // (with an address, a registration key, an aging counter and a valid bit). |
---|
1557 | // - LL requests from the processor are transmitted as a one flit VCI command |
---|
1558 | // (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must |
---|
1559 | // be 8 as the response is 2 flits long (data and registration key) |
---|
1560 | // - SC requests from the processor are systematically transmitted to the |
---|
1561 | // memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC |
---|
1562 | // as PKTID value). The first flit contains the registration key, the second |
---|
1563 | // flit contains the data to write in case of success. |
---|
1564 | // The cache is not updated, as this is done in case of success by the |
---|
1565 | // coherence transaction. |
---|
1566 | // |
---|
1567 | // 5/ Non cacheable access: |
---|
1568 | // This component implement a strong order between non cacheable access |
---|
1569 | // (read or write) : A new non cacheable VCI transaction starts only when |
---|
1570 | // the previous non cacheable transaction is completed. After send the VCI |
---|
1571 | // transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state. |
---|
1572 | // So the processor is blocked until the respone arrives in CACHE L1. |
---|
1573 | // |
---|
1574 | // 6/ Error handling: |
---|
1575 | // When the MMU is not activated, Read Bus Errors are synchronous events, |
---|
1576 | // Some Write Bus Errors are synchronous events when the request is a non cacheable access |
---|
1577 | // but some Write Bus Errors are asynchronous events when the request is cacheable access |
---|
1578 | // (processor is not frozen). |
---|
1579 | // - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the |
---|
1580 | // r_vci_rsp_data_error flip-flop, without writing any data in the |
---|
1581 | // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled |
---|
1582 | // by the DCACHE FSM. |
---|
1583 | // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals |
---|
1584 | // the asynchronous error using the setWriteBerr() method. |
---|
1585 | // When the MMU is activated bus error are rare events, as the MMU |
---|
1586 | // checks the physical address before the VCI transaction starts. |
---|
1587 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
1588 | |
---|
1589 | // default value for m_drsp |
---|
1590 | m_drsp.valid = false; |
---|
1591 | m_drsp.error = false; |
---|
1592 | m_drsp.rdata = 0; |
---|
1593 | |
---|
1594 | switch (r_dcache_fsm.read()) { |
---|
1595 | case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state : |
---|
1596 | // 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN |
---|
1597 | // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS |
---|
1598 | // 4) XTN request (processor) => DCACHE_XTN_* |
---|
1599 | // 5) DTLB miss (processor) => DCACHE_TLB_MISS |
---|
1600 | // 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE |
---|
1601 | // 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT |
---|
1602 | // 8) Uncacheable read (processor) => DCACHE_UNC_WAIT |
---|
1603 | // 9) LL access (processor) => DCACHE_LL_WAIT |
---|
1604 | // 10) SC access (processor) => DCACHE_SC_WAIT |
---|
1605 | // |
---|
1606 | // There is a fixed priority to handle requests to DCACHE: |
---|
1607 | // 1/ the ITLB/DTLB invalidate requests |
---|
1608 | // 2/ the coherence requests, |
---|
1609 | // 3/ the processor requests (including DTLB miss), |
---|
1610 | // 4/ the ITLB miss requests, |
---|
1611 | // The address space processor request are handled as follows: |
---|
1612 | // - WRITE request is blocked if the Dirty bit mus be set. |
---|
1613 | // If DTLB hit, the P1 stage is activated (writes WBUF, and |
---|
1614 | // updates DCACHE if DCACHE hit) & processor request acknowledged. |
---|
1615 | // - READ request generate a simultaneouss access to DCACHE.DATA |
---|
1616 | // and DCACHE.DIR, but is delayed if DCACHE update required. |
---|
1617 | // |
---|
1618 | // There is 4 configurations defining the access type to |
---|
1619 | // DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the |
---|
1620 | // dreq.valid (dreq) and r_dcache_updt_req (updt) signals: |
---|
1621 | // dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA / |
---|
1622 | // 0 / 0 / NOP / NOP / NOP / |
---|
1623 | // 0 / 1 / NOP / NOP / WRITE / |
---|
1624 | // 1 / 0 / READ / READ / NOP / |
---|
1625 | // 1 / 1 / READ / READ / WRITE / |
---|
1626 | // Those two registers are set at each cycle from the 3 signals |
---|
1627 | // updt_request, wbuf_request, wbuf_write_miss. |
---|
1628 | { |
---|
1629 | paddr_t paddr; |
---|
1630 | pte_info_t tlb_flags; |
---|
1631 | size_t tlb_way; |
---|
1632 | size_t tlb_set; |
---|
1633 | paddr_t tlb_nline = 0; |
---|
1634 | size_t cache_way; |
---|
1635 | size_t cache_set; |
---|
1636 | size_t cache_word; |
---|
1637 | uint32_t cache_rdata = 0; |
---|
1638 | bool tlb_hit = false; |
---|
1639 | int cache_state = CACHE_SLOT_STATE_INVALID; |
---|
1640 | |
---|
1641 | bool tlb_inval_required = false; // request TLB inval after cache update |
---|
1642 | bool wbuf_write_miss = false; // miss a WBUF write request |
---|
1643 | bool updt_request = false; // request DCACHE update in P1 stage |
---|
1644 | bool wbuf_request = false; // request WBUF write in P1 stage |
---|
1645 | |
---|
1646 | // physical address computation : systematic DTLB access if activated |
---|
1647 | paddr = (paddr_t) m_dreq.addr; |
---|
1648 | if (m_dreq.valid) { |
---|
1649 | if (r_mmu_mode.read() & DATA_TLB_MASK) { |
---|
1650 | // DTLB activated |
---|
1651 | tlb_hit = r_dtlb.translate(m_dreq.addr, |
---|
1652 | &paddr, |
---|
1653 | &tlb_flags, |
---|
1654 | &tlb_nline, |
---|
1655 | &tlb_way, |
---|
1656 | &tlb_set); |
---|
1657 | } |
---|
1658 | else { |
---|
1659 | // identity mapping |
---|
1660 | // we take into account the paddr extension |
---|
1661 | if (vci_param::N > 32) { |
---|
1662 | paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32); |
---|
1663 | } |
---|
1664 | } |
---|
1665 | } // end physical address computation |
---|
1666 | |
---|
1667 | // systematic DCACHE access depending on r_dcache_updt_req (if activated) |
---|
1668 | if (r_mmu_mode.read() & DATA_CACHE_MASK) { |
---|
1669 | |
---|
1670 | if (m_dreq.valid and r_dcache_updt_req.read()) { |
---|
1671 | // read DIR and write DATA |
---|
1672 | r_dcache.read_dir(paddr, |
---|
1673 | &cache_state, |
---|
1674 | &cache_way, |
---|
1675 | &cache_set, |
---|
1676 | &cache_word); |
---|
1677 | |
---|
1678 | r_dcache.write(r_dcache_save_cache_way.read(), |
---|
1679 | r_dcache_save_cache_set.read(), |
---|
1680 | r_dcache_save_cache_word.read(), |
---|
1681 | r_dcache_save_wdata.read(), |
---|
1682 | r_dcache_save_be.read()); |
---|
1683 | } |
---|
1684 | else if (m_dreq.valid and not r_dcache_updt_req.read()) { |
---|
1685 | // read DIR and DATA |
---|
1686 | r_dcache.read(paddr, |
---|
1687 | &cache_rdata, |
---|
1688 | &cache_way, |
---|
1689 | &cache_set, |
---|
1690 | &cache_word, |
---|
1691 | &cache_state); |
---|
1692 | } |
---|
1693 | else if (not m_dreq.valid and r_dcache_updt_req.read()) { |
---|
1694 | // write DATA |
---|
1695 | r_dcache.write(r_dcache_save_cache_way.read(), |
---|
1696 | r_dcache_save_cache_set.read(), |
---|
1697 | r_dcache_save_cache_word.read(), |
---|
1698 | r_dcache_save_wdata.read(), |
---|
1699 | r_dcache_save_be.read()); |
---|
1700 | } |
---|
1701 | } // end dcache access |
---|
1702 | |
---|
1703 | // DCACHE update in P1 stage can require ITLB / DTLB inval or flush |
---|
1704 | if (r_dcache_updt_req.read()) { |
---|
1705 | size_t way = r_dcache_save_cache_way.read(); |
---|
1706 | size_t set = r_dcache_save_cache_set.read(); |
---|
1707 | |
---|
1708 | if (r_dcache_in_tlb[way * m_dcache_sets + set]) { |
---|
1709 | tlb_inval_required = true; |
---|
1710 | r_dcache_tlb_inval_set = 0; |
---|
1711 | r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >> |
---|
1712 | (uint32_log2(m_dcache_words << 2)); |
---|
1713 | r_dcache_in_tlb[way * m_dcache_sets + set] = false; |
---|
1714 | } |
---|
1715 | else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) { |
---|
1716 | r_itlb.reset(); |
---|
1717 | r_dtlb.reset(); |
---|
1718 | r_dcache_contains_ptd[way * m_dcache_sets + set] = false; |
---|
1719 | } |
---|
1720 | |
---|
1721 | #if DEBUG_DCACHE |
---|
1722 | if (m_debug_dcache_fsm) { |
---|
1723 | std::cout << " <PROC " << name() << " DCACHE_IDLE>" |
---|
1724 | << " Cache update in P1 stage" << std::dec |
---|
1725 | << " / WAY = " << r_dcache_save_cache_way.read() |
---|
1726 | << " / SET = " << r_dcache_save_cache_set.read() |
---|
1727 | << " / WORD = " << r_dcache_save_cache_word.read() << std::hex |
---|
1728 | << " / WDATA = " << r_dcache_save_wdata.read() |
---|
1729 | << " / BE = " << r_dcache_save_be.read() << std::endl; |
---|
1730 | } |
---|
1731 | #endif |
---|
1732 | } // end test TLB inval |
---|
1733 | |
---|
1734 | // Try WBUF update in P1 stage |
---|
1735 | // Miss if the write request is non cacheable, and there is a pending |
---|
1736 | // non cacheable write, or if the write buffer is full. |
---|
1737 | if (r_dcache_wbuf_req.read()) { |
---|
1738 | bool wok = r_wbuf.write(r_dcache_save_paddr.read(), |
---|
1739 | r_dcache_save_be.read(), |
---|
1740 | r_dcache_save_wdata.read(), |
---|
1741 | true); |
---|
1742 | if (not wok) { |
---|
1743 | // miss if write buffer full |
---|
1744 | wbuf_write_miss = true; |
---|
1745 | } |
---|
1746 | } // end WBUF update |
---|
1747 | |
---|
1748 | // Computing the response to processor, |
---|
1749 | // and the next value for r_dcache_fsm |
---|
1750 | |
---|
1751 | // itlb/dtlb invalidation self-request |
---|
1752 | if (tlb_inval_required) { |
---|
1753 | r_dcache_fsm_scan_save = r_dcache_fsm.read(); |
---|
1754 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
1755 | } |
---|
1756 | |
---|
1757 | // processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE) |
---|
1758 | // we don't take the processor request, and registers |
---|
1759 | // are frozen in case of wbuf_write_miss |
---|
1760 | else if (m_dreq.valid and not wbuf_write_miss) { |
---|
1761 | // register processor request and DCACHE response |
---|
1762 | r_dcache_save_vaddr = m_dreq.addr; |
---|
1763 | r_dcache_save_be = m_dreq.be; |
---|
1764 | r_dcache_save_wdata = m_dreq.wdata; |
---|
1765 | |
---|
1766 | // QM debug |
---|
1767 | if (m_debug_dcache_fsm) { |
---|
1768 | std::cout << "(1) In DCACHE_IDLE, r_dcache_save_paddr <- " << std::hex << paddr << std::endl; |
---|
1769 | } |
---|
1770 | r_dcache_save_paddr = paddr; |
---|
1771 | r_dcache_save_cache_way = cache_way; |
---|
1772 | r_dcache_save_cache_set = cache_set; |
---|
1773 | r_dcache_save_cache_word = cache_word; |
---|
1774 | |
---|
1775 | // READ XTN requests from processor |
---|
1776 | // They are executed in this DCACHE_IDLE state. |
---|
1777 | // The processor must not be in user mode |
---|
1778 | if (m_dreq.type == iss_t::XTN_READ) { |
---|
1779 | int xtn_opcode = (int) m_dreq.addr / 4; |
---|
1780 | |
---|
1781 | // checking processor mode: |
---|
1782 | if (m_dreq.mode == iss_t::MODE_USER) { |
---|
1783 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
1784 | r_mmu_dbvar = m_dreq.addr; |
---|
1785 | m_drsp.valid = true; |
---|
1786 | m_drsp.error = true; |
---|
1787 | m_drsp.rdata = 0; |
---|
1788 | r_dcache_fsm = DCACHE_IDLE; |
---|
1789 | } |
---|
1790 | else { |
---|
1791 | switch (xtn_opcode) { |
---|
1792 | case iss_t::XTN_INS_ERROR_TYPE: |
---|
1793 | m_drsp.rdata = r_mmu_ietr.read(); |
---|
1794 | m_drsp.valid = true; |
---|
1795 | m_drsp.error = false; |
---|
1796 | break; |
---|
1797 | |
---|
1798 | case iss_t::XTN_DATA_ERROR_TYPE: |
---|
1799 | m_drsp.rdata = r_mmu_detr.read(); |
---|
1800 | m_drsp.valid = true; |
---|
1801 | m_drsp.error = false; |
---|
1802 | break; |
---|
1803 | |
---|
1804 | case iss_t::XTN_INS_BAD_VADDR: |
---|
1805 | m_drsp.rdata = r_mmu_ibvar.read(); |
---|
1806 | m_drsp.valid = true; |
---|
1807 | m_drsp.error = false; |
---|
1808 | break; |
---|
1809 | |
---|
1810 | case iss_t::XTN_DATA_BAD_VADDR: |
---|
1811 | m_drsp.rdata = r_mmu_dbvar.read(); |
---|
1812 | m_drsp.valid = true; |
---|
1813 | m_drsp.error = false; |
---|
1814 | break; |
---|
1815 | |
---|
1816 | case iss_t::XTN_PTPR: |
---|
1817 | m_drsp.rdata = r_mmu_ptpr.read(); |
---|
1818 | m_drsp.valid = true; |
---|
1819 | m_drsp.error = false; |
---|
1820 | break; |
---|
1821 | |
---|
1822 | case iss_t::XTN_TLB_MODE: |
---|
1823 | m_drsp.rdata = r_mmu_mode.read(); |
---|
1824 | m_drsp.valid = true; |
---|
1825 | m_drsp.error = false; |
---|
1826 | break; |
---|
1827 | |
---|
1828 | case iss_t::XTN_MMU_PARAMS: |
---|
1829 | m_drsp.rdata = r_mmu_params; |
---|
1830 | m_drsp.valid = true; |
---|
1831 | m_drsp.error = false; |
---|
1832 | break; |
---|
1833 | |
---|
1834 | case iss_t::XTN_MMU_RELEASE: |
---|
1835 | m_drsp.rdata = r_mmu_release; |
---|
1836 | m_drsp.valid = true; |
---|
1837 | m_drsp.error = false; |
---|
1838 | break; |
---|
1839 | |
---|
1840 | case iss_t::XTN_MMU_WORD_LO: |
---|
1841 | m_drsp.rdata = r_mmu_word_lo.read(); |
---|
1842 | m_drsp.valid = true; |
---|
1843 | m_drsp.error = false; |
---|
1844 | break; |
---|
1845 | |
---|
1846 | case iss_t::XTN_MMU_WORD_HI: |
---|
1847 | m_drsp.rdata = r_mmu_word_hi.read(); |
---|
1848 | m_drsp.valid = true; |
---|
1849 | m_drsp.error = false; |
---|
1850 | break; |
---|
1851 | |
---|
1852 | case iss_t::XTN_DATA_PADDR_EXT: |
---|
1853 | m_drsp.rdata = r_dcache_paddr_ext.read(); |
---|
1854 | m_drsp.valid = true; |
---|
1855 | m_drsp.error = false; |
---|
1856 | break; |
---|
1857 | |
---|
1858 | case iss_t::XTN_INST_PADDR_EXT: |
---|
1859 | m_drsp.rdata = r_icache_paddr_ext.read(); |
---|
1860 | m_drsp.valid = true; |
---|
1861 | m_drsp.error = false; |
---|
1862 | break; |
---|
1863 | |
---|
1864 | default: |
---|
1865 | r_mmu_detr = MMU_READ_UNDEFINED_XTN; |
---|
1866 | r_mmu_dbvar = m_dreq.addr; |
---|
1867 | m_drsp.valid = true; |
---|
1868 | m_drsp.error = true; |
---|
1869 | m_drsp.rdata = 0; |
---|
1870 | break; |
---|
1871 | } // end switch xtn_opcode |
---|
1872 | } // end else |
---|
1873 | } // end if XTN_READ |
---|
1874 | |
---|
1875 | // Handling WRITE XTN requests from processor. |
---|
1876 | // They are not executed in this DCACHE_IDLE state |
---|
1877 | // if they require access to the caches or the TLBs |
---|
1878 | // that are already accessed. |
---|
1879 | // Caches can be invalidated or flushed in user mode, |
---|
1880 | // and the sync instruction can be executed in user mode |
---|
1881 | else if (m_dreq.type == iss_t::XTN_WRITE) { |
---|
1882 | int xtn_opcode = (int) m_dreq.addr / 4; |
---|
1883 | r_dcache_xtn_opcode = xtn_opcode; |
---|
1884 | |
---|
1885 | // checking processor mode: |
---|
1886 | if ((m_dreq.mode == iss_t::MODE_USER) && |
---|
1887 | (xtn_opcode != iss_t::XTN_SYNC) && |
---|
1888 | (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && |
---|
1889 | (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && |
---|
1890 | (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && |
---|
1891 | (xtn_opcode != iss_t::XTN_ICACHE_FLUSH)) { |
---|
1892 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
1893 | r_mmu_dbvar = m_dreq.addr; |
---|
1894 | m_drsp.valid = true; |
---|
1895 | m_drsp.error = true; |
---|
1896 | m_drsp.rdata = 0; |
---|
1897 | r_dcache_fsm = DCACHE_IDLE; |
---|
1898 | } |
---|
1899 | else { |
---|
1900 | switch (xtn_opcode) { |
---|
1901 | case iss_t::XTN_PTPR: // itlb & dtlb must be flushed |
---|
1902 | r_dcache_xtn_req = true; |
---|
1903 | r_dcache_fsm = DCACHE_XTN_SWITCH; |
---|
1904 | break; |
---|
1905 | |
---|
1906 | case iss_t::XTN_TLB_MODE: // no cache or tlb access |
---|
1907 | r_mmu_mode = m_dreq.wdata; |
---|
1908 | m_drsp.valid = true; |
---|
1909 | r_dcache_fsm = DCACHE_IDLE; |
---|
1910 | break; |
---|
1911 | |
---|
1912 | case iss_t::XTN_DTLB_INVAL: // dtlb access |
---|
1913 | r_dcache_fsm = DCACHE_XTN_DT_INVAL; |
---|
1914 | break; |
---|
1915 | |
---|
1916 | case iss_t::XTN_ITLB_INVAL: // itlb access |
---|
1917 | r_dcache_xtn_req = true; |
---|
1918 | r_dcache_fsm = DCACHE_XTN_IT_INVAL; |
---|
1919 | break; |
---|
1920 | |
---|
1921 | case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access |
---|
1922 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; |
---|
1923 | break; |
---|
1924 | |
---|
1925 | case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access |
---|
1926 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
1927 | if (sizeof(paddr_t) <= 32) { |
---|
1928 | assert(r_mmu_word_hi.read() == 0 && |
---|
1929 | "high bits should be 0 for 32bit paddr"); |
---|
1930 | |
---|
1931 | // QM debug |
---|
1932 | if (m_debug_dcache_fsm) { |
---|
1933 | std::cout << "(2) In DCACHE_IDLE, r_dcache_save_paddr <- " << std::hex << (paddr_t) r_mmu_word_lo.read() << std::endl; |
---|
1934 | } |
---|
1935 | r_dcache_save_paddr = (paddr_t) r_mmu_word_lo.read(); |
---|
1936 | } |
---|
1937 | else { |
---|
1938 | r_dcache_save_paddr = (paddr_t) r_mmu_word_hi.read() << 32 | |
---|
1939 | (paddr_t) r_mmu_word_lo.read(); |
---|
1940 | } |
---|
1941 | break; |
---|
1942 | |
---|
1943 | case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset |
---|
1944 | r_dcache_flush_count = 0; |
---|
1945 | r_dcache_fsm = DCACHE_XTN_DC_FLUSH; |
---|
1946 | break; |
---|
1947 | |
---|
1948 | case iss_t::XTN_ICACHE_INVAL: // icache and itlb access |
---|
1949 | r_dcache_xtn_req = true; |
---|
1950 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; |
---|
1951 | break; |
---|
1952 | |
---|
1953 | case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access |
---|
1954 | r_dcache_xtn_req = true; |
---|
1955 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; |
---|
1956 | break; |
---|
1957 | |
---|
1958 | case iss_t::XTN_ICACHE_FLUSH: // icache access |
---|
1959 | r_dcache_xtn_req = true; |
---|
1960 | r_dcache_fsm = DCACHE_XTN_IC_FLUSH; |
---|
1961 | break; |
---|
1962 | |
---|
1963 | case iss_t::XTN_SYNC: // wait until write buffer empty |
---|
1964 | r_dcache_fsm = DCACHE_XTN_SYNC; |
---|
1965 | break; |
---|
1966 | |
---|
1967 | case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access |
---|
1968 | r_mmu_word_lo = m_dreq.wdata; |
---|
1969 | m_drsp.valid = true; |
---|
1970 | r_dcache_fsm = DCACHE_IDLE; |
---|
1971 | break; |
---|
1972 | |
---|
1973 | case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access |
---|
1974 | r_mmu_word_hi = m_dreq.wdata; |
---|
1975 | m_drsp.valid = true; |
---|
1976 | r_dcache_fsm = DCACHE_IDLE; |
---|
1977 | break; |
---|
1978 | |
---|
1979 | case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access |
---|
1980 | r_dcache_llsc_valid = false; |
---|
1981 | m_drsp.valid = true; |
---|
1982 | r_dcache_fsm = DCACHE_IDLE; |
---|
1983 | break; |
---|
1984 | |
---|
1985 | case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access |
---|
1986 | r_dcache_paddr_ext = m_dreq.wdata; |
---|
1987 | m_drsp.valid = true; |
---|
1988 | r_dcache_fsm = DCACHE_IDLE; |
---|
1989 | break; |
---|
1990 | |
---|
1991 | case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access |
---|
1992 | r_dcache_xtn_req = true; |
---|
1993 | r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; |
---|
1994 | break; |
---|
1995 | |
---|
1996 | case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action |
---|
1997 | case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action |
---|
1998 | m_drsp.valid = true; |
---|
1999 | r_dcache_fsm = DCACHE_IDLE; |
---|
2000 | break; |
---|
2001 | |
---|
2002 | case iss_t::XTN_DEBUG_MASK: // debug mask |
---|
2003 | m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0); |
---|
2004 | m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0); |
---|
2005 | m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0); |
---|
2006 | m_drsp.valid = true; |
---|
2007 | r_dcache_fsm = DCACHE_IDLE; |
---|
2008 | break; |
---|
2009 | |
---|
2010 | default: |
---|
2011 | r_mmu_detr = MMU_WRITE_UNDEFINED_XTN; |
---|
2012 | r_mmu_dbvar = m_dreq.addr; |
---|
2013 | m_drsp.valid = true; |
---|
2014 | m_drsp.error = true; |
---|
2015 | r_dcache_fsm = DCACHE_IDLE; |
---|
2016 | break; |
---|
2017 | } // end switch xtn_opcode |
---|
2018 | } // end else |
---|
2019 | } // end if XTN_WRITE |
---|
2020 | |
---|
2021 | // Handling processor requests to address space (READ/WRITE/LL/SC) |
---|
2022 | // The dtlb and dcache can be activated or not. |
---|
2023 | // We compute the cacheability, and check processor request validity: |
---|
2024 | // - If DTLB not activated : cacheability is defined by the segment table, |
---|
2025 | // and there is no access rights checking. |
---|
2026 | // - If DTLB activated : cacheability is defined by the C bit in the PTE, |
---|
2027 | // and the U & W bits of the PTE are checked, as well as the DTLB hit. |
---|
2028 | // Jumps to the TLB_MISS sub-fsm in case of dtlb miss. |
---|
2029 | else { |
---|
2030 | bool valid_req; |
---|
2031 | bool cacheable; |
---|
2032 | |
---|
2033 | if (not (r_mmu_mode.read() & DATA_TLB_MASK)) { |
---|
2034 | // dtlb not activated |
---|
2035 | valid_req = true; |
---|
2036 | |
---|
2037 | if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) { |
---|
2038 | cacheable = false; |
---|
2039 | } |
---|
2040 | else { |
---|
2041 | cacheable = m_cacheability_table[(uint64_t) m_dreq.addr]; |
---|
2042 | } |
---|
2043 | } |
---|
2044 | else { |
---|
2045 | // dtlb activated |
---|
2046 | if (tlb_hit) { |
---|
2047 | // cacheability |
---|
2048 | if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) { |
---|
2049 | cacheable = false; |
---|
2050 | } |
---|
2051 | else { |
---|
2052 | cacheable = tlb_flags.c; |
---|
2053 | } |
---|
2054 | |
---|
2055 | // access rights checking |
---|
2056 | if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) { |
---|
2057 | if ((m_dreq.type == iss_t::DATA_READ) or |
---|
2058 | (m_dreq.type == iss_t::DATA_LL)) { |
---|
2059 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
2060 | } |
---|
2061 | else { |
---|
2062 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
2063 | } |
---|
2064 | valid_req = false; |
---|
2065 | r_mmu_dbvar = m_dreq.addr; |
---|
2066 | m_drsp.valid = true; |
---|
2067 | m_drsp.error = true; |
---|
2068 | m_drsp.rdata = 0; |
---|
2069 | #if DEBUG_DCACHE |
---|
2070 | if (m_debug_dcache_fsm) { |
---|
2071 | std::cout << " <PROC " << name() << " DCACHE_IDLE>" |
---|
2072 | << " HIT in dtlb, but privilege violation" << std::endl; |
---|
2073 | } |
---|
2074 | #endif |
---|
2075 | } |
---|
2076 | else if (not tlb_flags.w and |
---|
2077 | ((m_dreq.type == iss_t::DATA_WRITE) or |
---|
2078 | (m_dreq.type == iss_t::DATA_SC))) { |
---|
2079 | r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; |
---|
2080 | valid_req = false; |
---|
2081 | r_mmu_dbvar = m_dreq.addr; |
---|
2082 | m_drsp.valid = true; |
---|
2083 | m_drsp.error = true; |
---|
2084 | m_drsp.rdata = 0; |
---|
2085 | #if DEBUG_DCACHE |
---|
2086 | if (m_debug_dcache_fsm) { |
---|
2087 | std::cout << " <PROC " << name() << " DCACHE_IDLE>" |
---|
2088 | << " HIT in dtlb, but writable violation" << std::endl; |
---|
2089 | } |
---|
2090 | #endif |
---|
2091 | } |
---|
2092 | else { |
---|
2093 | valid_req = true; |
---|
2094 | } |
---|
2095 | } |
---|
2096 | else { |
---|
2097 | // tlb miss |
---|
2098 | valid_req = false; |
---|
2099 | r_dcache_tlb_vaddr = m_dreq.addr; |
---|
2100 | r_dcache_tlb_ins = false; |
---|
2101 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
2102 | } |
---|
2103 | } // end DTLB activated |
---|
2104 | |
---|
2105 | if (valid_req) { |
---|
2106 | // processor request is valid (after MMU check) |
---|
2107 | // READ request |
---|
2108 | // The read requests are taken only if there is no cache update. |
---|
2109 | // We request a VCI transaction to CMD FSM if miss or uncachable |
---|
2110 | |
---|
2111 | if (((m_dreq.type == iss_t::DATA_READ)) |
---|
2112 | and not r_dcache_updt_req.read()) { |
---|
2113 | if (cacheable) { |
---|
2114 | // cacheable read |
---|
2115 | if (cache_state == CACHE_SLOT_STATE_INVALID) { |
---|
2116 | // cache miss |
---|
2117 | // request a VCI DMISS transaction |
---|
2118 | r_dcache_vci_paddr = paddr; |
---|
2119 | r_dcache_vci_miss_req = true; |
---|
2120 | r_dcache_miss_type = PROC_MISS; |
---|
2121 | r_dcache_fsm = DCACHE_MISS_SELECT; |
---|
2122 | #if DEBUG_DCACHE |
---|
2123 | if (m_debug_dcache_fsm) { |
---|
2124 | std::cout << " <PROC " << name() << " DCACHE_IDLE>" |
---|
2125 | << " READ MISS in dcache" |
---|
2126 | << " / PADDR = " << std::hex << paddr << std::endl; |
---|
2127 | } |
---|
2128 | #endif |
---|
2129 | } |
---|
2130 | else { |
---|
2131 | // cache hit |
---|
2132 | // returns data to processor |
---|
2133 | m_drsp.valid = true; |
---|
2134 | m_drsp.error = false; |
---|
2135 | m_drsp.rdata = cache_rdata; |
---|
2136 | #if DEBUG_DCACHE |
---|
2137 | if (m_debug_dcache_fsm) |
---|
2138 | std::cout << " <PROC " << name() << " DCACHE_IDLE>" |
---|
2139 | << " READ HIT in dcache" |
---|
2140 | << " : PADDR = " << std::hex << paddr |
---|
2141 | << " / DATA = " << std::hex << cache_rdata << std::endl; |
---|
2142 | #endif |
---|
2143 | } |
---|
2144 | } |
---|
2145 | else { |
---|
2146 | // uncacheable read |
---|
2147 | r_dcache_vci_paddr = paddr; |
---|
2148 | r_dcache_vci_unc_be = m_dreq.be; |
---|
2149 | r_dcache_vci_unc_write = false; |
---|
2150 | r_dcache_vci_unc_req = true; |
---|
2151 | r_dcache_fsm = DCACHE_UNC_WAIT; |
---|
2152 | #if DEBUG_DCACHE |
---|
2153 | if (m_debug_dcache_fsm) { |
---|
2154 | std::cout << " <PROC " << name() << " DCACHE_IDLE>" |
---|
2155 | << " READ UNCACHEABLE in dcache" |
---|
2156 | << " / PADDR = " << std::hex << paddr << std::endl; |
---|
2157 | } |
---|
2158 | #endif |
---|
2159 | } |
---|
2160 | } // end READ |
---|
2161 | |
---|
2162 | // LL request (non cachable) |
---|
2163 | // We request a VCI LL transaction to CMD FSM and register |
---|
2164 | // the LL/SC operation in llsc buffer. |
---|
2165 | else if (m_dreq.type == iss_t::DATA_LL) { |
---|
2166 | // register paddr in LLSC buffer |
---|
2167 | r_dcache_llsc_paddr = paddr; |
---|
2168 | r_dcache_llsc_count = LLSC_TIMEOUT; |
---|
2169 | r_dcache_llsc_valid = true; |
---|
2170 | |
---|
2171 | // request an LL VCI transaction and go to DCACHE_LL_WAIT state |
---|
2172 | r_dcache_vci_ll_req = true; |
---|
2173 | r_dcache_vci_paddr = paddr; |
---|
2174 | r_dcache_ll_rsp_count = 0; |
---|
2175 | r_dcache_fsm = DCACHE_LL_WAIT; |
---|
2176 | |
---|
2177 | } // end LL |
---|
2178 | |
---|
2179 | // WRITE request: |
---|
2180 | // If the TLB is activated and the PTE Dirty bit is not set, we stall |
---|
2181 | // the processor and set the Dirty bit before handling the write request, |
---|
2182 | // going to the DCACHE_DIRTY_GT_PTE state. |
---|
2183 | // If we don't need to set the Dirty bit, we can acknowledge |
---|
2184 | // the processor request, as the write arguments (including the |
---|
2185 | // physical address) are registered in r_dcache_save registers, |
---|
2186 | // and the write will be done in the P1 pipeline stage. |
---|
2187 | else if (m_dreq.type == iss_t::DATA_WRITE) { |
---|
2188 | if ((r_mmu_mode.read() & DATA_TLB_MASK) and not tlb_flags.d) { |
---|
2189 | // Dirty bit must be set |
---|
2190 | // The PTE physical address is obtained from the nline value (dtlb), |
---|
2191 | // and from the virtual address (word index) |
---|
2192 | if (tlb_flags.b) { |
---|
2193 | // PTE1 |
---|
2194 | r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | |
---|
2195 | (paddr_t) ((m_dreq.addr >> 19) & 0x3c); |
---|
2196 | } |
---|
2197 | else { |
---|
2198 | // PTE2 |
---|
2199 | r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | |
---|
2200 | (paddr_t) ((m_dreq.addr >> 9) & 0x38); |
---|
2201 | } |
---|
2202 | r_dcache_fsm = DCACHE_DIRTY_GET_PTE; |
---|
2203 | } |
---|
2204 | else { |
---|
2205 | // Write request accepted |
---|
2206 | // cleaning llsc buffer if address matching |
---|
2207 | if (paddr == r_dcache_llsc_paddr.read()) { |
---|
2208 | r_dcache_llsc_valid = false; |
---|
2209 | } |
---|
2210 | |
---|
2211 | if (not cacheable) { |
---|
2212 | r_dcache_vci_paddr = paddr; |
---|
2213 | r_dcache_vci_wdata = m_dreq.wdata; |
---|
2214 | r_dcache_vci_unc_write = true; |
---|
2215 | r_dcache_vci_unc_be = m_dreq.be; |
---|
2216 | r_dcache_vci_unc_req = true; |
---|
2217 | r_dcache_fsm = DCACHE_UNC_WAIT; |
---|
2218 | } |
---|
2219 | else { |
---|
2220 | // response to processor |
---|
2221 | m_drsp.valid = true; |
---|
2222 | // activating P1 stage |
---|
2223 | wbuf_request = true; |
---|
2224 | updt_request = (cache_state == CACHE_SLOT_STATE_VALID); |
---|
2225 | } |
---|
2226 | } |
---|
2227 | } // end WRITE |
---|
2228 | |
---|
2229 | // SC request: |
---|
2230 | // If the TLB is activated and the PTE Dirty bit is not set, we stall |
---|
2231 | // the processor and set the Dirty bit before handling the write request, |
---|
2232 | // going to the DCACHE_DIRTY_GT_PTE state. |
---|
2233 | // If we don't need to set the Dirty bit, we test the llsc buffer: |
---|
2234 | // If failure, we send a negative response to processor. |
---|
2235 | // If success, we request a SC transaction to CMD FSM and go |
---|
2236 | // to DCACHE_SC_WAIT state. |
---|
2237 | // We don't check a possible write hit in dcache, as the cache update |
---|
2238 | // is done by the coherence transaction induced by the SC... |
---|
2239 | else if (m_dreq.type == iss_t::DATA_SC) { |
---|
2240 | if ((r_mmu_mode.read() & DATA_TLB_MASK) and not tlb_flags.d) { |
---|
2241 | // Dirty bit must be set |
---|
2242 | // The PTE physical address is obtained from the nline value (dtlb), |
---|
2243 | // and the word index (virtual address) |
---|
2244 | if (tlb_flags.b) { |
---|
2245 | // PTE1 |
---|
2246 | r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | |
---|
2247 | (paddr_t) ((m_dreq.addr >> 19) & 0x3c); |
---|
2248 | } |
---|
2249 | else { |
---|
2250 | // PTE2 |
---|
2251 | r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | |
---|
2252 | (paddr_t) ((m_dreq.addr >> 9) & 0x38); |
---|
2253 | } |
---|
2254 | r_dcache_fsm = DCACHE_DIRTY_GET_PTE; |
---|
2255 | m_drsp.valid = false; |
---|
2256 | m_drsp.error = false; |
---|
2257 | m_drsp.rdata = 0; |
---|
2258 | } |
---|
2259 | else { |
---|
2260 | // SC request accepted |
---|
2261 | // checking local success |
---|
2262 | if (r_dcache_llsc_valid.read() and |
---|
2263 | (r_dcache_llsc_paddr.read() == paddr)) { |
---|
2264 | // local success |
---|
2265 | // request an SC CMD and go to DCACHE_SC_WAIT state |
---|
2266 | r_dcache_vci_paddr = paddr; |
---|
2267 | r_dcache_vci_sc_req = true; |
---|
2268 | r_dcache_vci_sc_data = m_dreq.wdata; |
---|
2269 | r_dcache_fsm = DCACHE_SC_WAIT; |
---|
2270 | } |
---|
2271 | else { |
---|
2272 | // local fail |
---|
2273 | m_drsp.valid = true; |
---|
2274 | m_drsp.error = false; |
---|
2275 | m_drsp.rdata = 0x1; |
---|
2276 | } |
---|
2277 | } |
---|
2278 | } // end SC |
---|
2279 | } // end valid_req |
---|
2280 | } // end if read/write/ll/sc request |
---|
2281 | } // end processor request |
---|
2282 | |
---|
2283 | // itlb miss request |
---|
2284 | else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss) { |
---|
2285 | r_dcache_tlb_ins = true; |
---|
2286 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
2287 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
2288 | } |
---|
2289 | |
---|
2290 | // Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req |
---|
2291 | r_dcache_updt_req = updt_request; |
---|
2292 | r_dcache_wbuf_req = wbuf_request or (r_dcache_wbuf_req.read() and wbuf_write_miss); |
---|
2293 | break; |
---|
2294 | } |
---|
2295 | ///////////////////// |
---|
2296 | case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss. |
---|
2297 | // Input arguments are: |
---|
2298 | // - r_dcache_tlb_vaddr |
---|
2299 | // - r_dcache_tlb_ins (true when itlb miss) |
---|
2300 | // The sub-fsm access the dcache to find the missing TLB entry, |
---|
2301 | // and activates the cache miss procedure in case of miss. |
---|
2302 | // It bypass the first level page table access if possible. |
---|
2303 | // It uses atomic access to update the R/L access bits |
---|
2304 | // in the page table if required. |
---|
2305 | // It directly updates the itlb or dtlb, and writes into the |
---|
2306 | // r_mmu_ins_* or r_mmu_data* error reporting registers. |
---|
2307 | { |
---|
2308 | uint32_t ptba = 0; |
---|
2309 | bool bypass; |
---|
2310 | paddr_t pte_paddr; |
---|
2311 | |
---|
2312 | // evaluate bypass in order to skip first level page table access |
---|
2313 | if (r_dcache_tlb_ins.read()) { |
---|
2314 | // itlb miss |
---|
2315 | bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
2316 | } |
---|
2317 | else { |
---|
2318 | // dtlb miss |
---|
2319 | bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
2320 | } |
---|
2321 | |
---|
2322 | if (not bypass) { |
---|
2323 | // Try to read PTE1/PTD1 in dcache |
---|
2324 | pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) | |
---|
2325 | ((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); |
---|
2326 | r_dcache_tlb_paddr = pte_paddr; |
---|
2327 | r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
2328 | } |
---|
2329 | else { |
---|
2330 | // Try to read PTE2 in dcache |
---|
2331 | pte_paddr = (paddr_t) ptba << PAGE_K_NBITS | |
---|
2332 | (paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3); |
---|
2333 | r_dcache_tlb_paddr = pte_paddr; |
---|
2334 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
2335 | } |
---|
2336 | |
---|
2337 | #if DEBUG_DCACHE |
---|
2338 | if (m_debug_dcache_fsm) { |
---|
2339 | if (r_dcache_tlb_ins.read()) { |
---|
2340 | std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss"; |
---|
2341 | } |
---|
2342 | else { |
---|
2343 | std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss"; |
---|
2344 | std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() |
---|
2345 | << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) |
---|
2346 | << " / BYPASS = " << bypass |
---|
2347 | << " / PTE_ADR = " << pte_paddr << std::endl; |
---|
2348 | } |
---|
2349 | } |
---|
2350 | #endif |
---|
2351 | |
---|
2352 | break; |
---|
2353 | } |
---|
2354 | ///////////////////////// |
---|
2355 | case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache |
---|
2356 | { |
---|
2357 | uint32_t entry; |
---|
2358 | size_t way; |
---|
2359 | size_t set; |
---|
2360 | size_t word; |
---|
2361 | int cache_state; |
---|
2362 | |
---|
2363 | r_dcache.read(r_dcache_tlb_paddr.read(), |
---|
2364 | &entry, |
---|
2365 | &way, |
---|
2366 | &set, |
---|
2367 | &word, |
---|
2368 | &cache_state); |
---|
2369 | |
---|
2370 | if (cache_state == CACHE_SLOT_STATE_VALID) { |
---|
2371 | // hit in dcache |
---|
2372 | if (not (entry & PTE_V_MASK)) { |
---|
2373 | // unmapped |
---|
2374 | if (r_dcache_tlb_ins.read()) { |
---|
2375 | r_mmu_ietr = MMU_READ_PT1_UNMAPPED; |
---|
2376 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
2377 | r_icache_tlb_miss_req = false; |
---|
2378 | r_icache_tlb_rsp_error = true; |
---|
2379 | } |
---|
2380 | else { |
---|
2381 | r_mmu_detr = MMU_READ_PT1_UNMAPPED; |
---|
2382 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
2383 | m_drsp.valid = true; |
---|
2384 | m_drsp.error = true; |
---|
2385 | } |
---|
2386 | r_dcache_fsm = DCACHE_IDLE; |
---|
2387 | |
---|
2388 | #if DEBUG_DCACHE |
---|
2389 | if (m_debug_dcache_fsm) { |
---|
2390 | std::cout << " <PROC " << name() |
---|
2391 | << " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped" |
---|
2392 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
2393 | << std::dec << " / way = " << way |
---|
2394 | << std::dec << " / set = " << set |
---|
2395 | << std::dec << " / word = " << word |
---|
2396 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
2397 | } |
---|
2398 | #endif |
---|
2399 | } |
---|
2400 | else if (entry & PTE_T_MASK) { |
---|
2401 | // PTD : me must access PT2 |
---|
2402 | // mark the cache line ac containing a PTD |
---|
2403 | r_dcache_contains_ptd[m_dcache_sets * way + set] = true; |
---|
2404 | |
---|
2405 | // register bypass |
---|
2406 | if (r_dcache_tlb_ins.read()) { |
---|
2407 | // itlb |
---|
2408 | r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
2409 | entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1), |
---|
2410 | r_dcache_tlb_paddr.read() / (m_icache_words << 2)); |
---|
2411 | } |
---|
2412 | else { |
---|
2413 | // dtlb |
---|
2414 | r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
2415 | entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1), |
---|
2416 | r_dcache_tlb_paddr.read() / (m_dcache_words << 2)); |
---|
2417 | } |
---|
2418 | r_dcache_tlb_paddr = |
---|
2419 | (paddr_t) (entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS | |
---|
2420 | (paddr_t) (((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); |
---|
2421 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
2422 | |
---|
2423 | #if DEBUG_DCACHE |
---|
2424 | if (m_debug_dcache_fsm) { |
---|
2425 | std::cout << " <PROC " << name() |
---|
2426 | << " DCACHE_TLB_PTE1_GET> HIT in dcache" |
---|
2427 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
2428 | << std::dec << " / way = " << way |
---|
2429 | << std::dec << " / set = " << set |
---|
2430 | << std::dec << " / word = " << word |
---|
2431 | << std::hex << " / PTD = " << entry << std::endl; |
---|
2432 | } |
---|
2433 | #endif |
---|
2434 | } |
---|
2435 | else { |
---|
2436 | // PTE1 : we must update the TLB |
---|
2437 | r_dcache_in_tlb[m_icache_sets * way + set] = true; |
---|
2438 | r_dcache_tlb_pte_flags = entry; |
---|
2439 | r_dcache_tlb_cache_way = way; |
---|
2440 | r_dcache_tlb_cache_set = set; |
---|
2441 | r_dcache_tlb_cache_word = word; |
---|
2442 | r_dcache_fsm = DCACHE_TLB_PTE1_SELECT; |
---|
2443 | |
---|
2444 | #if DEBUG_DCACHE |
---|
2445 | if (m_debug_dcache_fsm) { |
---|
2446 | std::cout << " <PROC " << name() |
---|
2447 | << " DCACHE_TLB_PTE1_GET> HIT in dcache" |
---|
2448 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
2449 | << std::dec << " / way = " << way |
---|
2450 | << std::dec << " / set = " << set |
---|
2451 | << std::dec << " / word = " << word |
---|
2452 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
2453 | } |
---|
2454 | #endif |
---|
2455 | } |
---|
2456 | } |
---|
2457 | else { |
---|
2458 | // we must load the missing cache line in dcache |
---|
2459 | r_dcache_vci_miss_req = true; |
---|
2460 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
2461 | |
---|
2462 | // QM debug |
---|
2463 | if (m_debug_dcache_fsm) { |
---|
2464 | std::cout << "(3) In DCACHE_TLB_PTE1_GET, r_dcache_save_paddr <- " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
2465 | } |
---|
2466 | |
---|
2467 | r_dcache_save_paddr = r_dcache_tlb_paddr.read(); |
---|
2468 | r_dcache_miss_type = PTE1_MISS; |
---|
2469 | r_dcache_fsm = DCACHE_MISS_SELECT; |
---|
2470 | |
---|
2471 | #if DEBUG_DCACHE |
---|
2472 | if (m_debug_dcache_fsm) { |
---|
2473 | std::cout << " <PROC " << name() |
---|
2474 | << " DCACHE_TLB_PTE1_GET> MISS in dcache:" |
---|
2475 | << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
2476 | } |
---|
2477 | #endif |
---|
2478 | } |
---|
2479 | break; |
---|
2480 | } |
---|
2481 | //////////////////////////// |
---|
2482 | case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 |
---|
2483 | { |
---|
2484 | size_t way; |
---|
2485 | size_t set; |
---|
2486 | |
---|
2487 | if (r_dcache_tlb_ins.read()) { |
---|
2488 | r_itlb.select(r_dcache_tlb_vaddr.read(), |
---|
2489 | true, // PTE1 |
---|
2490 | &way, |
---|
2491 | &set); |
---|
2492 | } |
---|
2493 | else { |
---|
2494 | r_dtlb.select(r_dcache_tlb_vaddr.read(), |
---|
2495 | true, // PTE1 |
---|
2496 | &way, |
---|
2497 | &set); |
---|
2498 | } |
---|
2499 | r_dcache_tlb_way = way; |
---|
2500 | r_dcache_tlb_set = set; |
---|
2501 | r_dcache_fsm = DCACHE_TLB_PTE1_UPDT; |
---|
2502 | |
---|
2503 | #if DEBUG_DCACHE |
---|
2504 | if (m_debug_dcache_fsm) { |
---|
2505 | if (r_dcache_tlb_ins.read()) { |
---|
2506 | std::cout << " <PROC " << name() << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:"; |
---|
2507 | } |
---|
2508 | else { |
---|
2509 | std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:"; |
---|
2510 | } |
---|
2511 | std::cout << " way = " << std::dec << way << " / set = " << set << std::endl; |
---|
2512 | } |
---|
2513 | #endif |
---|
2514 | break; |
---|
2515 | } |
---|
2516 | ////////////////////////// |
---|
2517 | case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit |
---|
2518 | // - if L/R bit already set, exit the sub-fsm. |
---|
2519 | // - if not, we update the page table but we dont write |
---|
2520 | // neither in DCACHE, nor in TLB, as this will be done by |
---|
2521 | // the coherence mechanism. |
---|
2522 | { |
---|
2523 | paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); |
---|
2524 | uint32_t pte = r_dcache_tlb_pte_flags.read(); |
---|
2525 | bool pt_updt = false; |
---|
2526 | bool local = true; |
---|
2527 | |
---|
2528 | // We should compute the access locality: |
---|
2529 | // The PPN MSB bits define the destination cluster index. |
---|
2530 | // The m_srcid MSB bits define the source cluster index. |
---|
2531 | // The number of bits to compare depends on the number of clusters, |
---|
2532 | // and can be obtained in the mapping table. |
---|
2533 | // As long as this computation is not done, all access are local. |
---|
2534 | |
---|
2535 | if (local) { |
---|
2536 | // local access |
---|
2537 | if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) { |
---|
2538 | // we must set the L bit |
---|
2539 | pt_updt = true; |
---|
2540 | r_dcache_vci_cas_old = pte; |
---|
2541 | r_dcache_vci_cas_new = pte | PTE_L_MASK; |
---|
2542 | pte = pte | PTE_L_MASK; |
---|
2543 | r_dcache_tlb_pte_flags = pte; |
---|
2544 | } |
---|
2545 | } |
---|
2546 | else { |
---|
2547 | // remote access |
---|
2548 | if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) { |
---|
2549 | // we must set the R bit |
---|
2550 | pt_updt = true; |
---|
2551 | r_dcache_vci_cas_old = pte; |
---|
2552 | r_dcache_vci_cas_new = pte | PTE_R_MASK; |
---|
2553 | pte = pte | PTE_R_MASK; |
---|
2554 | r_dcache_tlb_pte_flags = pte; |
---|
2555 | } |
---|
2556 | } |
---|
2557 | |
---|
2558 | if (not pt_updt) { |
---|
2559 | // update TLB and return |
---|
2560 | if (r_dcache_tlb_ins.read()) { |
---|
2561 | r_itlb.write(true, // 2M page |
---|
2562 | pte, |
---|
2563 | 0, // argument unused for a PTE1 |
---|
2564 | r_dcache_tlb_vaddr.read(), |
---|
2565 | r_dcache_tlb_way.read(), |
---|
2566 | r_dcache_tlb_set.read(), |
---|
2567 | nline); |
---|
2568 | |
---|
2569 | #if DEBUG_DCACHE |
---|
2570 | if (m_debug_dcache_fsm) { |
---|
2571 | std::cout << " <PROC " << name() |
---|
2572 | << " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB" |
---|
2573 | << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
2574 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
2575 | r_itlb.printTrace(); |
---|
2576 | } |
---|
2577 | #endif |
---|
2578 | } |
---|
2579 | else { |
---|
2580 | r_dtlb.write(true, // 2M page |
---|
2581 | pte, |
---|
2582 | 0, // argument unused for a PTE1 |
---|
2583 | r_dcache_tlb_vaddr.read(), |
---|
2584 | r_dcache_tlb_way.read(), |
---|
2585 | r_dcache_tlb_set.read(), |
---|
2586 | nline); |
---|
2587 | #if DEBUG_DCACHE |
---|
2588 | if (m_debug_dcache_fsm) { |
---|
2589 | std::cout << " <PROC " << name() |
---|
2590 | << " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB" |
---|
2591 | << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
2592 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
2593 | r_dtlb.printTrace(); |
---|
2594 | } |
---|
2595 | #endif |
---|
2596 | } |
---|
2597 | r_dcache_fsm = DCACHE_TLB_RETURN; |
---|
2598 | } |
---|
2599 | else { |
---|
2600 | // update page table but not TLB |
---|
2601 | r_dcache_fsm = DCACHE_TLB_LR_UPDT; |
---|
2602 | |
---|
2603 | #if DEBUG_DCACHE |
---|
2604 | if (m_debug_dcache_fsm) { |
---|
2605 | std::cout << " <PROC " << name() |
---|
2606 | << " DCACHE_TLB_PTE1_UPDT> L/R bit update required" |
---|
2607 | << std::endl; |
---|
2608 | } |
---|
2609 | #endif |
---|
2610 | } |
---|
2611 | break; |
---|
2612 | } |
---|
2613 | ///////////////////////// |
---|
2614 | case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache |
---|
2615 | { |
---|
2616 | uint32_t pte_flags; |
---|
2617 | uint32_t pte_ppn; |
---|
2618 | size_t way; |
---|
2619 | size_t set; |
---|
2620 | size_t word; |
---|
2621 | int cache_state; |
---|
2622 | |
---|
2623 | r_dcache.read(r_dcache_tlb_paddr.read(), |
---|
2624 | &pte_flags, |
---|
2625 | &pte_ppn, |
---|
2626 | &way, |
---|
2627 | &set, |
---|
2628 | &word, |
---|
2629 | &cache_state); |
---|
2630 | |
---|
2631 | if (cache_state == CACHE_SLOT_STATE_VALID) { |
---|
2632 | // hit in dcache |
---|
2633 | if (not (pte_flags & PTE_V_MASK)) { |
---|
2634 | // unmapped |
---|
2635 | if (r_dcache_tlb_ins.read()) { |
---|
2636 | r_mmu_ietr = MMU_READ_PT2_UNMAPPED; |
---|
2637 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
2638 | r_icache_tlb_miss_req = false; |
---|
2639 | r_icache_tlb_rsp_error = true; |
---|
2640 | } |
---|
2641 | else { |
---|
2642 | r_mmu_detr = MMU_READ_PT2_UNMAPPED; |
---|
2643 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
2644 | m_drsp.valid = true; |
---|
2645 | m_drsp.error = true; |
---|
2646 | } |
---|
2647 | r_dcache_fsm = DCACHE_IDLE; |
---|
2648 | |
---|
2649 | #if DEBUG_DCACHE |
---|
2650 | if (m_debug_dcache_fsm) { |
---|
2651 | std::cout << " <PROC " << name() |
---|
2652 | << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped" |
---|
2653 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
2654 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
2655 | } |
---|
2656 | #endif |
---|
2657 | } |
---|
2658 | else { |
---|
2659 | // mapped : we must update the TLB |
---|
2660 | r_dcache_in_tlb[m_dcache_sets * way + set] = true; |
---|
2661 | r_dcache_tlb_pte_flags = pte_flags; |
---|
2662 | r_dcache_tlb_pte_ppn = pte_ppn; |
---|
2663 | r_dcache_tlb_cache_way = way; |
---|
2664 | r_dcache_tlb_cache_set = set; |
---|
2665 | r_dcache_tlb_cache_word = word; |
---|
2666 | r_dcache_fsm = DCACHE_TLB_PTE2_SELECT; |
---|
2667 | |
---|
2668 | #if DEBUG_DCACHE |
---|
2669 | if (m_debug_dcache_fsm) { |
---|
2670 | std::cout << " <PROC " << name() |
---|
2671 | << " DCACHE_TLB_PTE2_GET> HIT in dcache:" |
---|
2672 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
2673 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
2674 | } |
---|
2675 | #endif |
---|
2676 | } |
---|
2677 | } |
---|
2678 | else { |
---|
2679 | // we must load the missing cache line in dcache |
---|
2680 | r_dcache_fsm = DCACHE_MISS_SELECT; |
---|
2681 | r_dcache_vci_miss_req = true; |
---|
2682 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
2683 | |
---|
2684 | // QM debug |
---|
2685 | if (m_debug_dcache_fsm) { |
---|
2686 | std::cout << "(4) In DCACHE_TLB_PTE2_GET, r_dcache_save_paddr <- " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
2687 | } |
---|
2688 | r_dcache_save_paddr = r_dcache_tlb_paddr.read(); |
---|
2689 | r_dcache_miss_type = PTE2_MISS; |
---|
2690 | |
---|
2691 | #if DEBUG_DCACHE |
---|
2692 | if (m_debug_dcache_fsm) { |
---|
2693 | std::cout << " <PROC " << name() |
---|
2694 | << " DCACHE_TLB_PTE2_GET> MISS in dcache:" |
---|
2695 | << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
2696 | } |
---|
2697 | #endif |
---|
2698 | } |
---|
2699 | break; |
---|
2700 | } |
---|
2701 | //////////////////////////// |
---|
2702 | case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2 |
---|
2703 | { |
---|
2704 | size_t way; |
---|
2705 | size_t set; |
---|
2706 | |
---|
2707 | if (r_dcache_tlb_ins.read()) { |
---|
2708 | r_itlb.select(r_dcache_tlb_vaddr.read(), |
---|
2709 | false, // PTE2 |
---|
2710 | &way, |
---|
2711 | &set); |
---|
2712 | } |
---|
2713 | else { |
---|
2714 | r_dtlb.select(r_dcache_tlb_vaddr.read(), |
---|
2715 | false, // PTE2 |
---|
2716 | &way, |
---|
2717 | &set); |
---|
2718 | } |
---|
2719 | |
---|
2720 | #if DEBUG_DCACHE |
---|
2721 | if (m_debug_dcache_fsm) { |
---|
2722 | if (r_dcache_tlb_ins.read()) { |
---|
2723 | std::cout << " <PROC " << name() |
---|
2724 | << " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:"; |
---|
2725 | } |
---|
2726 | else { |
---|
2727 | std::cout << " <PROC " << name() |
---|
2728 | << " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:"; |
---|
2729 | } |
---|
2730 | std::cout << " way = " << std::dec << way |
---|
2731 | << " / set = " << set << std::endl; |
---|
2732 | } |
---|
2733 | #endif |
---|
2734 | r_dcache_tlb_way = way; |
---|
2735 | r_dcache_tlb_set = set; |
---|
2736 | r_dcache_fsm = DCACHE_TLB_PTE2_UPDT; |
---|
2737 | break; |
---|
2738 | } |
---|
2739 | ////////////////////////// |
---|
2740 | case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit |
---|
2741 | // - if L/R bit already set, exit the sub-fsm. |
---|
2742 | // - if not, we update the page table but we dont write |
---|
2743 | // neither in DCACHE, nor in TLB, as this will be done by |
---|
2744 | // the coherence mechanism. |
---|
2745 | { |
---|
2746 | paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); |
---|
2747 | uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); |
---|
2748 | uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); |
---|
2749 | bool pt_updt = false; |
---|
2750 | bool local = true; |
---|
2751 | |
---|
2752 | // We should compute the access locality: |
---|
2753 | // The PPN MSB bits define the destination cluster index. |
---|
2754 | // The m_srcid MSB bits define the source cluster index. |
---|
2755 | // The number of bits to compare depends on the number of clusters, |
---|
2756 | // and can be obtained in the mapping table. |
---|
2757 | // As long as this computation is not done, all access are local. |
---|
2758 | |
---|
2759 | if (local) { |
---|
2760 | // local access |
---|
2761 | if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) { |
---|
2762 | // we must set the L bit |
---|
2763 | pt_updt = true; |
---|
2764 | r_dcache_vci_cas_old = pte_flags; |
---|
2765 | r_dcache_vci_cas_new = pte_flags | PTE_L_MASK; |
---|
2766 | pte_flags = pte_flags | PTE_L_MASK; |
---|
2767 | r_dcache_tlb_pte_flags = pte_flags; |
---|
2768 | } |
---|
2769 | } |
---|
2770 | else { |
---|
2771 | // remote access |
---|
2772 | if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) { |
---|
2773 | // we must set the R bit |
---|
2774 | pt_updt = true; |
---|
2775 | r_dcache_vci_cas_old = pte_flags; |
---|
2776 | r_dcache_vci_cas_new = pte_flags | PTE_R_MASK; |
---|
2777 | pte_flags = pte_flags | PTE_R_MASK; |
---|
2778 | r_dcache_tlb_pte_flags = pte_flags; |
---|
2779 | } |
---|
2780 | } |
---|
2781 | |
---|
2782 | if (not pt_updt) { |
---|
2783 | // update TLB |
---|
2784 | if (r_dcache_tlb_ins.read()) { |
---|
2785 | r_itlb.write(false, // 4K page |
---|
2786 | pte_flags, |
---|
2787 | pte_ppn, |
---|
2788 | r_dcache_tlb_vaddr.read(), |
---|
2789 | r_dcache_tlb_way.read(), |
---|
2790 | r_dcache_tlb_set.read(), |
---|
2791 | nline); |
---|
2792 | |
---|
2793 | #if DEBUG_DCACHE |
---|
2794 | if (m_debug_dcache_fsm) { |
---|
2795 | std::cout << " <PROC " << name() |
---|
2796 | << " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB" |
---|
2797 | << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
2798 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
2799 | r_itlb.printTrace(); |
---|
2800 | } |
---|
2801 | #endif |
---|
2802 | } |
---|
2803 | else { |
---|
2804 | r_dtlb.write(false, // 4K page |
---|
2805 | pte_flags, |
---|
2806 | pte_ppn, |
---|
2807 | r_dcache_tlb_vaddr.read(), |
---|
2808 | r_dcache_tlb_way.read(), |
---|
2809 | r_dcache_tlb_set.read(), |
---|
2810 | nline); |
---|
2811 | |
---|
2812 | #if DEBUG_DCACHE |
---|
2813 | if (m_debug_dcache_fsm) { |
---|
2814 | std::cout << " <PROC " << name() |
---|
2815 | << " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB" |
---|
2816 | << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
2817 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
2818 | r_dtlb.printTrace(); |
---|
2819 | } |
---|
2820 | #endif |
---|
2821 | |
---|
2822 | } |
---|
2823 | r_dcache_fsm = DCACHE_TLB_RETURN; |
---|
2824 | } |
---|
2825 | else { |
---|
2826 | // update page table but not TLB |
---|
2827 | r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update |
---|
2828 | |
---|
2829 | #if DEBUG_DCACHE |
---|
2830 | if (m_debug_dcache_fsm) { |
---|
2831 | std::cout << " <PROC " << name() |
---|
2832 | << " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl; |
---|
2833 | } |
---|
2834 | #endif |
---|
2835 | } |
---|
2836 | break; |
---|
2837 | } |
---|
2838 | //////////////////////// |
---|
2839 | case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit |
---|
2840 | { |
---|
2841 | #if DEBUG_DCACHE |
---|
2842 | if (m_debug_dcache_fsm) { |
---|
2843 | std::cout << " <PROC " << name() |
---|
2844 | << " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl; |
---|
2845 | } |
---|
2846 | #endif |
---|
2847 | // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set |
---|
2848 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
2849 | |
---|
2850 | // checking llsc reservation buffer |
---|
2851 | if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read()) { |
---|
2852 | r_dcache_llsc_valid = false; |
---|
2853 | } |
---|
2854 | |
---|
2855 | // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state |
---|
2856 | r_dcache_vci_cas_req = true; |
---|
2857 | r_dcache_fsm = DCACHE_TLB_LR_WAIT; |
---|
2858 | break; |
---|
2859 | } |
---|
2860 | //////////////////////// |
---|
2861 | case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit. |
---|
2862 | // We consume the response in rsp FIFO, |
---|
2863 | // and exit the sub-fsm, but we don't |
---|
2864 | // analyse the response, because we don't |
---|
2865 | // care if the L/R bit update is not done. |
---|
2866 | // We must take the coherence requests because |
---|
2867 | // there is a risk of dead-lock |
---|
2868 | |
---|
2869 | { |
---|
2870 | if (r_vci_rsp_data_error.read()) { |
---|
2871 | std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl; |
---|
2872 | std::cout << "This should not happen in this state" << std::endl; |
---|
2873 | exit(0); |
---|
2874 | } |
---|
2875 | else if (r_vci_rsp_fifo_dcache.rok()) { |
---|
2876 | // response available |
---|
2877 | #if DEBUG_DCACHE |
---|
2878 | if (m_debug_dcache_fsm) { |
---|
2879 | std::cout << " <PROC " << name() << " DCACHE_TLB_LR_WAIT> SC response received" << std::endl; |
---|
2880 | } |
---|
2881 | #endif |
---|
2882 | vci_rsp_fifo_dcache_get = true; |
---|
2883 | r_dcache_fsm = DCACHE_TLB_RETURN; |
---|
2884 | } |
---|
2885 | break; |
---|
2886 | } |
---|
2887 | /////////////////////// |
---|
2888 | case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type |
---|
2889 | { |
---|
2890 | #if DEBUG_DCACHE |
---|
2891 | if (m_debug_dcache_fsm) { |
---|
2892 | std::cout << " <PROC " << name() |
---|
2893 | << " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl; |
---|
2894 | } |
---|
2895 | #endif |
---|
2896 | if (r_dcache_tlb_ins.read()) { |
---|
2897 | r_icache_tlb_miss_req = false; |
---|
2898 | } |
---|
2899 | r_dcache_fsm = DCACHE_IDLE; |
---|
2900 | break; |
---|
2901 | } |
---|
2902 | /////////////////////// |
---|
2903 | case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written, |
---|
2904 | // and both itlb and dtlb must be flushed. |
---|
2905 | // Caution : the itlb miss requests must be taken |
---|
2906 | // to avoid dead-lock in case of simultaneous ITLB miss |
---|
2907 | // Caution : the clack and cc requests must be taken |
---|
2908 | // to avoid dead-lock |
---|
2909 | { |
---|
2910 | // itlb miss request |
---|
2911 | if (r_icache_tlb_miss_req.read()) { |
---|
2912 | r_dcache_tlb_ins = true; |
---|
2913 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
2914 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
2915 | break; |
---|
2916 | } |
---|
2917 | |
---|
2918 | if (not r_dcache_xtn_req.read()) { |
---|
2919 | r_dtlb.flush(); |
---|
2920 | r_mmu_ptpr = m_dreq.wdata; |
---|
2921 | r_dcache_fsm = DCACHE_IDLE; |
---|
2922 | m_drsp.valid = true; |
---|
2923 | } |
---|
2924 | break; |
---|
2925 | } |
---|
2926 | ///////////////////// |
---|
2927 | case DCACHE_XTN_SYNC: // waiting until write buffer empty |
---|
2928 | // The coherence request must be taken |
---|
2929 | // as there is a risk of dead-lock |
---|
2930 | { |
---|
2931 | if (r_wbuf.empty()) { |
---|
2932 | m_drsp.valid = true; |
---|
2933 | r_dcache_fsm = DCACHE_IDLE; |
---|
2934 | } |
---|
2935 | break; |
---|
2936 | } |
---|
2937 | //////////////////////// |
---|
2938 | case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM |
---|
2939 | case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken |
---|
2940 | case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache |
---|
2941 | case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss, |
---|
2942 | case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss |
---|
2943 | |
---|
2944 | { |
---|
2945 | // itlb miss request |
---|
2946 | if (r_icache_tlb_miss_req.read()) { |
---|
2947 | r_dcache_tlb_ins = true; |
---|
2948 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
2949 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
2950 | break; |
---|
2951 | } |
---|
2952 | |
---|
2953 | // test if XTN request to icache completed |
---|
2954 | if (not r_dcache_xtn_req.read()) { |
---|
2955 | r_dcache_fsm = DCACHE_IDLE; |
---|
2956 | m_drsp.valid = true; |
---|
2957 | } |
---|
2958 | break; |
---|
2959 | } |
---|
2960 | ///////////////////////// |
---|
2961 | case DCACHE_XTN_DC_FLUSH: // Invalidate sequentially all cache lines, using |
---|
2962 | // r_dcache_flush_count as a slot counter, |
---|
2963 | // looping in this state until all slots have been visited. |
---|
2964 | // It can require two cycles per slot: |
---|
2965 | // We test here the slot state, and make the actual inval |
---|
2966 | // (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state. |
---|
2967 | // A cleanup request is generated for each valid line. |
---|
2968 | // returns to IDLE and flush TLBs when last slot |
---|
2969 | { |
---|
2970 | int state; |
---|
2971 | paddr_t tag; |
---|
2972 | size_t way = r_dcache_flush_count.read() / m_dcache_sets; |
---|
2973 | size_t set = r_dcache_flush_count.read() % m_dcache_sets; |
---|
2974 | |
---|
2975 | r_dcache.read_dir(way, |
---|
2976 | set, |
---|
2977 | &tag, |
---|
2978 | &state); |
---|
2979 | |
---|
2980 | if (state == CACHE_SLOT_STATE_VALID) { |
---|
2981 | // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory |
---|
2982 | r_dcache_miss_way = way; |
---|
2983 | r_dcache_miss_set = set; |
---|
2984 | r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; |
---|
2985 | } |
---|
2986 | else if (r_dcache_flush_count.read() == (m_dcache_sets * m_dcache_ways - 1)) { |
---|
2987 | // last slot |
---|
2988 | r_dtlb.reset(); |
---|
2989 | r_itlb.reset(); |
---|
2990 | r_dcache_fsm = DCACHE_IDLE; |
---|
2991 | m_drsp.valid = true; |
---|
2992 | } |
---|
2993 | |
---|
2994 | // saturation counter |
---|
2995 | if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1)) { |
---|
2996 | r_dcache_flush_count = r_dcache_flush_count.read() + 1; |
---|
2997 | } |
---|
2998 | break; |
---|
2999 | } |
---|
3000 | //////////////////////////// |
---|
3001 | case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state |
---|
3002 | // and reset directory extension. |
---|
3003 | // returns to IDLE and flush TLBs when last slot |
---|
3004 | { |
---|
3005 | size_t way = r_dcache_miss_way.read(); |
---|
3006 | size_t set = r_dcache_miss_set.read(); |
---|
3007 | |
---|
3008 | r_dcache_in_tlb[m_dcache_sets * way + set] = false; |
---|
3009 | r_dcache_contains_ptd[m_dcache_sets * way + set] = false; |
---|
3010 | |
---|
3011 | r_dcache.write_dir(way, |
---|
3012 | set, |
---|
3013 | CACHE_SLOT_STATE_INVALID); |
---|
3014 | |
---|
3015 | if (r_dcache_flush_count.read() == (m_dcache_sets * m_dcache_ways - 1)) { |
---|
3016 | // last slot |
---|
3017 | r_dtlb.reset(); |
---|
3018 | r_itlb.reset(); |
---|
3019 | r_dcache_fsm = DCACHE_IDLE; |
---|
3020 | m_drsp.valid = true; |
---|
3021 | } |
---|
3022 | else { |
---|
3023 | r_dcache_fsm = DCACHE_XTN_DC_FLUSH; |
---|
3024 | } |
---|
3025 | break; |
---|
3026 | } |
---|
3027 | ///////////////////////// |
---|
3028 | case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request |
---|
3029 | { |
---|
3030 | r_dtlb.inval(r_dcache_save_wdata.read()); |
---|
3031 | r_dcache_fsm = DCACHE_IDLE; |
---|
3032 | m_drsp.valid = true; |
---|
3033 | break; |
---|
3034 | } |
---|
3035 | //////////////////////////// |
---|
3036 | case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address |
---|
3037 | // requires 3 cycles: access tlb, read cache, inval cache |
---|
3038 | // we compute the physical address in this state |
---|
3039 | { |
---|
3040 | paddr_t paddr; |
---|
3041 | bool hit; |
---|
3042 | |
---|
3043 | if (r_mmu_mode.read() & DATA_TLB_MASK) { |
---|
3044 | // dtlb activated |
---|
3045 | hit = r_dtlb.translate(r_dcache_save_wdata.read(), &paddr); |
---|
3046 | } |
---|
3047 | else { |
---|
3048 | // dtlb not activated |
---|
3049 | paddr = (paddr_t) r_dcache_save_wdata.read(); |
---|
3050 | if (vci_param::N > 32) { |
---|
3051 | paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32); |
---|
3052 | } |
---|
3053 | hit = true; |
---|
3054 | } |
---|
3055 | |
---|
3056 | if (hit) { |
---|
3057 | // tlb hit |
---|
3058 | |
---|
3059 | // QM debug |
---|
3060 | if (m_debug_dcache_fsm) { |
---|
3061 | std::cout << "(5) In DCACHE_XTN_DC_INVAL_VA, r_dcache_save_paddr <- " << std::hex << paddr << std::endl; |
---|
3062 | } |
---|
3063 | r_dcache_save_paddr = paddr; |
---|
3064 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
3065 | } |
---|
3066 | else { |
---|
3067 | // tlb miss |
---|
3068 | r_dcache_tlb_ins = false; // dtlb |
---|
3069 | r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); |
---|
3070 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
3071 | } |
---|
3072 | |
---|
3073 | #if DEBUG_DCACHE |
---|
3074 | if (m_debug_dcache_fsm) { |
---|
3075 | std::cout << " <PROC " << name() |
---|
3076 | << " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex |
---|
3077 | << " / VADDR = " << r_dcache_save_wdata.read() |
---|
3078 | << " / PADDR = " << paddr << std::endl; |
---|
3079 | } |
---|
3080 | #endif |
---|
3081 | |
---|
3082 | break; |
---|
3083 | } |
---|
3084 | //////////////////////////// |
---|
3085 | case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address |
---|
3086 | // requires 2 cycles: read cache / inval cache |
---|
3087 | // In this state we read dcache. |
---|
3088 | { |
---|
3089 | size_t way; |
---|
3090 | size_t set; |
---|
3091 | size_t word; |
---|
3092 | int state; |
---|
3093 | |
---|
3094 | r_dcache.read_dir(r_dcache_save_paddr.read(), |
---|
3095 | &state, |
---|
3096 | &way, |
---|
3097 | &set, |
---|
3098 | &word); |
---|
3099 | |
---|
3100 | if (state == CACHE_SLOT_STATE_VALID) { |
---|
3101 | // inval to be done |
---|
3102 | r_dcache_xtn_way = way; |
---|
3103 | r_dcache_xtn_set = set; |
---|
3104 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; |
---|
3105 | } |
---|
3106 | else { |
---|
3107 | // miss : nothing to do |
---|
3108 | r_dcache_fsm = DCACHE_IDLE; |
---|
3109 | m_drsp.valid = true; |
---|
3110 | } |
---|
3111 | |
---|
3112 | #if DEBUG_DCACHE |
---|
3113 | if (m_debug_dcache_fsm) { |
---|
3114 | std::cout << " <PROC " << name() |
---|
3115 | << " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex |
---|
3116 | << " / PADDR = " << r_dcache_save_paddr.read() << std::dec |
---|
3117 | << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) |
---|
3118 | << " / SET = " << set |
---|
3119 | << " / WAY = " << way << std::endl; |
---|
3120 | } |
---|
3121 | #endif |
---|
3122 | break; |
---|
3123 | } |
---|
3124 | //////////////////////////// |
---|
3125 | case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line |
---|
3126 | // Blocked if previous cleanup not completed |
---|
3127 | // Test if itlb or dtlb inval is required |
---|
3128 | { |
---|
3129 | size_t way = r_dcache_xtn_way.read(); |
---|
3130 | size_t set = r_dcache_xtn_set.read(); |
---|
3131 | paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2); |
---|
3132 | |
---|
3133 | r_dcache.write_dir(way, |
---|
3134 | set, |
---|
3135 | CACHE_SLOT_STATE_INVALID); |
---|
3136 | |
---|
3137 | // possible itlb & dtlb invalidate |
---|
3138 | if (r_dcache_in_tlb[way * m_dcache_sets + set]) { |
---|
3139 | r_dcache_tlb_inval_line = nline; |
---|
3140 | r_dcache_tlb_inval_set = 0; |
---|
3141 | r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; |
---|
3142 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
3143 | r_dcache_in_tlb[way * m_dcache_sets + set] = false; |
---|
3144 | } |
---|
3145 | else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) { |
---|
3146 | r_itlb.reset(); |
---|
3147 | r_dtlb.reset(); |
---|
3148 | r_dcache_contains_ptd[way * m_dcache_sets + set] = false; |
---|
3149 | r_dcache_fsm = DCACHE_IDLE; |
---|
3150 | m_drsp.valid = true; |
---|
3151 | } |
---|
3152 | else { |
---|
3153 | r_dcache_fsm = DCACHE_IDLE; |
---|
3154 | m_drsp.valid = true; |
---|
3155 | } |
---|
3156 | |
---|
3157 | #if DEBUG_DCACHE |
---|
3158 | if (m_debug_dcache_fsm) { |
---|
3159 | std::cout << " <PROC " << name() |
---|
3160 | << " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex |
---|
3161 | << " / PADDR = " << r_dcache_save_paddr.read() << std::endl; |
---|
3162 | } |
---|
3163 | #endif |
---|
3164 | break; |
---|
3165 | } |
---|
3166 | ////////////////////////////// |
---|
3167 | case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request |
---|
3168 | { |
---|
3169 | r_dcache_fsm = DCACHE_IDLE; |
---|
3170 | m_drsp.valid = true; |
---|
3171 | break; |
---|
3172 | } |
---|
3173 | //////////////////////// |
---|
3174 | case DCACHE_MISS_SELECT: // Try to select a slot in associative set, |
---|
3175 | // Waiting in this state if no slot available. |
---|
3176 | // If a victim slot has been choosen and the r_icache_cc_send_req is false, |
---|
3177 | // we send the cleanup request in this state. |
---|
3178 | // If not, a r_icache_cleanup_victim_req flip-flop is |
---|
3179 | // utilized for saving this cleanup request, and it will be sent later |
---|
3180 | // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. |
---|
3181 | // The r_icache_miss_clack flip-flop is set |
---|
3182 | // when a cleanup is required |
---|
3183 | { |
---|
3184 | bool found = false; |
---|
3185 | bool cleanup = false; |
---|
3186 | size_t way = 0; |
---|
3187 | size_t set = 0; |
---|
3188 | paddr_t victim = 0; |
---|
3189 | |
---|
3190 | r_dcache.read_select(r_dcache_save_paddr.read(), |
---|
3191 | &victim, |
---|
3192 | &way, |
---|
3193 | &set, |
---|
3194 | &found, |
---|
3195 | &cleanup); |
---|
3196 | |
---|
3197 | if (not found) { |
---|
3198 | break; |
---|
3199 | } |
---|
3200 | else { |
---|
3201 | r_dcache_miss_way = way; |
---|
3202 | r_dcache_miss_set = set; |
---|
3203 | r_dcache_miss_victim = victim; |
---|
3204 | |
---|
3205 | r_dcache_fsm = DCACHE_MISS_VICTIM_CHECK; |
---|
3206 | |
---|
3207 | #if DEBUG_DCACHE |
---|
3208 | if (m_debug_dcache_fsm) { |
---|
3209 | std::cout << " <PROC " << name() |
---|
3210 | << " DCACHE_MISS_SELECT> Select a slot:" << std::dec |
---|
3211 | << " / WAY = " << way |
---|
3212 | << " / SET = " << set |
---|
3213 | << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); |
---|
3214 | if (cleanup) std::cout << " / VICTIM = " << (victim * m_dcache_words * 4) << std::endl; |
---|
3215 | else std::cout << std::endl; |
---|
3216 | } |
---|
3217 | #endif |
---|
3218 | } // end found |
---|
3219 | break; |
---|
3220 | } |
---|
3221 | /////////////////////// |
---|
3222 | case DCACHE_MISS_VICTIM_CHECK: // possibly request itlb or dtlb invalidate |
---|
3223 | { |
---|
3224 | // Invalidation of the line to avoid the "famous" bug |
---|
3225 | // of a direct update matching the previous line while |
---|
3226 | // the missed line is being written |
---|
3227 | size_t way = r_dcache_miss_way.read(); |
---|
3228 | size_t set = r_dcache_miss_set.read(); |
---|
3229 | |
---|
3230 | r_dcache.write_dir(r_dcache_save_paddr.read(), |
---|
3231 | way, |
---|
3232 | set, |
---|
3233 | CACHE_SLOT_STATE_INVALID); |
---|
3234 | |
---|
3235 | // if an itlb or dtlb invalidation is required |
---|
3236 | // the miss response is not handled before the invalidatation is complete |
---|
3237 | if (r_dcache_in_tlb[way * m_dcache_sets + set]) { |
---|
3238 | r_dcache_in_tlb[way * m_dcache_sets + set] = false; |
---|
3239 | |
---|
3240 | r_dcache_tlb_inval_line = r_dcache_miss_victim.read(); |
---|
3241 | r_dcache_tlb_inval_set = 0; |
---|
3242 | r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; |
---|
3243 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
3244 | #if DEBUG_DCACHE |
---|
3245 | if (m_debug_dcache_fsm) { |
---|
3246 | std::cout << " <PROC " << name() |
---|
3247 | << " DCACHE_MISS_VICTIM_CHECK> Line in TLB" << std::dec |
---|
3248 | << " / way = " << way |
---|
3249 | << " / set = " << set |
---|
3250 | << std::hex << |
---|
3251 | " / victim = " << r_dcache_miss_victim.read() |
---|
3252 | << std::dec << std::endl; |
---|
3253 | } |
---|
3254 | #endif |
---|
3255 | } |
---|
3256 | else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) { |
---|
3257 | r_itlb.reset(); |
---|
3258 | r_dtlb.reset(); |
---|
3259 | r_dcache_contains_ptd[way * m_dcache_sets + set] = false; |
---|
3260 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
3261 | #if DEBUG_DCACHE |
---|
3262 | if (m_debug_dcache_fsm) { |
---|
3263 | std::cout << " <PROC " << name() |
---|
3264 | << " DCACHE_MISS_VICTIM_CHECK> Reset ITLB and DTLB" |
---|
3265 | << std::dec << std::endl; |
---|
3266 | } |
---|
3267 | #endif |
---|
3268 | } |
---|
3269 | else { |
---|
3270 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
3271 | } |
---|
3272 | break; |
---|
3273 | } |
---|
3274 | ////////////////////// |
---|
3275 | case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM |
---|
3276 | // This state is in charge of error signaling |
---|
3277 | // There is 5 types of error depending on the requester |
---|
3278 | { |
---|
3279 | if (r_vci_rsp_data_error.read()) { |
---|
3280 | // bus error |
---|
3281 | switch (r_dcache_miss_type.read()) { |
---|
3282 | case PROC_MISS: |
---|
3283 | { |
---|
3284 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
3285 | r_mmu_dbvar = r_dcache_save_vaddr.read(); |
---|
3286 | m_drsp.valid = true; |
---|
3287 | m_drsp.error = true; |
---|
3288 | r_dcache_fsm = DCACHE_IDLE; |
---|
3289 | break; |
---|
3290 | } |
---|
3291 | case PTE1_MISS: |
---|
3292 | { |
---|
3293 | if (r_dcache_tlb_ins.read()) { |
---|
3294 | r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
3295 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
3296 | r_icache_tlb_miss_req = false; |
---|
3297 | r_icache_tlb_rsp_error = true; |
---|
3298 | } |
---|
3299 | else { |
---|
3300 | r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
3301 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
3302 | m_drsp.valid = true; |
---|
3303 | m_drsp.error = true; |
---|
3304 | } |
---|
3305 | r_dcache_fsm = DCACHE_IDLE; |
---|
3306 | break; |
---|
3307 | } |
---|
3308 | case PTE2_MISS: |
---|
3309 | { |
---|
3310 | if (r_dcache_tlb_ins.read()) { |
---|
3311 | r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
3312 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
3313 | r_icache_tlb_miss_req = false; |
---|
3314 | r_icache_tlb_rsp_error = true; |
---|
3315 | } |
---|
3316 | else { |
---|
3317 | r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
3318 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
3319 | m_drsp.valid = true; |
---|
3320 | m_drsp.error = true; |
---|
3321 | } |
---|
3322 | r_dcache_fsm = DCACHE_IDLE; |
---|
3323 | break; |
---|
3324 | } |
---|
3325 | } // end switch type |
---|
3326 | r_vci_rsp_data_error = false; |
---|
3327 | } |
---|
3328 | else if (r_vci_rsp_fifo_dcache.rok()) { |
---|
3329 | // valid response available |
---|
3330 | r_dcache_miss_word = 0; |
---|
3331 | r_dcache_fsm = DCACHE_MISS_DATA_UPDT; |
---|
3332 | } |
---|
3333 | break; |
---|
3334 | } |
---|
3335 | ////////////////////////// |
---|
3336 | case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) |
---|
3337 | { |
---|
3338 | if (r_vci_rsp_fifo_dcache.rok()) { |
---|
3339 | // one word available |
---|
3340 | r_dcache.write(r_dcache_miss_way.read(), |
---|
3341 | r_dcache_miss_set.read(), |
---|
3342 | r_dcache_miss_word.read(), |
---|
3343 | r_vci_rsp_fifo_dcache.read()); |
---|
3344 | #if DEBUG_DCACHE |
---|
3345 | if (m_debug_dcache_fsm) { |
---|
3346 | std::cout << " <PROC " << name() |
---|
3347 | << " DCACHE_MISS_DATA_UPDT> Write one word:" |
---|
3348 | << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() |
---|
3349 | << " / WAY = " << std::dec << r_dcache_miss_way.read() |
---|
3350 | << " / SET = " << r_dcache_miss_set.read() |
---|
3351 | << " / WORD = " << r_dcache_miss_word.read() << std::endl; |
---|
3352 | } |
---|
3353 | #endif |
---|
3354 | vci_rsp_fifo_dcache_get = true; |
---|
3355 | r_dcache_miss_word = r_dcache_miss_word.read() + 1; |
---|
3356 | |
---|
3357 | if (r_dcache_miss_word.read() == (m_dcache_words - 1)) { |
---|
3358 | // last word |
---|
3359 | r_dcache_fsm = DCACHE_MISS_DIR_UPDT; |
---|
3360 | } |
---|
3361 | } |
---|
3362 | break; |
---|
3363 | } |
---|
3364 | ////////////////////////// |
---|
3365 | case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted |
---|
3366 | // and the cleanup ack has not been received, |
---|
3367 | // as indicated by the r_dcache_miss clack. |
---|
3368 | // - If no matching coherence request (r_dcache_inval_miss) |
---|
3369 | // switch directory slot to VALID state. |
---|
3370 | // - If matching coherence request, switch directory slot |
---|
3371 | // to ZOMBI state, and send a cleanup request. |
---|
3372 | { |
---|
3373 | // switch slot to VALID state |
---|
3374 | r_dcache.write_dir(r_dcache_save_paddr.read(), |
---|
3375 | r_dcache_miss_way.read(), |
---|
3376 | r_dcache_miss_set.read(), |
---|
3377 | CACHE_SLOT_STATE_VALID); |
---|
3378 | |
---|
3379 | #if DEBUG_DCACHE |
---|
3380 | if (m_debug_dcache_fsm) { |
---|
3381 | std::cout << " <PROC " << name() |
---|
3382 | << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state" |
---|
3383 | << " PADDR = " << std::hex << r_dcache_save_paddr.read() |
---|
3384 | << " / WAY = " << std::dec << r_dcache_miss_way.read() |
---|
3385 | << " / SET = " << r_dcache_miss_set.read() << std::endl; |
---|
3386 | } |
---|
3387 | #endif |
---|
3388 | |
---|
3389 | // Immediate coherence test: |
---|
3390 | // If we have received one or several updates on the line during the miss, we have stored them |
---|
3391 | // and we update the values now |
---|
3392 | for (std::list<VcacheUpdate>::iterator it = m_dpending_updates.begin(); it != m_dpending_updates.end(); it++) |
---|
3393 | { |
---|
3394 | bool cache_hit; |
---|
3395 | size_t cache_way = 0; |
---|
3396 | size_t cache_set = 0; |
---|
3397 | size_t cache_word = 0; |
---|
3398 | uint32_t cache_rdata = 0; |
---|
3399 | |
---|
3400 | // Test if hit in dcache |
---|
3401 | cache_hit = r_dcache.read_neutral(it->m_addr, |
---|
3402 | &cache_rdata, |
---|
3403 | &cache_way, |
---|
3404 | &cache_set, |
---|
3405 | &cache_word); |
---|
3406 | |
---|
3407 | assert(cache_hit); |
---|
3408 | paddr_t mask = ~((m_dcache_words << 2) - 1); |
---|
3409 | if ((it->m_addr & mask) != (mask & r_dcache_save_paddr.read())) { |
---|
3410 | std::cerr << " <PROC " << name() << " (" << std::hex << m_srcid << ")" |
---|
3411 | << " cycle " << std::dec << m_cpt_total_cycles << " ERROR: it->m_addr = " << std::hex << it->m_addr |
---|
3412 | << " != r_dcache_save_paddr = " << r_dcache_save_paddr.read() << ">" |
---|
3413 | << std::endl; |
---|
3414 | } |
---|
3415 | if (cache_way != r_dcache_miss_way.read()) { |
---|
3416 | std::cerr << " <PROC " << name() << " (" << std::hex << m_srcid << ")" |
---|
3417 | << " cycle " << std::dec << m_cpt_total_cycles << " ERROR: cache_way = " << std::dec << cache_way |
---|
3418 | << " != r_dcache_miss_way = " << r_dcache_miss_way.read() << ">" |
---|
3419 | << std::endl; |
---|
3420 | } |
---|
3421 | if (cache_set != r_dcache_miss_set.read()) { |
---|
3422 | std::cerr << " <PROC " << name() << " (" << std::hex << m_srcid << ")" |
---|
3423 | << " cycle " << std::dec << m_cpt_total_cycles << " ERROR: cache_set = " << std::dec << cache_set |
---|
3424 | << " != r_dcache_miss_set = " << r_dcache_miss_set.read() << ">" |
---|
3425 | << std::endl; |
---|
3426 | } |
---|
3427 | //assert(it->m_addr == r_dcache_save_paddr.read()); |
---|
3428 | assert(cache_way == r_dcache_miss_way.read()); |
---|
3429 | assert(cache_set == r_dcache_miss_set.read()); |
---|
3430 | |
---|
3431 | r_dcache.write(cache_way, cache_set, cache_word, it->m_value, it->m_be); |
---|
3432 | #if DEBUG_DCACHE |
---|
3433 | if (m_debug_dcache_fsm) { |
---|
3434 | std::cout << " <Cache " << name() |
---|
3435 | << " CACHE_MISS_DIR_UPDT> Updating pending update:" |
---|
3436 | << " ADDR = " << std::hex << it->m_addr |
---|
3437 | << " / WAY = " << std::dec << cache_way |
---|
3438 | << " / SET = " << cache_set |
---|
3439 | << " / VALUE = " << std::hex << it->m_value |
---|
3440 | << " / BE = " << it->m_be << std::endl; |
---|
3441 | } |
---|
3442 | #endif |
---|
3443 | } |
---|
3444 | m_dpending_updates.clear(); |
---|
3445 | |
---|
3446 | // reset directory extension |
---|
3447 | size_t way = r_dcache_miss_way.read(); |
---|
3448 | size_t set = r_dcache_miss_set.read(); |
---|
3449 | r_dcache_in_tlb[way * m_dcache_sets + set] = false; |
---|
3450 | r_dcache_contains_ptd[way * m_dcache_sets + set] = false; |
---|
3451 | if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
3452 | else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
3453 | else r_dcache_fsm = DCACHE_IDLE; |
---|
3454 | |
---|
3455 | break; |
---|
3456 | } |
---|
3457 | ///////////////////// |
---|
3458 | case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read |
---|
3459 | { |
---|
3460 | if (r_vci_rsp_data_error.read()) { |
---|
3461 | // bus error |
---|
3462 | if (r_dcache_vci_unc_write.read()) { |
---|
3463 | r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; |
---|
3464 | } |
---|
3465 | else { |
---|
3466 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
3467 | } |
---|
3468 | |
---|
3469 | r_mmu_dbvar = m_dreq.addr; |
---|
3470 | r_vci_rsp_data_error = false; |
---|
3471 | m_drsp.error = true; |
---|
3472 | m_drsp.valid = true; |
---|
3473 | r_dcache_fsm = DCACHE_IDLE; |
---|
3474 | break; |
---|
3475 | } |
---|
3476 | else if (r_vci_rsp_fifo_dcache.rok()) { |
---|
3477 | // data available |
---|
3478 | // consume data |
---|
3479 | vci_rsp_fifo_dcache_get = true; |
---|
3480 | r_dcache_fsm = DCACHE_IDLE; |
---|
3481 | |
---|
3482 | // acknowledge the processor request if it has not been modified |
---|
3483 | if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) { |
---|
3484 | m_drsp.valid = true; |
---|
3485 | m_drsp.error = false; |
---|
3486 | m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
3487 | } |
---|
3488 | } |
---|
3489 | break; |
---|
3490 | } |
---|
3491 | ///////////////////// |
---|
3492 | case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction |
---|
3493 | { |
---|
3494 | if (r_vci_rsp_data_error.read()) { |
---|
3495 | // bus error |
---|
3496 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
3497 | r_mmu_dbvar = m_dreq.addr; |
---|
3498 | r_vci_rsp_data_error = false; |
---|
3499 | m_drsp.error = true; |
---|
3500 | m_drsp.valid = true; |
---|
3501 | r_dcache_fsm = DCACHE_IDLE; |
---|
3502 | break; |
---|
3503 | } |
---|
3504 | else if (r_vci_rsp_fifo_dcache.rok()) { |
---|
3505 | // data available |
---|
3506 | // consume data |
---|
3507 | vci_rsp_fifo_dcache_get = true; |
---|
3508 | |
---|
3509 | if (r_dcache_ll_rsp_count.read() == 0) { |
---|
3510 | // first flit |
---|
3511 | // set key value in llsc reservation buffer |
---|
3512 | r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read(); |
---|
3513 | r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1; |
---|
3514 | } |
---|
3515 | else { |
---|
3516 | // last flit |
---|
3517 | // acknowledge the processor request if it has not been modified |
---|
3518 | if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) { |
---|
3519 | m_drsp.valid = true; |
---|
3520 | m_drsp.error = false; |
---|
3521 | m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
3522 | } |
---|
3523 | r_dcache_fsm = DCACHE_IDLE; |
---|
3524 | } |
---|
3525 | } |
---|
3526 | break; |
---|
3527 | } |
---|
3528 | //////////////////// |
---|
3529 | case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction |
---|
3530 | { |
---|
3531 | if (r_vci_rsp_data_error.read()) { |
---|
3532 | // bus error |
---|
3533 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
3534 | r_mmu_dbvar = m_dreq.addr; |
---|
3535 | r_vci_rsp_data_error = false; |
---|
3536 | m_drsp.error = true; |
---|
3537 | m_drsp.valid = true; |
---|
3538 | r_dcache_fsm = DCACHE_IDLE; |
---|
3539 | break; |
---|
3540 | } |
---|
3541 | else if (r_vci_rsp_fifo_dcache.rok()) { |
---|
3542 | // response available |
---|
3543 | // consume response |
---|
3544 | vci_rsp_fifo_dcache_get = true; |
---|
3545 | m_drsp.valid = true; |
---|
3546 | m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
3547 | r_dcache_fsm = DCACHE_IDLE; |
---|
3548 | } |
---|
3549 | break; |
---|
3550 | } |
---|
3551 | ////////////////////////// |
---|
3552 | case DCACHE_DIRTY_GET_PTE: // This sub_fsm sets the PTE Dirty bit in memory |
---|
3553 | // before handling a processor WRITE or SC request |
---|
3554 | // Input argument is r_dcache_dirty_paddr |
---|
3555 | // In this first state, we get PTE value in dcache |
---|
3556 | // and post a CAS request to CMD FSM |
---|
3557 | { |
---|
3558 | // get PTE in dcache |
---|
3559 | uint32_t pte; |
---|
3560 | size_t way; |
---|
3561 | size_t set; |
---|
3562 | size_t word; // unused |
---|
3563 | int state; |
---|
3564 | |
---|
3565 | r_dcache.read(r_dcache_dirty_paddr.read(), |
---|
3566 | &pte, |
---|
3567 | &way, |
---|
3568 | &set, |
---|
3569 | &word, |
---|
3570 | &state); |
---|
3571 | |
---|
3572 | assert((state == CACHE_SLOT_STATE_VALID) and |
---|
3573 | "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache"); |
---|
3574 | |
---|
3575 | // request CAS transaction to CMD_FSM |
---|
3576 | r_dcache_dirty_way = way; |
---|
3577 | r_dcache_dirty_set = set; |
---|
3578 | |
---|
3579 | // check llsc reservation buffer |
---|
3580 | if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read()) { |
---|
3581 | r_dcache_llsc_valid = false; |
---|
3582 | } |
---|
3583 | |
---|
3584 | // request a CAS CMD and go to DCACHE_DIRTY_WAIT state |
---|
3585 | r_dcache_vci_cas_req = true; |
---|
3586 | r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); |
---|
3587 | r_dcache_vci_cas_old = pte; |
---|
3588 | r_dcache_vci_cas_new = pte | PTE_D_MASK; |
---|
3589 | r_dcache_fsm = DCACHE_DIRTY_WAIT; |
---|
3590 | |
---|
3591 | #if DEBUG_DCACHE |
---|
3592 | if (m_debug_dcache_fsm) { |
---|
3593 | std::cout << " <PROC " << name() |
---|
3594 | << " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex |
---|
3595 | << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() |
---|
3596 | << " / PTE_VALUE = " << pte << std::dec |
---|
3597 | << " / SET = " << set |
---|
3598 | << " / WAY = " << way << std::endl; |
---|
3599 | } |
---|
3600 | #endif |
---|
3601 | break; |
---|
3602 | } |
---|
3603 | /////////////////////// |
---|
3604 | case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, |
---|
3605 | // and return to IDLE state when response is received. |
---|
3606 | // we don't care if the CAS is a failure: |
---|
3607 | // - if the CAS is a success, the coherence mechanism |
---|
3608 | // updates the local copy. |
---|
3609 | // - if the CAS is a failure, we just retry the write. |
---|
3610 | { |
---|
3611 | if (r_vci_rsp_data_error.read()) { |
---|
3612 | std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; |
---|
3613 | std::cout << "This should not happen in this state" << std::endl; |
---|
3614 | exit(0); |
---|
3615 | } |
---|
3616 | else if (r_vci_rsp_fifo_dcache.rok()) { |
---|
3617 | // response available |
---|
3618 | vci_rsp_fifo_dcache_get = true; |
---|
3619 | r_dcache_fsm = DCACHE_IDLE; |
---|
3620 | |
---|
3621 | #if DEBUG_DCACHE |
---|
3622 | if (m_debug_dcache_fsm) { |
---|
3623 | std::cout << " <PROC " << name() |
---|
3624 | << " DCACHE_DIRTY_WAIT> CAS completed" << std::endl; |
---|
3625 | } |
---|
3626 | #endif |
---|
3627 | } |
---|
3628 | break; |
---|
3629 | } |
---|
3630 | |
---|
3631 | |
---|
3632 | /////////////////////////// |
---|
3633 | case DCACHE_INVAL_TLB_SCAN: // Scan sequentially all sets for both ITLB & DTLB |
---|
3634 | // It makes assumption: m_itlb_sets == m_dtlb_sets |
---|
3635 | // All ways are handled in parallel. |
---|
3636 | // We enter this state when a DCACHE line is modified, |
---|
3637 | // and there is a copy in itlb or dtlb. |
---|
3638 | // It can be caused by: |
---|
3639 | // - a coherence inval or updt transaction, |
---|
3640 | // - a line inval caused by a cache miss |
---|
3641 | // - a processor XTN inval request, |
---|
3642 | // - a WRITE hit, |
---|
3643 | // - a Dirty bit update |
---|
3644 | // Input arguments are: |
---|
3645 | // - r_dcache_tlb_inval_line |
---|
3646 | // - r_dcache_tlb_inval_set |
---|
3647 | // - r_dcache_fsm_scan_save |
---|
3648 | { |
---|
3649 | paddr_t line = r_dcache_tlb_inval_line.read(); |
---|
3650 | size_t set = r_dcache_tlb_inval_set.read(); |
---|
3651 | size_t way; |
---|
3652 | bool ok; |
---|
3653 | |
---|
3654 | for (way = 0; way < m_itlb_ways; way++) { |
---|
3655 | ok = r_itlb.inval(line, way, set); |
---|
3656 | #if DEBUG_DCACHE |
---|
3657 | if (m_debug_dcache_fsm and ok) { |
---|
3658 | std::cout << " <PROC " << name() |
---|
3659 | << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex |
---|
3660 | << " line = " << line << std::dec |
---|
3661 | << " / set = " << set |
---|
3662 | << " / way = " << way << std::endl; |
---|
3663 | } |
---|
3664 | #endif |
---|
3665 | } |
---|
3666 | |
---|
3667 | for (way = 0; way < m_dtlb_ways; way++) { |
---|
3668 | ok = r_dtlb.inval(line, way, set); |
---|
3669 | #if DEBUG_DCACHE |
---|
3670 | if (m_debug_dcache_fsm and ok) |
---|
3671 | std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>" |
---|
3672 | << " Invalidate DTLB entry" << std::hex |
---|
3673 | << " / line = " << line << std::dec |
---|
3674 | << " / set = " << set |
---|
3675 | << " / way = " << way << std::endl; |
---|
3676 | #endif |
---|
3677 | } |
---|
3678 | |
---|
3679 | // return to the calling state when TLB inval completed |
---|
3680 | if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1)) { |
---|
3681 | r_dcache_fsm = r_dcache_fsm_scan_save.read(); |
---|
3682 | } |
---|
3683 | r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1; |
---|
3684 | break; |
---|
3685 | } |
---|
3686 | } // end switch r_dcache_fsm |
---|
3687 | |
---|
3688 | ///////////////// wbuf update /////////////////////////////////////////////////////// |
---|
3689 | r_wbuf.update(); |
---|
3690 | |
---|
3691 | ///////////////// llsc update /////////////////////////////////////////////////////// |
---|
3692 | if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1; |
---|
3693 | if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false; |
---|
3694 | |
---|
3695 | //////////////// test processor frozen ////////////////////////////////////////////// |
---|
3696 | // The simulation exit if the number of consecutive frozen cycles |
---|
3697 | // is larger than the m_max_frozen_cycles (constructor parameter) |
---|
3698 | if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid)) { |
---|
3699 | m_cpt_frz_cycles++; // used for instrumentation |
---|
3700 | m_cpt_stop_simulation++; // used for debug |
---|
3701 | if (m_cpt_stop_simulation > m_max_frozen_cycles) { |
---|
3702 | std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl |
---|
3703 | << " stop at cycle " << m_cpt_total_cycles << std::endl |
---|
3704 | << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles |
---|
3705 | << std::endl; |
---|
3706 | r_iss.dump(); |
---|
3707 | exit(1); |
---|
3708 | } |
---|
3709 | } |
---|
3710 | else { |
---|
3711 | m_cpt_stop_simulation = 0; |
---|
3712 | } |
---|
3713 | |
---|
3714 | /////////// execute one iss cycle ///////////////////////////////// |
---|
3715 | { |
---|
3716 | uint32_t it = 0; |
---|
3717 | for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) { |
---|
3718 | if (p_irq[i].read()) { |
---|
3719 | it |= (1 << i); |
---|
3720 | } |
---|
3721 | } |
---|
3722 | r_iss.executeNCycles(1, m_irsp, m_drsp, it); |
---|
3723 | } |
---|
3724 | |
---|
3725 | //////////////////////////////////////////////////////////////////////////// |
---|
3726 | // The VCI_CMD FSM controls the following ressources: |
---|
3727 | // - r_vci_cmd_fsm |
---|
3728 | // - r_vci_cmd_min |
---|
3729 | // - r_vci_cmd_max |
---|
3730 | // - r_vci_cmd_cpt |
---|
3731 | // - r_vci_cmd_imiss_prio |
---|
3732 | // - wbuf (reset) |
---|
3733 | // - r_icache_miss_req (reset) |
---|
3734 | // - r_icache_unc_req (reset) |
---|
3735 | // - r_dcache_vci_miss_req (reset) |
---|
3736 | // - r_dcache_vci_unc_req (reset) |
---|
3737 | // - r_dcache_vci_ll_req (reset) |
---|
3738 | // - r_dcache_vci_sc_req (reset in case of local sc fail) |
---|
3739 | // - r_dcache_vci_cas_req (reset) |
---|
3740 | // |
---|
3741 | // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM. |
---|
3742 | // There are 8 request types, with the following priorities : |
---|
3743 | // 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer |
---|
3744 | // 2 - Data Read Uncachable : r_dcache_vci_unc_req |
---|
3745 | // 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer |
---|
3746 | // 4 - Instruction Uncachable : r_icache_unc_req |
---|
3747 | // 5 - Data Write : r_wbuf.rok() |
---|
3748 | // 6 - Data Linked Load : r_dcache_vci_ll_req |
---|
3749 | // 7 - Data Store Conditionnal: r_dcache_vci_sc_req |
---|
3750 | // 8 - Compare And Swap : r_dcache_vci_cas_req |
---|
3751 | // |
---|
3752 | // As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM |
---|
3753 | // and the VCI_RSP_FSM are fully desynchronized. |
---|
3754 | // |
---|
3755 | // VCI formats: |
---|
3756 | // According to the VCI advanced specification, all read requests packets |
---|
3757 | // (data Uncached, Miss data, instruction Uncached, Miss instruction) |
---|
3758 | // are one word packets. |
---|
3759 | // For write burst packets, all words are in the same cache line, |
---|
3760 | // and addresses must be contiguous (the BE field is 0 in case of "holes"). |
---|
3761 | // The sc command packet implements actually a compare-and-swap mechanism |
---|
3762 | // and the packet contains two flits. |
---|
3763 | //////////////////////////////////////////////////////////////////////////////////// |
---|
3764 | |
---|
3765 | |
---|
3766 | switch (r_vci_cmd_fsm.read()) { |
---|
3767 | ////////////// |
---|
3768 | case CMD_IDLE: |
---|
3769 | { |
---|
3770 | // DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and |
---|
3771 | // ICACHE read requests (r_icache_miss_req) require both a write_buffer access |
---|
3772 | // to check a possible pending write on the same cache line. |
---|
3773 | // As there is only one possible access per cycle to write buffer, we implement |
---|
3774 | // a round-robin priority between DCACHE and ICACHE for this access, |
---|
3775 | // using the r_vci_cmd_imiss_prio flip-flop. |
---|
3776 | |
---|
3777 | size_t wbuf_min; |
---|
3778 | size_t wbuf_max; |
---|
3779 | |
---|
3780 | bool dcache_miss_req = r_dcache_vci_miss_req.read() and |
---|
3781 | (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read()); |
---|
3782 | |
---|
3783 | bool dcache_ll_req = r_dcache_vci_ll_req.read() and |
---|
3784 | (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read()); |
---|
3785 | |
---|
3786 | bool dcache_sc_req = r_dcache_vci_sc_req.read() and |
---|
3787 | (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read()); |
---|
3788 | |
---|
3789 | bool dcache_cas_req = r_dcache_vci_cas_req.read() and |
---|
3790 | (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read()); |
---|
3791 | |
---|
3792 | bool icache_miss_req = r_icache_miss_req.read() and |
---|
3793 | (not (r_dcache_vci_miss_req.read() or |
---|
3794 | r_dcache_vci_ll_req.read() or |
---|
3795 | r_dcache_vci_cas_req.read() or |
---|
3796 | r_dcache_vci_sc_req.read()) or |
---|
3797 | r_vci_cmd_imiss_prio.read()); |
---|
3798 | |
---|
3799 | // 1 - Data unc write |
---|
3800 | if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read()) { |
---|
3801 | r_vci_cmd_fsm = CMD_DATA_UNC_WRITE; |
---|
3802 | r_dcache_vci_unc_req = false; |
---|
3803 | } |
---|
3804 | // 2 data read miss |
---|
3805 | else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read())) { |
---|
3806 | r_vci_cmd_fsm = CMD_DATA_MISS; |
---|
3807 | r_dcache_vci_miss_req = false; |
---|
3808 | r_vci_cmd_imiss_prio = true; |
---|
3809 | } |
---|
3810 | // 3 - Data Read Uncachable |
---|
3811 | else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read()) { |
---|
3812 | r_vci_cmd_fsm = CMD_DATA_UNC_READ; |
---|
3813 | r_dcache_vci_unc_req = false; |
---|
3814 | } |
---|
3815 | // 4 - Data Linked Load |
---|
3816 | else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read())) { |
---|
3817 | r_vci_cmd_fsm = CMD_DATA_LL; |
---|
3818 | r_dcache_vci_ll_req = false; |
---|
3819 | r_vci_cmd_imiss_prio = true; |
---|
3820 | } |
---|
3821 | // 5 - Instruction Miss |
---|
3822 | else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read())) { |
---|
3823 | r_vci_cmd_fsm = CMD_INS_MISS; |
---|
3824 | r_icache_miss_req = false; |
---|
3825 | r_vci_cmd_imiss_prio = false; |
---|
3826 | } |
---|
3827 | // 6 - Instruction Uncachable |
---|
3828 | else if (r_icache_unc_req.read()) { |
---|
3829 | r_vci_cmd_fsm = CMD_INS_UNC; |
---|
3830 | r_icache_unc_req = false; |
---|
3831 | } |
---|
3832 | // 7 - Data Write |
---|
3833 | else if (r_wbuf.rok(&wbuf_min, &wbuf_max)) { |
---|
3834 | r_vci_cmd_fsm = CMD_DATA_WRITE; |
---|
3835 | r_vci_cmd_cpt = wbuf_min; |
---|
3836 | r_vci_cmd_min = wbuf_min; |
---|
3837 | r_vci_cmd_max = wbuf_max; |
---|
3838 | } |
---|
3839 | // 8 - Data Store Conditionnal |
---|
3840 | else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read())) { |
---|
3841 | r_vci_cmd_fsm = CMD_DATA_SC; |
---|
3842 | r_dcache_vci_sc_req = false; |
---|
3843 | r_vci_cmd_imiss_prio = true; |
---|
3844 | r_vci_cmd_cpt = 0; |
---|
3845 | } |
---|
3846 | // 9 - Compare And Swap |
---|
3847 | else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read())) { |
---|
3848 | r_vci_cmd_fsm = CMD_DATA_CAS; |
---|
3849 | r_dcache_vci_cas_req = false; |
---|
3850 | r_vci_cmd_imiss_prio = true; |
---|
3851 | r_vci_cmd_cpt = 0; |
---|
3852 | } |
---|
3853 | |
---|
3854 | #if DEBUG_CMD |
---|
3855 | if (m_debug_cmd_fsm) { |
---|
3856 | std::cout << " <PROC " << name() << " CMD_IDLE>" |
---|
3857 | << " / dmiss_req = " << dcache_miss_req |
---|
3858 | << " / imiss_req = " << icache_miss_req |
---|
3859 | << std::endl; |
---|
3860 | } |
---|
3861 | #endif |
---|
3862 | break; |
---|
3863 | } |
---|
3864 | //////////////////// |
---|
3865 | case CMD_DATA_WRITE: |
---|
3866 | { |
---|
3867 | if (p_vci.cmdack.read()) { |
---|
3868 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
3869 | if (r_vci_cmd_cpt == r_vci_cmd_max) { |
---|
3870 | // last flit sent |
---|
3871 | r_vci_cmd_fsm = CMD_IDLE; |
---|
3872 | r_wbuf.sent(); |
---|
3873 | } |
---|
3874 | } |
---|
3875 | break; |
---|
3876 | } |
---|
3877 | ///////////////// |
---|
3878 | case CMD_DATA_SC: |
---|
3879 | case CMD_DATA_CAS: |
---|
3880 | { |
---|
3881 | // The CAS and SC VCI commands contain two flits |
---|
3882 | if (p_vci.cmdack.read()) { |
---|
3883 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
3884 | if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ; |
---|
3885 | } |
---|
3886 | break; |
---|
3887 | } |
---|
3888 | ////////////////// |
---|
3889 | case CMD_INS_MISS: |
---|
3890 | case CMD_INS_UNC: |
---|
3891 | case CMD_DATA_MISS: |
---|
3892 | case CMD_DATA_UNC_READ: |
---|
3893 | case CMD_DATA_UNC_WRITE: |
---|
3894 | case CMD_DATA_LL: |
---|
3895 | { |
---|
3896 | // all read VCI commands contain one single flit |
---|
3897 | if (p_vci.cmdack.read()) { |
---|
3898 | r_vci_cmd_fsm = CMD_IDLE; |
---|
3899 | } |
---|
3900 | break; |
---|
3901 | } |
---|
3902 | |
---|
3903 | } // end switch r_vci_cmd_fsm |
---|
3904 | |
---|
3905 | ////////////////////////////////////////////////////////////////////////// |
---|
3906 | // The VCI_RSP FSM controls the following ressources: |
---|
3907 | // - r_vci_rsp_fsm: |
---|
3908 | // - r_vci_rsp_fifo_icache (push) |
---|
3909 | // - r_vci_rsp_fifo_dcache (push) |
---|
3910 | // - r_vci_rsp_data_error (set) |
---|
3911 | // - r_vci_rsp_ins_error (set) |
---|
3912 | // - r_vci_rsp_cpt |
---|
3913 | // - r_dcache_vci_sc_req (reset when SC response recieved) |
---|
3914 | // |
---|
3915 | // As the VCI_RSP and VCI_CMD are fully desynchronized to support several |
---|
3916 | // simultaneous VCI transactions, this FSM uses the VCI RPKTID field |
---|
3917 | // to identify the transactions. |
---|
3918 | // |
---|
3919 | // VCI vormat: |
---|
3920 | // This component checks the response packet length and accepts only |
---|
3921 | // single word packets for write response packets. |
---|
3922 | // |
---|
3923 | // Error handling: |
---|
3924 | // This FSM analyzes the VCI error code and signals directly the Write Bus Error. |
---|
3925 | // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error |
---|
3926 | // flip_flop and the error is signaled by the DCACHE FSM. |
---|
3927 | // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error |
---|
3928 | // flip_flop and the error is signaled by the ICACHE FSM. |
---|
3929 | // In case of Cleanup Error, the simulation stops with an error message... |
---|
3930 | ////////////////////////////////////////////////////////////////////////// |
---|
3931 | |
---|
3932 | switch (r_vci_rsp_fsm.read()) { |
---|
3933 | ////////////// |
---|
3934 | case RSP_IDLE: |
---|
3935 | { |
---|
3936 | if (p_vci.rspval.read()) { |
---|
3937 | r_vci_rsp_cpt = 0; |
---|
3938 | |
---|
3939 | if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC) { |
---|
3940 | r_vci_rsp_fsm = RSP_DATA_UNC; |
---|
3941 | } |
---|
3942 | else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS) { |
---|
3943 | r_vci_rsp_fsm = RSP_DATA_MISS; |
---|
3944 | } |
---|
3945 | else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC) { |
---|
3946 | r_vci_rsp_fsm = RSP_INS_UNC; |
---|
3947 | } |
---|
3948 | else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS) { |
---|
3949 | r_vci_rsp_fsm = RSP_INS_MISS; |
---|
3950 | } |
---|
3951 | else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE) { |
---|
3952 | r_vci_rsp_fsm = RSP_DATA_WRITE; |
---|
3953 | } |
---|
3954 | else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS) { |
---|
3955 | r_vci_rsp_fsm = RSP_DATA_UNC; |
---|
3956 | } |
---|
3957 | else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL) { |
---|
3958 | r_vci_rsp_fsm = RSP_DATA_LL; |
---|
3959 | } |
---|
3960 | else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC) { |
---|
3961 | r_vci_rsp_fsm = RSP_DATA_UNC; |
---|
3962 | } |
---|
3963 | else { |
---|
3964 | assert(false and "Unexpected VCI response"); |
---|
3965 | } |
---|
3966 | } |
---|
3967 | break; |
---|
3968 | } |
---|
3969 | ////////////////// |
---|
3970 | case RSP_INS_MISS: |
---|
3971 | { |
---|
3972 | if (p_vci.rspval.read()) { |
---|
3973 | if ((p_vci.rerror.read() & 0x1) != 0) { |
---|
3974 | r_vci_rsp_ins_error = true; |
---|
3975 | if (p_vci.reop.read()) { |
---|
3976 | r_vci_rsp_fsm = RSP_IDLE; |
---|
3977 | } |
---|
3978 | } |
---|
3979 | else { |
---|
3980 | if (r_vci_rsp_fifo_icache.wok()) { |
---|
3981 | if (r_vci_rsp_cpt.read() >= m_icache_words) { |
---|
3982 | std::cout << "ERROR in VCI_CC_VCACHE " << name() |
---|
3983 | << " VCI response packet too long " |
---|
3984 | << " for instruction miss" << std::endl; |
---|
3985 | exit(0); |
---|
3986 | } |
---|
3987 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
3988 | vci_rsp_fifo_icache_put = true, |
---|
3989 | vci_rsp_fifo_icache_data = p_vci.rdata.read(); |
---|
3990 | if (p_vci.reop.read()) { |
---|
3991 | if (r_vci_rsp_cpt.read() != (m_icache_words - 1)) { |
---|
3992 | std::cout << "ERROR in VCI_CC_VCACHE " << name() |
---|
3993 | << " VCI response packet too short" |
---|
3994 | << " for instruction miss" << std::endl; |
---|
3995 | exit(0); |
---|
3996 | } |
---|
3997 | r_vci_rsp_fsm = RSP_IDLE; |
---|
3998 | } |
---|
3999 | } |
---|
4000 | } |
---|
4001 | } |
---|
4002 | break; |
---|
4003 | } |
---|
4004 | ///////////////// |
---|
4005 | case RSP_INS_UNC: |
---|
4006 | { |
---|
4007 | if (p_vci.rspval.read()) { |
---|
4008 | assert(p_vci.reop.read() and |
---|
4009 | "illegal VCI response packet for uncachable instruction"); |
---|
4010 | |
---|
4011 | if ((p_vci.rerror.read() & 0x1) != 0) { |
---|
4012 | r_vci_rsp_ins_error = true; |
---|
4013 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4014 | } |
---|
4015 | else { |
---|
4016 | if (r_vci_rsp_fifo_icache.wok()) { |
---|
4017 | vci_rsp_fifo_icache_put = true; |
---|
4018 | vci_rsp_fifo_icache_data = p_vci.rdata.read(); |
---|
4019 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4020 | } |
---|
4021 | } |
---|
4022 | } |
---|
4023 | break; |
---|
4024 | } |
---|
4025 | /////////////////// |
---|
4026 | case RSP_DATA_MISS: |
---|
4027 | { |
---|
4028 | if (p_vci.rspval.read()) { |
---|
4029 | if ((p_vci.rerror.read() & 0x1) != 0) { |
---|
4030 | r_vci_rsp_data_error = true; |
---|
4031 | if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE; |
---|
4032 | } |
---|
4033 | else { |
---|
4034 | if (r_vci_rsp_fifo_dcache.wok()) { |
---|
4035 | assert((r_vci_rsp_cpt.read() < m_dcache_words) and |
---|
4036 | "The VCI response packet for data miss is too long"); |
---|
4037 | |
---|
4038 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
4039 | vci_rsp_fifo_dcache_put = true, |
---|
4040 | vci_rsp_fifo_dcache_data = p_vci.rdata.read(); |
---|
4041 | if (p_vci.reop.read()) { |
---|
4042 | assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and |
---|
4043 | "The VCI response packet for data miss is too short"); |
---|
4044 | |
---|
4045 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4046 | } |
---|
4047 | } |
---|
4048 | } |
---|
4049 | } |
---|
4050 | break; |
---|
4051 | } |
---|
4052 | ////////////////// |
---|
4053 | case RSP_DATA_UNC: |
---|
4054 | { |
---|
4055 | if (p_vci.rspval.read()) { |
---|
4056 | assert(p_vci.reop.read() and |
---|
4057 | "illegal VCI response packet for uncachable read data"); |
---|
4058 | |
---|
4059 | if ((p_vci.rerror.read() & 0x1) != 0) { |
---|
4060 | r_vci_rsp_data_error = true; |
---|
4061 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4062 | } |
---|
4063 | else { |
---|
4064 | if (r_vci_rsp_fifo_dcache.wok()) { |
---|
4065 | vci_rsp_fifo_dcache_put = true; |
---|
4066 | vci_rsp_fifo_dcache_data = p_vci.rdata.read(); |
---|
4067 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4068 | } |
---|
4069 | } |
---|
4070 | } |
---|
4071 | break; |
---|
4072 | } |
---|
4073 | ///////////////// |
---|
4074 | case RSP_DATA_LL: |
---|
4075 | { |
---|
4076 | if (p_vci.rspval.read()) { |
---|
4077 | if ((p_vci.rerror.read() & 0x1) != 0) { |
---|
4078 | r_vci_rsp_data_error = true; |
---|
4079 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4080 | break; |
---|
4081 | } |
---|
4082 | if (r_vci_rsp_cpt.read() == 0) { |
---|
4083 | if (r_vci_rsp_fifo_dcache.wok()) { |
---|
4084 | assert(!p_vci.reop.read() && "illegal VCI response packet for LL"); |
---|
4085 | vci_rsp_fifo_dcache_put = true; |
---|
4086 | vci_rsp_fifo_dcache_data = p_vci.rdata.read(); |
---|
4087 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
4088 | } |
---|
4089 | break; |
---|
4090 | } |
---|
4091 | else { |
---|
4092 | // last flit |
---|
4093 | if (r_vci_rsp_fifo_dcache.wok()) { |
---|
4094 | assert(p_vci.reop.read() && |
---|
4095 | "illegal VCI response packet for LL"); |
---|
4096 | vci_rsp_fifo_dcache_put = true; |
---|
4097 | vci_rsp_fifo_dcache_data = p_vci.rdata.read(); |
---|
4098 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4099 | } |
---|
4100 | break; |
---|
4101 | } |
---|
4102 | } |
---|
4103 | break; |
---|
4104 | } |
---|
4105 | //////////////////// |
---|
4106 | case RSP_DATA_WRITE: |
---|
4107 | { |
---|
4108 | if (p_vci.rspval.read()) { |
---|
4109 | assert(p_vci.reop.read() and |
---|
4110 | "a VCI response packet must contain one flit for a write transaction"); |
---|
4111 | |
---|
4112 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4113 | uint32_t wbuf_index = p_vci.rtrdid.read(); |
---|
4114 | r_wbuf.completed(wbuf_index); |
---|
4115 | if ((p_vci.rerror.read() & 0x1) != 0) { |
---|
4116 | r_iss.setWriteBerr(); |
---|
4117 | } |
---|
4118 | } |
---|
4119 | break; |
---|
4120 | } |
---|
4121 | } // end switch r_vci_rsp_fsm |
---|
4122 | |
---|
4123 | |
---|
4124 | ///////////////// Response FIFOs update ////////////////////// |
---|
4125 | r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, |
---|
4126 | vci_rsp_fifo_icache_put, |
---|
4127 | vci_rsp_fifo_icache_data); |
---|
4128 | |
---|
4129 | r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get, |
---|
4130 | vci_rsp_fifo_dcache_put, |
---|
4131 | vci_rsp_fifo_dcache_data); |
---|
4132 | |
---|
4133 | |
---|
4134 | } // end transition() |
---|
4135 | |
---|
4136 | |
---|
4137 | |
---|
4138 | /////////////////////// |
---|
4139 | tmpl(void)::genMoore() |
---|
4140 | /////////////////////// |
---|
4141 | { |
---|
4142 | // VCI initiator command on the direct network |
---|
4143 | // it depends on the CMD FSM state |
---|
4144 | |
---|
4145 | bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or |
---|
4146 | (r_vci_cmd_fsm.read() == CMD_DATA_SC); |
---|
4147 | |
---|
4148 | p_vci.pktid = 0; |
---|
4149 | p_vci.srcid = m_srcid; |
---|
4150 | p_vci.cons = is_sc_or_cas; |
---|
4151 | p_vci.contig = not is_sc_or_cas; |
---|
4152 | p_vci.wrap = false; |
---|
4153 | p_vci.clen = 0; |
---|
4154 | p_vci.cfixed = false; |
---|
4155 | |
---|
4156 | if (m_monitor_ok) { |
---|
4157 | if (p_vci.cmdack.read() == true and p_vci.cmdval == true) { |
---|
4158 | if (((p_vci.address.read()) >= m_monitor_base) and |
---|
4159 | ((p_vci.address.read()) < m_monitor_base + m_monitor_length)) { |
---|
4160 | std::cout << "CC_VCACHE Monitor " << name() << std::hex |
---|
4161 | << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] |
---|
4162 | << " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()] |
---|
4163 | << " : address = " << p_vci.address.read() |
---|
4164 | << " / be = " << p_vci.be.read(); |
---|
4165 | if (p_vci.cmd.read() == vci_param::CMD_WRITE) { |
---|
4166 | std::cout << " / data = " << p_vci.wdata.read(); |
---|
4167 | } |
---|
4168 | std::cout << std::dec << std::endl; |
---|
4169 | } |
---|
4170 | } |
---|
4171 | } |
---|
4172 | |
---|
4173 | switch (r_vci_cmd_fsm.read()) { |
---|
4174 | |
---|
4175 | case CMD_IDLE: |
---|
4176 | p_vci.cmdval = false; |
---|
4177 | p_vci.address = 0; |
---|
4178 | p_vci.wdata = 0; |
---|
4179 | p_vci.be = 0; |
---|
4180 | p_vci.trdid = 0; |
---|
4181 | p_vci.pktid = 0; |
---|
4182 | p_vci.plen = 0; |
---|
4183 | p_vci.cmd = vci_param::CMD_NOP; |
---|
4184 | p_vci.eop = false; |
---|
4185 | break; |
---|
4186 | |
---|
4187 | case CMD_INS_MISS: |
---|
4188 | p_vci.cmdval = true; |
---|
4189 | p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask; |
---|
4190 | p_vci.wdata = 0; |
---|
4191 | p_vci.be = 0xF; |
---|
4192 | p_vci.trdid = 0; |
---|
4193 | p_vci.pktid = TYPE_READ_INS_MISS; |
---|
4194 | p_vci.plen = m_icache_words << 2; |
---|
4195 | p_vci.cmd = vci_param::CMD_READ; |
---|
4196 | p_vci.eop = true; |
---|
4197 | break; |
---|
4198 | |
---|
4199 | case CMD_INS_UNC: |
---|
4200 | p_vci.cmdval = true; |
---|
4201 | p_vci.address = r_icache_vci_paddr.read() & ~0x3; |
---|
4202 | p_vci.wdata = 0; |
---|
4203 | p_vci.be = 0xF; |
---|
4204 | p_vci.trdid = 0; |
---|
4205 | p_vci.pktid = TYPE_READ_INS_UNC; |
---|
4206 | p_vci.plen = 4; |
---|
4207 | p_vci.cmd = vci_param::CMD_READ; |
---|
4208 | p_vci.eop = true; |
---|
4209 | break; |
---|
4210 | |
---|
4211 | case CMD_DATA_MISS: |
---|
4212 | p_vci.cmdval = true; |
---|
4213 | p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; |
---|
4214 | p_vci.wdata = 0; |
---|
4215 | p_vci.be = 0xF; |
---|
4216 | p_vci.trdid = 0; |
---|
4217 | p_vci.pktid = TYPE_READ_DATA_MISS; |
---|
4218 | p_vci.plen = m_dcache_words << 2; |
---|
4219 | p_vci.cmd = vci_param::CMD_READ; |
---|
4220 | p_vci.eop = true; |
---|
4221 | break; |
---|
4222 | |
---|
4223 | case CMD_DATA_UNC_READ: |
---|
4224 | p_vci.cmdval = true; |
---|
4225 | p_vci.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
4226 | p_vci.wdata = 0; |
---|
4227 | p_vci.be = r_dcache_vci_unc_be.read(); |
---|
4228 | p_vci.trdid = 0; |
---|
4229 | p_vci.pktid = TYPE_DATA_UNC; |
---|
4230 | p_vci.plen = 4; |
---|
4231 | p_vci.cmd = vci_param::CMD_READ; |
---|
4232 | p_vci.eop = true; |
---|
4233 | break; |
---|
4234 | |
---|
4235 | case CMD_DATA_UNC_WRITE: |
---|
4236 | p_vci.cmdval = true; |
---|
4237 | p_vci.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
4238 | p_vci.wdata = r_dcache_vci_wdata.read(); |
---|
4239 | p_vci.be = r_dcache_vci_unc_be.read(); |
---|
4240 | p_vci.trdid = 0; |
---|
4241 | p_vci.pktid = TYPE_DATA_UNC; |
---|
4242 | p_vci.plen = 4; |
---|
4243 | p_vci.cmd = vci_param::CMD_WRITE; |
---|
4244 | p_vci.eop = true; |
---|
4245 | break; |
---|
4246 | |
---|
4247 | case CMD_DATA_WRITE: |
---|
4248 | p_vci.cmdval = true; |
---|
4249 | p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; |
---|
4250 | p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); |
---|
4251 | p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); |
---|
4252 | p_vci.trdid = r_wbuf.getIndex(); |
---|
4253 | p_vci.pktid = TYPE_WRITE; |
---|
4254 | p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; |
---|
4255 | p_vci.cmd = vci_param::CMD_WRITE; |
---|
4256 | p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); |
---|
4257 | break; |
---|
4258 | |
---|
4259 | case CMD_DATA_LL: |
---|
4260 | p_vci.cmdval = true; |
---|
4261 | p_vci.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
4262 | p_vci.wdata = 0; |
---|
4263 | p_vci.be = 0xF; |
---|
4264 | p_vci.trdid = 0; |
---|
4265 | p_vci.pktid = TYPE_LL; |
---|
4266 | p_vci.plen = 8; |
---|
4267 | p_vci.cmd = vci_param::CMD_LOCKED_READ; |
---|
4268 | p_vci.eop = true; |
---|
4269 | break; |
---|
4270 | |
---|
4271 | case CMD_DATA_SC: |
---|
4272 | p_vci.cmdval = true; |
---|
4273 | p_vci.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
4274 | if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read(); |
---|
4275 | else p_vci.wdata = r_dcache_vci_sc_data.read(); |
---|
4276 | p_vci.be = 0xF; |
---|
4277 | p_vci.trdid = 0; |
---|
4278 | p_vci.pktid = TYPE_SC; |
---|
4279 | p_vci.plen = 8; |
---|
4280 | p_vci.cmd = vci_param::CMD_NOP; |
---|
4281 | p_vci.eop = (r_vci_cmd_cpt.read() == 1); |
---|
4282 | break; |
---|
4283 | |
---|
4284 | case CMD_DATA_CAS: |
---|
4285 | p_vci.cmdval = true; |
---|
4286 | p_vci.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
4287 | if (r_vci_cmd_cpt.read() == 0) { |
---|
4288 | p_vci.wdata = r_dcache_vci_cas_old.read(); |
---|
4289 | } |
---|
4290 | else { |
---|
4291 | p_vci.wdata = r_dcache_vci_cas_new.read(); |
---|
4292 | } |
---|
4293 | p_vci.be = 0xF; |
---|
4294 | p_vci.trdid = 0; |
---|
4295 | p_vci.pktid = TYPE_CAS; |
---|
4296 | p_vci.plen = 8; |
---|
4297 | p_vci.cmd = vci_param::CMD_NOP; |
---|
4298 | p_vci.eop = (r_vci_cmd_cpt.read() == 1); |
---|
4299 | break; |
---|
4300 | } // end switch r_vci_cmd_fsm |
---|
4301 | |
---|
4302 | // VCI initiator response on the direct network |
---|
4303 | // it depends on the VCI_RSP FSM |
---|
4304 | |
---|
4305 | switch (r_vci_rsp_fsm.read()) { |
---|
4306 | case RSP_DATA_WRITE : p_vci.rspack = true; break; |
---|
4307 | case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
4308 | case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
4309 | case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
4310 | case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
4311 | case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
4312 | case RSP_IDLE : p_vci.rspack = false; break; |
---|
4313 | } // end switch r_vci_rsp_fsm |
---|
4314 | |
---|
4315 | |
---|
4316 | // No coherence |
---|
4317 | p_dspin_p2m.write = false; |
---|
4318 | p_dspin_p2m.eop = false; |
---|
4319 | p_dspin_p2m.data = 0; |
---|
4320 | |
---|
4321 | p_dspin_m2p.read = false; |
---|
4322 | p_dspin_clack.read = false; |
---|
4323 | |
---|
4324 | } // end genMoore |
---|
4325 | |
---|
4326 | tmpl(void)::start_monitor(paddr_t base, paddr_t length) |
---|
4327 | // This version of monitor print both Read and Write request |
---|
4328 | { |
---|
4329 | m_monitor_ok = true; |
---|
4330 | m_monitor_base = base; |
---|
4331 | m_monitor_length = length; |
---|
4332 | } |
---|
4333 | |
---|
4334 | tmpl(void)::stop_monitor() { |
---|
4335 | m_monitor_ok = false; |
---|
4336 | } |
---|
4337 | |
---|
4338 | }} |
---|
4339 | |
---|
4340 | // Local Variables: |
---|
4341 | // tab-width: 4 |
---|
4342 | // c-basic-offset: 4 |
---|
4343 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
4344 | // indent-tabs-mode: nil |
---|
4345 | // End: |
---|
4346 | |
---|
4347 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|