[151] | 1 | |
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| 2 | /* -*- c++ -*- |
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| 3 | * |
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| 4 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 5 | * |
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| 6 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 7 | * |
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| 8 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU Lesser General Public License as published |
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| 10 | * by the Free Software Foundation; version 2.1 of the License. |
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| 11 | * |
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| 12 | * SoCLib is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * Lesser General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU Lesser General Public |
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| 18 | * License along with SoCLib; if not, write to the Free Software |
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| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 20 | * 02110-1301 USA |
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| 21 | * |
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| 22 | * SOCLIB_LGPL_HEADER_END |
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| 23 | * |
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| 24 | * Copyright (c) UPMC, Lip6, Asim |
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| 25 | * alain.greiner@lip6.fr april 2011 |
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| 26 | * |
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| 27 | * Maintainers: alain |
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| 28 | */ |
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| 29 | |
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| 30 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 31 | // This component is a simplified disk controller with a VCI interface. |
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[400] | 32 | // It supports only 32 or 64 bits VCI DATA width, but all addressable registers |
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| 33 | // contain 32 bits words. It supports VCI addresss lartger than 32 bits. |
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| 34 | // |
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[151] | 35 | // This component can perform data transfers between one single file belonging |
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| 36 | // to the host system and a buffer in the memory of the virtual prototype. |
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[260] | 37 | // The file name is an argument of the constructor. |
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[151] | 38 | // This component has a DMA capability, and is both a target and an initiator. |
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[260] | 39 | // The block size (bytes), and the burst size (bytes) must be power of 2. |
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| 40 | // The burst size is typically a cache line. |
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[400] | 41 | // The memory buffer is not constrained to be aligned on a burst boundary, |
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| 42 | // but must be aligned on a 32 bits word boundary. |
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[151] | 43 | // Both read and write transfers are supported. An IRQ is optionally |
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| 44 | // asserted when the transfer is completed. |
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| 45 | // |
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[400] | 46 | // As a target this block device controler contains 9 32 bits memory mapped registers, |
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[392] | 47 | // taking 36 bytes in the address space. |
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[400] | 48 | // - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address (LSB bits) |
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| 49 | // - BLOCK_DEVICE_COUNT 0x04 (read/write) Number of blocks to be transfered. |
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| 50 | // - BLOCK_DEVICE_LBA 0x08 (read/write) Index of first block in the file. |
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| 51 | // - BLOCK_DEVICE_OP 0x0C (write-only) Writing here starts the operation. |
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| 52 | // - BLOCK_DEVICE_STATUS 0x10 (read-only) Block Device status. |
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| 53 | // - BLOCK_DEVICE_IRQ_ENABLE 0x14 (read/write) IRQ enabled if non zero. |
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| 54 | // - BLOCK_DEVICE_SIZE 0x18 (read-only) Number of addressable blocks. |
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| 55 | // - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) Block size in bytes. |
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| 56 | // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read_only) Memory buffer base address (MSB bits) |
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[151] | 57 | // |
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| 58 | // The following operations codes are supported: |
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| 59 | // - BLOCK_DEVICE_NOOP No operation |
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| 60 | // - BLOCK_DEVICE_READ From block device to memory |
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| 61 | // - BLOCK_DEVICE_WRITE From memory to block device |
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| 62 | // |
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| 63 | // The BLOCK_DEVICE_STATUS is actually defined by the initiator FSM state. |
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| 64 | // The following values are defined for device status: |
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| 65 | // -BLOCK_DEVICE_IDLE 0 |
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| 66 | // -BLOCK_DEVICE_BUSY 1 |
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| 67 | // -BLOCK_DEVICE_READ_SUCCESS 2 |
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| 68 | // -BLOCK_DEVICE_WRITE_SUCCESS 3 |
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| 69 | // -BLOCK_DEVICE_READ_ERROR 4 |
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| 70 | // -BLOCK_DEVICE_WRITE_ERROR 5 |
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| 71 | // |
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| 72 | // In the 4 states READ_ERROR, READ_SUCCESS, WRITE_ERROR, WRITE_SUCCESS, |
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| 73 | // the IRQ is asserted (if it is enabled). |
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| 74 | // A read access to the BLOCK_DEVICE_STATUS in these 4 states reset |
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| 75 | // the initiator FSM state to IDLE, and acknowledge the IRQ. |
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| 76 | // Any write access to registers BUFFER, COUNT, LBA, OP is ignored |
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| 77 | // if the device is not IDLE. |
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| 78 | /////////////////////////////////////////////////////////////////////////// |
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| 79 | |
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[374] | 80 | #ifndef SOCLIB_VCI_BLOCK_DEVICE_TSAR_H |
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| 81 | #define SOCLIB_VCI_BLOCK_DEVICE_TSAR_H |
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[151] | 82 | |
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| 83 | #include <stdint.h> |
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| 84 | #include <systemc> |
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[391] | 85 | #include <unistd.h> |
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[151] | 86 | #include "caba_base_module.h" |
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| 87 | #include "mapping_table.h" |
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[301] | 88 | #include "vci_initiator.h" |
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[164] | 89 | #include "vci_target.h" |
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[151] | 90 | |
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| 91 | namespace soclib { |
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| 92 | namespace caba { |
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| 93 | |
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| 94 | using namespace sc_core; |
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| 95 | |
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| 96 | template<typename vci_param> |
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[374] | 97 | class VciBlockDeviceTsar |
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[151] | 98 | : public caba::BaseModule |
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| 99 | { |
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| 100 | private: |
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| 101 | |
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| 102 | // Registers |
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[408] | 103 | sc_signal<int> r_target_fsm; // target fsm state register |
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| 104 | sc_signal<int> r_initiator_fsm; // initiator fsm state register |
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| 105 | sc_signal<bool> r_irq_enable; // default value is true |
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| 106 | sc_signal<uint32_t> r_nblocks; // number of blocks in transfer |
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| 107 | sc_signal<uint64_t> r_buf_address; // memory buffer address |
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| 108 | sc_signal<uint32_t> r_lba; // first block index |
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| 109 | sc_signal<bool> r_read; // requested operation |
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| 110 | sc_signal<uint32_t> r_index; // word index in local buffer |
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| 111 | sc_signal<uint32_t> r_latency_count; // latency counter |
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| 112 | sc_signal<uint32_t> r_words_count; // word counter (in a burst) |
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| 113 | sc_signal<uint32_t> r_burst_count; // burst counter (in a block) |
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| 114 | sc_signal<uint32_t> r_block_count; // block counter (in a transfer) |
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| 115 | sc_signal<uint32_t> r_burst_offset; // number of non aligned words |
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| 116 | sc_signal<uint32_t> r_burst_nwords; // number of words in a burst |
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| 117 | sc_signal<bool> r_go; // command from T_FSM to M_FSM |
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[260] | 118 | |
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[408] | 119 | sc_signal<sc_dt::sc_uint<vci_param::S> > r_srcid; // save srcid |
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| 120 | sc_signal<sc_dt::sc_uint<vci_param::T> > r_trdid; // save trdid |
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| 121 | sc_signal<sc_dt::sc_uint<vci_param::P> > r_pktid; // save pktid |
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[151] | 122 | |
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[408] | 123 | uint32_t* r_local_buffer; // capacity is one block |
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[151] | 124 | |
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| 125 | // structural parameters |
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[408] | 126 | std::list<soclib::common::Segment> m_seglist; |
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| 127 | size_t m_nbseg; |
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| 128 | uint32_t m_srcid; // initiator index |
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| 129 | int m_fd; // File descriptor |
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| 130 | uint64_t m_device_size; // Total number of blocks |
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| 131 | const uint32_t m_words_per_block; // number of words in a block |
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| 132 | const uint32_t m_words_per_burst; // number of words in a burst |
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| 133 | const uint32_t m_bursts_per_block; // number of bursts in a block |
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| 134 | const uint32_t m_latency; // device latency |
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[151] | 135 | |
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| 136 | // methods |
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| 137 | void transition(); |
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| 138 | void genMoore(); |
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| 139 | |
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| 140 | // Master FSM states |
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| 141 | enum { |
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| 142 | M_IDLE = 0, |
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[260] | 143 | |
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[151] | 144 | M_READ_BLOCK = 1, |
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[260] | 145 | M_READ_BURST = 2, |
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| 146 | M_READ_CMD = 3, |
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| 147 | M_READ_RSP = 4, |
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[151] | 148 | M_READ_SUCCESS = 5, |
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| 149 | M_READ_ERROR = 6, |
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[260] | 150 | |
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| 151 | M_WRITE_BURST = 7, |
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[151] | 152 | M_WRITE_CMD = 8, |
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| 153 | M_WRITE_RSP = 9, |
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[260] | 154 | M_WRITE_BLOCK = 10, |
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[151] | 155 | M_WRITE_SUCCESS = 11, |
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| 156 | M_WRITE_ERROR = 12, |
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| 157 | }; |
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| 158 | |
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| 159 | // Target FSM states |
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| 160 | enum { |
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| 161 | T_IDLE = 0, |
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| 162 | T_WRITE_BUFFER = 1, |
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| 163 | T_READ_BUFFER = 2, |
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[392] | 164 | T_WRITE_BUFFER_EXT = 3, |
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| 165 | T_READ_BUFFER_EXT = 4, |
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| 166 | T_WRITE_COUNT = 5, |
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| 167 | T_READ_COUNT = 6, |
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| 168 | T_WRITE_LBA = 7, |
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| 169 | T_READ_LBA = 8, |
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| 170 | T_WRITE_OP = 9, |
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| 171 | T_READ_STATUS = 10, |
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| 172 | T_WRITE_IRQEN = 11, |
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| 173 | T_READ_IRQEN = 12, |
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| 174 | T_READ_SIZE = 13, |
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| 175 | T_READ_BLOCK = 14, |
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| 176 | T_READ_ERROR = 15, |
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| 177 | T_WRITE_ERROR = 16, |
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[151] | 178 | }; |
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| 179 | |
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| 180 | // Error codes values |
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| 181 | enum { |
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| 182 | VCI_READ_OK = 0, |
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| 183 | VCI_READ_ERROR = 1, |
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| 184 | VCI_WRITE_OK = 2, |
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| 185 | VCI_WRITE_ERROR = 3, |
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| 186 | }; |
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| 187 | |
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[284] | 188 | /* transaction type, pktid field */ |
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| 189 | enum transaction_type_e |
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| 190 | { |
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| 191 | // b3 unused |
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| 192 | // b2 READ / NOT READ |
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| 193 | // Si READ |
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| 194 | // b1 DATA / INS |
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| 195 | // b0 UNC / MISS |
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| 196 | // Si NOT READ |
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| 197 | // b1 accÚs table llsc type SW / other |
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| 198 | // b2 WRITE/CAS/LL/SC |
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| 199 | TYPE_READ_DATA_UNC = 0x0, |
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| 200 | TYPE_READ_DATA_MISS = 0x1, |
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| 201 | TYPE_READ_INS_UNC = 0x2, |
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| 202 | TYPE_READ_INS_MISS = 0x3, |
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| 203 | TYPE_WRITE = 0x4, |
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| 204 | TYPE_CAS = 0x5, |
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| 205 | TYPE_LL = 0x6, |
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| 206 | TYPE_SC = 0x7 |
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| 207 | }; |
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| 208 | |
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[151] | 209 | protected: |
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| 210 | |
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[374] | 211 | SC_HAS_PROCESS(VciBlockDeviceTsar); |
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[151] | 212 | |
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| 213 | public: |
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| 214 | |
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| 215 | // ports |
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[164] | 216 | sc_in<bool> p_clk; |
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| 217 | sc_in<bool> p_resetn; |
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| 218 | soclib::caba::VciInitiator<vci_param> p_vci_initiator; |
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| 219 | soclib::caba::VciTarget<vci_param> p_vci_target; |
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| 220 | sc_out<bool> p_irq; |
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[151] | 221 | |
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| 222 | void print_trace(); |
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| 223 | |
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| 224 | // Constructor |
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[374] | 225 | VciBlockDeviceTsar( |
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[260] | 226 | sc_module_name name, |
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[151] | 227 | const soclib::common::MappingTable &mt, |
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| 228 | const soclib::common::IntTab &srcid, |
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| 229 | const soclib::common::IntTab &tgtid, |
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[260] | 230 | const std::string &filename, |
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| 231 | const uint32_t block_size = 512, |
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| 232 | const uint32_t burst_size = 64, |
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| 233 | const uint32_t latency = 0); |
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[151] | 234 | }; |
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| 235 | |
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| 236 | }} |
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| 237 | |
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[374] | 238 | #endif /* SOCLIB_VCI_BLOCK_DEVICE_TSAR_H */ |
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[151] | 239 | |
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| 240 | // Local Variables: |
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| 241 | // tab-width: 4 |
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| 242 | // c-basic-offset: 4 |
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| 243 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 244 | // indent-tabs-mode: nil |
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| 245 | // End: |
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| 246 | |
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| 247 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 248 | |
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