[151] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, Asim |
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| 24 | * alain.greiner@lip6.fr april 2011 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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| 29 | #include <stdint.h> |
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| 30 | #include <iostream> |
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| 31 | #include <fcntl.h> |
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[374] | 32 | #include "vci_block_device_tsar.h" |
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[151] | 33 | |
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| 34 | namespace soclib { namespace caba { |
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| 35 | |
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[374] | 36 | #define tmpl(t) template<typename vci_param> t VciBlockDeviceTsar<vci_param> |
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[151] | 37 | |
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| 38 | using namespace soclib::caba; |
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| 39 | using namespace soclib::common; |
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| 40 | |
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| 41 | //////////////////////// |
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| 42 | tmpl(void)::transition() |
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| 43 | { |
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| 44 | if(p_resetn.read() == false) |
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| 45 | { |
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| 46 | r_initiator_fsm = M_IDLE; |
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[260] | 47 | r_target_fsm = T_IDLE; |
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| 48 | r_irq_enable = true; |
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| 49 | r_go = false; |
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| 50 | return; |
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[151] | 51 | } |
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| 52 | |
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| 53 | ////////////////////////////////////////////////////////////////////////////// |
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| 54 | // The Target FSM controls the following registers: |
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| 55 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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| 56 | ////////////////////////////////////////////////////////////////////////////// |
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| 57 | |
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| 58 | switch(r_target_fsm) { |
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[260] | 59 | //////////// |
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[151] | 60 | case T_IDLE: |
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| 61 | { |
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| 62 | if ( p_vci_target.cmdval.read() ) |
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| 63 | { |
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| 64 | r_srcid = p_vci_target.srcid.read(); |
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| 65 | r_trdid = p_vci_target.trdid.read(); |
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| 66 | r_pktid = p_vci_target.pktid.read(); |
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[260] | 67 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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[151] | 68 | bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); |
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| 69 | uint32_t cell = (uint32_t)((address & 0x1F)>>2); |
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| 70 | |
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[260] | 71 | if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; |
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| 72 | else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR; |
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| 73 | else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; |
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| 74 | else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; |
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| 75 | else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; |
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| 76 | else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; |
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| 77 | else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; |
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| 78 | else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; |
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| 79 | else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; |
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| 80 | else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; |
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| 81 | else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; |
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| 82 | else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; |
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| 83 | else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; |
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| 84 | else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; |
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| 85 | else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; |
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| 86 | else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; |
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[151] | 87 | } |
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| 88 | break; |
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| 89 | } |
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[260] | 90 | //////////////////// |
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[151] | 91 | case T_WRITE_BUFFER: |
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| 92 | { |
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| 93 | if ( r_initiator_fsm == M_IDLE ) r_buf_address = (uint32_t)p_vci_target.wdata.read(); |
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| 94 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 95 | break; |
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| 96 | } |
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[260] | 97 | /////////////////// |
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[151] | 98 | case T_WRITE_COUNT: |
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| 99 | { |
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| 100 | if ( r_initiator_fsm == M_IDLE ) r_nblocks = (uint32_t)p_vci_target.wdata.read(); |
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| 101 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 102 | break; |
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| 103 | } |
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[260] | 104 | ///////////////// |
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[151] | 105 | case T_WRITE_LBA: |
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| 106 | { |
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| 107 | if ( r_initiator_fsm == M_IDLE ) r_lba = (uint32_t)p_vci_target.wdata.read(); |
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| 108 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 109 | break; |
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| 110 | } |
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[260] | 111 | //////////////// |
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[151] | 112 | case T_WRITE_OP: |
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| 113 | { |
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| 114 | if ( r_initiator_fsm == M_IDLE ) |
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| 115 | { |
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| 116 | if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ ) |
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| 117 | { |
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| 118 | r_read = true; |
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| 119 | r_go = true; |
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| 120 | } |
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| 121 | else if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE) |
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| 122 | { |
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| 123 | r_read = false; |
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| 124 | r_go = true; |
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| 125 | } |
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| 126 | } |
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| 127 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 128 | break; |
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| 129 | } |
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[260] | 130 | /////////////////// |
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[151] | 131 | case T_WRITE_IRQEN: |
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| 132 | { |
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| 133 | r_irq_enable = (p_vci_target.wdata.read() != 0); |
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| 134 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 135 | break; |
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| 136 | } |
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[260] | 137 | /////////////////// |
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[151] | 138 | case T_READ_BUFFER: |
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| 139 | case T_READ_COUNT: |
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| 140 | case T_READ_LBA: |
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| 141 | case T_READ_IRQEN: |
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| 142 | case T_READ_SIZE: |
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| 143 | case T_READ_BLOCK: |
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| 144 | case T_READ_ERROR: |
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| 145 | case T_WRITE_ERROR: |
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| 146 | { |
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| 147 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 148 | break; |
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| 149 | } |
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[260] | 150 | /////////////////// |
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[151] | 151 | case T_READ_STATUS: |
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| 152 | { |
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| 153 | if ( p_vci_target.rspack.read() ) |
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| 154 | { |
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| 155 | r_target_fsm = T_IDLE; |
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| 156 | if( (r_initiator_fsm == M_READ_SUCCESS ) || |
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| 157 | (r_initiator_fsm == M_READ_ERROR ) || |
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| 158 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
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| 159 | (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; |
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| 160 | } |
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| 161 | break; |
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| 162 | } |
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| 163 | } // end switch target fsm |
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| 164 | |
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[260] | 165 | ////////////////////////////////////////////////////////////////////////////// |
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| 166 | // The initiator FSM executes a loop, transfering one block per iteration. |
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| 167 | // Each block is split in bursts, and the number of bursts depends |
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| 168 | // on the memory buffer alignment on a burst boundary: |
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| 169 | // - If buffer aligned, all burst have the same length (m_flits_per burst) |
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| 170 | // and the number of bursts is (m_bursts_per_block). |
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| 171 | // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) |
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| 172 | // and first and last burst are shorter, because all flits in a burst |
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| 173 | // must be contained in a single cache line. |
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| 174 | // first burst => nflits = m_flits_per_burst - offset |
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| 175 | // last burst => nflits = offset |
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| 176 | // other burst => nflits = m_flits_per_burst |
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| 177 | ////////////////////////////////////////////////////////////////////////////// |
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| 178 | |
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| 179 | switch( r_initiator_fsm.read() ) { |
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| 180 | //////////// |
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| 181 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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[151] | 182 | { |
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[260] | 183 | if ( r_go.read() ) |
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[151] | 184 | { |
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[260] | 185 | r_index = 0; |
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[151] | 186 | r_block_count = 0; |
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| 187 | r_burst_count = 0; |
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| 188 | r_flit_count = 0; |
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| 189 | r_latency_count = m_latency; |
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| 190 | |
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[260] | 191 | // compute r_burst_offset (zero when buffer aligned) |
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| 192 | r_burst_offset = (r_buf_address.read()>>2) % m_flits_per_burst; |
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| 193 | |
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| 194 | // start tranfer |
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| 195 | if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; |
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| 196 | else r_initiator_fsm = M_WRITE_BURST; |
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[151] | 197 | } |
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| 198 | break; |
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[260] | 199 | } |
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| 200 | ////////////////// |
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[228] | 201 | case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles |
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[151] | 202 | { |
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[260] | 203 | if ( r_latency_count.read() == 0 ) |
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[151] | 204 | { |
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| 205 | r_latency_count = m_latency; |
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[260] | 206 | ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*4, SEEK_SET); |
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| 207 | if( ::read(m_fd, r_local_buffer, m_flits_per_block*4) < 0 ) |
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[151] | 208 | { |
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[260] | 209 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 210 | } |
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| 211 | else |
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| 212 | { |
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[260] | 213 | r_burst_count = 0; |
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| 214 | r_flit_count = 0; |
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| 215 | r_initiator_fsm = M_READ_BURST; |
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[151] | 216 | } |
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| 217 | } |
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| 218 | else |
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| 219 | { |
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[260] | 220 | r_latency_count = r_latency_count.read() - 1; |
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[151] | 221 | } |
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| 222 | break; |
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| 223 | } |
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[260] | 224 | ////////////////// |
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| 225 | case M_READ_BURST: // Compute the number of flits in the burst |
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[151] | 226 | { |
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[260] | 227 | uint32_t offset = r_burst_offset.read(); |
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| 228 | |
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| 229 | if ( offset ) // buffer not aligned |
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| 230 | { |
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| 231 | if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; |
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| 232 | else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; |
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| 233 | else r_burst_nflits = m_flits_per_burst; |
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| 234 | } |
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| 235 | else // buffer aligned |
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| 236 | { |
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| 237 | r_burst_nflits = m_flits_per_burst; |
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| 238 | } |
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| 239 | r_initiator_fsm = M_READ_CMD; |
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| 240 | break; |
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| 241 | } |
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| 242 | //////////////// |
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| 243 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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| 244 | { |
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[151] | 245 | if ( p_vci_initiator.cmdack.read() ) |
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| 246 | { |
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[260] | 247 | if ( r_flit_count == (r_burst_nflits.read() - 1) ) // last flit in a burst |
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[151] | 248 | { |
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| 249 | r_initiator_fsm = M_READ_RSP; |
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| 250 | r_flit_count = 0; |
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| 251 | } |
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[260] | 252 | else // not the last flit |
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[151] | 253 | { |
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[260] | 254 | r_flit_count = r_flit_count.read() + 1; |
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[151] | 255 | } |
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[260] | 256 | |
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| 257 | // compute next flit address and next local buffer index |
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| 258 | r_buf_address = r_buf_address.read() + 4; |
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| 259 | r_index = r_index.read() + 1; |
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[151] | 260 | } |
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| 261 | break; |
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| 262 | } |
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[260] | 263 | //////////////// |
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| 264 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
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[151] | 265 | { |
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| 266 | if ( p_vci_initiator.rspval.read() ) |
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| 267 | { |
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[260] | 268 | bool aligned = (r_burst_offset.read() == 0); |
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| 269 | |
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| 270 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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[151] | 271 | { |
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[260] | 272 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 273 | } |
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[260] | 274 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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| 275 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) |
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[151] | 276 | { |
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[260] | 277 | if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block |
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| 278 | { |
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| 279 | r_initiator_fsm = M_READ_SUCCESS; |
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| 280 | } |
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| 281 | else // last burst not last block |
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| 282 | { |
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| 283 | r_index = 0; |
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| 284 | r_burst_count = 0; |
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| 285 | r_block_count = r_block_count.read() + 1; |
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| 286 | r_initiator_fsm = M_READ_BLOCK; |
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| 287 | } |
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[151] | 288 | } |
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[260] | 289 | else // not the last burst |
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| 290 | { |
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| 291 | r_burst_count = r_burst_count.read() + 1; |
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| 292 | r_initiator_fsm = M_READ_BURST; |
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| 293 | } |
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[151] | 294 | } |
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| 295 | break; |
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| 296 | } |
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[260] | 297 | /////////////////// |
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[151] | 298 | case M_READ_SUCCESS: |
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[260] | 299 | case M_READ_ERROR: |
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[151] | 300 | { |
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| 301 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 302 | break; |
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| 303 | } |
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[260] | 304 | /////////////////// |
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| 305 | case M_WRITE_BURST: // Compute the number of flits in the burst |
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[151] | 306 | { |
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[260] | 307 | uint32_t offset = r_burst_offset.read(); |
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| 308 | |
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| 309 | if ( offset ) // buffer not aligned |
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| 310 | { |
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| 311 | if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; |
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| 312 | else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; |
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| 313 | else r_burst_nflits = m_flits_per_burst; |
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| 314 | } |
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| 315 | else // buffer aligned |
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| 316 | { |
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| 317 | r_burst_nflits = m_flits_per_burst; |
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| 318 | } |
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| 319 | r_initiator_fsm = M_WRITE_CMD; |
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[151] | 320 | break; |
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| 321 | } |
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[260] | 322 | ///////////////// |
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[151] | 323 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
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| 324 | { |
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[228] | 325 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
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[151] | 326 | break; |
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| 327 | } |
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[260] | 328 | ///////////////// |
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[151] | 329 | case M_WRITE_RSP: // This is actually a multi-flits VCI READ response |
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| 330 | { |
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[260] | 331 | bool aligned = (r_burst_offset.read() == 0); |
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| 332 | |
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[151] | 333 | if ( p_vci_initiator.rspval.read() ) |
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| 334 | { |
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[260] | 335 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
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| 336 | r_index = r_index.read() + 1; |
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| 337 | |
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| 338 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
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[151] | 339 | { |
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[272] | 340 | r_flit_count = 0; |
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| 341 | r_buf_address = r_buf_address.read() + (r_burst_nflits.read()<<2); |
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[260] | 342 | |
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[272] | 343 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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[260] | 344 | { |
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| 345 | r_initiator_fsm = M_WRITE_ERROR; |
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| 346 | } |
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| 347 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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| 348 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst |
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| 349 | { |
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| 350 | r_initiator_fsm = M_WRITE_BLOCK; |
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| 351 | } |
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| 352 | else // not the last burst |
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| 353 | { |
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| 354 | r_burst_count = r_burst_count.read() + 1; |
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| 355 | r_initiator_fsm = M_WRITE_BURST; |
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| 356 | } |
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[151] | 357 | } |
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| 358 | else |
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| 359 | { |
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[228] | 360 | r_flit_count = r_flit_count.read() + 1; |
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[151] | 361 | } |
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| 362 | } |
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| 363 | break; |
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| 364 | } |
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[260] | 365 | /////////////////// |
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[151] | 366 | case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles |
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| 367 | { |
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| 368 | if ( r_latency_count == 0 ) |
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| 369 | { |
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| 370 | r_latency_count = m_latency; |
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[216] | 371 | ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); |
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[260] | 372 | if( ::write(m_fd, r_local_buffer, m_flits_per_block*vci_param::B) < 0 ) |
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[151] | 373 | { |
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| 374 | r_initiator_fsm = M_WRITE_ERROR; |
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| 375 | } |
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[272] | 376 | else if ( r_block_count.read() == r_nblocks.read() - 1 ) |
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[151] | 377 | { |
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| 378 | r_initiator_fsm = M_WRITE_SUCCESS; |
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| 379 | } |
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| 380 | else |
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| 381 | { |
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[272] | 382 | r_burst_count = 0; |
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| 383 | r_index = 0; |
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| 384 | r_block_count = r_block_count.read() + 1; |
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[260] | 385 | r_initiator_fsm = M_WRITE_BURST; |
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[151] | 386 | } |
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| 387 | } |
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| 388 | else |
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| 389 | { |
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| 390 | r_latency_count = r_latency_count - 1; |
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| 391 | } |
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| 392 | break; |
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| 393 | } |
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[260] | 394 | ///////////////////// |
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[151] | 395 | case M_WRITE_SUCCESS: |
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| 396 | case M_WRITE_ERROR: |
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| 397 | { |
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| 398 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 399 | break; |
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| 400 | } |
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| 401 | } // end switch r_initiator_fsm |
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| 402 | } // end transition |
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| 403 | |
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| 404 | ////////////////////// |
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| 405 | tmpl(void)::genMoore() |
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| 406 | { |
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| 407 | // p_vci_target port |
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[164] | 408 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
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| 409 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
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| 410 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
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[151] | 411 | p_vci_target.reop = true; |
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| 412 | |
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| 413 | switch(r_target_fsm) { |
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| 414 | case T_IDLE: |
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| 415 | p_vci_target.cmdack = true; |
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[260] | 416 | p_vci_target.rspval = false; |
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[151] | 417 | break; |
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| 418 | case T_READ_STATUS: |
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| 419 | p_vci_target.cmdack = false; |
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[260] | 420 | p_vci_target.rspval = true; |
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| 421 | if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; |
---|
| 422 | else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; |
---|
| 423 | else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; |
---|
[151] | 424 | else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; |
---|
| 425 | else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; |
---|
| 426 | else p_vci_target.rdata = BLOCK_DEVICE_BUSY; |
---|
| 427 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 428 | break; |
---|
| 429 | case T_READ_BUFFER: |
---|
| 430 | p_vci_target.cmdack = false; |
---|
[260] | 431 | p_vci_target.rspval = true; |
---|
| 432 | p_vci_target.rdata = (uint32_t)r_buf_address.read(); |
---|
[151] | 433 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 434 | break; |
---|
| 435 | case T_READ_COUNT: |
---|
| 436 | p_vci_target.cmdack = false; |
---|
[260] | 437 | p_vci_target.rspval = true; |
---|
| 438 | p_vci_target.rdata = (uint32_t)r_nblocks.read(); |
---|
[151] | 439 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 440 | break; |
---|
| 441 | case T_READ_LBA: |
---|
| 442 | p_vci_target.cmdack = false; |
---|
[260] | 443 | p_vci_target.rspval = true; |
---|
| 444 | p_vci_target.rdata = (uint32_t)r_lba.read(); |
---|
[151] | 445 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 446 | break; |
---|
| 447 | case T_READ_IRQEN: |
---|
| 448 | p_vci_target.cmdack = false; |
---|
[260] | 449 | p_vci_target.rspval = true; |
---|
| 450 | p_vci_target.rdata = (uint32_t)r_irq_enable.read(); |
---|
[151] | 451 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 452 | break; |
---|
| 453 | case T_READ_SIZE: |
---|
| 454 | p_vci_target.cmdack = false; |
---|
[260] | 455 | p_vci_target.rspval = true; |
---|
[151] | 456 | p_vci_target.rdata = (uint32_t)m_device_size; |
---|
| 457 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 458 | break; |
---|
| 459 | case T_READ_BLOCK: |
---|
| 460 | p_vci_target.cmdack = false; |
---|
[260] | 461 | p_vci_target.rspval = true; |
---|
[216] | 462 | p_vci_target.rdata = (uint32_t)m_flits_per_block*vci_param::B; |
---|
[151] | 463 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 464 | break; |
---|
| 465 | case T_READ_ERROR: |
---|
| 466 | p_vci_target.cmdack = false; |
---|
[260] | 467 | p_vci_target.rspval = true; |
---|
[151] | 468 | p_vci_target.rdata = 0; |
---|
| 469 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
| 470 | break; |
---|
| 471 | case T_WRITE_ERROR: |
---|
| 472 | p_vci_target.cmdack = false; |
---|
[260] | 473 | p_vci_target.rspval = true; |
---|
[151] | 474 | p_vci_target.rdata = 0; |
---|
| 475 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
| 476 | break; |
---|
| 477 | default: |
---|
| 478 | p_vci_target.cmdack = false; |
---|
| 479 | p_vci_target.rspval = true; |
---|
| 480 | p_vci_target.rdata = 0; |
---|
| 481 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
| 482 | break; |
---|
| 483 | } // end switch target fsm |
---|
| 484 | |
---|
| 485 | // p_vci_initiator port |
---|
[164] | 486 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
[151] | 487 | p_vci_initiator.trdid = 0; |
---|
| 488 | p_vci_initiator.contig = true; |
---|
| 489 | p_vci_initiator.cons = false; |
---|
| 490 | p_vci_initiator.wrap = false; |
---|
| 491 | p_vci_initiator.cfixed = false; |
---|
| 492 | p_vci_initiator.clen = 0; |
---|
| 493 | |
---|
| 494 | switch (r_initiator_fsm) { |
---|
| 495 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
| 496 | p_vci_initiator.rspack = false; |
---|
| 497 | p_vci_initiator.cmdval = true; |
---|
[260] | 498 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 499 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
[284] | 500 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; // or _MISS ? |
---|
[151] | 501 | p_vci_initiator.wdata = 0; |
---|
| 502 | p_vci_initiator.be = (uint32_t)0xF; |
---|
[260] | 503 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2); |
---|
[151] | 504 | p_vci_initiator.eop = true; |
---|
| 505 | break; |
---|
| 506 | case M_READ_CMD: // It is actually a multi-flits VCI WRITE command |
---|
| 507 | p_vci_initiator.rspack = false; |
---|
| 508 | p_vci_initiator.cmdval = true; |
---|
[260] | 509 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 510 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
[284] | 511 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
[260] | 512 | p_vci_initiator.wdata = (uint32_t)r_local_buffer[r_index.read()]; |
---|
[151] | 513 | p_vci_initiator.be = 0xF; |
---|
[260] | 514 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2); |
---|
| 515 | p_vci_initiator.eop = ( r_flit_count.read() == (r_burst_nflits.read() - 1) ); |
---|
[151] | 516 | break; |
---|
| 517 | case M_READ_RSP: |
---|
| 518 | case M_WRITE_RSP: |
---|
| 519 | p_vci_initiator.rspack = true; |
---|
| 520 | p_vci_initiator.cmdval = false; |
---|
[260] | 521 | break; |
---|
[151] | 522 | default: |
---|
[260] | 523 | p_vci_initiator.rspack = false; |
---|
| 524 | p_vci_initiator.cmdval = false; |
---|
| 525 | break; |
---|
[151] | 526 | } |
---|
| 527 | |
---|
| 528 | // IRQ signal |
---|
| 529 | if(((r_initiator_fsm == M_READ_SUCCESS) || |
---|
| 530 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
---|
| 531 | (r_initiator_fsm == M_READ_ERROR) || |
---|
| 532 | (r_initiator_fsm == M_WRITE_ERROR) ) && r_irq_enable) p_irq = true; |
---|
| 533 | else p_irq = false; |
---|
| 534 | } // end GenMoore() |
---|
| 535 | |
---|
| 536 | ////////////////////////////////////////////////////////////////////////////// |
---|
[374] | 537 | tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name name, |
---|
[260] | 538 | const soclib::common::MappingTable &mt, |
---|
| 539 | const soclib::common::IntTab &srcid, |
---|
| 540 | const soclib::common::IntTab &tgtid, |
---|
| 541 | const std::string &filename, |
---|
| 542 | const uint32_t block_size, |
---|
| 543 | const uint32_t burst_size, |
---|
| 544 | const uint32_t latency) |
---|
[151] | 545 | |
---|
| 546 | : caba::BaseModule(name), |
---|
| 547 | m_segment(mt.getSegment(tgtid)), |
---|
| 548 | m_srcid(mt.indexForId(srcid)), |
---|
| 549 | m_flits_per_block(block_size/vci_param::B), |
---|
| 550 | m_flits_per_burst(burst_size/vci_param::B), |
---|
| 551 | m_bursts_per_block(block_size/burst_size), |
---|
| 552 | m_latency(latency), |
---|
| 553 | p_clk("p_clk"), |
---|
| 554 | p_resetn("p_resetn"), |
---|
| 555 | p_vci_initiator("p_vci_initiator"), |
---|
| 556 | p_vci_target("p_vci_target"), |
---|
| 557 | p_irq("p_irq") |
---|
| 558 | { |
---|
| 559 | SC_METHOD(transition); |
---|
| 560 | sensitive_pos << p_clk; |
---|
| 561 | |
---|
| 562 | SC_METHOD(genMoore); |
---|
| 563 | sensitive_neg << p_clk; |
---|
| 564 | |
---|
[256] | 565 | if( (block_size != 64 ) && |
---|
| 566 | (block_size != 128) && |
---|
| 567 | (block_size != 256) && |
---|
| 568 | (block_size != 512) && |
---|
| 569 | (block_size != 1024) && |
---|
| 570 | (block_size != 2048) && |
---|
| 571 | (block_size != 4096) ) |
---|
[151] | 572 | { |
---|
[374] | 573 | std::cout << "Error in component VciBlockDeviceTsar : " << name << std::endl; |
---|
[256] | 574 | std::cout << "The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" << std::endl; |
---|
[151] | 575 | exit(1); |
---|
| 576 | } |
---|
[260] | 577 | if( (burst_size != 1 ) && |
---|
| 578 | (burst_size != 2 ) && |
---|
| 579 | (burst_size != 4 ) && |
---|
| 580 | (burst_size != 8 ) && |
---|
| 581 | (burst_size != 16) && |
---|
| 582 | (burst_size != 32) && |
---|
| 583 | (burst_size != 64) ) |
---|
| 584 | { |
---|
[374] | 585 | std::cout << "Error in component VciBlockDeviceTsar : " << name << std::endl; |
---|
[260] | 586 | std::cout << "The burst size must be 1, 2, 4, 8, 16, 32 or 64 bytes" << std::endl; |
---|
| 587 | exit(1); |
---|
| 588 | } |
---|
[151] | 589 | if ( m_segment.size() < 32 ) |
---|
| 590 | { |
---|
[374] | 591 | std::cout << "Error in component VciBlockDeviceTsar : " << name << std::endl; |
---|
[151] | 592 | std::cout << "The size of the segment cannot be smaller than 32 bytes" << std::endl; |
---|
| 593 | exit(1); |
---|
| 594 | } |
---|
| 595 | if ( (m_segment.baseAddress() & 0x0000001F) != 0 ) |
---|
| 596 | { |
---|
[374] | 597 | std::cout << "Error in component VciBlockDeviceTsar : " << name << std::endl; |
---|
[151] | 598 | std::cout << "The base address of the segment must be multiple of 32 bytes" << std::endl; |
---|
| 599 | exit(1); |
---|
| 600 | } |
---|
| 601 | if ( vci_param::B != 4 ) |
---|
| 602 | { |
---|
[374] | 603 | std::cout << "Error in component VciBlockDeviceTsar : " << name << std::endl; |
---|
[151] | 604 | std::cout << "The VCI data fields must have 32 bits" << std::endl; |
---|
| 605 | exit(1); |
---|
| 606 | } |
---|
| 607 | m_fd = ::open(filename.c_str(), O_RDWR); |
---|
| 608 | if ( m_fd < 0 ) |
---|
| 609 | { |
---|
[374] | 610 | std::cout << "Error in component VciBlockDeviceTsar : " << name << std::endl; |
---|
[151] | 611 | std::cout << "Unable to open file " << filename << std::endl; |
---|
| 612 | exit(1); |
---|
| 613 | } |
---|
| 614 | m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; |
---|
| 615 | if ( m_device_size > ((uint64_t)1<<32) ) |
---|
| 616 | { |
---|
| 617 | std::cout << "Warning: block device " << name << std::endl; |
---|
| 618 | std::cout << "The file " << filename << std::endl; |
---|
| 619 | std::cout << "has more blocks than addressable with the 32 bits PIBUS address" << std::endl; |
---|
| 620 | m_device_size = ((uint64_t)1<<32); |
---|
| 621 | } |
---|
| 622 | |
---|
[260] | 623 | r_local_buffer = new uint32_t[m_flits_per_block]; |
---|
| 624 | |
---|
[151] | 625 | } // end constructor |
---|
| 626 | |
---|
| 627 | ////////////////////////// |
---|
| 628 | tmpl(void)::print_trace() |
---|
| 629 | { |
---|
| 630 | const char* initiator_str[] = { |
---|
[260] | 631 | "IDLE", |
---|
| 632 | |
---|
| 633 | "READ_BLOCK", |
---|
| 634 | "READ_BURST", |
---|
| 635 | "READ_CMD", |
---|
| 636 | "READ_RSP", |
---|
| 637 | "READ_TEST", |
---|
| 638 | "READ_SUCCESS", |
---|
| 639 | "READ_ERROR", |
---|
| 640 | |
---|
| 641 | "WRITE_BURST", |
---|
| 642 | "WRITE_CMD", |
---|
| 643 | "WRITE_RSP", |
---|
| 644 | "WRITE_BLOCK", |
---|
[151] | 645 | "WRITE_SUCCESS", |
---|
[260] | 646 | "WRITE_ERROR", |
---|
[151] | 647 | }; |
---|
| 648 | const char* target_str[] = { |
---|
| 649 | "IDLE ", |
---|
| 650 | "WRITE_BUFFER", |
---|
| 651 | "READ_BUFFER ", |
---|
| 652 | "WRITE_COUNT ", |
---|
| 653 | "READ_COUNT ", |
---|
| 654 | "WRITE_LBA ", |
---|
| 655 | "READ_LBA ", |
---|
| 656 | "WRITE_OP ", |
---|
| 657 | "READ_STATUS ", |
---|
| 658 | "WRITE_IRQEN ", |
---|
| 659 | "READ_IRQEN ", |
---|
| 660 | "READ_SIZE ", |
---|
| 661 | "READ_BLOCK ", |
---|
| 662 | "READ_ERROR ", |
---|
| 663 | "WRITE_ERROR ", |
---|
| 664 | }; |
---|
| 665 | |
---|
| 666 | std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()] |
---|
| 667 | << " BDEV_INI : " << initiator_str[r_initiator_fsm.read()] |
---|
| 668 | << " block = " << r_block_count.read() |
---|
| 669 | << " burst = " << r_burst_count.read() |
---|
| 670 | << " flit = " << r_flit_count.read() <<std::endl; |
---|
| 671 | } |
---|
| 672 | |
---|
| 673 | |
---|
| 674 | }} // end namespace |
---|
| 675 | |
---|
| 676 | // Local Variables: |
---|
| 677 | // tab-width: 4 |
---|
| 678 | // c-basic-offset: 4 |
---|
| 679 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 680 | // indent-tabs-mode: nil |
---|
| 681 | // End: |
---|
| 682 | |
---|
| 683 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 684 | |
---|