[151] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, Asim |
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| 24 | * alain.greiner@lip6.fr april 2011 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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| 29 | #include <stdint.h> |
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| 30 | #include <iostream> |
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| 31 | #include <fcntl.h> |
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[374] | 32 | #include "vci_block_device_tsar.h" |
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[151] | 33 | |
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[580] | 34 | #define DEBUG_BDEV 0 |
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| 35 | |
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[151] | 36 | namespace soclib { namespace caba { |
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| 37 | |
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[374] | 38 | #define tmpl(t) template<typename vci_param> t VciBlockDeviceTsar<vci_param> |
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[151] | 39 | |
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| 40 | using namespace soclib::caba; |
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| 41 | using namespace soclib::common; |
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| 42 | |
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| 43 | //////////////////////// |
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| 44 | tmpl(void)::transition() |
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| 45 | { |
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| 46 | if(p_resetn.read() == false) |
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| 47 | { |
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[392] | 48 | r_initiator_fsm = M_IDLE; |
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| 49 | r_target_fsm = T_IDLE; |
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| 50 | r_irq_enable = true; |
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| 51 | r_go = false; |
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[260] | 52 | return; |
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[151] | 53 | } |
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| 54 | |
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| 55 | ////////////////////////////////////////////////////////////////////////////// |
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| 56 | // The Target FSM controls the following registers: |
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| 57 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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| 58 | ////////////////////////////////////////////////////////////////////////////// |
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| 59 | |
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| 60 | switch(r_target_fsm) { |
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[260] | 61 | //////////// |
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[151] | 62 | case T_IDLE: |
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| 63 | { |
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| 64 | if ( p_vci_target.cmdval.read() ) |
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| 65 | { |
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| 66 | r_srcid = p_vci_target.srcid.read(); |
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| 67 | r_trdid = p_vci_target.trdid.read(); |
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| 68 | r_pktid = p_vci_target.pktid.read(); |
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[260] | 69 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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[408] | 70 | |
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| 71 | bool found = false; |
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| 72 | std::list<soclib::common::Segment>::iterator seg; |
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| 73 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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| 74 | { |
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| 75 | if ( seg->contains(address) ) found = true; |
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| 76 | } |
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| 77 | |
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[151] | 78 | bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); |
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[392] | 79 | uint32_t cell = (uint32_t)((address & 0x3F)>>2); |
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[151] | 80 | |
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[408] | 81 | if ( !read && not found ) r_target_fsm = T_WRITE_ERROR; |
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| 82 | else if( read && not found ) r_target_fsm = T_READ_ERROR; |
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| 83 | else if( !read && not p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; |
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| 84 | else if( read && not p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; |
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[260] | 85 | else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; |
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| 86 | else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; |
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[392] | 87 | else if( !read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_WRITE_BUFFER_EXT; |
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| 88 | else if( read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_READ_BUFFER_EXT; |
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[260] | 89 | else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; |
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| 90 | else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; |
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| 91 | else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; |
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| 92 | else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; |
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| 93 | else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; |
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| 94 | else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; |
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| 95 | else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; |
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| 96 | else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; |
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| 97 | else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; |
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| 98 | else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; |
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[580] | 99 | |
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| 100 | // get write data value for both 32 bits and 64 bits data width |
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| 101 | if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) |
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| 102 | r_tdata = (uint32_t)(p_vci_target.wdata.read()>>32); |
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| 103 | else |
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| 104 | r_tdata = p_vci_target.wdata.read(); |
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[151] | 105 | } |
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| 106 | break; |
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| 107 | } |
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[260] | 108 | //////////////////// |
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[151] | 109 | case T_WRITE_BUFFER: |
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| 110 | { |
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[580] | 111 | if (p_vci_target.rspack.read() ) |
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| 112 | { |
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[522] | 113 | if (r_initiator_fsm.read() == M_IDLE) |
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| 114 | { |
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[580] | 115 | |
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| 116 | #if DEBUG_BDEV |
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| 117 | std::cout << " <BDEV_TGT WRITE_BUFFER> value = " << r_tdata.read() << std::endl; |
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| 118 | #endif |
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[522] | 119 | r_buf_address = (uint64_t)r_tdata.read(); |
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| 120 | r_target_fsm = T_IDLE; |
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[580] | 121 | } |
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[392] | 122 | } |
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[151] | 123 | break; |
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| 124 | } |
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[392] | 125 | //////////////////////// |
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| 126 | case T_WRITE_BUFFER_EXT: |
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| 127 | { |
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[580] | 128 | if (p_vci_target.rspack.read() ) |
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| 129 | { |
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[522] | 130 | if (r_initiator_fsm.read() == M_IDLE) |
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| 131 | { |
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[580] | 132 | |
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| 133 | #if DEBUG_BDEV |
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| 134 | std::cout << " <BDEV_TGT WRITE_BUFFER_EXT> value = " << r_tdata.read() << std::endl; |
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| 135 | #endif |
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| 136 | r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32); |
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[522] | 137 | r_target_fsm = T_IDLE; |
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[580] | 138 | } |
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[392] | 139 | } |
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| 140 | break; |
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| 141 | } |
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[260] | 142 | /////////////////// |
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[151] | 143 | case T_WRITE_COUNT: |
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| 144 | { |
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[580] | 145 | if (p_vci_target.rspack.read() ) |
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| 146 | { |
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[522] | 147 | if (r_initiator_fsm.read() == M_IDLE) |
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| 148 | { |
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[580] | 149 | |
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| 150 | #if DEBUG_BDEV |
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| 151 | std::cout << " <BDEV_TGT WRITE_COUNT> value = " << r_tdata.read() << std::endl; |
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| 152 | #endif |
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[522] | 153 | r_nblocks = (uint32_t)r_tdata.read(); |
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| 154 | r_target_fsm = T_IDLE; |
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| 155 | } |
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[580] | 156 | } |
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[151] | 157 | break; |
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| 158 | } |
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[260] | 159 | ///////////////// |
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[151] | 160 | case T_WRITE_LBA: |
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| 161 | { |
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[580] | 162 | if (p_vci_target.rspack.read() ) |
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| 163 | { |
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| 164 | if (r_initiator_fsm.read() == M_IDLE) |
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| 165 | { |
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| 166 | |
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| 167 | #if DEBUG_BDEV |
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| 168 | std::cout << " <BDEV_TGT WRITE_LBA> value = " << r_tdata.read() << std::endl; |
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[522] | 169 | #endif |
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| 170 | r_lba = (uint32_t)r_tdata.read(); |
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| 171 | r_target_fsm = T_IDLE; |
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| 172 | } |
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[580] | 173 | } |
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[151] | 174 | break; |
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| 175 | } |
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[260] | 176 | //////////////// |
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[151] | 177 | case T_WRITE_OP: |
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| 178 | { |
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[392] | 179 | if ( p_vci_target.rspack.read() ) |
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[151] | 180 | { |
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[522] | 181 | if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_READ) and |
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[392] | 182 | (r_initiator_fsm.read() == M_IDLE) ) |
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[151] | 183 | { |
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[580] | 184 | |
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| 185 | #if DEBUG_BDEV |
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| 186 | std::cout << " <BDEV_TGT WRITE_LBA> value = READ" << std::endl; |
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| 187 | #endif |
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[151] | 188 | r_read = true; |
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[392] | 189 | r_go = true; |
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[151] | 190 | } |
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[522] | 191 | else if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_WRITE) and |
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[392] | 192 | (r_initiator_fsm.read() == M_IDLE) ) |
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[151] | 193 | { |
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[580] | 194 | |
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| 195 | #if DEBUG_BDEV |
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| 196 | std::cout << " <BDEV_TGT WRITE_LBA> value = WRITE" << std::endl; |
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| 197 | #endif |
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[151] | 198 | r_read = false; |
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[392] | 199 | r_go = true; |
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[151] | 200 | } |
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[392] | 201 | else |
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| 202 | { |
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[580] | 203 | |
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| 204 | #if DEBUG_BDEV |
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| 205 | std::cout << " <BDEV_TGT WRITE_LBA> value = SOFT RESET" << std::endl; |
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| 206 | #endif |
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[392] | 207 | r_go = false; |
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| 208 | } |
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| 209 | r_target_fsm = T_IDLE; |
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[151] | 210 | } |
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| 211 | break; |
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| 212 | } |
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[260] | 213 | /////////////////// |
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[151] | 214 | case T_WRITE_IRQEN: |
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| 215 | { |
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[392] | 216 | if ( p_vci_target.rspack.read() ) |
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| 217 | { |
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[580] | 218 | |
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| 219 | #if DEBUG_BDEV |
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| 220 | std::cout << " <BDEV_TGT WRITE_IRQEN> value = " << r_tdata.read() << std::endl; |
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[522] | 221 | #endif |
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[392] | 222 | r_target_fsm = T_IDLE; |
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[522] | 223 | r_irq_enable = (r_tdata.read() != 0); |
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[392] | 224 | } |
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[151] | 225 | break; |
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| 226 | } |
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[260] | 227 | /////////////////// |
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[151] | 228 | case T_READ_BUFFER: |
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[392] | 229 | case T_READ_BUFFER_EXT: |
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[151] | 230 | case T_READ_COUNT: |
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| 231 | case T_READ_LBA: |
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| 232 | case T_READ_IRQEN: |
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| 233 | case T_READ_SIZE: |
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| 234 | case T_READ_BLOCK: |
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| 235 | case T_READ_ERROR: |
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| 236 | case T_WRITE_ERROR: |
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| 237 | { |
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| 238 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 239 | break; |
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| 240 | } |
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[260] | 241 | /////////////////// |
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[151] | 242 | case T_READ_STATUS: |
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| 243 | { |
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| 244 | if ( p_vci_target.rspack.read() ) |
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| 245 | { |
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| 246 | r_target_fsm = T_IDLE; |
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| 247 | if( (r_initiator_fsm == M_READ_SUCCESS ) || |
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| 248 | (r_initiator_fsm == M_READ_ERROR ) || |
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| 249 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
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| 250 | (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; |
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| 251 | } |
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| 252 | break; |
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| 253 | } |
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| 254 | } // end switch target fsm |
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| 255 | |
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[260] | 256 | ////////////////////////////////////////////////////////////////////////////// |
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| 257 | // The initiator FSM executes a loop, transfering one block per iteration. |
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| 258 | // Each block is split in bursts, and the number of bursts depends |
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| 259 | // on the memory buffer alignment on a burst boundary: |
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[400] | 260 | // - If buffer aligned, all burst have the same length (m_words_per burst) |
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[260] | 261 | // and the number of bursts is (m_bursts_per_block). |
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| 262 | // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) |
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[400] | 263 | // and first and last burst are shorter, because all words in a burst |
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[260] | 264 | // must be contained in a single cache line. |
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[400] | 265 | // first burst => nwords = m_words_per_burst - offset |
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| 266 | // last burst => nwords = offset |
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| 267 | // other burst => nwords = m_words_per_burst |
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[260] | 268 | ////////////////////////////////////////////////////////////////////////////// |
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| 269 | |
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| 270 | switch( r_initiator_fsm.read() ) { |
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| 271 | //////////// |
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| 272 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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[151] | 273 | { |
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[260] | 274 | if ( r_go.read() ) |
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[151] | 275 | { |
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[260] | 276 | r_index = 0; |
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[151] | 277 | r_block_count = 0; |
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| 278 | r_burst_count = 0; |
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[433] | 279 | r_words_count = 0; |
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[151] | 280 | r_latency_count = m_latency; |
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| 281 | |
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[260] | 282 | // compute r_burst_offset (zero when buffer aligned) |
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[400] | 283 | r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_words_per_burst); |
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[260] | 284 | |
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| 285 | // start tranfer |
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| 286 | if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; |
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| 287 | else r_initiator_fsm = M_WRITE_BURST; |
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[151] | 288 | } |
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| 289 | break; |
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[260] | 290 | } |
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| 291 | ////////////////// |
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[228] | 292 | case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles |
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[151] | 293 | { |
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[260] | 294 | if ( r_latency_count.read() == 0 ) |
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[151] | 295 | { |
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| 296 | r_latency_count = m_latency; |
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[400] | 297 | ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); |
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| 298 | if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) |
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[151] | 299 | { |
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[260] | 300 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 301 | } |
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| 302 | else |
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| 303 | { |
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[260] | 304 | r_burst_count = 0; |
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[580] | 305 | r_words_count = 0; |
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[260] | 306 | r_initiator_fsm = M_READ_BURST; |
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[151] | 307 | } |
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| 308 | } |
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| 309 | else |
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| 310 | { |
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[260] | 311 | r_latency_count = r_latency_count.read() - 1; |
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[151] | 312 | } |
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| 313 | break; |
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| 314 | } |
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[260] | 315 | ////////////////// |
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[400] | 316 | case M_READ_BURST: // Compute the number of words and the number of flits in the burst |
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| 317 | // The number of flits can be smaller than the number of words |
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| 318 | // in case of 8 bytes flits... |
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[151] | 319 | { |
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[400] | 320 | uint32_t nwords; |
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[260] | 321 | uint32_t offset = r_burst_offset.read(); |
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| 322 | |
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| 323 | if ( offset ) // buffer not aligned |
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| 324 | { |
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[400] | 325 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
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| 326 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
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| 327 | else nwords = m_words_per_burst; |
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[260] | 328 | } |
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| 329 | else // buffer aligned |
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| 330 | { |
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[400] | 331 | nwords = m_words_per_burst; |
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[260] | 332 | } |
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[400] | 333 | |
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| 334 | r_burst_nwords = nwords; |
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| 335 | r_initiator_fsm = M_READ_CMD; |
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[260] | 336 | break; |
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| 337 | } |
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| 338 | //////////////// |
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| 339 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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| 340 | { |
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[151] | 341 | if ( p_vci_initiator.cmdack.read() ) |
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| 342 | { |
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[400] | 343 | uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); |
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| 344 | |
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| 345 | if ( vci_param::B == 4 ) // one word per flit |
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[151] | 346 | { |
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[400] | 347 | if ( nwords <= 1 ) // last flit |
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| 348 | { |
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| 349 | r_initiator_fsm = M_READ_RSP; |
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| 350 | r_words_count = 0; |
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| 351 | } |
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| 352 | else // not the last flit |
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| 353 | { |
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| 354 | r_words_count = r_words_count.read() + 1; |
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| 355 | } |
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| 356 | |
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| 357 | // compute next word address and next local buffer index |
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| 358 | r_buf_address = r_buf_address.read() + 4; |
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| 359 | r_index = r_index.read() + 1; |
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[151] | 360 | } |
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[400] | 361 | else // 2 words per flit |
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[151] | 362 | { |
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[400] | 363 | if ( nwords <= 2 ) // last flit |
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| 364 | { |
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| 365 | r_initiator_fsm = M_READ_RSP; |
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| 366 | r_words_count = 0; |
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| 367 | } |
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| 368 | else // not the last flit |
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| 369 | { |
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| 370 | r_words_count = r_words_count.read() + 2; |
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| 371 | } |
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| 372 | |
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| 373 | // compute next word address and next local buffer index |
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| 374 | if ( nwords == 1 ) |
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| 375 | { |
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| 376 | r_buf_address = r_buf_address.read() + 4; |
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| 377 | r_index = r_index.read() + 1; |
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| 378 | } |
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| 379 | else |
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| 380 | { |
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| 381 | r_buf_address = r_buf_address.read() + 8; |
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| 382 | r_index = r_index.read() + 2; |
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| 383 | } |
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[151] | 384 | } |
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| 385 | } |
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| 386 | break; |
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| 387 | } |
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[260] | 388 | //////////////// |
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| 389 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
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[151] | 390 | { |
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| 391 | if ( p_vci_initiator.rspval.read() ) |
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| 392 | { |
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[260] | 393 | bool aligned = (r_burst_offset.read() == 0); |
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| 394 | |
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| 395 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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[151] | 396 | { |
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[260] | 397 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 398 | } |
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[260] | 399 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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| 400 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) |
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[151] | 401 | { |
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[260] | 402 | if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block |
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| 403 | { |
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| 404 | r_initiator_fsm = M_READ_SUCCESS; |
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| 405 | } |
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| 406 | else // last burst not last block |
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| 407 | { |
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| 408 | r_index = 0; |
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| 409 | r_burst_count = 0; |
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| 410 | r_block_count = r_block_count.read() + 1; |
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| 411 | r_initiator_fsm = M_READ_BLOCK; |
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| 412 | } |
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[151] | 413 | } |
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[260] | 414 | else // not the last burst |
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| 415 | { |
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| 416 | r_burst_count = r_burst_count.read() + 1; |
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| 417 | r_initiator_fsm = M_READ_BURST; |
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| 418 | } |
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[151] | 419 | } |
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| 420 | break; |
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| 421 | } |
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[260] | 422 | /////////////////// |
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[151] | 423 | case M_READ_SUCCESS: |
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[260] | 424 | case M_READ_ERROR: |
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[151] | 425 | { |
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| 426 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 427 | break; |
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| 428 | } |
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[260] | 429 | /////////////////// |
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[400] | 430 | case M_WRITE_BURST: // Compute the number of words in the burst |
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[151] | 431 | { |
---|
[400] | 432 | uint32_t nwords; |
---|
[260] | 433 | uint32_t offset = r_burst_offset.read(); |
---|
| 434 | |
---|
| 435 | if ( offset ) // buffer not aligned |
---|
| 436 | { |
---|
[400] | 437 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
---|
| 438 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
---|
| 439 | else nwords = m_words_per_burst; |
---|
[260] | 440 | } |
---|
| 441 | else // buffer aligned |
---|
| 442 | { |
---|
[400] | 443 | nwords = m_words_per_burst; |
---|
[260] | 444 | } |
---|
[400] | 445 | |
---|
| 446 | r_burst_nwords = nwords; |
---|
[260] | 447 | r_initiator_fsm = M_WRITE_CMD; |
---|
[151] | 448 | break; |
---|
| 449 | } |
---|
[260] | 450 | ///////////////// |
---|
[151] | 451 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
---|
| 452 | { |
---|
[228] | 453 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
---|
[151] | 454 | break; |
---|
| 455 | } |
---|
[260] | 456 | ///////////////// |
---|
[400] | 457 | case M_WRITE_RSP: // This is actually a multi-words VCI READ response |
---|
[151] | 458 | { |
---|
| 459 | if ( p_vci_initiator.rspval.read() ) |
---|
| 460 | { |
---|
[400] | 461 | bool aligned = (r_burst_offset.read() == 0); |
---|
[260] | 462 | |
---|
[400] | 463 | if ( (vci_param::B == 8) and (r_burst_nwords.read() > 1) ) |
---|
| 464 | { |
---|
| 465 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
---|
| 466 | r_local_buffer[r_index.read()+1] = (uint32_t)(p_vci_initiator.rdata.read()>>32); |
---|
| 467 | r_index = r_index.read() + 2; |
---|
| 468 | } |
---|
| 469 | else |
---|
| 470 | { |
---|
| 471 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
---|
| 472 | r_index = r_index.read() + 1; |
---|
| 473 | } |
---|
| 474 | |
---|
[260] | 475 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
---|
[151] | 476 | { |
---|
[400] | 477 | r_words_count = 0; |
---|
| 478 | r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); |
---|
[260] | 479 | |
---|
[392] | 480 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
[260] | 481 | { |
---|
| 482 | r_initiator_fsm = M_WRITE_ERROR; |
---|
| 483 | } |
---|
| 484 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
---|
[400] | 485 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst |
---|
[260] | 486 | { |
---|
| 487 | r_initiator_fsm = M_WRITE_BLOCK; |
---|
| 488 | } |
---|
| 489 | else // not the last burst |
---|
| 490 | { |
---|
| 491 | r_burst_count = r_burst_count.read() + 1; |
---|
| 492 | r_initiator_fsm = M_WRITE_BURST; |
---|
| 493 | } |
---|
[151] | 494 | } |
---|
| 495 | else |
---|
| 496 | { |
---|
[400] | 497 | r_words_count = r_words_count.read() + 1; |
---|
[151] | 498 | } |
---|
| 499 | } |
---|
| 500 | break; |
---|
| 501 | } |
---|
[260] | 502 | /////////////////// |
---|
[151] | 503 | case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles |
---|
| 504 | { |
---|
| 505 | if ( r_latency_count == 0 ) |
---|
| 506 | { |
---|
| 507 | r_latency_count = m_latency; |
---|
[581] | 508 | ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); |
---|
| 509 | if( ::write(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) |
---|
[151] | 510 | { |
---|
| 511 | r_initiator_fsm = M_WRITE_ERROR; |
---|
| 512 | } |
---|
[272] | 513 | else if ( r_block_count.read() == r_nblocks.read() - 1 ) |
---|
[151] | 514 | { |
---|
| 515 | r_initiator_fsm = M_WRITE_SUCCESS; |
---|
| 516 | } |
---|
| 517 | else |
---|
| 518 | { |
---|
[272] | 519 | r_burst_count = 0; |
---|
[400] | 520 | r_index = 0; |
---|
[272] | 521 | r_block_count = r_block_count.read() + 1; |
---|
[400] | 522 | r_initiator_fsm = M_WRITE_BURST; |
---|
[151] | 523 | } |
---|
| 524 | } |
---|
| 525 | else |
---|
| 526 | { |
---|
| 527 | r_latency_count = r_latency_count - 1; |
---|
| 528 | } |
---|
| 529 | break; |
---|
| 530 | } |
---|
[260] | 531 | ///////////////////// |
---|
[151] | 532 | case M_WRITE_SUCCESS: |
---|
| 533 | case M_WRITE_ERROR: |
---|
| 534 | { |
---|
| 535 | if( !r_go ) r_initiator_fsm = M_IDLE; |
---|
| 536 | break; |
---|
| 537 | } |
---|
| 538 | } // end switch r_initiator_fsm |
---|
| 539 | } // end transition |
---|
| 540 | |
---|
| 541 | ////////////////////// |
---|
| 542 | tmpl(void)::genMoore() |
---|
| 543 | { |
---|
| 544 | // p_vci_target port |
---|
[164] | 545 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
---|
| 546 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
---|
| 547 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
---|
[151] | 548 | p_vci_target.reop = true; |
---|
| 549 | |
---|
| 550 | switch(r_target_fsm) { |
---|
| 551 | case T_IDLE: |
---|
| 552 | p_vci_target.cmdack = true; |
---|
[260] | 553 | p_vci_target.rspval = false; |
---|
[514] | 554 | p_vci_target.rdata = 0; |
---|
[151] | 555 | break; |
---|
| 556 | case T_READ_STATUS: |
---|
| 557 | p_vci_target.cmdack = false; |
---|
[260] | 558 | p_vci_target.rspval = true; |
---|
| 559 | if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; |
---|
| 560 | else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; |
---|
| 561 | else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; |
---|
[151] | 562 | else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; |
---|
| 563 | else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; |
---|
| 564 | else p_vci_target.rdata = BLOCK_DEVICE_BUSY; |
---|
| 565 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 566 | break; |
---|
| 567 | case T_READ_BUFFER: |
---|
| 568 | p_vci_target.cmdack = false; |
---|
[260] | 569 | p_vci_target.rspval = true; |
---|
| 570 | p_vci_target.rdata = (uint32_t)r_buf_address.read(); |
---|
[151] | 571 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 572 | break; |
---|
[392] | 573 | case T_READ_BUFFER_EXT: |
---|
| 574 | p_vci_target.cmdack = false; |
---|
| 575 | p_vci_target.rspval = true; |
---|
| 576 | p_vci_target.rdata = (uint32_t)(r_buf_address.read()>>32); |
---|
| 577 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 578 | break; |
---|
[151] | 579 | case T_READ_COUNT: |
---|
| 580 | p_vci_target.cmdack = false; |
---|
[260] | 581 | p_vci_target.rspval = true; |
---|
[400] | 582 | p_vci_target.rdata = r_nblocks.read(); |
---|
[151] | 583 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 584 | break; |
---|
| 585 | case T_READ_LBA: |
---|
| 586 | p_vci_target.cmdack = false; |
---|
[260] | 587 | p_vci_target.rspval = true; |
---|
[400] | 588 | p_vci_target.rdata = r_lba.read(); |
---|
[151] | 589 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 590 | break; |
---|
| 591 | case T_READ_IRQEN: |
---|
| 592 | p_vci_target.cmdack = false; |
---|
[260] | 593 | p_vci_target.rspval = true; |
---|
[400] | 594 | p_vci_target.rdata = r_irq_enable.read(); |
---|
[151] | 595 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 596 | break; |
---|
| 597 | case T_READ_SIZE: |
---|
| 598 | p_vci_target.cmdack = false; |
---|
[260] | 599 | p_vci_target.rspval = true; |
---|
[400] | 600 | p_vci_target.rdata = m_device_size; |
---|
[151] | 601 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 602 | break; |
---|
| 603 | case T_READ_BLOCK: |
---|
| 604 | p_vci_target.cmdack = false; |
---|
[260] | 605 | p_vci_target.rspval = true; |
---|
[451] | 606 | p_vci_target.rdata = m_words_per_block*4; |
---|
[151] | 607 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 608 | break; |
---|
| 609 | case T_READ_ERROR: |
---|
| 610 | p_vci_target.cmdack = false; |
---|
[260] | 611 | p_vci_target.rspval = true; |
---|
[400] | 612 | p_vci_target.rdata = 0; |
---|
[151] | 613 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
| 614 | break; |
---|
| 615 | case T_WRITE_ERROR: |
---|
| 616 | p_vci_target.cmdack = false; |
---|
[260] | 617 | p_vci_target.rspval = true; |
---|
[400] | 618 | p_vci_target.rdata = 0; |
---|
[151] | 619 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
| 620 | break; |
---|
| 621 | default: |
---|
| 622 | p_vci_target.cmdack = false; |
---|
| 623 | p_vci_target.rspval = true; |
---|
[400] | 624 | p_vci_target.rdata = 0; |
---|
[151] | 625 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
| 626 | break; |
---|
| 627 | } // end switch target fsm |
---|
| 628 | |
---|
| 629 | // p_vci_initiator port |
---|
[164] | 630 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
[151] | 631 | p_vci_initiator.trdid = 0; |
---|
| 632 | p_vci_initiator.contig = true; |
---|
| 633 | p_vci_initiator.cons = false; |
---|
| 634 | p_vci_initiator.wrap = false; |
---|
| 635 | p_vci_initiator.cfixed = false; |
---|
| 636 | p_vci_initiator.clen = 0; |
---|
| 637 | |
---|
| 638 | switch (r_initiator_fsm) { |
---|
[401] | 639 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
[151] | 640 | p_vci_initiator.rspack = false; |
---|
| 641 | p_vci_initiator.cmdval = true; |
---|
[260] | 642 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 643 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
[401] | 644 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; |
---|
[151] | 645 | p_vci_initiator.wdata = 0; |
---|
[401] | 646 | p_vci_initiator.be = 0; |
---|
[400] | 647 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
[151] | 648 | p_vci_initiator.eop = true; |
---|
| 649 | break; |
---|
[400] | 650 | case M_READ_CMD: // It is actually a multi-words VCI WRITE command |
---|
[151] | 651 | p_vci_initiator.rspack = false; |
---|
| 652 | p_vci_initiator.cmdval = true; |
---|
[260] | 653 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 654 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
[284] | 655 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
[400] | 656 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
[401] | 657 | if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) |
---|
| 658 | { |
---|
[424] | 659 | p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + |
---|
| 660 | (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); |
---|
[401] | 661 | p_vci_initiator.be = 0xFF; |
---|
[433] | 662 | p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); |
---|
[401] | 663 | } |
---|
| 664 | else |
---|
| 665 | { |
---|
| 666 | p_vci_initiator.wdata = r_local_buffer[r_index.read()]; |
---|
| 667 | p_vci_initiator.be = 0xF; |
---|
[433] | 668 | p_vci_initiator.eop = ( r_words_count.read() == (r_burst_nwords.read() - 1) ); |
---|
[401] | 669 | } |
---|
[151] | 670 | break; |
---|
| 671 | case M_READ_RSP: |
---|
| 672 | case M_WRITE_RSP: |
---|
| 673 | p_vci_initiator.rspack = true; |
---|
| 674 | p_vci_initiator.cmdval = false; |
---|
[260] | 675 | break; |
---|
[151] | 676 | default: |
---|
[260] | 677 | p_vci_initiator.rspack = false; |
---|
| 678 | p_vci_initiator.cmdval = false; |
---|
| 679 | break; |
---|
[151] | 680 | } |
---|
| 681 | |
---|
| 682 | // IRQ signal |
---|
[433] | 683 | if ( ((r_initiator_fsm == M_READ_SUCCESS) || |
---|
| 684 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
---|
| 685 | (r_initiator_fsm == M_READ_ERROR) || |
---|
| 686 | (r_initiator_fsm == M_WRITE_ERROR) ) && |
---|
[580] | 687 | r_irq_enable.read() ) |
---|
| 688 | { |
---|
| 689 | |
---|
| 690 | #if DEBUG_BDEV |
---|
| 691 | std::cout << " <BDEV_INI send IRQ>" << std::endl; |
---|
[522] | 692 | #endif |
---|
| 693 | p_irq = true; |
---|
[580] | 694 | } |
---|
| 695 | else |
---|
| 696 | { |
---|
| 697 | p_irq = false; |
---|
| 698 | } |
---|
[151] | 699 | } // end GenMoore() |
---|
| 700 | |
---|
| 701 | ////////////////////////////////////////////////////////////////////////////// |
---|
[374] | 702 | tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name name, |
---|
[400] | 703 | const soclib::common::MappingTable &mt, |
---|
| 704 | const soclib::common::IntTab &srcid, |
---|
| 705 | const soclib::common::IntTab &tgtid, |
---|
| 706 | const std::string &filename, |
---|
| 707 | const uint32_t block_size, |
---|
| 708 | const uint32_t burst_size, |
---|
| 709 | const uint32_t latency) |
---|
[151] | 710 | |
---|
| 711 | : caba::BaseModule(name), |
---|
[408] | 712 | m_seglist(mt.getSegmentList(tgtid)), |
---|
[151] | 713 | m_srcid(mt.indexForId(srcid)), |
---|
[400] | 714 | m_words_per_block(block_size/4), |
---|
| 715 | m_words_per_burst(burst_size/4), |
---|
[151] | 716 | m_bursts_per_block(block_size/burst_size), |
---|
| 717 | m_latency(latency), |
---|
| 718 | p_clk("p_clk"), |
---|
| 719 | p_resetn("p_resetn"), |
---|
| 720 | p_vci_initiator("p_vci_initiator"), |
---|
| 721 | p_vci_target("p_vci_target"), |
---|
| 722 | p_irq("p_irq") |
---|
| 723 | { |
---|
[433] | 724 | std::cout << " - Building VciBlockDeviceTsar " << name << std::endl; |
---|
| 725 | |
---|
[151] | 726 | SC_METHOD(transition); |
---|
[381] | 727 | dont_initialize(); |
---|
| 728 | sensitive << p_clk.pos(); |
---|
[151] | 729 | |
---|
| 730 | SC_METHOD(genMoore); |
---|
[381] | 731 | dont_initialize(); |
---|
| 732 | sensitive << p_clk.neg(); |
---|
[151] | 733 | |
---|
[409] | 734 | size_t nbsegs = 0; |
---|
[408] | 735 | std::list<soclib::common::Segment>::iterator seg; |
---|
| 736 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
---|
| 737 | { |
---|
[409] | 738 | nbsegs++; |
---|
[408] | 739 | |
---|
| 740 | if ( (seg->baseAddress() & 0x0000003F) != 0 ) |
---|
| 741 | { |
---|
| 742 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 743 | << "The base address of segment " << seg->name() |
---|
| 744 | << " must be multiple of 64 bytes" << std::endl; |
---|
| 745 | exit(1); |
---|
| 746 | } |
---|
| 747 | if ( seg->size() < 64 ) |
---|
| 748 | { |
---|
| 749 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 750 | << "The size of segment " << seg->name() |
---|
| 751 | << " cannot be smaller than 64 bytes" << std::endl; |
---|
| 752 | exit(1); |
---|
| 753 | } |
---|
[433] | 754 | std::cout << " => segment " << seg->name() |
---|
| 755 | << " / base = " << std::hex << seg->baseAddress() |
---|
| 756 | << " / size = " << seg->size() << std::endl; |
---|
[408] | 757 | } |
---|
| 758 | |
---|
[409] | 759 | if( nbsegs == 0 ) |
---|
[408] | 760 | { |
---|
| 761 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 762 | << " No segment allocated" << std::endl; |
---|
| 763 | exit(1); |
---|
| 764 | } |
---|
| 765 | |
---|
[400] | 766 | if( (block_size != 128) && |
---|
[256] | 767 | (block_size != 256) && |
---|
| 768 | (block_size != 512) && |
---|
| 769 | (block_size != 1024) && |
---|
| 770 | (block_size != 2048) && |
---|
| 771 | (block_size != 4096) ) |
---|
[151] | 772 | { |
---|
[408] | 773 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 774 | << " The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" |
---|
| 775 | << std::endl; |
---|
[151] | 776 | exit(1); |
---|
| 777 | } |
---|
[408] | 778 | |
---|
[433] | 779 | if( (burst_size != 8 ) && |
---|
[260] | 780 | (burst_size != 16) && |
---|
| 781 | (burst_size != 32) && |
---|
| 782 | (burst_size != 64) ) |
---|
| 783 | { |
---|
[408] | 784 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
[433] | 785 | << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; |
---|
[260] | 786 | exit(1); |
---|
| 787 | } |
---|
[408] | 788 | |
---|
[400] | 789 | if ( (vci_param::B != 4) and (vci_param::B != 8) ) |
---|
[151] | 790 | { |
---|
[408] | 791 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 792 | << " The VCI data fields must have 32 bits or 64 bits" << std::endl; |
---|
[151] | 793 | exit(1); |
---|
| 794 | } |
---|
[408] | 795 | |
---|
[151] | 796 | m_fd = ::open(filename.c_str(), O_RDWR); |
---|
| 797 | if ( m_fd < 0 ) |
---|
| 798 | { |
---|
[408] | 799 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 800 | << " Unable to open file " << filename << std::endl; |
---|
[151] | 801 | exit(1); |
---|
| 802 | } |
---|
| 803 | m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; |
---|
[408] | 804 | |
---|
| 805 | if ( m_device_size > ((uint64_t)1<<vci_param::N ) ) |
---|
[151] | 806 | { |
---|
[408] | 807 | std::cout << "Error in component VciBlockDeviceTsar" << name |
---|
| 808 | << " The file " << filename |
---|
| 809 | << " has more blocks than addressable with the VCI address" << std::endl; |
---|
| 810 | exit(1); |
---|
[151] | 811 | } |
---|
| 812 | |
---|
[400] | 813 | r_local_buffer = new uint32_t[m_words_per_block]; |
---|
[260] | 814 | |
---|
[151] | 815 | } // end constructor |
---|
| 816 | |
---|
[580] | 817 | ///////////////////////////////// |
---|
[514] | 818 | tmpl(/**/)::~VciBlockDeviceTsar() |
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| 819 | { |
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| 820 | delete [] r_local_buffer; |
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| 821 | } |
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| 822 | |
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| 823 | |
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[151] | 824 | ////////////////////////// |
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| 825 | tmpl(void)::print_trace() |
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| 826 | { |
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[500] | 827 | const char* initiator_str[] = |
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| 828 | { |
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[580] | 829 | "INI_IDLE", |
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[260] | 830 | |
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[580] | 831 | "INI_READ_BLOCK", |
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| 832 | "INI_READ_BURST", |
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| 833 | "INI_READ_CMD", |
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| 834 | "INI_READ_RSP", |
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| 835 | "INI_READ_SUCCESS", |
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| 836 | "INI_READ_ERROR", |
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[260] | 837 | |
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[580] | 838 | "INI_WRITE_BURST", |
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| 839 | "INI_WRITE_CMD", |
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| 840 | "INI_WRITE_RSP", |
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| 841 | "INI_WRITE_BLOCK", |
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| 842 | "INI_WRITE_SUCCESS", |
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| 843 | "INI_WRITE_ERROR", |
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[151] | 844 | }; |
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[500] | 845 | const char* target_str[] = |
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| 846 | { |
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[580] | 847 | "TGT_IDLE", |
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| 848 | "TGT_WRITE_BUFFER", |
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| 849 | "TGT_READ_BUFFER", |
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| 850 | "TGT_WRITE_BUFFER_EXT", |
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| 851 | "TGT_READ_BUFFER_EXT", |
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| 852 | "TGT_WRITE_COUNT", |
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| 853 | "TGT_READ_COUNT", |
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| 854 | "TGT_WRITE_LBA", |
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| 855 | "TGT_READ_LBA", |
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| 856 | "TGT_WRITE_OP", |
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| 857 | "TGT_READ_STATUS", |
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| 858 | "TGT_WRITE_IRQEN", |
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| 859 | "TGT_READ_IRQEN", |
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| 860 | "TGT_READ_SIZE", |
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| 861 | "TGT_READ_BLOCK", |
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| 862 | "TGT_READ_ERROR", |
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| 863 | "TGT_WRITE_ERROR ", |
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[151] | 864 | }; |
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| 865 | |
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[580] | 866 | std::cout << "BDEV " << name() |
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| 867 | << " : " << target_str[r_target_fsm.read()] |
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| 868 | << " / " << initiator_str[r_initiator_fsm.read()] |
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| 869 | << " / buf = " << std::hex << r_buf_address.read() |
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| 870 | << " / lba = " << std::hex << r_lba.read() |
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| 871 | << " / block_count = " << std::dec << r_block_count.read() |
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| 872 | << " / burst_count = " << r_burst_count.read() |
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| 873 | << " / word_count = " << r_words_count.read() <<std::endl; |
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[151] | 874 | } |
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| 875 | |
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| 876 | }} // end namespace |
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| 877 | |
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| 878 | // Local Variables: |
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| 879 | // tab-width: 4 |
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| 880 | // c-basic-offset: 4 |
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| 881 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 882 | // indent-tabs-mode: nil |
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| 883 | // End: |
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| 884 | |
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| 885 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 886 | |
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