[151] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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[898] | 4 | * |
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[151] | 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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[898] | 6 | * |
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[151] | 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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[898] | 10 | * |
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[151] | 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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[898] | 15 | * |
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[151] | 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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[898] | 20 | * |
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[151] | 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, Asim |
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| 24 | * alain.greiner@lip6.fr april 2011 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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| 29 | #include <stdint.h> |
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| 30 | #include <iostream> |
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| 31 | #include <fcntl.h> |
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[374] | 32 | #include "vci_block_device_tsar.h" |
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[599] | 33 | #include "block_device_tsar.h" |
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[151] | 34 | |
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[580] | 35 | #define DEBUG_BDEV 0 |
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| 36 | |
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[151] | 37 | namespace soclib { namespace caba { |
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| 38 | |
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[374] | 39 | #define tmpl(t) template<typename vci_param> t VciBlockDeviceTsar<vci_param> |
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[151] | 40 | |
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| 41 | using namespace soclib::caba; |
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| 42 | using namespace soclib::common; |
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| 43 | |
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| 44 | //////////////////////// |
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| 45 | tmpl(void)::transition() |
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| 46 | { |
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[898] | 47 | if(p_resetn.read() == false) |
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[151] | 48 | { |
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[392] | 49 | r_initiator_fsm = M_IDLE; |
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| 50 | r_target_fsm = T_IDLE; |
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| 51 | r_irq_enable = true; |
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| 52 | r_go = false; |
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[260] | 53 | return; |
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[898] | 54 | } |
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[151] | 55 | |
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| 56 | ////////////////////////////////////////////////////////////////////////////// |
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| 57 | // The Target FSM controls the following registers: |
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| 58 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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| 59 | ////////////////////////////////////////////////////////////////////////////// |
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| 60 | |
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| 61 | switch(r_target_fsm) { |
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[260] | 62 | //////////// |
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[151] | 63 | case T_IDLE: |
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| 64 | { |
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[898] | 65 | if ( p_vci_target.cmdval.read() ) |
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| 66 | { |
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[151] | 67 | r_srcid = p_vci_target.srcid.read(); |
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| 68 | r_trdid = p_vci_target.trdid.read(); |
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| 69 | r_pktid = p_vci_target.pktid.read(); |
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[260] | 70 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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[408] | 71 | |
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| 72 | bool found = false; |
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| 73 | std::list<soclib::common::Segment>::iterator seg; |
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[898] | 74 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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[408] | 75 | { |
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| 76 | if ( seg->contains(address) ) found = true; |
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| 77 | } |
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[151] | 78 | |
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[898] | 79 | bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); |
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| 80 | uint32_t cell = (uint32_t)((address & 0x3F)>>2); |
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| 81 | bool pending = (r_initiator_fsm.read() != M_IDLE); |
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| 82 | |
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[408] | 83 | if ( !read && not found ) r_target_fsm = T_WRITE_ERROR; |
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| 84 | else if( read && not found ) r_target_fsm = T_READ_ERROR; |
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| 85 | else if( !read && not p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; |
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| 86 | else if( read && not p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; |
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[898] | 87 | else if( !read && pending ) r_target_fsm = T_WRITE_ERROR; |
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[260] | 88 | else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; |
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| 89 | else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; |
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[392] | 90 | else if( !read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_WRITE_BUFFER_EXT; |
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| 91 | else if( read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_READ_BUFFER_EXT; |
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[260] | 92 | else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; |
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| 93 | else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; |
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| 94 | else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; |
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| 95 | else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; |
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| 96 | else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; |
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| 97 | else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; |
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| 98 | else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; |
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| 99 | else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; |
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| 100 | else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; |
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| 101 | else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; |
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[580] | 102 | |
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| 103 | // get write data value for both 32 bits and 64 bits data width |
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[898] | 104 | if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) |
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[580] | 105 | r_tdata = (uint32_t)(p_vci_target.wdata.read()>>32); |
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| 106 | else |
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| 107 | r_tdata = p_vci_target.wdata.read(); |
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[151] | 108 | } |
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| 109 | break; |
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| 110 | } |
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[260] | 111 | //////////////////// |
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[151] | 112 | case T_WRITE_BUFFER: |
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| 113 | { |
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[898] | 114 | if (p_vci_target.rspack.read() ) |
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[580] | 115 | { |
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| 116 | #if DEBUG_BDEV |
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| 117 | std::cout << " <BDEV_TGT WRITE_BUFFER> value = " << r_tdata.read() << std::endl; |
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| 118 | #endif |
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[898] | 119 | r_buf_address = (uint64_t)r_tdata.read(); |
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| 120 | r_target_fsm = T_IDLE; |
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[392] | 121 | } |
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[151] | 122 | break; |
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| 123 | } |
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[392] | 124 | //////////////////////// |
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| 125 | case T_WRITE_BUFFER_EXT: |
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| 126 | { |
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[898] | 127 | if (p_vci_target.rspack.read() ) |
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[580] | 128 | { |
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| 129 | #if DEBUG_BDEV |
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| 130 | std::cout << " <BDEV_TGT WRITE_BUFFER_EXT> value = " << r_tdata.read() << std::endl; |
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| 131 | #endif |
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[898] | 132 | r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32); |
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| 133 | r_target_fsm = T_IDLE; |
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[392] | 134 | } |
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| 135 | break; |
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| 136 | } |
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[260] | 137 | /////////////////// |
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[151] | 138 | case T_WRITE_COUNT: |
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| 139 | { |
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[898] | 140 | if (p_vci_target.rspack.read() ) |
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[580] | 141 | { |
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| 142 | #if DEBUG_BDEV |
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| 143 | std::cout << " <BDEV_TGT WRITE_COUNT> value = " << r_tdata.read() << std::endl; |
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| 144 | #endif |
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[898] | 145 | r_nblocks = (uint32_t)r_tdata.read(); |
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| 146 | r_target_fsm = T_IDLE; |
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[580] | 147 | } |
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[151] | 148 | break; |
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| 149 | } |
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[260] | 150 | ///////////////// |
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[151] | 151 | case T_WRITE_LBA: |
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| 152 | { |
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[898] | 153 | if (p_vci_target.rspack.read() ) |
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[580] | 154 | { |
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| 155 | #if DEBUG_BDEV |
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| 156 | std::cout << " <BDEV_TGT WRITE_LBA> value = " << r_tdata.read() << std::endl; |
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[522] | 157 | #endif |
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[898] | 158 | r_lba = (uint32_t)r_tdata.read(); |
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| 159 | r_target_fsm = T_IDLE; |
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[580] | 160 | } |
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[151] | 161 | break; |
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| 162 | } |
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[260] | 163 | //////////////// |
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[151] | 164 | case T_WRITE_OP: |
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| 165 | { |
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[898] | 166 | if ( p_vci_target.rspack.read() ) |
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[151] | 167 | { |
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[522] | 168 | if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_READ) and |
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[392] | 169 | (r_initiator_fsm.read() == M_IDLE) ) |
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[151] | 170 | { |
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[580] | 171 | |
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| 172 | #if DEBUG_BDEV |
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[848] | 173 | std::cout << " <BDEV_TGT WRITE_OP> value = READ" << std::endl; |
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[580] | 174 | #endif |
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[151] | 175 | r_read = true; |
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[392] | 176 | r_go = true; |
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[151] | 177 | } |
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[522] | 178 | else if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_WRITE) and |
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[392] | 179 | (r_initiator_fsm.read() == M_IDLE) ) |
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[151] | 180 | { |
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[580] | 181 | |
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| 182 | #if DEBUG_BDEV |
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[848] | 183 | std::cout << " <BDEV_TGT WRITE_OP> value = WRITE" << std::endl; |
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[580] | 184 | #endif |
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[151] | 185 | r_read = false; |
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[392] | 186 | r_go = true; |
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[151] | 187 | } |
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[392] | 188 | else |
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| 189 | { |
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[580] | 190 | |
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| 191 | #if DEBUG_BDEV |
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[848] | 192 | std::cout << " <BDEV_TGT WRITE_OP> value = SOFT RESET" << std::endl; |
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[580] | 193 | #endif |
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[392] | 194 | r_go = false; |
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| 195 | } |
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| 196 | r_target_fsm = T_IDLE; |
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[151] | 197 | } |
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| 198 | break; |
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| 199 | } |
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[260] | 200 | /////////////////// |
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[151] | 201 | case T_WRITE_IRQEN: |
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| 202 | { |
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[898] | 203 | if ( p_vci_target.rspack.read() ) |
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[392] | 204 | { |
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[580] | 205 | |
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| 206 | #if DEBUG_BDEV |
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| 207 | std::cout << " <BDEV_TGT WRITE_IRQEN> value = " << r_tdata.read() << std::endl; |
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[522] | 208 | #endif |
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[392] | 209 | r_target_fsm = T_IDLE; |
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[522] | 210 | r_irq_enable = (r_tdata.read() != 0); |
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[392] | 211 | } |
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[151] | 212 | break; |
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| 213 | } |
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[260] | 214 | /////////////////// |
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[151] | 215 | case T_READ_BUFFER: |
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[392] | 216 | case T_READ_BUFFER_EXT: |
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[151] | 217 | case T_READ_COUNT: |
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| 218 | case T_READ_LBA: |
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| 219 | case T_READ_IRQEN: |
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| 220 | case T_READ_SIZE: |
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| 221 | case T_READ_BLOCK: |
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| 222 | case T_READ_ERROR: |
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| 223 | case T_WRITE_ERROR: |
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| 224 | { |
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| 225 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 226 | break; |
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| 227 | } |
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[260] | 228 | /////////////////// |
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[151] | 229 | case T_READ_STATUS: |
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| 230 | { |
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[898] | 231 | if ( p_vci_target.rspack.read() ) |
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[151] | 232 | { |
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| 233 | r_target_fsm = T_IDLE; |
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| 234 | if( (r_initiator_fsm == M_READ_SUCCESS ) || |
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| 235 | (r_initiator_fsm == M_READ_ERROR ) || |
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| 236 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
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| 237 | (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; |
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| 238 | } |
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| 239 | break; |
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| 240 | } |
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| 241 | } // end switch target fsm |
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[898] | 242 | |
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[260] | 243 | ////////////////////////////////////////////////////////////////////////////// |
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| 244 | // The initiator FSM executes a loop, transfering one block per iteration. |
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| 245 | // Each block is split in bursts, and the number of bursts depends |
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| 246 | // on the memory buffer alignment on a burst boundary: |
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[400] | 247 | // - If buffer aligned, all burst have the same length (m_words_per burst) |
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[260] | 248 | // and the number of bursts is (m_bursts_per_block). |
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| 249 | // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) |
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[898] | 250 | // and first and last burst are shorter, because all words in a burst |
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[260] | 251 | // must be contained in a single cache line. |
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[400] | 252 | // first burst => nwords = m_words_per_burst - offset |
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| 253 | // last burst => nwords = offset |
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| 254 | // other burst => nwords = m_words_per_burst |
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[260] | 255 | ////////////////////////////////////////////////////////////////////////////// |
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| 256 | |
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| 257 | switch( r_initiator_fsm.read() ) { |
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| 258 | //////////// |
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[898] | 259 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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[151] | 260 | { |
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[898] | 261 | if ( r_go.read() ) |
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[151] | 262 | { |
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[260] | 263 | r_index = 0; |
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[151] | 264 | r_block_count = 0; |
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| 265 | r_burst_count = 0; |
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[433] | 266 | r_words_count = 0; |
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[151] | 267 | r_latency_count = m_latency; |
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| 268 | |
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[260] | 269 | // compute r_burst_offset (zero when buffer aligned) |
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[400] | 270 | r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_words_per_burst); |
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[260] | 271 | |
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| 272 | // start tranfer |
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[898] | 273 | if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; |
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[260] | 274 | else r_initiator_fsm = M_WRITE_BURST; |
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[151] | 275 | } |
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| 276 | break; |
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[898] | 277 | } |
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[260] | 278 | ////////////////// |
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[228] | 279 | case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles |
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[151] | 280 | { |
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[260] | 281 | if ( r_latency_count.read() == 0 ) |
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[151] | 282 | { |
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| 283 | r_latency_count = m_latency; |
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[400] | 284 | ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); |
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[898] | 285 | if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) |
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[151] | 286 | { |
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[260] | 287 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 288 | } |
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[898] | 289 | else |
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[151] | 290 | { |
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[260] | 291 | r_burst_count = 0; |
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[580] | 292 | r_words_count = 0; |
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[260] | 293 | r_initiator_fsm = M_READ_BURST; |
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[151] | 294 | } |
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[608] | 295 | |
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| 296 | //////////////////////////////////////////////////////////////////////////////////////// |
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[898] | 297 | //std::cout << "***** Block content after read for lba " |
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[608] | 298 | // << std::hex << r_lba.read() << " **************" << std::endl; |
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| 299 | //for ( size_t line=0 ; line<16 ; line++ ) |
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| 300 | //{ |
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| 301 | // for ( size_t word=0 ; word<8 ; word++ ) |
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| 302 | // { |
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| 303 | // std::cout << std::hex << r_local_buffer[line*8 + word] << " "; |
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| 304 | // } |
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| 305 | // std::cout << std::endl; |
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| 306 | //} |
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| 307 | //std::cout << "**********************************************************" << std::endl; |
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| 308 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 309 | |
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[151] | 310 | } |
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| 311 | else |
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| 312 | { |
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[260] | 313 | r_latency_count = r_latency_count.read() - 1; |
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[151] | 314 | } |
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| 315 | break; |
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| 316 | } |
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[260] | 317 | ////////////////// |
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[400] | 318 | case M_READ_BURST: // Compute the number of words and the number of flits in the burst |
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[898] | 319 | // The number of flits can be smaller than the number of words |
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[400] | 320 | // in case of 8 bytes flits... |
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[151] | 321 | { |
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[400] | 322 | uint32_t nwords; |
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[260] | 323 | uint32_t offset = r_burst_offset.read(); |
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| 324 | |
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| 325 | if ( offset ) // buffer not aligned |
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| 326 | { |
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[400] | 327 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
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| 328 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
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| 329 | else nwords = m_words_per_burst; |
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[260] | 330 | } |
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| 331 | else // buffer aligned |
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| 332 | { |
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[400] | 333 | nwords = m_words_per_burst; |
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[260] | 334 | } |
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[400] | 335 | |
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| 336 | r_burst_nwords = nwords; |
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| 337 | r_initiator_fsm = M_READ_CMD; |
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[260] | 338 | break; |
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| 339 | } |
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| 340 | //////////////// |
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[898] | 341 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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[260] | 342 | { |
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[151] | 343 | if ( p_vci_initiator.cmdack.read() ) |
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| 344 | { |
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[400] | 345 | uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); |
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| 346 | |
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[898] | 347 | if ( vci_param::B == 4 ) // one word per flit |
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[151] | 348 | { |
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[400] | 349 | if ( nwords <= 1 ) // last flit |
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| 350 | { |
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| 351 | r_initiator_fsm = M_READ_RSP; |
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| 352 | r_words_count = 0; |
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| 353 | } |
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| 354 | else // not the last flit |
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| 355 | { |
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| 356 | r_words_count = r_words_count.read() + 1; |
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| 357 | } |
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| 358 | |
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| 359 | // compute next word address and next local buffer index |
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| 360 | r_buf_address = r_buf_address.read() + 4; |
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| 361 | r_index = r_index.read() + 1; |
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[151] | 362 | } |
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[400] | 363 | else // 2 words per flit |
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[151] | 364 | { |
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[400] | 365 | if ( nwords <= 2 ) // last flit |
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| 366 | { |
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| 367 | r_initiator_fsm = M_READ_RSP; |
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| 368 | r_words_count = 0; |
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| 369 | } |
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| 370 | else // not the last flit |
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| 371 | { |
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| 372 | r_words_count = r_words_count.read() + 2; |
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| 373 | } |
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[898] | 374 | |
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[400] | 375 | // compute next word address and next local buffer index |
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| 376 | if ( nwords == 1 ) |
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| 377 | { |
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| 378 | r_buf_address = r_buf_address.read() + 4; |
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| 379 | r_index = r_index.read() + 1; |
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| 380 | } |
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| 381 | else |
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| 382 | { |
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| 383 | r_buf_address = r_buf_address.read() + 8; |
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| 384 | r_index = r_index.read() + 2; |
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| 385 | } |
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[151] | 386 | } |
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| 387 | } |
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| 388 | break; |
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| 389 | } |
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[260] | 390 | //////////////// |
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[898] | 391 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
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[151] | 392 | { |
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| 393 | if ( p_vci_initiator.rspval.read() ) |
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| 394 | { |
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[260] | 395 | bool aligned = (r_burst_offset.read() == 0); |
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| 396 | |
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[898] | 397 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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[151] | 398 | { |
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[260] | 399 | r_initiator_fsm = M_READ_ERROR; |
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[151] | 400 | } |
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[898] | 401 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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[260] | 402 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) |
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[151] | 403 | { |
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[898] | 404 | if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block |
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[260] | 405 | { |
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| 406 | r_initiator_fsm = M_READ_SUCCESS; |
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| 407 | } |
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| 408 | else // last burst not last block |
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| 409 | { |
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| 410 | r_index = 0; |
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| 411 | r_burst_count = 0; |
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| 412 | r_block_count = r_block_count.read() + 1; |
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| 413 | r_initiator_fsm = M_READ_BLOCK; |
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| 414 | } |
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[151] | 415 | } |
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[260] | 416 | else // not the last burst |
---|
| 417 | { |
---|
| 418 | r_burst_count = r_burst_count.read() + 1; |
---|
| 419 | r_initiator_fsm = M_READ_BURST; |
---|
| 420 | } |
---|
[151] | 421 | } |
---|
| 422 | break; |
---|
| 423 | } |
---|
[260] | 424 | /////////////////// |
---|
[151] | 425 | case M_READ_SUCCESS: |
---|
[260] | 426 | case M_READ_ERROR: |
---|
[151] | 427 | { |
---|
| 428 | if( !r_go ) r_initiator_fsm = M_IDLE; |
---|
| 429 | break; |
---|
| 430 | } |
---|
[260] | 431 | /////////////////// |
---|
[400] | 432 | case M_WRITE_BURST: // Compute the number of words in the burst |
---|
[151] | 433 | { |
---|
[400] | 434 | uint32_t nwords; |
---|
[260] | 435 | uint32_t offset = r_burst_offset.read(); |
---|
| 436 | |
---|
| 437 | if ( offset ) // buffer not aligned |
---|
| 438 | { |
---|
[400] | 439 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
---|
| 440 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
---|
| 441 | else nwords = m_words_per_burst; |
---|
[260] | 442 | } |
---|
| 443 | else // buffer aligned |
---|
| 444 | { |
---|
[400] | 445 | nwords = m_words_per_burst; |
---|
[260] | 446 | } |
---|
[400] | 447 | |
---|
| 448 | r_burst_nwords = nwords; |
---|
[260] | 449 | r_initiator_fsm = M_WRITE_CMD; |
---|
[151] | 450 | break; |
---|
| 451 | } |
---|
[260] | 452 | ///////////////// |
---|
[898] | 453 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
---|
[151] | 454 | { |
---|
[898] | 455 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
---|
[151] | 456 | break; |
---|
| 457 | } |
---|
[260] | 458 | ///////////////// |
---|
[898] | 459 | case M_WRITE_RSP: // This is actually a multi-words VCI READ response |
---|
[151] | 460 | { |
---|
| 461 | if ( p_vci_initiator.rspval.read() ) |
---|
| 462 | { |
---|
[400] | 463 | bool aligned = (r_burst_offset.read() == 0); |
---|
[260] | 464 | |
---|
[400] | 465 | if ( (vci_param::B == 8) and (r_burst_nwords.read() > 1) ) |
---|
| 466 | { |
---|
| 467 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
---|
| 468 | r_local_buffer[r_index.read()+1] = (uint32_t)(p_vci_initiator.rdata.read()>>32); |
---|
| 469 | r_index = r_index.read() + 2; |
---|
| 470 | } |
---|
| 471 | else |
---|
| 472 | { |
---|
| 473 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
---|
| 474 | r_index = r_index.read() + 1; |
---|
| 475 | } |
---|
| 476 | |
---|
[260] | 477 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
---|
[151] | 478 | { |
---|
[898] | 479 | r_words_count = 0; |
---|
| 480 | r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); |
---|
[260] | 481 | |
---|
[898] | 482 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
[260] | 483 | { |
---|
| 484 | r_initiator_fsm = M_WRITE_ERROR; |
---|
| 485 | } |
---|
[898] | 486 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
---|
[400] | 487 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst |
---|
[260] | 488 | { |
---|
| 489 | r_initiator_fsm = M_WRITE_BLOCK; |
---|
| 490 | } |
---|
| 491 | else // not the last burst |
---|
| 492 | { |
---|
| 493 | r_burst_count = r_burst_count.read() + 1; |
---|
| 494 | r_initiator_fsm = M_WRITE_BURST; |
---|
| 495 | } |
---|
[151] | 496 | } |
---|
| 497 | else |
---|
| 498 | { |
---|
[898] | 499 | r_words_count = r_words_count.read() + 1; |
---|
[151] | 500 | } |
---|
| 501 | } |
---|
| 502 | break; |
---|
| 503 | } |
---|
[260] | 504 | /////////////////// |
---|
[898] | 505 | case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles |
---|
[151] | 506 | { |
---|
| 507 | if ( r_latency_count == 0 ) |
---|
| 508 | { |
---|
[608] | 509 | |
---|
| 510 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
[898] | 511 | //std::cout << "***** Block content before write for lba " |
---|
[608] | 512 | // << std::hex << r_lba.read() << " ***********" << std::endl; |
---|
| 513 | //for ( size_t line=0 ; line<16 ; line++ ) |
---|
| 514 | //{ |
---|
| 515 | // for ( size_t word=0 ; word<8 ; word++ ) |
---|
| 516 | // { |
---|
| 517 | // std::cout << std::hex << r_local_buffer[line*8 + word] << " "; |
---|
| 518 | // } |
---|
| 519 | // std::cout << std::endl; |
---|
| 520 | //} |
---|
| 521 | //std::cout << "**********************************************************" << std::endl; |
---|
| 522 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
| 523 | |
---|
[151] | 524 | r_latency_count = m_latency; |
---|
[581] | 525 | ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); |
---|
| 526 | if( ::write(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) |
---|
[151] | 527 | { |
---|
[898] | 528 | r_initiator_fsm = M_WRITE_ERROR; |
---|
[151] | 529 | } |
---|
[898] | 530 | else if ( r_block_count.read() == r_nblocks.read() - 1 ) |
---|
[151] | 531 | { |
---|
[898] | 532 | r_initiator_fsm = M_WRITE_SUCCESS; |
---|
[151] | 533 | } |
---|
| 534 | else |
---|
| 535 | { |
---|
[272] | 536 | r_burst_count = 0; |
---|
[400] | 537 | r_index = 0; |
---|
[272] | 538 | r_block_count = r_block_count.read() + 1; |
---|
[400] | 539 | r_initiator_fsm = M_WRITE_BURST; |
---|
[151] | 540 | } |
---|
[898] | 541 | } |
---|
[151] | 542 | else |
---|
| 543 | { |
---|
| 544 | r_latency_count = r_latency_count - 1; |
---|
| 545 | } |
---|
| 546 | break; |
---|
| 547 | } |
---|
[260] | 548 | ///////////////////// |
---|
[151] | 549 | case M_WRITE_SUCCESS: |
---|
| 550 | case M_WRITE_ERROR: |
---|
| 551 | { |
---|
| 552 | if( !r_go ) r_initiator_fsm = M_IDLE; |
---|
| 553 | break; |
---|
| 554 | } |
---|
| 555 | } // end switch r_initiator_fsm |
---|
| 556 | } // end transition |
---|
| 557 | |
---|
| 558 | ////////////////////// |
---|
| 559 | tmpl(void)::genMoore() |
---|
| 560 | { |
---|
[898] | 561 | // p_vci_target port |
---|
[164] | 562 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
---|
| 563 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
---|
| 564 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
---|
[151] | 565 | p_vci_target.reop = true; |
---|
| 566 | |
---|
| 567 | switch(r_target_fsm) { |
---|
| 568 | case T_IDLE: |
---|
| 569 | p_vci_target.cmdack = true; |
---|
[260] | 570 | p_vci_target.rspval = false; |
---|
[514] | 571 | p_vci_target.rdata = 0; |
---|
[151] | 572 | break; |
---|
| 573 | case T_READ_STATUS: |
---|
| 574 | p_vci_target.cmdack = false; |
---|
[260] | 575 | p_vci_target.rspval = true; |
---|
| 576 | if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; |
---|
| 577 | else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; |
---|
| 578 | else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; |
---|
[898] | 579 | else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; |
---|
| 580 | else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; |
---|
| 581 | else p_vci_target.rdata = BLOCK_DEVICE_BUSY; |
---|
[151] | 582 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 583 | break; |
---|
| 584 | case T_READ_BUFFER: |
---|
| 585 | p_vci_target.cmdack = false; |
---|
[260] | 586 | p_vci_target.rspval = true; |
---|
| 587 | p_vci_target.rdata = (uint32_t)r_buf_address.read(); |
---|
[151] | 588 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 589 | break; |
---|
[392] | 590 | case T_READ_BUFFER_EXT: |
---|
| 591 | p_vci_target.cmdack = false; |
---|
| 592 | p_vci_target.rspval = true; |
---|
| 593 | p_vci_target.rdata = (uint32_t)(r_buf_address.read()>>32); |
---|
| 594 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 595 | break; |
---|
[151] | 596 | case T_READ_COUNT: |
---|
| 597 | p_vci_target.cmdack = false; |
---|
[260] | 598 | p_vci_target.rspval = true; |
---|
[400] | 599 | p_vci_target.rdata = r_nblocks.read(); |
---|
[151] | 600 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 601 | break; |
---|
| 602 | case T_READ_LBA: |
---|
| 603 | p_vci_target.cmdack = false; |
---|
[260] | 604 | p_vci_target.rspval = true; |
---|
[400] | 605 | p_vci_target.rdata = r_lba.read(); |
---|
[151] | 606 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 607 | break; |
---|
| 608 | case T_READ_IRQEN: |
---|
| 609 | p_vci_target.cmdack = false; |
---|
[260] | 610 | p_vci_target.rspval = true; |
---|
[400] | 611 | p_vci_target.rdata = r_irq_enable.read(); |
---|
[151] | 612 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 613 | break; |
---|
| 614 | case T_READ_SIZE: |
---|
| 615 | p_vci_target.cmdack = false; |
---|
[260] | 616 | p_vci_target.rspval = true; |
---|
[400] | 617 | p_vci_target.rdata = m_device_size; |
---|
[151] | 618 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 619 | break; |
---|
| 620 | case T_READ_BLOCK: |
---|
| 621 | p_vci_target.cmdack = false; |
---|
[260] | 622 | p_vci_target.rspval = true; |
---|
[451] | 623 | p_vci_target.rdata = m_words_per_block*4; |
---|
[151] | 624 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 625 | break; |
---|
| 626 | case T_READ_ERROR: |
---|
| 627 | p_vci_target.cmdack = false; |
---|
[260] | 628 | p_vci_target.rspval = true; |
---|
[400] | 629 | p_vci_target.rdata = 0; |
---|
[151] | 630 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
| 631 | break; |
---|
| 632 | case T_WRITE_ERROR: |
---|
| 633 | p_vci_target.cmdack = false; |
---|
[260] | 634 | p_vci_target.rspval = true; |
---|
[400] | 635 | p_vci_target.rdata = 0; |
---|
[151] | 636 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
| 637 | break; |
---|
| 638 | default: |
---|
| 639 | p_vci_target.cmdack = false; |
---|
| 640 | p_vci_target.rspval = true; |
---|
[400] | 641 | p_vci_target.rdata = 0; |
---|
[151] | 642 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
| 643 | break; |
---|
| 644 | } // end switch target fsm |
---|
| 645 | |
---|
| 646 | // p_vci_initiator port |
---|
[164] | 647 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
[151] | 648 | p_vci_initiator.trdid = 0; |
---|
| 649 | p_vci_initiator.contig = true; |
---|
| 650 | p_vci_initiator.cons = false; |
---|
| 651 | p_vci_initiator.wrap = false; |
---|
| 652 | p_vci_initiator.cfixed = false; |
---|
| 653 | p_vci_initiator.clen = 0; |
---|
| 654 | |
---|
| 655 | switch (r_initiator_fsm) { |
---|
[898] | 656 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
[151] | 657 | p_vci_initiator.rspack = false; |
---|
| 658 | p_vci_initiator.cmdval = true; |
---|
[260] | 659 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 660 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
[898] | 661 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; |
---|
[151] | 662 | p_vci_initiator.wdata = 0; |
---|
[401] | 663 | p_vci_initiator.be = 0; |
---|
[400] | 664 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
[151] | 665 | p_vci_initiator.eop = true; |
---|
| 666 | break; |
---|
[898] | 667 | case M_READ_CMD: // It is actually a multi-words VCI WRITE command |
---|
[151] | 668 | p_vci_initiator.rspack = false; |
---|
| 669 | p_vci_initiator.cmdval = true; |
---|
[898] | 670 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[151] | 671 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
[284] | 672 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
[400] | 673 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
[898] | 674 | if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) |
---|
[401] | 675 | { |
---|
[424] | 676 | p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + |
---|
[898] | 677 | (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); |
---|
[401] | 678 | p_vci_initiator.be = 0xFF; |
---|
[433] | 679 | p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); |
---|
[401] | 680 | } |
---|
| 681 | else |
---|
| 682 | { |
---|
| 683 | p_vci_initiator.wdata = r_local_buffer[r_index.read()]; |
---|
| 684 | p_vci_initiator.be = 0xF; |
---|
[433] | 685 | p_vci_initiator.eop = ( r_words_count.read() == (r_burst_nwords.read() - 1) ); |
---|
[401] | 686 | } |
---|
[151] | 687 | break; |
---|
| 688 | case M_READ_RSP: |
---|
| 689 | case M_WRITE_RSP: |
---|
| 690 | p_vci_initiator.rspack = true; |
---|
| 691 | p_vci_initiator.cmdval = false; |
---|
[260] | 692 | break; |
---|
[151] | 693 | default: |
---|
[260] | 694 | p_vci_initiator.rspack = false; |
---|
| 695 | p_vci_initiator.cmdval = false; |
---|
| 696 | break; |
---|
[151] | 697 | } |
---|
| 698 | |
---|
| 699 | // IRQ signal |
---|
[433] | 700 | if ( ((r_initiator_fsm == M_READ_SUCCESS) || |
---|
[898] | 701 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
---|
[433] | 702 | (r_initiator_fsm == M_READ_ERROR) || |
---|
[898] | 703 | (r_initiator_fsm == M_WRITE_ERROR) ) && |
---|
| 704 | r_irq_enable.read() ) |
---|
[580] | 705 | { |
---|
| 706 | |
---|
| 707 | #if DEBUG_BDEV |
---|
[895] | 708 | if (p_irq != true) |
---|
| 709 | std::cout << " <BDEV_INI send IRQ>" << std::endl; |
---|
[522] | 710 | #endif |
---|
[898] | 711 | p_irq = true; |
---|
| 712 | } |
---|
| 713 | else |
---|
[580] | 714 | { |
---|
| 715 | p_irq = false; |
---|
| 716 | } |
---|
[151] | 717 | } // end GenMoore() |
---|
| 718 | |
---|
| 719 | ////////////////////////////////////////////////////////////////////////////// |
---|
[898] | 720 | tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name name, |
---|
[400] | 721 | const soclib::common::MappingTable &mt, |
---|
| 722 | const soclib::common::IntTab &srcid, |
---|
| 723 | const soclib::common::IntTab &tgtid, |
---|
| 724 | const std::string &filename, |
---|
| 725 | const uint32_t block_size, |
---|
| 726 | const uint32_t burst_size, |
---|
| 727 | const uint32_t latency) |
---|
[151] | 728 | |
---|
| 729 | : caba::BaseModule(name), |
---|
[898] | 730 | m_seglist(mt.getSegmentList(tgtid)), |
---|
| 731 | m_srcid(mt.indexForId(srcid)), |
---|
| 732 | m_words_per_block(block_size/4), |
---|
| 733 | m_words_per_burst(burst_size/4), |
---|
| 734 | m_bursts_per_block(block_size/burst_size), |
---|
| 735 | m_latency(latency), |
---|
| 736 | p_clk("p_clk"), |
---|
| 737 | p_resetn("p_resetn"), |
---|
| 738 | p_vci_initiator("p_vci_initiator"), |
---|
| 739 | p_vci_target("p_vci_target"), |
---|
| 740 | p_irq("p_irq") |
---|
[151] | 741 | { |
---|
[433] | 742 | std::cout << " - Building VciBlockDeviceTsar " << name << std::endl; |
---|
| 743 | |
---|
[898] | 744 | SC_METHOD(transition); |
---|
[381] | 745 | dont_initialize(); |
---|
| 746 | sensitive << p_clk.pos(); |
---|
[151] | 747 | |
---|
[898] | 748 | SC_METHOD(genMoore); |
---|
[381] | 749 | dont_initialize(); |
---|
| 750 | sensitive << p_clk.neg(); |
---|
[151] | 751 | |
---|
[409] | 752 | size_t nbsegs = 0; |
---|
[408] | 753 | std::list<soclib::common::Segment>::iterator seg; |
---|
[898] | 754 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
---|
[408] | 755 | { |
---|
[409] | 756 | nbsegs++; |
---|
[898] | 757 | |
---|
| 758 | if ( (seg->baseAddress() & 0x0000003F) != 0 ) |
---|
| 759 | { |
---|
| 760 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 761 | << "The base address of segment " << seg->name() |
---|
[408] | 762 | << " must be multiple of 64 bytes" << std::endl; |
---|
[898] | 763 | exit(1); |
---|
| 764 | } |
---|
| 765 | if ( seg->size() < 64 ) |
---|
| 766 | { |
---|
| 767 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 768 | << "The size of segment " << seg->name() |
---|
[408] | 769 | << " cannot be smaller than 64 bytes" << std::endl; |
---|
[898] | 770 | exit(1); |
---|
| 771 | } |
---|
[433] | 772 | std::cout << " => segment " << seg->name() |
---|
| 773 | << " / base = " << std::hex << seg->baseAddress() |
---|
[898] | 774 | << " / size = " << seg->size() << std::endl; |
---|
[408] | 775 | } |
---|
| 776 | |
---|
[409] | 777 | if( nbsegs == 0 ) |
---|
[408] | 778 | { |
---|
[898] | 779 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 780 | << " No segment allocated" << std::endl; |
---|
| 781 | exit(1); |
---|
[408] | 782 | } |
---|
| 783 | |
---|
[898] | 784 | if( (block_size != 128) && |
---|
| 785 | (block_size != 256) && |
---|
| 786 | (block_size != 512) && |
---|
[256] | 787 | (block_size != 1024) && |
---|
[898] | 788 | (block_size != 2048) && |
---|
[256] | 789 | (block_size != 4096) ) |
---|
[898] | 790 | { |
---|
| 791 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 792 | << " The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" |
---|
[408] | 793 | << std::endl; |
---|
[898] | 794 | exit(1); |
---|
| 795 | } |
---|
[408] | 796 | |
---|
[898] | 797 | if( (burst_size != 8 ) && |
---|
| 798 | (burst_size != 16) && |
---|
| 799 | (burst_size != 32) && |
---|
| 800 | (burst_size != 64) ) |
---|
| 801 | { |
---|
| 802 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 803 | << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; |
---|
| 804 | exit(1); |
---|
| 805 | } |
---|
[408] | 806 | |
---|
[898] | 807 | if ( (vci_param::B != 4) and (vci_param::B != 8) ) |
---|
| 808 | { |
---|
| 809 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 810 | << " The VCI data fields must have 32 bits or 64 bits" << std::endl; |
---|
| 811 | exit(1); |
---|
| 812 | } |
---|
[408] | 813 | |
---|
[898] | 814 | m_fd = ::open(filename.c_str(), O_RDWR); |
---|
| 815 | if ( m_fd < 0 ) |
---|
| 816 | { |
---|
| 817 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
| 818 | << " Unable to open file " << filename << std::endl; |
---|
| 819 | exit(1); |
---|
| 820 | } |
---|
| 821 | m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; |
---|
[408] | 822 | |
---|
[898] | 823 | if ( m_device_size > ((uint64_t)1<<vci_param::N ) ) |
---|
| 824 | { |
---|
| 825 | std::cout << "Error in component VciBlockDeviceTsar" << name |
---|
| 826 | << " The file " << filename |
---|
| 827 | << " has more blocks than addressable with the VCI address" << std::endl; |
---|
| 828 | exit(1); |
---|
| 829 | } |
---|
[151] | 830 | |
---|
[898] | 831 | r_local_buffer = new uint32_t[m_words_per_block]; |
---|
[260] | 832 | |
---|
[151] | 833 | } // end constructor |
---|
| 834 | |
---|
[580] | 835 | ///////////////////////////////// |
---|
[514] | 836 | tmpl(/**/)::~VciBlockDeviceTsar() |
---|
| 837 | { |
---|
[895] | 838 | ::close(m_fd); |
---|
[514] | 839 | delete [] r_local_buffer; |
---|
| 840 | } |
---|
| 841 | |
---|
| 842 | |
---|
[151] | 843 | ////////////////////////// |
---|
| 844 | tmpl(void)::print_trace() |
---|
| 845 | { |
---|
[898] | 846 | const char* initiator_str[] = |
---|
[500] | 847 | { |
---|
[898] | 848 | "INI_IDLE", |
---|
[260] | 849 | |
---|
[898] | 850 | "INI_READ_BLOCK", |
---|
| 851 | "INI_READ_BURST", |
---|
| 852 | "INI_READ_CMD", |
---|
| 853 | "INI_READ_RSP", |
---|
| 854 | "INI_READ_SUCCESS", |
---|
| 855 | "INI_READ_ERROR", |
---|
[260] | 856 | |
---|
[898] | 857 | "INI_WRITE_BURST", |
---|
| 858 | "INI_WRITE_CMD", |
---|
| 859 | "INI_WRITE_RSP", |
---|
| 860 | "INI_WRITE_BLOCK", |
---|
| 861 | "INI_WRITE_SUCCESS", |
---|
| 862 | "INI_WRITE_ERROR", |
---|
| 863 | }; |
---|
| 864 | const char* target_str[] = |
---|
[500] | 865 | { |
---|
[898] | 866 | "TGT_IDLE", |
---|
| 867 | "TGT_WRITE_BUFFER", |
---|
| 868 | "TGT_READ_BUFFER", |
---|
| 869 | "TGT_WRITE_BUFFER_EXT", |
---|
| 870 | "TGT_READ_BUFFER_EXT", |
---|
| 871 | "TGT_WRITE_COUNT", |
---|
| 872 | "TGT_READ_COUNT", |
---|
| 873 | "TGT_WRITE_LBA", |
---|
| 874 | "TGT_READ_LBA", |
---|
| 875 | "TGT_WRITE_OP", |
---|
| 876 | "TGT_READ_STATUS", |
---|
| 877 | "TGT_WRITE_IRQEN", |
---|
| 878 | "TGT_READ_IRQEN", |
---|
| 879 | "TGT_READ_SIZE", |
---|
| 880 | "TGT_READ_BLOCK", |
---|
| 881 | "TGT_READ_ERROR", |
---|
| 882 | "TGT_WRITE_ERROR ", |
---|
| 883 | }; |
---|
[151] | 884 | |
---|
[898] | 885 | std::cout << "BDEV " << name() |
---|
| 886 | << " : " << target_str[r_target_fsm.read()] |
---|
| 887 | << " / " << initiator_str[r_initiator_fsm.read()] |
---|
[580] | 888 | << " / buf = " << std::hex << r_buf_address.read() |
---|
| 889 | << " / lba = " << std::hex << r_lba.read() |
---|
[898] | 890 | << " / block_count = " << std::dec << r_block_count.read() |
---|
| 891 | << " / burst_count = " << r_burst_count.read() |
---|
| 892 | << " / word_count = " << r_words_count.read() <<std::endl; |
---|
[151] | 893 | } |
---|
| 894 | |
---|
| 895 | }} // end namespace |
---|
| 896 | |
---|
| 897 | // Local Variables: |
---|
| 898 | // tab-width: 4 |
---|
| 899 | // c-basic-offset: 4 |
---|
| 900 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 901 | // indent-tabs-mode: nil |
---|
| 902 | // End: |
---|
| 903 | |
---|
| 904 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 905 | |
---|