1 | /* -*- c++ -*- |
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2 | * |
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3 | * SOCLIB_LGPL_HEADER_BEGIN |
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4 | * |
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5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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6 | * |
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7 | * SoCLib is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU Lesser General Public License as published |
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9 | * by the Free Software Foundation; version 2.1 of the License. |
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10 | * |
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11 | * SoCLib is distributed in the hope that it will be useful, but |
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12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with SoCLib; if not, write to the Free Software |
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18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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19 | * 02110-1301 USA |
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20 | * |
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21 | * SOCLIB_LGPL_HEADER_END |
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22 | * |
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23 | * Copyright (c) UPMC, Lip6, Asim |
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24 | * alain.greiner@lip6.fr april 2011 |
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25 | * |
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26 | * Maintainers: alain |
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27 | */ |
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28 | |
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29 | #include <stdint.h> |
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30 | #include <iostream> |
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31 | #include <fcntl.h> |
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32 | #include "vci_block_device_tsar.h" |
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33 | #include "block_device_tsar.h" |
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34 | |
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35 | #define DEBUG_BDEV 0 |
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36 | |
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37 | namespace soclib { namespace caba { |
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38 | |
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39 | #define tmpl(t) template<typename vci_param> t VciBlockDeviceTsar<vci_param> |
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40 | |
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41 | using namespace soclib::caba; |
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42 | using namespace soclib::common; |
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43 | |
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44 | //////////////////////// |
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45 | tmpl(void)::transition() |
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46 | { |
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47 | if(p_resetn.read() == false) |
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48 | { |
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49 | r_initiator_fsm = M_IDLE; |
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50 | r_target_fsm = T_IDLE; |
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51 | r_irq_enable = true; |
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52 | r_go = false; |
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53 | return; |
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54 | } |
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55 | |
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56 | ////////////////////////////////////////////////////////////////////////////// |
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57 | // The Target FSM controls the following registers: |
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58 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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59 | ////////////////////////////////////////////////////////////////////////////// |
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60 | |
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61 | switch(r_target_fsm) { |
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62 | //////////// |
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63 | case T_IDLE: |
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64 | { |
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65 | if ( p_vci_target.cmdval.read() ) |
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66 | { |
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67 | r_srcid = p_vci_target.srcid.read(); |
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68 | r_trdid = p_vci_target.trdid.read(); |
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69 | r_pktid = p_vci_target.pktid.read(); |
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70 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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71 | |
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72 | bool found = false; |
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73 | std::list<soclib::common::Segment>::iterator seg; |
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74 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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75 | { |
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76 | if ( seg->contains(address) ) found = true; |
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77 | } |
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78 | |
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79 | bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); |
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80 | uint32_t cell = (uint32_t)((address & 0x3F)>>2); |
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81 | |
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82 | if ( !read && not found ) r_target_fsm = T_WRITE_ERROR; |
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83 | else if( read && not found ) r_target_fsm = T_READ_ERROR; |
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84 | else if( !read && not p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; |
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85 | else if( read && not p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; |
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86 | else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; |
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87 | else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; |
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88 | else if( !read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_WRITE_BUFFER_EXT; |
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89 | else if( read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_READ_BUFFER_EXT; |
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90 | else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; |
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91 | else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; |
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92 | else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; |
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93 | else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; |
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94 | else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; |
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95 | else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; |
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96 | else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; |
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97 | else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; |
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98 | else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; |
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99 | else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; |
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100 | |
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101 | // get write data value for both 32 bits and 64 bits data width |
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102 | if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) |
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103 | r_tdata = (uint32_t)(p_vci_target.wdata.read()>>32); |
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104 | else |
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105 | r_tdata = p_vci_target.wdata.read(); |
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106 | } |
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107 | break; |
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108 | } |
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109 | //////////////////// |
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110 | case T_WRITE_BUFFER: |
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111 | { |
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112 | if (p_vci_target.rspack.read() ) |
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113 | { |
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114 | if (r_initiator_fsm.read() == M_IDLE) |
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115 | { |
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116 | |
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117 | #if DEBUG_BDEV |
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118 | std::cout << " <BDEV_TGT WRITE_BUFFER> value = " << r_tdata.read() << std::endl; |
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119 | #endif |
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120 | r_buf_address = (uint64_t)r_tdata.read(); |
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121 | r_target_fsm = T_IDLE; |
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122 | } |
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123 | } |
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124 | break; |
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125 | } |
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126 | //////////////////////// |
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127 | case T_WRITE_BUFFER_EXT: |
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128 | { |
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129 | if (p_vci_target.rspack.read() ) |
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130 | { |
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131 | if (r_initiator_fsm.read() == M_IDLE) |
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132 | { |
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133 | |
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134 | #if DEBUG_BDEV |
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135 | std::cout << " <BDEV_TGT WRITE_BUFFER_EXT> value = " << r_tdata.read() << std::endl; |
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136 | #endif |
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137 | r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32); |
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138 | r_target_fsm = T_IDLE; |
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139 | } |
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140 | } |
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141 | break; |
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142 | } |
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143 | /////////////////// |
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144 | case T_WRITE_COUNT: |
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145 | { |
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146 | if (p_vci_target.rspack.read() ) |
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147 | { |
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148 | if (r_initiator_fsm.read() == M_IDLE) |
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149 | { |
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150 | |
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151 | #if DEBUG_BDEV |
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152 | std::cout << " <BDEV_TGT WRITE_COUNT> value = " << r_tdata.read() << std::endl; |
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153 | #endif |
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154 | r_nblocks = (uint32_t)r_tdata.read(); |
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155 | r_target_fsm = T_IDLE; |
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156 | } |
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157 | } |
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158 | break; |
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159 | } |
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160 | ///////////////// |
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161 | case T_WRITE_LBA: |
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162 | { |
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163 | if (p_vci_target.rspack.read() ) |
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164 | { |
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165 | if (r_initiator_fsm.read() == M_IDLE) |
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166 | { |
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167 | |
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168 | #if DEBUG_BDEV |
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169 | std::cout << " <BDEV_TGT WRITE_LBA> value = " << r_tdata.read() << std::endl; |
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170 | #endif |
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171 | r_lba = (uint32_t)r_tdata.read(); |
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172 | r_target_fsm = T_IDLE; |
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173 | } |
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174 | } |
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175 | break; |
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176 | } |
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177 | //////////////// |
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178 | case T_WRITE_OP: |
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179 | { |
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180 | if ( p_vci_target.rspack.read() ) |
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181 | { |
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182 | if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_READ) and |
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183 | (r_initiator_fsm.read() == M_IDLE) ) |
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184 | { |
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185 | |
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186 | #if DEBUG_BDEV |
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187 | std::cout << " <BDEV_TGT WRITE_OP> value = READ" << std::endl; |
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188 | #endif |
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189 | r_read = true; |
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190 | r_go = true; |
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191 | } |
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192 | else if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_WRITE) and |
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193 | (r_initiator_fsm.read() == M_IDLE) ) |
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194 | { |
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195 | |
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196 | #if DEBUG_BDEV |
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197 | std::cout << " <BDEV_TGT WRITE_OP> value = WRITE" << std::endl; |
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198 | #endif |
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199 | r_read = false; |
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200 | r_go = true; |
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201 | } |
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202 | else |
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203 | { |
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204 | |
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205 | #if DEBUG_BDEV |
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206 | std::cout << " <BDEV_TGT WRITE_OP> value = SOFT RESET" << std::endl; |
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207 | #endif |
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208 | r_go = false; |
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209 | } |
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210 | r_target_fsm = T_IDLE; |
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211 | } |
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212 | break; |
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213 | } |
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214 | /////////////////// |
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215 | case T_WRITE_IRQEN: |
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216 | { |
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217 | if ( p_vci_target.rspack.read() ) |
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218 | { |
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219 | |
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220 | #if DEBUG_BDEV |
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221 | std::cout << " <BDEV_TGT WRITE_IRQEN> value = " << r_tdata.read() << std::endl; |
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222 | #endif |
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223 | r_target_fsm = T_IDLE; |
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224 | r_irq_enable = (r_tdata.read() != 0); |
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225 | } |
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226 | break; |
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227 | } |
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228 | /////////////////// |
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229 | case T_READ_BUFFER: |
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230 | case T_READ_BUFFER_EXT: |
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231 | case T_READ_COUNT: |
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232 | case T_READ_LBA: |
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233 | case T_READ_IRQEN: |
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234 | case T_READ_SIZE: |
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235 | case T_READ_BLOCK: |
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236 | case T_READ_ERROR: |
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237 | case T_WRITE_ERROR: |
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238 | { |
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239 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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240 | break; |
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241 | } |
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242 | /////////////////// |
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243 | case T_READ_STATUS: |
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244 | { |
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245 | if ( p_vci_target.rspack.read() ) |
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246 | { |
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247 | r_target_fsm = T_IDLE; |
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248 | if( (r_initiator_fsm == M_READ_SUCCESS ) || |
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249 | (r_initiator_fsm == M_READ_ERROR ) || |
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250 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
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251 | (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; |
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252 | } |
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253 | break; |
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254 | } |
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255 | } // end switch target fsm |
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256 | |
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257 | ////////////////////////////////////////////////////////////////////////////// |
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258 | // The initiator FSM executes a loop, transfering one block per iteration. |
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259 | // Each block is split in bursts, and the number of bursts depends |
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260 | // on the memory buffer alignment on a burst boundary: |
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261 | // - If buffer aligned, all burst have the same length (m_words_per burst) |
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262 | // and the number of bursts is (m_bursts_per_block). |
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263 | // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) |
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264 | // and first and last burst are shorter, because all words in a burst |
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265 | // must be contained in a single cache line. |
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266 | // first burst => nwords = m_words_per_burst - offset |
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267 | // last burst => nwords = offset |
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268 | // other burst => nwords = m_words_per_burst |
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269 | ////////////////////////////////////////////////////////////////////////////// |
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270 | |
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271 | switch( r_initiator_fsm.read() ) { |
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272 | //////////// |
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273 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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274 | { |
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275 | if ( r_go.read() ) |
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276 | { |
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277 | r_index = 0; |
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278 | r_block_count = 0; |
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279 | r_burst_count = 0; |
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280 | r_words_count = 0; |
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281 | r_latency_count = m_latency; |
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282 | |
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283 | // compute r_burst_offset (zero when buffer aligned) |
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284 | r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_words_per_burst); |
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285 | |
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286 | // start tranfer |
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287 | if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; |
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288 | else r_initiator_fsm = M_WRITE_BURST; |
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289 | } |
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290 | break; |
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291 | } |
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292 | ////////////////// |
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293 | case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles |
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294 | { |
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295 | if ( r_latency_count.read() == 0 ) |
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296 | { |
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297 | r_latency_count = m_latency; |
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298 | ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); |
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299 | if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) |
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300 | { |
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301 | r_initiator_fsm = M_READ_ERROR; |
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302 | } |
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303 | else |
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304 | { |
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305 | r_burst_count = 0; |
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306 | r_words_count = 0; |
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307 | r_initiator_fsm = M_READ_BURST; |
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308 | } |
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309 | |
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310 | //////////////////////////////////////////////////////////////////////////////////////// |
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311 | //std::cout << "***** Block content after read for lba " |
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312 | // << std::hex << r_lba.read() << " **************" << std::endl; |
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313 | //for ( size_t line=0 ; line<16 ; line++ ) |
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314 | //{ |
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315 | // for ( size_t word=0 ; word<8 ; word++ ) |
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316 | // { |
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317 | // std::cout << std::hex << r_local_buffer[line*8 + word] << " "; |
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318 | // } |
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319 | // std::cout << std::endl; |
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320 | //} |
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321 | //std::cout << "**********************************************************" << std::endl; |
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322 | //////////////////////////////////////////////////////////////////////////////////////// |
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323 | |
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324 | } |
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325 | else |
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326 | { |
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327 | r_latency_count = r_latency_count.read() - 1; |
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328 | } |
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329 | break; |
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330 | } |
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331 | ////////////////// |
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332 | case M_READ_BURST: // Compute the number of words and the number of flits in the burst |
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333 | // The number of flits can be smaller than the number of words |
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334 | // in case of 8 bytes flits... |
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335 | { |
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336 | uint32_t nwords; |
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337 | uint32_t offset = r_burst_offset.read(); |
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338 | |
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339 | if ( offset ) // buffer not aligned |
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340 | { |
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341 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
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342 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
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343 | else nwords = m_words_per_burst; |
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344 | } |
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345 | else // buffer aligned |
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346 | { |
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347 | nwords = m_words_per_burst; |
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348 | } |
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349 | |
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350 | r_burst_nwords = nwords; |
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351 | r_initiator_fsm = M_READ_CMD; |
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352 | break; |
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353 | } |
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354 | //////////////// |
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355 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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356 | { |
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357 | if ( p_vci_initiator.cmdack.read() ) |
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358 | { |
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359 | uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); |
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360 | |
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361 | if ( vci_param::B == 4 ) // one word per flit |
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362 | { |
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363 | if ( nwords <= 1 ) // last flit |
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364 | { |
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365 | r_initiator_fsm = M_READ_RSP; |
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366 | r_words_count = 0; |
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367 | } |
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368 | else // not the last flit |
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369 | { |
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370 | r_words_count = r_words_count.read() + 1; |
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371 | } |
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372 | |
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373 | // compute next word address and next local buffer index |
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374 | r_buf_address = r_buf_address.read() + 4; |
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375 | r_index = r_index.read() + 1; |
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376 | } |
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377 | else // 2 words per flit |
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378 | { |
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379 | if ( nwords <= 2 ) // last flit |
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380 | { |
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381 | r_initiator_fsm = M_READ_RSP; |
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382 | r_words_count = 0; |
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383 | } |
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384 | else // not the last flit |
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385 | { |
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386 | r_words_count = r_words_count.read() + 2; |
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387 | } |
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388 | |
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389 | // compute next word address and next local buffer index |
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390 | if ( nwords == 1 ) |
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391 | { |
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392 | r_buf_address = r_buf_address.read() + 4; |
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393 | r_index = r_index.read() + 1; |
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394 | } |
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395 | else |
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396 | { |
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397 | r_buf_address = r_buf_address.read() + 8; |
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398 | r_index = r_index.read() + 2; |
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399 | } |
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400 | } |
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401 | } |
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402 | break; |
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403 | } |
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404 | //////////////// |
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405 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
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406 | { |
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407 | if ( p_vci_initiator.rspval.read() ) |
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408 | { |
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409 | bool aligned = (r_burst_offset.read() == 0); |
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410 | |
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411 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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412 | { |
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413 | r_initiator_fsm = M_READ_ERROR; |
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414 | } |
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415 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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416 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) |
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417 | { |
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418 | if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block |
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419 | { |
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420 | r_initiator_fsm = M_READ_SUCCESS; |
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421 | } |
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422 | else // last burst not last block |
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423 | { |
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424 | r_index = 0; |
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425 | r_burst_count = 0; |
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426 | r_block_count = r_block_count.read() + 1; |
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427 | r_initiator_fsm = M_READ_BLOCK; |
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428 | } |
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429 | } |
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430 | else // not the last burst |
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431 | { |
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432 | r_burst_count = r_burst_count.read() + 1; |
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433 | r_initiator_fsm = M_READ_BURST; |
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434 | } |
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435 | } |
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436 | break; |
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437 | } |
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438 | /////////////////// |
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439 | case M_READ_SUCCESS: |
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440 | case M_READ_ERROR: |
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441 | { |
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442 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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443 | break; |
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444 | } |
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445 | /////////////////// |
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446 | case M_WRITE_BURST: // Compute the number of words in the burst |
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447 | { |
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448 | uint32_t nwords; |
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449 | uint32_t offset = r_burst_offset.read(); |
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450 | |
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451 | if ( offset ) // buffer not aligned |
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452 | { |
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453 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
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454 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
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455 | else nwords = m_words_per_burst; |
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456 | } |
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457 | else // buffer aligned |
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458 | { |
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459 | nwords = m_words_per_burst; |
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460 | } |
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461 | |
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462 | r_burst_nwords = nwords; |
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463 | r_initiator_fsm = M_WRITE_CMD; |
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464 | break; |
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465 | } |
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466 | ///////////////// |
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467 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
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468 | { |
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469 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
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470 | break; |
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471 | } |
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472 | ///////////////// |
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473 | case M_WRITE_RSP: // This is actually a multi-words VCI READ response |
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474 | { |
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475 | if ( p_vci_initiator.rspval.read() ) |
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476 | { |
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477 | bool aligned = (r_burst_offset.read() == 0); |
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478 | |
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479 | if ( (vci_param::B == 8) and (r_burst_nwords.read() > 1) ) |
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480 | { |
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481 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
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482 | r_local_buffer[r_index.read()+1] = (uint32_t)(p_vci_initiator.rdata.read()>>32); |
---|
483 | r_index = r_index.read() + 2; |
---|
484 | } |
---|
485 | else |
---|
486 | { |
---|
487 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
---|
488 | r_index = r_index.read() + 1; |
---|
489 | } |
---|
490 | |
---|
491 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
---|
492 | { |
---|
493 | r_words_count = 0; |
---|
494 | r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); |
---|
495 | |
---|
496 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
497 | { |
---|
498 | r_initiator_fsm = M_WRITE_ERROR; |
---|
499 | } |
---|
500 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
---|
501 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst |
---|
502 | { |
---|
503 | r_initiator_fsm = M_WRITE_BLOCK; |
---|
504 | } |
---|
505 | else // not the last burst |
---|
506 | { |
---|
507 | r_burst_count = r_burst_count.read() + 1; |
---|
508 | r_initiator_fsm = M_WRITE_BURST; |
---|
509 | } |
---|
510 | } |
---|
511 | else |
---|
512 | { |
---|
513 | r_words_count = r_words_count.read() + 1; |
---|
514 | } |
---|
515 | } |
---|
516 | break; |
---|
517 | } |
---|
518 | /////////////////// |
---|
519 | case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles |
---|
520 | { |
---|
521 | if ( r_latency_count == 0 ) |
---|
522 | { |
---|
523 | |
---|
524 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
525 | //std::cout << "***** Block content before write for lba " |
---|
526 | // << std::hex << r_lba.read() << " ***********" << std::endl; |
---|
527 | //for ( size_t line=0 ; line<16 ; line++ ) |
---|
528 | //{ |
---|
529 | // for ( size_t word=0 ; word<8 ; word++ ) |
---|
530 | // { |
---|
531 | // std::cout << std::hex << r_local_buffer[line*8 + word] << " "; |
---|
532 | // } |
---|
533 | // std::cout << std::endl; |
---|
534 | //} |
---|
535 | //std::cout << "**********************************************************" << std::endl; |
---|
536 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
537 | |
---|
538 | r_latency_count = m_latency; |
---|
539 | ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); |
---|
540 | if( ::write(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) |
---|
541 | { |
---|
542 | r_initiator_fsm = M_WRITE_ERROR; |
---|
543 | } |
---|
544 | else if ( r_block_count.read() == r_nblocks.read() - 1 ) |
---|
545 | { |
---|
546 | r_initiator_fsm = M_WRITE_SUCCESS; |
---|
547 | } |
---|
548 | else |
---|
549 | { |
---|
550 | r_burst_count = 0; |
---|
551 | r_index = 0; |
---|
552 | r_block_count = r_block_count.read() + 1; |
---|
553 | r_initiator_fsm = M_WRITE_BURST; |
---|
554 | } |
---|
555 | } |
---|
556 | else |
---|
557 | { |
---|
558 | r_latency_count = r_latency_count - 1; |
---|
559 | } |
---|
560 | break; |
---|
561 | } |
---|
562 | ///////////////////// |
---|
563 | case M_WRITE_SUCCESS: |
---|
564 | case M_WRITE_ERROR: |
---|
565 | { |
---|
566 | if( !r_go ) r_initiator_fsm = M_IDLE; |
---|
567 | break; |
---|
568 | } |
---|
569 | } // end switch r_initiator_fsm |
---|
570 | } // end transition |
---|
571 | |
---|
572 | ////////////////////// |
---|
573 | tmpl(void)::genMoore() |
---|
574 | { |
---|
575 | // p_vci_target port |
---|
576 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
---|
577 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
---|
578 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
---|
579 | p_vci_target.reop = true; |
---|
580 | |
---|
581 | switch(r_target_fsm) { |
---|
582 | case T_IDLE: |
---|
583 | p_vci_target.cmdack = true; |
---|
584 | p_vci_target.rspval = false; |
---|
585 | p_vci_target.rdata = 0; |
---|
586 | break; |
---|
587 | case T_READ_STATUS: |
---|
588 | p_vci_target.cmdack = false; |
---|
589 | p_vci_target.rspval = true; |
---|
590 | if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; |
---|
591 | else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; |
---|
592 | else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; |
---|
593 | else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; |
---|
594 | else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; |
---|
595 | else p_vci_target.rdata = BLOCK_DEVICE_BUSY; |
---|
596 | p_vci_target.rerror = VCI_READ_OK; |
---|
597 | break; |
---|
598 | case T_READ_BUFFER: |
---|
599 | p_vci_target.cmdack = false; |
---|
600 | p_vci_target.rspval = true; |
---|
601 | p_vci_target.rdata = (uint32_t)r_buf_address.read(); |
---|
602 | p_vci_target.rerror = VCI_READ_OK; |
---|
603 | break; |
---|
604 | case T_READ_BUFFER_EXT: |
---|
605 | p_vci_target.cmdack = false; |
---|
606 | p_vci_target.rspval = true; |
---|
607 | p_vci_target.rdata = (uint32_t)(r_buf_address.read()>>32); |
---|
608 | p_vci_target.rerror = VCI_READ_OK; |
---|
609 | break; |
---|
610 | case T_READ_COUNT: |
---|
611 | p_vci_target.cmdack = false; |
---|
612 | p_vci_target.rspval = true; |
---|
613 | p_vci_target.rdata = r_nblocks.read(); |
---|
614 | p_vci_target.rerror = VCI_READ_OK; |
---|
615 | break; |
---|
616 | case T_READ_LBA: |
---|
617 | p_vci_target.cmdack = false; |
---|
618 | p_vci_target.rspval = true; |
---|
619 | p_vci_target.rdata = r_lba.read(); |
---|
620 | p_vci_target.rerror = VCI_READ_OK; |
---|
621 | break; |
---|
622 | case T_READ_IRQEN: |
---|
623 | p_vci_target.cmdack = false; |
---|
624 | p_vci_target.rspval = true; |
---|
625 | p_vci_target.rdata = r_irq_enable.read(); |
---|
626 | p_vci_target.rerror = VCI_READ_OK; |
---|
627 | break; |
---|
628 | case T_READ_SIZE: |
---|
629 | p_vci_target.cmdack = false; |
---|
630 | p_vci_target.rspval = true; |
---|
631 | p_vci_target.rdata = m_device_size; |
---|
632 | p_vci_target.rerror = VCI_READ_OK; |
---|
633 | break; |
---|
634 | case T_READ_BLOCK: |
---|
635 | p_vci_target.cmdack = false; |
---|
636 | p_vci_target.rspval = true; |
---|
637 | p_vci_target.rdata = m_words_per_block*4; |
---|
638 | p_vci_target.rerror = VCI_READ_OK; |
---|
639 | break; |
---|
640 | case T_READ_ERROR: |
---|
641 | p_vci_target.cmdack = false; |
---|
642 | p_vci_target.rspval = true; |
---|
643 | p_vci_target.rdata = 0; |
---|
644 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
645 | break; |
---|
646 | case T_WRITE_ERROR: |
---|
647 | p_vci_target.cmdack = false; |
---|
648 | p_vci_target.rspval = true; |
---|
649 | p_vci_target.rdata = 0; |
---|
650 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
651 | break; |
---|
652 | default: |
---|
653 | p_vci_target.cmdack = false; |
---|
654 | p_vci_target.rspval = true; |
---|
655 | p_vci_target.rdata = 0; |
---|
656 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
657 | break; |
---|
658 | } // end switch target fsm |
---|
659 | |
---|
660 | // p_vci_initiator port |
---|
661 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
662 | p_vci_initiator.trdid = 0; |
---|
663 | p_vci_initiator.contig = true; |
---|
664 | p_vci_initiator.cons = false; |
---|
665 | p_vci_initiator.wrap = false; |
---|
666 | p_vci_initiator.cfixed = false; |
---|
667 | p_vci_initiator.clen = 0; |
---|
668 | |
---|
669 | switch (r_initiator_fsm) { |
---|
670 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
671 | p_vci_initiator.rspack = false; |
---|
672 | p_vci_initiator.cmdval = true; |
---|
673 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
674 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
675 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; |
---|
676 | p_vci_initiator.wdata = 0; |
---|
677 | p_vci_initiator.be = 0; |
---|
678 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
679 | p_vci_initiator.eop = true; |
---|
680 | break; |
---|
681 | case M_READ_CMD: // It is actually a multi-words VCI WRITE command |
---|
682 | p_vci_initiator.rspack = false; |
---|
683 | p_vci_initiator.cmdval = true; |
---|
684 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
685 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
686 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
687 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
688 | if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) |
---|
689 | { |
---|
690 | p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + |
---|
691 | (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); |
---|
692 | p_vci_initiator.be = 0xFF; |
---|
693 | p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); |
---|
694 | } |
---|
695 | else |
---|
696 | { |
---|
697 | p_vci_initiator.wdata = r_local_buffer[r_index.read()]; |
---|
698 | p_vci_initiator.be = 0xF; |
---|
699 | p_vci_initiator.eop = ( r_words_count.read() == (r_burst_nwords.read() - 1) ); |
---|
700 | } |
---|
701 | break; |
---|
702 | case M_READ_RSP: |
---|
703 | case M_WRITE_RSP: |
---|
704 | p_vci_initiator.rspack = true; |
---|
705 | p_vci_initiator.cmdval = false; |
---|
706 | break; |
---|
707 | default: |
---|
708 | p_vci_initiator.rspack = false; |
---|
709 | p_vci_initiator.cmdval = false; |
---|
710 | break; |
---|
711 | } |
---|
712 | |
---|
713 | // IRQ signal |
---|
714 | if ( ((r_initiator_fsm == M_READ_SUCCESS) || |
---|
715 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
---|
716 | (r_initiator_fsm == M_READ_ERROR) || |
---|
717 | (r_initiator_fsm == M_WRITE_ERROR) ) && |
---|
718 | r_irq_enable.read() ) |
---|
719 | { |
---|
720 | |
---|
721 | #if DEBUG_BDEV |
---|
722 | std::cout << " <BDEV_INI send IRQ>" << std::endl; |
---|
723 | #endif |
---|
724 | p_irq = true; |
---|
725 | } |
---|
726 | else |
---|
727 | { |
---|
728 | p_irq = false; |
---|
729 | } |
---|
730 | } // end GenMoore() |
---|
731 | |
---|
732 | ////////////////////////////////////////////////////////////////////////////// |
---|
733 | tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name name, |
---|
734 | const soclib::common::MappingTable &mt, |
---|
735 | const soclib::common::IntTab &srcid, |
---|
736 | const soclib::common::IntTab &tgtid, |
---|
737 | const std::string &filename, |
---|
738 | const uint32_t block_size, |
---|
739 | const uint32_t burst_size, |
---|
740 | const uint32_t latency) |
---|
741 | |
---|
742 | : caba::BaseModule(name), |
---|
743 | m_seglist(mt.getSegmentList(tgtid)), |
---|
744 | m_srcid(mt.indexForId(srcid)), |
---|
745 | m_words_per_block(block_size/4), |
---|
746 | m_words_per_burst(burst_size/4), |
---|
747 | m_bursts_per_block(block_size/burst_size), |
---|
748 | m_latency(latency), |
---|
749 | p_clk("p_clk"), |
---|
750 | p_resetn("p_resetn"), |
---|
751 | p_vci_initiator("p_vci_initiator"), |
---|
752 | p_vci_target("p_vci_target"), |
---|
753 | p_irq("p_irq") |
---|
754 | { |
---|
755 | std::cout << " - Building VciBlockDeviceTsar " << name << std::endl; |
---|
756 | |
---|
757 | SC_METHOD(transition); |
---|
758 | dont_initialize(); |
---|
759 | sensitive << p_clk.pos(); |
---|
760 | |
---|
761 | SC_METHOD(genMoore); |
---|
762 | dont_initialize(); |
---|
763 | sensitive << p_clk.neg(); |
---|
764 | |
---|
765 | size_t nbsegs = 0; |
---|
766 | std::list<soclib::common::Segment>::iterator seg; |
---|
767 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
---|
768 | { |
---|
769 | nbsegs++; |
---|
770 | |
---|
771 | if ( (seg->baseAddress() & 0x0000003F) != 0 ) |
---|
772 | { |
---|
773 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
774 | << "The base address of segment " << seg->name() |
---|
775 | << " must be multiple of 64 bytes" << std::endl; |
---|
776 | exit(1); |
---|
777 | } |
---|
778 | if ( seg->size() < 64 ) |
---|
779 | { |
---|
780 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
781 | << "The size of segment " << seg->name() |
---|
782 | << " cannot be smaller than 64 bytes" << std::endl; |
---|
783 | exit(1); |
---|
784 | } |
---|
785 | std::cout << " => segment " << seg->name() |
---|
786 | << " / base = " << std::hex << seg->baseAddress() |
---|
787 | << " / size = " << seg->size() << std::endl; |
---|
788 | } |
---|
789 | |
---|
790 | if( nbsegs == 0 ) |
---|
791 | { |
---|
792 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
793 | << " No segment allocated" << std::endl; |
---|
794 | exit(1); |
---|
795 | } |
---|
796 | |
---|
797 | if( (block_size != 128) && |
---|
798 | (block_size != 256) && |
---|
799 | (block_size != 512) && |
---|
800 | (block_size != 1024) && |
---|
801 | (block_size != 2048) && |
---|
802 | (block_size != 4096) ) |
---|
803 | { |
---|
804 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
805 | << " The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" |
---|
806 | << std::endl; |
---|
807 | exit(1); |
---|
808 | } |
---|
809 | |
---|
810 | if( (burst_size != 8 ) && |
---|
811 | (burst_size != 16) && |
---|
812 | (burst_size != 32) && |
---|
813 | (burst_size != 64) ) |
---|
814 | { |
---|
815 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
816 | << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; |
---|
817 | exit(1); |
---|
818 | } |
---|
819 | |
---|
820 | if ( (vci_param::B != 4) and (vci_param::B != 8) ) |
---|
821 | { |
---|
822 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
823 | << " The VCI data fields must have 32 bits or 64 bits" << std::endl; |
---|
824 | exit(1); |
---|
825 | } |
---|
826 | |
---|
827 | m_fd = ::open(filename.c_str(), O_RDWR); |
---|
828 | if ( m_fd < 0 ) |
---|
829 | { |
---|
830 | std::cout << "Error in component VciBlockDeviceTsar : " << name |
---|
831 | << " Unable to open file " << filename << std::endl; |
---|
832 | exit(1); |
---|
833 | } |
---|
834 | m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; |
---|
835 | |
---|
836 | if ( m_device_size > ((uint64_t)1<<vci_param::N ) ) |
---|
837 | { |
---|
838 | std::cout << "Error in component VciBlockDeviceTsar" << name |
---|
839 | << " The file " << filename |
---|
840 | << " has more blocks than addressable with the VCI address" << std::endl; |
---|
841 | exit(1); |
---|
842 | } |
---|
843 | |
---|
844 | r_local_buffer = new uint32_t[m_words_per_block]; |
---|
845 | |
---|
846 | } // end constructor |
---|
847 | |
---|
848 | ///////////////////////////////// |
---|
849 | tmpl(/**/)::~VciBlockDeviceTsar() |
---|
850 | { |
---|
851 | delete [] r_local_buffer; |
---|
852 | } |
---|
853 | |
---|
854 | |
---|
855 | ////////////////////////// |
---|
856 | tmpl(void)::print_trace() |
---|
857 | { |
---|
858 | const char* initiator_str[] = |
---|
859 | { |
---|
860 | "INI_IDLE", |
---|
861 | |
---|
862 | "INI_READ_BLOCK", |
---|
863 | "INI_READ_BURST", |
---|
864 | "INI_READ_CMD", |
---|
865 | "INI_READ_RSP", |
---|
866 | "INI_READ_SUCCESS", |
---|
867 | "INI_READ_ERROR", |
---|
868 | |
---|
869 | "INI_WRITE_BURST", |
---|
870 | "INI_WRITE_CMD", |
---|
871 | "INI_WRITE_RSP", |
---|
872 | "INI_WRITE_BLOCK", |
---|
873 | "INI_WRITE_SUCCESS", |
---|
874 | "INI_WRITE_ERROR", |
---|
875 | }; |
---|
876 | const char* target_str[] = |
---|
877 | { |
---|
878 | "TGT_IDLE", |
---|
879 | "TGT_WRITE_BUFFER", |
---|
880 | "TGT_READ_BUFFER", |
---|
881 | "TGT_WRITE_BUFFER_EXT", |
---|
882 | "TGT_READ_BUFFER_EXT", |
---|
883 | "TGT_WRITE_COUNT", |
---|
884 | "TGT_READ_COUNT", |
---|
885 | "TGT_WRITE_LBA", |
---|
886 | "TGT_READ_LBA", |
---|
887 | "TGT_WRITE_OP", |
---|
888 | "TGT_READ_STATUS", |
---|
889 | "TGT_WRITE_IRQEN", |
---|
890 | "TGT_READ_IRQEN", |
---|
891 | "TGT_READ_SIZE", |
---|
892 | "TGT_READ_BLOCK", |
---|
893 | "TGT_READ_ERROR", |
---|
894 | "TGT_WRITE_ERROR ", |
---|
895 | }; |
---|
896 | |
---|
897 | std::cout << "BDEV " << name() |
---|
898 | << " : " << target_str[r_target_fsm.read()] |
---|
899 | << " / " << initiator_str[r_initiator_fsm.read()] |
---|
900 | << " / buf = " << std::hex << r_buf_address.read() |
---|
901 | << " / lba = " << std::hex << r_lba.read() |
---|
902 | << " / block_count = " << std::dec << r_block_count.read() |
---|
903 | << " / burst_count = " << r_burst_count.read() |
---|
904 | << " / word_count = " << r_words_count.read() <<std::endl; |
---|
905 | } |
---|
906 | |
---|
907 | }} // end namespace |
---|
908 | |
---|
909 | // Local Variables: |
---|
910 | // tab-width: 4 |
---|
911 | // c-basic-offset: 4 |
---|
912 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
913 | // indent-tabs-mode: nil |
---|
914 | // End: |
---|
915 | |
---|
916 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
917 | |
---|