[151] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, Asim |
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| 24 | * alain.greiner@lip6.fr april 2011 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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| 29 | #include <stdint.h> |
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| 30 | #include <iostream> |
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| 31 | #include <fcntl.h> |
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[164] | 32 | #include "vci_block_device_tsar_v4.h" |
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[151] | 33 | |
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| 34 | namespace soclib { namespace caba { |
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| 35 | |
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| 36 | #define tmpl(t) template<typename vci_param> t VciBlockDeviceTsarV4<vci_param> |
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| 37 | |
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| 38 | using namespace soclib::caba; |
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| 39 | using namespace soclib::common; |
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| 40 | |
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| 41 | //////////////////////// |
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| 42 | tmpl(void)::transition() |
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| 43 | { |
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| 44 | if(p_resetn.read() == false) |
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| 45 | { |
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| 46 | r_initiator_fsm = M_IDLE; |
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| 47 | r_target_fsm = T_IDLE; |
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| 48 | r_irq_enable = true; |
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| 49 | r_go = false; |
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| 50 | return; |
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| 51 | } |
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| 52 | |
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| 53 | ////////////////////////////////////////////////////////////////////////////// |
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| 54 | // The Target FSM controls the following registers: |
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| 55 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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| 56 | ////////////////////////////////////////////////////////////////////////////// |
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| 57 | |
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| 58 | switch(r_target_fsm) { |
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| 59 | case T_IDLE: |
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| 60 | { |
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| 61 | if ( p_vci_target.cmdval.read() ) |
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| 62 | { |
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| 63 | r_srcid = p_vci_target.srcid.read(); |
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| 64 | r_trdid = p_vci_target.trdid.read(); |
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| 65 | r_pktid = p_vci_target.pktid.read(); |
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[164] | 66 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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[151] | 67 | bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); |
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| 68 | uint32_t cell = (uint32_t)((address & 0x1F)>>2); |
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| 69 | |
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| 70 | if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; |
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| 71 | else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR; |
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| 72 | else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; |
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| 73 | else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; |
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| 74 | else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; |
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| 75 | else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; |
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| 76 | else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; |
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| 77 | else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; |
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| 78 | else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; |
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| 79 | else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; |
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| 80 | else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; |
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| 81 | else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; |
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| 82 | else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; |
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| 83 | else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; |
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| 84 | else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; |
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| 85 | else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; |
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| 86 | } |
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| 87 | break; |
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| 88 | } |
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| 89 | case T_WRITE_BUFFER: |
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| 90 | { |
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| 91 | if ( r_initiator_fsm == M_IDLE ) r_buf_address = (uint32_t)p_vci_target.wdata.read(); |
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| 92 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 93 | break; |
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| 94 | } |
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| 95 | case T_WRITE_COUNT: |
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| 96 | { |
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| 97 | if ( r_initiator_fsm == M_IDLE ) r_nblocks = (uint32_t)p_vci_target.wdata.read(); |
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| 98 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 99 | break; |
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| 100 | } |
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| 101 | case T_WRITE_LBA: |
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| 102 | { |
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| 103 | if ( r_initiator_fsm == M_IDLE ) r_lba = (uint32_t)p_vci_target.wdata.read(); |
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| 104 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 105 | break; |
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| 106 | } |
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| 107 | case T_WRITE_OP: |
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| 108 | { |
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| 109 | if ( r_initiator_fsm == M_IDLE ) |
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| 110 | { |
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| 111 | if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ ) |
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| 112 | { |
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| 113 | r_read = true; |
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| 114 | r_go = true; |
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| 115 | } |
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| 116 | else if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE) |
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| 117 | { |
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| 118 | r_read = false; |
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| 119 | r_go = true; |
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| 120 | } |
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| 121 | } |
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| 122 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 123 | break; |
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| 124 | } |
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| 125 | case T_WRITE_IRQEN: |
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| 126 | { |
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| 127 | r_irq_enable = (p_vci_target.wdata.read() != 0); |
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| 128 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 129 | break; |
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| 130 | } |
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| 131 | case T_READ_BUFFER: |
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| 132 | case T_READ_COUNT: |
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| 133 | case T_READ_LBA: |
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| 134 | case T_READ_IRQEN: |
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| 135 | case T_READ_SIZE: |
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| 136 | case T_READ_BLOCK: |
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| 137 | case T_READ_ERROR: |
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| 138 | case T_WRITE_ERROR: |
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| 139 | { |
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| 140 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 141 | break; |
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| 142 | } |
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| 143 | case T_READ_STATUS: |
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| 144 | { |
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| 145 | if ( p_vci_target.rspack.read() ) |
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| 146 | { |
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| 147 | r_target_fsm = T_IDLE; |
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| 148 | if( (r_initiator_fsm == M_READ_SUCCESS ) || |
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| 149 | (r_initiator_fsm == M_READ_ERROR ) || |
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| 150 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
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| 151 | (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; |
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| 152 | } |
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| 153 | break; |
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| 154 | } |
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| 155 | } // end switch target fsm |
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| 156 | |
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| 157 | ///////////////////////////////////////////////////////////////////////// |
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| 158 | // The initiator FSM controls the following registers : |
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| 159 | // r_initiator_fsm, r_flit_count, r_block_count, m_local_buffer |
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| 160 | ///////////////////////////////////////////////////////////////////////// |
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| 161 | switch(r_initiator_fsm) { |
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| 162 | case M_IDLE : // waiting for activation |
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| 163 | { |
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[228] | 164 | if ( r_go ) |
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[151] | 165 | { |
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| 166 | r_block_count = 0; |
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| 167 | r_burst_count = 0; |
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| 168 | r_flit_count = 0; |
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| 169 | r_latency_count = m_latency; |
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| 170 | |
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| 171 | if ( r_read ) r_initiator_fsm = M_READ_BLOCK; |
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[228] | 172 | else r_initiator_fsm = M_WRITE_CMD; |
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[151] | 173 | } |
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| 174 | break; |
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| 175 | } |
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[228] | 176 | case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles |
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[151] | 177 | { |
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[228] | 178 | if ( r_latency_count == 0 ) |
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[151] | 179 | { |
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| 180 | r_latency_count = m_latency; |
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[216] | 181 | ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); |
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| 182 | if( ::read(m_fd, m_local_buffer, m_flits_per_block*vci_param::B) < 0 ) |
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[151] | 183 | { |
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| 184 | r_initiator_fsm = M_READ_ERROR; |
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| 185 | } |
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| 186 | else |
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| 187 | { |
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| 188 | r_initiator_fsm = M_READ_CMD; |
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| 189 | } |
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| 190 | } |
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| 191 | else |
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| 192 | { |
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| 193 | r_latency_count = r_latency_count - 1; |
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| 194 | } |
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| 195 | break; |
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| 196 | } |
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| 197 | case M_READ_CMD: // This is actually a multi-flits VCI WRITE command |
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| 198 | { |
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| 199 | if ( p_vci_initiator.cmdack.read() ) |
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| 200 | { |
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| 201 | if ( r_flit_count == (m_flits_per_burst - 1) ) |
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| 202 | { |
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| 203 | r_initiator_fsm = M_READ_RSP; |
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| 204 | r_flit_count = 0; |
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| 205 | } |
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| 206 | else |
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| 207 | { |
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| 208 | r_flit_count = r_flit_count + 1; |
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| 209 | } |
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| 210 | } |
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| 211 | break; |
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| 212 | } |
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| 213 | case M_READ_RSP: // This is actually a single flit VCI WRITE response |
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| 214 | { |
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| 215 | if ( p_vci_initiator.rspval.read() ) |
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| 216 | { |
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| 217 | if ( (p_vci_initiator.rerror.read()&0x1) == 0 ) r_initiator_fsm = M_READ_TEST; |
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| 218 | else r_initiator_fsm = M_READ_ERROR; |
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| 219 | } |
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| 220 | break; |
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| 221 | } |
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| 222 | case M_READ_TEST: |
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| 223 | { |
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| 224 | if ( r_burst_count.read() == (m_bursts_per_block - 1) ) |
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| 225 | { |
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| 226 | if ( r_block_count.read() == (r_nblocks.read() - 1) ) // last burst of the last block |
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| 227 | { |
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| 228 | r_burst_count = 0; |
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| 229 | r_block_count = 0; |
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| 230 | r_initiator_fsm = M_READ_SUCCESS; |
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| 231 | } |
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| 232 | else // last burst but not last block |
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| 233 | { |
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| 234 | r_burst_count = 0; |
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| 235 | r_block_count = r_block_count.read() + 1; |
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| 236 | r_initiator_fsm = M_READ_BLOCK; |
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| 237 | } |
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| 238 | } |
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| 239 | else // not the last burst of the block |
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| 240 | { |
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| 241 | r_burst_count = r_burst_count.read() + 1; |
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| 242 | r_initiator_fsm = M_READ_CMD; |
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| 243 | } |
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| 244 | break; |
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| 245 | } |
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| 246 | case M_READ_SUCCESS: |
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| 247 | { |
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| 248 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 249 | break; |
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| 250 | } |
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| 251 | case M_READ_ERROR: |
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| 252 | { |
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| 253 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 254 | break; |
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| 255 | } |
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| 256 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
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| 257 | { |
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[228] | 258 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
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[151] | 259 | break; |
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| 260 | } |
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| 261 | case M_WRITE_RSP: // This is actually a multi-flits VCI READ response |
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| 262 | { |
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| 263 | if ( p_vci_initiator.rspval.read() ) |
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| 264 | { |
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| 265 | uint32_t index = (r_burst_count.read()*m_flits_per_burst) + r_flit_count.read(); |
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| 266 | m_local_buffer[index] = (uint32_t)p_vci_initiator.rdata.read(); |
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| 267 | if ( p_vci_initiator.reop.read() ) |
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| 268 | { |
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[228] | 269 | r_flit_count = 0; |
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| 270 | if( (p_vci_initiator.rerror.read()&0x1) == 0 ) r_initiator_fsm = M_WRITE_TEST; |
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[151] | 271 | else r_initiator_fsm = M_WRITE_ERROR; |
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| 272 | } |
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| 273 | else |
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| 274 | { |
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[228] | 275 | r_flit_count = r_flit_count.read() + 1; |
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[151] | 276 | } |
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| 277 | } |
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| 278 | break; |
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| 279 | } |
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| 280 | case M_WRITE_TEST: |
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| 281 | { |
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| 282 | if ( r_burst_count.read() == (m_bursts_per_block - 1) ) // last burst of the block |
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| 283 | { |
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| 284 | r_burst_count = 0; |
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| 285 | r_block_count = r_block_count.read() + 1; |
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| 286 | r_initiator_fsm = M_WRITE_BLOCK; |
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[228] | 287 | } |
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| 288 | else // not the last burst |
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[151] | 289 | { |
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| 290 | r_burst_count = r_burst_count.read() + 1; |
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| 291 | r_initiator_fsm = M_WRITE_CMD; |
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| 292 | } |
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| 293 | break; |
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| 294 | } |
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| 295 | case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles |
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| 296 | { |
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| 297 | if ( r_latency_count == 0 ) |
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| 298 | { |
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| 299 | r_latency_count = m_latency; |
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[216] | 300 | ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); |
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| 301 | if( ::write(m_fd, m_local_buffer, m_flits_per_block*vci_param::B) < 0 ) |
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[151] | 302 | { |
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| 303 | r_initiator_fsm = M_WRITE_ERROR; |
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| 304 | } |
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| 305 | else if ( r_block_count.read() == r_nblocks.read() ) |
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| 306 | { |
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| 307 | r_initiator_fsm = M_WRITE_SUCCESS; |
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| 308 | } |
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| 309 | else |
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| 310 | { |
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| 311 | r_initiator_fsm = M_WRITE_CMD; |
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| 312 | } |
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| 313 | } |
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| 314 | else |
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| 315 | { |
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| 316 | r_latency_count = r_latency_count - 1; |
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| 317 | } |
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| 318 | break; |
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| 319 | } |
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| 320 | case M_WRITE_SUCCESS: |
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| 321 | { |
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| 322 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 323 | break; |
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| 324 | } |
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| 325 | case M_WRITE_ERROR: |
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| 326 | { |
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| 327 | if( !r_go ) r_initiator_fsm = M_IDLE; |
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| 328 | break; |
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| 329 | } |
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| 330 | } // end switch r_initiator_fsm |
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| 331 | } // end transition |
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| 332 | |
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| 333 | ////////////////////// |
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| 334 | tmpl(void)::genMoore() |
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| 335 | { |
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[164] | 336 | sc_dt::sc_uint<vci_param::N> offset; |
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[151] | 337 | uint32_t index; |
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| 338 | |
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| 339 | // p_vci_target port |
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[164] | 340 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
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| 341 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
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| 342 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
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[151] | 343 | p_vci_target.reop = true; |
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| 344 | |
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| 345 | switch(r_target_fsm) { |
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| 346 | case T_IDLE: |
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| 347 | p_vci_target.cmdack = true; |
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| 348 | p_vci_target.rspval = false; |
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| 349 | break; |
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| 350 | case T_READ_STATUS: |
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| 351 | p_vci_target.cmdack = false; |
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| 352 | p_vci_target.rspval = true; |
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| 353 | if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; |
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| 354 | else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; |
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| 355 | else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; |
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| 356 | else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; |
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| 357 | else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; |
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| 358 | else p_vci_target.rdata = BLOCK_DEVICE_BUSY; |
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| 359 | p_vci_target.rerror = VCI_READ_OK; |
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| 360 | break; |
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| 361 | case T_READ_BUFFER: |
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| 362 | p_vci_target.cmdack = false; |
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| 363 | p_vci_target.rspval = true; |
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| 364 | p_vci_target.rdata = (uint32_t)r_buf_address; |
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| 365 | p_vci_target.rerror = VCI_READ_OK; |
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| 366 | break; |
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| 367 | case T_READ_COUNT: |
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| 368 | p_vci_target.cmdack = false; |
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| 369 | p_vci_target.rspval = true; |
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| 370 | p_vci_target.rdata = (uint32_t)r_nblocks; |
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| 371 | p_vci_target.rerror = VCI_READ_OK; |
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| 372 | break; |
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| 373 | case T_READ_LBA: |
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| 374 | p_vci_target.cmdack = false; |
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| 375 | p_vci_target.rspval = true; |
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| 376 | p_vci_target.rdata = (uint32_t)r_lba; |
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| 377 | p_vci_target.rerror = VCI_READ_OK; |
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| 378 | break; |
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| 379 | case T_READ_IRQEN: |
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| 380 | p_vci_target.cmdack = false; |
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| 381 | p_vci_target.rspval = true; |
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| 382 | p_vci_target.rdata = (uint32_t)r_irq_enable; |
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| 383 | p_vci_target.rerror = VCI_READ_OK; |
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| 384 | break; |
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| 385 | case T_READ_SIZE: |
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| 386 | p_vci_target.cmdack = false; |
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| 387 | p_vci_target.rspval = true; |
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| 388 | p_vci_target.rdata = (uint32_t)m_device_size; |
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| 389 | p_vci_target.rerror = VCI_READ_OK; |
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| 390 | break; |
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| 391 | case T_READ_BLOCK: |
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| 392 | p_vci_target.cmdack = false; |
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| 393 | p_vci_target.rspval = true; |
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[216] | 394 | p_vci_target.rdata = (uint32_t)m_flits_per_block*vci_param::B; |
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[151] | 395 | p_vci_target.rerror = VCI_READ_OK; |
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| 396 | break; |
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| 397 | case T_READ_ERROR: |
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| 398 | p_vci_target.cmdack = false; |
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| 399 | p_vci_target.rspval = true; |
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| 400 | p_vci_target.rdata = 0; |
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| 401 | p_vci_target.rerror = VCI_READ_ERROR; |
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| 402 | break; |
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| 403 | case T_WRITE_ERROR: |
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| 404 | p_vci_target.cmdack = false; |
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| 405 | p_vci_target.rspval = true; |
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| 406 | p_vci_target.rdata = 0; |
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| 407 | p_vci_target.rerror = VCI_WRITE_ERROR; |
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| 408 | break; |
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| 409 | default: |
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| 410 | p_vci_target.cmdack = false; |
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| 411 | p_vci_target.rspval = true; |
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| 412 | p_vci_target.rdata = 0; |
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| 413 | p_vci_target.rerror = VCI_WRITE_OK; |
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| 414 | break; |
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| 415 | } // end switch target fsm |
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| 416 | |
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| 417 | // p_vci_initiator port |
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[164] | 418 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
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[151] | 419 | p_vci_initiator.trdid = 0; |
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| 420 | p_vci_initiator.pktid = 0; |
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| 421 | p_vci_initiator.contig = true; |
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| 422 | p_vci_initiator.cons = false; |
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| 423 | p_vci_initiator.wrap = false; |
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| 424 | p_vci_initiator.cfixed = false; |
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| 425 | p_vci_initiator.clen = 0; |
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| 426 | |
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| 427 | switch (r_initiator_fsm) { |
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| 428 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
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| 429 | offset = (r_block_count.read()*m_flits_per_block + |
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| 430 | r_burst_count.read()*m_flits_per_burst) * vci_param::B; |
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| 431 | p_vci_initiator.rspack = false; |
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| 432 | p_vci_initiator.cmdval = true; |
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[164] | 433 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read() + offset; |
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[151] | 434 | p_vci_initiator.cmd = vci_param::CMD_READ; |
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| 435 | p_vci_initiator.wdata = 0; |
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| 436 | p_vci_initiator.be = (uint32_t)0xF; |
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[164] | 437 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)m_flits_per_burst*vci_param::B; |
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[151] | 438 | p_vci_initiator.eop = true; |
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| 439 | break; |
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| 440 | case M_READ_CMD: // It is actually a multi-flits VCI WRITE command |
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| 441 | offset = ( r_block_count.read()*m_flits_per_block + |
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| 442 | r_burst_count.read()*m_flits_per_burst + |
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| 443 | r_flit_count.read() ) * vci_param::B; |
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| 444 | index = (r_burst_count.read()*m_flits_per_burst) + r_flit_count.read(); |
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| 445 | p_vci_initiator.rspack = false; |
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| 446 | p_vci_initiator.cmdval = true; |
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[164] | 447 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read() + offset; |
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[151] | 448 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
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| 449 | p_vci_initiator.wdata = (uint32_t)m_local_buffer[index]; |
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| 450 | p_vci_initiator.be = 0xF; |
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[164] | 451 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)m_flits_per_burst*vci_param::B; |
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[151] | 452 | p_vci_initiator.eop = ( r_flit_count.read() == (m_flits_per_burst - 1) ); |
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| 453 | break; |
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| 454 | case M_READ_RSP: |
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| 455 | case M_WRITE_RSP: |
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| 456 | p_vci_initiator.rspack = true; |
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| 457 | p_vci_initiator.cmdval = false; |
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| 458 | break; |
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| 459 | default: |
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| 460 | p_vci_initiator.rspack = false; |
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| 461 | p_vci_initiator.cmdval = false; |
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| 462 | break; |
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| 463 | } |
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| 464 | |
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| 465 | // IRQ signal |
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| 466 | if(((r_initiator_fsm == M_READ_SUCCESS) || |
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| 467 | (r_initiator_fsm == M_WRITE_SUCCESS) || |
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| 468 | (r_initiator_fsm == M_READ_ERROR) || |
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| 469 | (r_initiator_fsm == M_WRITE_ERROR) ) && r_irq_enable) p_irq = true; |
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| 470 | else p_irq = false; |
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| 471 | } // end GenMoore() |
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| 472 | |
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| 473 | ////////////////////////////////////////////////////////////////////////////// |
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| 474 | tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_name name, |
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| 475 | const soclib::common::MappingTable &mt, |
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| 476 | const soclib::common::IntTab &srcid, |
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| 477 | const soclib::common::IntTab &tgtid, |
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| 478 | const std::string &filename, |
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| 479 | const uint32_t block_size, |
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| 480 | const uint32_t burst_size, |
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| 481 | const uint32_t latency) |
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| 482 | |
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| 483 | : caba::BaseModule(name), |
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| 484 | m_segment(mt.getSegment(tgtid)), |
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| 485 | m_srcid(mt.indexForId(srcid)), |
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| 486 | m_flits_per_block(block_size/vci_param::B), |
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| 487 | m_flits_per_burst(burst_size/vci_param::B), |
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| 488 | m_bursts_per_block(block_size/burst_size), |
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| 489 | m_latency(latency), |
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| 490 | p_clk("p_clk"), |
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| 491 | p_resetn("p_resetn"), |
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| 492 | p_vci_initiator("p_vci_initiator"), |
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| 493 | p_vci_target("p_vci_target"), |
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| 494 | p_irq("p_irq") |
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| 495 | { |
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| 496 | SC_METHOD(transition); |
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| 497 | sensitive_pos << p_clk; |
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| 498 | |
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| 499 | SC_METHOD(genMoore); |
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| 500 | sensitive_neg << p_clk; |
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| 501 | |
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| 502 | if( (block_size != 64 ) && |
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| 503 | (block_size != 128) && |
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| 504 | (block_size != 256) && |
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| 505 | (block_size != 512) && |
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| 506 | (block_size != 1024) ) |
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| 507 | { |
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| 508 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
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| 509 | std::cout << "The block size must be 128, 256, 512 or 1024 bytes" << std::endl; |
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| 510 | exit(1); |
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| 511 | } |
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| 512 | if ( m_segment.size() < 32 ) |
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| 513 | { |
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| 514 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
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| 515 | std::cout << "The size of the segment cannot be smaller than 32 bytes" << std::endl; |
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| 516 | exit(1); |
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| 517 | } |
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| 518 | if ( (m_segment.baseAddress() & 0x0000001F) != 0 ) |
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| 519 | { |
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| 520 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
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| 521 | std::cout << "The base address of the segment must be multiple of 32 bytes" << std::endl; |
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| 522 | exit(1); |
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| 523 | } |
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| 524 | if ( block_size%burst_size != 0 ) |
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| 525 | { |
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| 526 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
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| 527 | std::cout << "The block_size parameter must be a multiple of the burst_size" << std::endl; |
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| 528 | exit(1); |
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| 529 | } |
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| 530 | if ( vci_param::B != 4 ) |
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| 531 | { |
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| 532 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
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| 533 | std::cout << "The VCI data fields must have 32 bits" << std::endl; |
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| 534 | exit(1); |
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| 535 | } |
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| 536 | m_fd = ::open(filename.c_str(), O_RDWR); |
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| 537 | if ( m_fd < 0 ) |
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| 538 | { |
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| 539 | std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; |
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| 540 | std::cout << "Unable to open file " << filename << std::endl; |
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| 541 | exit(1); |
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| 542 | } |
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| 543 | m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; |
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| 544 | if ( m_device_size > ((uint64_t)1<<32) ) |
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| 545 | { |
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| 546 | std::cout << "Warning: block device " << name << std::endl; |
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| 547 | std::cout << "The file " << filename << std::endl; |
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| 548 | std::cout << "has more blocks than addressable with the 32 bits PIBUS address" << std::endl; |
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| 549 | m_device_size = ((uint64_t)1<<32); |
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| 550 | } |
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| 551 | |
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| 552 | m_local_buffer = new uint32_t[m_flits_per_block]; |
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| 553 | |
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| 554 | std::cout << std::endl << "Instanciation of VciBlockDeviceTsarV4 : " << name << std::endl; |
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| 555 | std::cout << " file_name = " << filename << std::endl; |
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| 556 | std::cout << " burst_size = " << std::dec << m_flits_per_burst*vci_param::B << std::endl; |
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| 557 | std::cout << " block_size = " << std::dec << m_flits_per_block*vci_param::B << std::endl; |
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| 558 | std::cout << " latency = " << std::dec << m_latency << std::endl; |
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| 559 | std::cout << " segment " << m_segment.name() |
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| 560 | << " | base = 0x" << std::hex << m_segment.baseAddress() |
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| 561 | << " | size = " << std::dec << m_segment.size() << std::endl; |
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| 562 | |
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| 563 | } // end constructor |
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| 564 | |
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| 565 | ////////////////////////// |
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| 566 | tmpl(void)::print_trace() |
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| 567 | { |
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| 568 | const char* initiator_str[] = { |
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| 569 | "IDLE ", |
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| 570 | "READ_BLOCK ", |
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| 571 | "READ_CMD ", |
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| 572 | "READ_RSP ", |
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| 573 | "READ_TEST ", |
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| 574 | "READ_SUCCESS ", |
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| 575 | "READ_ERROR ", |
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| 576 | "WRITE_BLOCK ", |
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| 577 | "WRITE_CMD ", |
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| 578 | "WRITE_RSP ", |
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| 579 | "WRITE_TEST ", |
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| 580 | "WRITE_SUCCESS", |
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| 581 | "WRITE_ERROR ", |
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| 582 | }; |
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| 583 | const char* target_str[] = { |
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| 584 | "IDLE ", |
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| 585 | "WRITE_BUFFER", |
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| 586 | "READ_BUFFER ", |
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| 587 | "WRITE_COUNT ", |
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| 588 | "READ_COUNT ", |
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| 589 | "WRITE_LBA ", |
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| 590 | "READ_LBA ", |
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| 591 | "WRITE_OP ", |
---|
| 592 | "READ_STATUS ", |
---|
| 593 | "WRITE_IRQEN ", |
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| 594 | "READ_IRQEN ", |
---|
| 595 | "READ_SIZE ", |
---|
| 596 | "READ_BLOCK ", |
---|
| 597 | "READ_ERROR ", |
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| 598 | "WRITE_ERROR ", |
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| 599 | }; |
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| 600 | |
---|
| 601 | std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()] |
---|
| 602 | << " BDEV_INI : " << initiator_str[r_initiator_fsm.read()] |
---|
| 603 | << " block = " << r_block_count.read() |
---|
| 604 | << " burst = " << r_burst_count.read() |
---|
| 605 | << " flit = " << r_flit_count.read() <<std::endl; |
---|
| 606 | } |
---|
| 607 | |
---|
| 608 | |
---|
| 609 | }} // end namespace |
---|
| 610 | |
---|
| 611 | // Local Variables: |
---|
| 612 | // tab-width: 4 |
---|
| 613 | // c-basic-offset: 4 |
---|
| 614 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 615 | // indent-tabs-mode: nil |
---|
| 616 | // End: |
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| 617 | |
---|
| 618 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 619 | |
---|