[331] | 1 | /* -*- c++ -*- |
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[346] | 2 | * |
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[331] | 3 | * File : vci_cc_vcache_wrapper.h |
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| 4 | * Copyright (c) UPMC, Lip6, SoC |
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| 5 | * Authors : Alain GREINER, Yang GAO |
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| 6 | * Date : 27/11/2011 |
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| 7 | * |
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| 8 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 9 | * |
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| 10 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 11 | * |
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| 12 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 13 | * under the terms of the GNU Lesser General Public License as published |
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| 14 | * by the Free Software Foundation; version 2.1 of the License. |
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| 15 | * |
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| 16 | * SoCLib is distributed in the hope that it will be useful, but |
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 19 | * Lesser General Public License for more details. |
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| 20 | * |
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| 21 | * You should have received a copy of the GNU Lesser General Public |
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| 22 | * License along with SoCLib; if not, write to the Free Software |
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| 23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 24 | * 02110-1301 USA |
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| 25 | * |
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| 26 | * SOCLIB_LGPL_HEADER_END |
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| 27 | * |
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| 28 | * Maintainers: cesar.fuguet-tortolero@lip6.fr |
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| 29 | * alexandre.joannou@lip6.fr |
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| 30 | */ |
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| 31 | |
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| 32 | #ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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| 33 | #define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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| 34 | |
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| 35 | #include <inttypes.h> |
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| 36 | #include <systemc> |
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| 37 | #include "caba_base_module.h" |
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| 38 | #include "multi_write_buffer.h" |
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| 39 | #include "generic_fifo.h" |
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| 40 | #include "generic_tlb.h" |
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| 41 | #include "generic_cache.h" |
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| 42 | #include "vci_initiator.h" |
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| 43 | #include "dspin_interface.h" |
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| 44 | #include "dspin_dhccp_param.h" |
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| 45 | #include "mapping_table.h" |
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| 46 | #include "static_assert.h" |
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| 47 | #include "iss2.h" |
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| 48 | |
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| 49 | #define LLSC_TIMEOUT 10000 |
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| 50 | |
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| 51 | namespace soclib { |
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| 52 | namespace caba { |
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| 53 | |
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| 54 | using namespace sc_core; |
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| 55 | |
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| 56 | //////////////////////////////////////////// |
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[386] | 57 | template<typename vci_param, |
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| 58 | size_t dspin_in_width, |
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| 59 | size_t dspin_out_width, |
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| 60 | typename iss_t> |
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[331] | 61 | class VciCcVCacheWrapper |
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| 62 | //////////////////////////////////////////// |
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| 63 | : public soclib::caba::BaseModule |
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| 64 | { |
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| 65 | |
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[394] | 66 | typedef typename vci_param::fast_addr_t paddr_t; |
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[331] | 67 | |
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[394] | 68 | enum icache_fsm_state_e |
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| 69 | { |
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[331] | 70 | ICACHE_IDLE, |
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| 71 | // handling XTN processor requests |
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| 72 | ICACHE_XTN_TLB_FLUSH, |
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| 73 | ICACHE_XTN_CACHE_FLUSH, |
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| 74 | ICACHE_XTN_CACHE_FLUSH_GO, |
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| 75 | ICACHE_XTN_TLB_INVAL, |
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| 76 | ICACHE_XTN_CACHE_INVAL_VA, |
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| 77 | ICACHE_XTN_CACHE_INVAL_PA, |
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| 78 | ICACHE_XTN_CACHE_INVAL_GO, |
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| 79 | // handling tlb miss |
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| 80 | ICACHE_TLB_WAIT, |
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| 81 | // handling cache miss |
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| 82 | ICACHE_MISS_SELECT, |
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| 83 | ICACHE_MISS_CLEAN, |
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| 84 | ICACHE_MISS_WAIT, |
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| 85 | ICACHE_MISS_DATA_UPDT, |
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| 86 | ICACHE_MISS_DIR_UPDT, |
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| 87 | // handling unc read |
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| 88 | ICACHE_UNC_WAIT, |
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| 89 | // handling coherence requests |
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| 90 | ICACHE_CC_CHECK, |
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[468] | 91 | ICACHE_CC_UPDT, |
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[331] | 92 | ICACHE_CC_INVAL, |
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| 93 | }; |
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| 94 | |
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[394] | 95 | enum dcache_fsm_state_e |
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| 96 | { |
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[331] | 97 | DCACHE_IDLE, |
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| 98 | // handling itlb & dtlb miss |
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| 99 | DCACHE_TLB_MISS, |
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| 100 | DCACHE_TLB_PTE1_GET, |
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| 101 | DCACHE_TLB_PTE1_SELECT, |
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| 102 | DCACHE_TLB_PTE1_UPDT, |
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| 103 | DCACHE_TLB_PTE2_GET, |
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| 104 | DCACHE_TLB_PTE2_SELECT, |
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| 105 | DCACHE_TLB_PTE2_UPDT, |
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| 106 | DCACHE_TLB_LR_UPDT, |
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| 107 | DCACHE_TLB_LR_WAIT, |
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| 108 | DCACHE_TLB_RETURN, |
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| 109 | // handling processor XTN requests |
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| 110 | DCACHE_XTN_SWITCH, |
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| 111 | DCACHE_XTN_SYNC, |
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| 112 | DCACHE_XTN_IC_INVAL_VA, |
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| 113 | DCACHE_XTN_IC_FLUSH, |
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| 114 | DCACHE_XTN_IC_INVAL_PA, |
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| 115 | DCACHE_XTN_IT_INVAL, |
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| 116 | DCACHE_XTN_DC_FLUSH, |
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| 117 | DCACHE_XTN_DC_FLUSH_GO, |
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| 118 | DCACHE_XTN_DC_INVAL_VA, |
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| 119 | DCACHE_XTN_DC_INVAL_PA, |
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| 120 | DCACHE_XTN_DC_INVAL_END, |
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| 121 | DCACHE_XTN_DC_INVAL_GO, |
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| 122 | DCACHE_XTN_DT_INVAL, |
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| 123 | //handling dirty bit update |
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| 124 | DCACHE_DIRTY_GET_PTE, |
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| 125 | DCACHE_DIRTY_WAIT, |
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| 126 | // handling processor miss requests |
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| 127 | DCACHE_MISS_SELECT, |
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| 128 | DCACHE_MISS_CLEAN, |
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| 129 | DCACHE_MISS_WAIT, |
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| 130 | DCACHE_MISS_DATA_UPDT, |
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| 131 | DCACHE_MISS_DIR_UPDT, |
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| 132 | // handling processor unc, ll and sc requests |
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| 133 | DCACHE_UNC_WAIT, |
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| 134 | DCACHE_LL_WAIT, |
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| 135 | DCACHE_SC_WAIT, |
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| 136 | // handling coherence requests |
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| 137 | DCACHE_CC_CHECK, |
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[468] | 138 | DCACHE_CC_UPDT, |
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[331] | 139 | DCACHE_CC_INVAL, |
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| 140 | // handling TLB inval (after a coherence or XTN request) |
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| 141 | DCACHE_INVAL_TLB_SCAN, |
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| 142 | }; |
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| 143 | |
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[394] | 144 | enum cmd_fsm_state_e |
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| 145 | { |
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[331] | 146 | CMD_IDLE, |
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| 147 | CMD_INS_MISS, |
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| 148 | CMD_INS_UNC, |
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| 149 | CMD_DATA_MISS, |
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[616] | 150 | CMD_DATA_UNC_READ, |
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| 151 | CMD_DATA_UNC_WRITE, |
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[331] | 152 | CMD_DATA_WRITE, |
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| 153 | CMD_DATA_LL, |
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| 154 | CMD_DATA_SC, |
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| 155 | CMD_DATA_CAS, |
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| 156 | }; |
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| 157 | |
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[394] | 158 | enum rsp_fsm_state_e |
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| 159 | { |
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[331] | 160 | RSP_IDLE, |
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| 161 | RSP_INS_MISS, |
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| 162 | RSP_INS_UNC, |
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| 163 | RSP_DATA_MISS, |
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| 164 | RSP_DATA_UNC, |
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| 165 | RSP_DATA_LL, |
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| 166 | RSP_DATA_WRITE, |
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| 167 | }; |
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| 168 | |
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[394] | 169 | enum cc_receive_fsm_state_e |
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| 170 | { |
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[331] | 171 | CC_RECEIVE_IDLE, |
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| 172 | CC_RECEIVE_BRDCAST_HEADER, |
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| 173 | CC_RECEIVE_BRDCAST_NLINE, |
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[468] | 174 | CC_RECEIVE_INS_INVAL_HEADER, |
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| 175 | CC_RECEIVE_INS_INVAL_NLINE, |
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| 176 | CC_RECEIVE_INS_UPDT_HEADER, |
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| 177 | CC_RECEIVE_INS_UPDT_NLINE, |
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| 178 | CC_RECEIVE_DATA_INVAL_HEADER, |
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| 179 | CC_RECEIVE_DATA_INVAL_NLINE, |
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| 180 | CC_RECEIVE_DATA_UPDT_HEADER, |
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| 181 | CC_RECEIVE_DATA_UPDT_NLINE, |
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[487] | 182 | CC_RECEIVE_INS_UPDT_DATA, |
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[468] | 183 | CC_RECEIVE_DATA_UPDT_DATA, |
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[331] | 184 | }; |
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| 185 | |
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[394] | 186 | enum cc_send_fsm_state_e |
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| 187 | { |
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[331] | 188 | CC_SEND_IDLE, |
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| 189 | CC_SEND_CLEANUP_1, |
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| 190 | CC_SEND_CLEANUP_2, |
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| 191 | CC_SEND_MULTI_ACK, |
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| 192 | }; |
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| 193 | |
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| 194 | /* transaction type, pktid field */ |
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| 195 | enum transaction_type_e |
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| 196 | { |
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| 197 | // b3 unused |
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| 198 | // b2 READ / NOT READ |
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| 199 | // if READ |
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| 200 | // b1 DATA / INS |
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| 201 | // b0 UNC / MISS |
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| 202 | // else |
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| 203 | // b1 accÚs table llsc type SW / other |
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| 204 | // b2 WRITE/CAS/LL/SC |
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[616] | 205 | TYPE_DATA_UNC = 0x0, |
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[331] | 206 | TYPE_READ_DATA_MISS = 0x1, |
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| 207 | TYPE_READ_INS_UNC = 0x2, |
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| 208 | TYPE_READ_INS_MISS = 0x3, |
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| 209 | TYPE_WRITE = 0x4, |
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| 210 | TYPE_CAS = 0x5, |
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| 211 | TYPE_LL = 0x6, |
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| 212 | TYPE_SC = 0x7 |
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| 213 | }; |
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| 214 | |
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| 215 | /* SC return values */ |
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| 216 | enum sc_status_type_e |
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| 217 | { |
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| 218 | SC_SUCCESS = 0x00000000, |
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| 219 | SC_FAIL = 0x00000001 |
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| 220 | }; |
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| 221 | |
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| 222 | // cc_send_type |
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[394] | 223 | typedef enum |
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| 224 | { |
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[331] | 225 | CC_TYPE_CLEANUP, |
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| 226 | CC_TYPE_MULTI_ACK, |
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| 227 | } cc_send_t; |
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| 228 | |
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| 229 | // cc_receive_type |
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[394] | 230 | typedef enum |
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| 231 | { |
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[331] | 232 | CC_TYPE_CLACK, |
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| 233 | CC_TYPE_BRDCAST, |
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| 234 | CC_TYPE_INVAL, |
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| 235 | CC_TYPE_UPDT, |
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| 236 | } cc_receive_t; |
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| 237 | |
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| 238 | // TLB Mode : ITLB / DTLB / ICACHE / DCACHE |
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[394] | 239 | enum |
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| 240 | { |
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[331] | 241 | INS_TLB_MASK = 0x8, |
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| 242 | DATA_TLB_MASK = 0x4, |
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| 243 | INS_CACHE_MASK = 0x2, |
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| 244 | DATA_CACHE_MASK = 0x1, |
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| 245 | }; |
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| 246 | |
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| 247 | // Error Type |
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| 248 | enum mmu_error_type_e |
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| 249 | { |
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| 250 | MMU_NONE = 0x0000, // None |
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| 251 | MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 |
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| 252 | MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 |
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| 253 | MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode |
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| 254 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page |
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| 255 | MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write & undefined external access |
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| 256 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write & Bus Error accessing PT1 |
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| 257 | MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 |
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| 258 | MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access |
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| 259 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 |
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| 260 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 |
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| 261 | MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode |
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| 262 | MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page |
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| 263 | MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access |
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| 264 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 |
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| 265 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 |
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| 266 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access |
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| 267 | }; |
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| 268 | |
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| 269 | // miss types for data cache |
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| 270 | enum dcache_miss_type_e |
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| 271 | { |
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| 272 | PTE1_MISS, |
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| 273 | PTE2_MISS, |
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| 274 | PROC_MISS, |
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| 275 | }; |
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| 276 | |
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[616] | 277 | // enum transaction_type_d_e |
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| 278 | // { |
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| 279 | // // b0 : 1 if cached |
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| 280 | // // b1 : 1 if instruction |
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| 281 | // TYPE_DATA_UNC = 0x0, |
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| 282 | // TYPE_DATA_MISS = 0x1, |
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| 283 | // TYPE_INS_UNC = 0x2, |
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| 284 | // TYPE_INS_MISS = 0x3, |
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| 285 | // }; |
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[331] | 286 | |
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| 287 | public: |
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[468] | 288 | sc_in<bool> p_clk; |
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| 289 | sc_in<bool> p_resetn; |
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| 290 | sc_in<bool> p_irq[iss_t::n_irq]; |
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| 291 | soclib::caba::VciInitiator<vci_param> p_vci; |
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| 292 | soclib::caba::DspinInput<dspin_in_width> p_dspin_m2p; |
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| 293 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m; |
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| 294 | soclib::caba::DspinInput<dspin_in_width> p_dspin_clack; |
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[331] | 295 | |
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| 296 | private: |
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| 297 | |
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| 298 | // STRUCTURAL PARAMETERS |
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[549] | 299 | soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table; |
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[331] | 300 | |
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[394] | 301 | const size_t m_srcid; |
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[346] | 302 | const size_t m_cc_global_id; |
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| 303 | const size_t m_nline_width; |
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[331] | 304 | const size_t m_itlb_ways; |
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| 305 | const size_t m_itlb_sets; |
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| 306 | const size_t m_dtlb_ways; |
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| 307 | const size_t m_dtlb_sets; |
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| 308 | const size_t m_icache_ways; |
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| 309 | const size_t m_icache_sets; |
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| 310 | const paddr_t m_icache_yzmask; |
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| 311 | const size_t m_icache_words; |
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| 312 | const size_t m_dcache_ways; |
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| 313 | const size_t m_dcache_sets; |
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| 314 | const paddr_t m_dcache_yzmask; |
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| 315 | const size_t m_dcache_words; |
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| 316 | const size_t m_x_width; |
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| 317 | const size_t m_y_width; |
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| 318 | const size_t m_proc_id; |
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| 319 | const uint32_t m_max_frozen_cycles; |
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| 320 | const size_t m_paddr_nbits; |
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[346] | 321 | uint32_t m_debug_start_cycle; |
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| 322 | bool m_debug_ok; |
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[331] | 323 | |
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| 324 | //////////////////////////////////////// |
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| 325 | // Communication with processor ISS |
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| 326 | //////////////////////////////////////// |
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| 327 | typename iss_t::InstructionRequest m_ireq; |
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| 328 | typename iss_t::InstructionResponse m_irsp; |
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| 329 | typename iss_t::DataRequest m_dreq; |
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| 330 | typename iss_t::DataResponse m_drsp; |
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| 331 | |
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| 332 | ///////////////////////////////////////////// |
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[394] | 333 | // debug variables |
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[331] | 334 | ///////////////////////////////////////////// |
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[394] | 335 | bool m_debug_previous_i_hit; |
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| 336 | bool m_debug_previous_d_hit; |
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[668] | 337 | bool m_debug_icache_fsm; |
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| 338 | bool m_debug_dcache_fsm; |
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| 339 | bool m_debug_cmd_fsm; |
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[331] | 340 | |
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| 341 | /////////////////////////////// |
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| 342 | // Software visible REGISTERS |
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| 343 | /////////////////////////////// |
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| 344 | sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register |
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| 345 | sc_signal<uint32_t> r_mmu_mode; // mmu mode register |
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| 346 | sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low |
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| 347 | sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight |
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| 348 | sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address |
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| 349 | sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address |
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| 350 | sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type |
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| 351 | sc_signal<uint32_t> r_mmu_detr; // mmu data error type |
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| 352 | uint32_t r_mmu_params; // read-only |
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| 353 | uint32_t r_mmu_release; // read_only |
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| 354 | |
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| 355 | |
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| 356 | ////////////////////////////// |
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| 357 | // ICACHE FSM REGISTERS |
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| 358 | ////////////////////////////// |
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| 359 | sc_signal<int> r_icache_fsm; // state register |
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| 360 | sc_signal<int> r_icache_fsm_save; // return state for coherence op |
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| 361 | sc_signal<paddr_t> r_icache_vci_paddr; // physical address |
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| 362 | sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor |
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| 363 | |
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| 364 | // icache miss handling |
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| 365 | sc_signal<size_t> r_icache_miss_way; // selected way for cache update |
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| 366 | sc_signal<size_t> r_icache_miss_set; // selected set for cache update |
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| 367 | sc_signal<size_t> r_icache_miss_word; // word index ( cache update) |
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| 368 | sc_signal<bool> r_icache_miss_inval; // coherence request matching a miss |
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| 369 | sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge |
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| 370 | |
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| 371 | // coherence request handling |
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| 372 | sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval |
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| 373 | sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval |
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| 374 | sc_signal<size_t> r_icache_cc_word; // word counter for cc update |
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| 375 | sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing |
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| 376 | |
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[468] | 377 | // coherence clack handling |
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| 378 | sc_signal<bool> r_icache_clack_req; // clack request |
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| 379 | sc_signal<size_t> r_icache_clack_way; // clack way |
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| 380 | sc_signal<size_t> r_icache_clack_set; // clack set |
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| 381 | |
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[331] | 382 | // icache flush handling |
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| 383 | sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush |
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| 384 | |
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| 385 | // communication between ICACHE FSM and VCI_CMD FSM |
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| 386 | sc_signal<bool> r_icache_miss_req; // cached read miss |
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| 387 | sc_signal<bool> r_icache_unc_req; // uncached read miss |
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| 388 | |
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| 389 | // communication between ICACHE FSM and DCACHE FSM |
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| 390 | sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache) |
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| 391 | sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error |
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| 392 | |
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[487] | 393 | // Filp-Flop in ICACHE FSM for saving the cleanup victim request |
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| 394 | sc_signal<bool> r_icache_cleanup_victim_req; |
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| 395 | sc_signal<paddr_t> r_icache_cleanup_victim_nline; |
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| 396 | |
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[331] | 397 | // communication between ICACHE FSM and CC_SEND FSM |
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| 398 | sc_signal<bool> r_icache_cc_send_req; // ICACHE cc_send request |
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[549] | 399 | sc_signal<int> r_icache_cc_send_type; // ICACHE cc_send request type |
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[331] | 400 | sc_signal<paddr_t> r_icache_cc_send_nline; // ICACHE cc_send nline |
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| 401 | sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way |
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| 402 | sc_signal<size_t> r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index |
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| 403 | |
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| 404 | /////////////////////////////// |
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| 405 | // DCACHE FSM REGISTERS |
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| 406 | /////////////////////////////// |
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| 407 | sc_signal<int> r_dcache_fsm; // state register |
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| 408 | sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence op |
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| 409 | sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op |
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| 410 | // registers written in P0 stage (used in P1 stage) |
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| 411 | sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage |
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| 412 | sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage |
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| 413 | sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) |
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| 414 | sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) |
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[394] | 415 | sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) |
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[331] | 416 | sc_signal<paddr_t> r_dcache_save_paddr; // physical address |
---|
| 417 | sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) |
---|
| 418 | sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) |
---|
| 419 | sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache) |
---|
| 420 | // registers used by the Dirty bit sub-fsm |
---|
| 421 | sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address |
---|
| 422 | sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache |
---|
| 423 | sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache |
---|
| 424 | |
---|
| 425 | // communication between DCACHE FSM and VCI_CMD FSM |
---|
| 426 | sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command |
---|
[616] | 427 | sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command |
---|
[331] | 428 | sc_signal<bool> r_dcache_vci_miss_req; // read miss request |
---|
[616] | 429 | sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) |
---|
| 430 | sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable byte enable |
---|
| 431 | sc_signal<uint32_t> r_dcache_vci_unc_write; // uncacheable data write request |
---|
[331] | 432 | sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS |
---|
| 433 | sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS |
---|
| 434 | sc_signal<uint32_t> r_dcache_vci_cas_new; // new data value for a CAS |
---|
| 435 | sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL |
---|
| 436 | sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC |
---|
[394] | 437 | sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) |
---|
[331] | 438 | |
---|
| 439 | // register used for XTN inval |
---|
| 440 | sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) |
---|
| 441 | sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) |
---|
| 442 | |
---|
| 443 | // handling dcache miss |
---|
| 444 | sc_signal<int> r_dcache_miss_type; // depending on the requester |
---|
| 445 | sc_signal<size_t> r_dcache_miss_word; // word index for cache update |
---|
| 446 | sc_signal<size_t> r_dcache_miss_way; // selected way for cache update |
---|
| 447 | sc_signal<size_t> r_dcache_miss_set; // selected set for cache update |
---|
| 448 | sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss |
---|
| 449 | sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge |
---|
| 450 | |
---|
| 451 | // handling coherence requests |
---|
| 452 | sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval |
---|
| 453 | sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval |
---|
| 454 | sc_signal<size_t> r_dcache_cc_word; // word counter for cc update |
---|
| 455 | sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing |
---|
| 456 | |
---|
[468] | 457 | // coherence clack handling |
---|
| 458 | sc_signal<bool> r_dcache_clack_req; // clack request |
---|
| 459 | sc_signal<size_t> r_dcache_clack_way; // clack way |
---|
| 460 | sc_signal<size_t> r_dcache_clack_set; // clack set |
---|
| 461 | |
---|
[331] | 462 | // dcache flush handling |
---|
| 463 | sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush |
---|
| 464 | |
---|
| 465 | // ll response handling |
---|
| 466 | sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp |
---|
| 467 | |
---|
| 468 | // used by the TLB miss sub-fsm |
---|
| 469 | sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss |
---|
| 470 | sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) |
---|
| 471 | sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte |
---|
| 472 | sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 |
---|
| 473 | sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 |
---|
| 474 | sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache |
---|
| 475 | sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache |
---|
| 476 | sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache |
---|
| 477 | sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb |
---|
| 478 | sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb |
---|
| 479 | |
---|
| 480 | // ITLB and DTLB invalidation |
---|
| 481 | sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index |
---|
| 482 | sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter |
---|
| 483 | |
---|
| 484 | // communication between DCACHE FSM and ICACHE FSM |
---|
| 485 | sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor) |
---|
| 486 | sc_signal<int> r_dcache_xtn_opcode; // xtn request type |
---|
| 487 | |
---|
[487] | 488 | // Filp-Flop in DCACHE FSM for saving the cleanup victim request |
---|
| 489 | sc_signal<bool> r_dcache_cleanup_victim_req; |
---|
| 490 | sc_signal<paddr_t> r_dcache_cleanup_victim_nline; |
---|
| 491 | |
---|
[331] | 492 | // communication between DCACHE FSM and CC_SEND FSM |
---|
| 493 | sc_signal<bool> r_dcache_cc_send_req; // DCACHE cc_send request |
---|
[549] | 494 | sc_signal<int> r_dcache_cc_send_type; // DCACHE cc_send request type |
---|
[331] | 495 | sc_signal<paddr_t> r_dcache_cc_send_nline; // DCACHE cc_send nline |
---|
| 496 | sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way |
---|
| 497 | sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index |
---|
| 498 | |
---|
| 499 | // dcache directory extension |
---|
[394] | 500 | bool *r_dcache_in_tlb; // copy exist in dtlb or itlb |
---|
| 501 | bool *r_dcache_contains_ptd; // cache line contains a PTD |
---|
[331] | 502 | |
---|
[394] | 503 | // Physical address extension for data access |
---|
| 504 | sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32) |
---|
| 505 | |
---|
[331] | 506 | /////////////////////////////////// |
---|
| 507 | // VCI_CMD FSM REGISTERS |
---|
| 508 | /////////////////////////////////// |
---|
| 509 | sc_signal<int> r_vci_cmd_fsm; |
---|
[394] | 510 | sc_signal<size_t> r_vci_cmd_min; // used for write bursts |
---|
| 511 | sc_signal<size_t> r_vci_cmd_max; // used for write bursts |
---|
| 512 | sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts |
---|
| 513 | sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss |
---|
[331] | 514 | |
---|
| 515 | /////////////////////////////////// |
---|
| 516 | // VCI_RSP FSM REGISTERS |
---|
| 517 | /////////////////////////////////// |
---|
| 518 | sc_signal<int> r_vci_rsp_fsm; |
---|
| 519 | sc_signal<size_t> r_vci_rsp_cpt; |
---|
| 520 | sc_signal<bool> r_vci_rsp_ins_error; |
---|
| 521 | sc_signal<bool> r_vci_rsp_data_error; |
---|
[394] | 522 | GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM |
---|
| 523 | GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM |
---|
[331] | 524 | |
---|
| 525 | /////////////////////////////////// |
---|
| 526 | // CC_SEND FSM REGISTER |
---|
| 527 | /////////////////////////////////// |
---|
[394] | 528 | sc_signal<int> r_cc_send_fsm; // state register |
---|
| 529 | sc_signal<bool> r_cc_send_last_client; // 0 dcache / 1 icache |
---|
[331] | 530 | |
---|
| 531 | /////////////////////////////////// |
---|
| 532 | // CC_RECEIVE FSM REGISTER |
---|
| 533 | /////////////////////////////////// |
---|
[394] | 534 | sc_signal<int> r_cc_receive_fsm; // state register |
---|
| 535 | sc_signal<bool> r_cc_receive_data_ins; // request to : 0 dcache / 1 icache |
---|
[331] | 536 | |
---|
[394] | 537 | // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM |
---|
| 538 | sc_signal<size_t> r_cc_receive_word_idx; // word index |
---|
[331] | 539 | GenericFifo<uint32_t> r_cc_receive_updt_fifo_be; |
---|
| 540 | GenericFifo<uint32_t> r_cc_receive_updt_fifo_data; |
---|
| 541 | GenericFifo<bool> r_cc_receive_updt_fifo_eop; |
---|
| 542 | |
---|
| 543 | // communication between CC_RECEIVE FSM and ICACHE FSM |
---|
[394] | 544 | sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request |
---|
[549] | 545 | sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request |
---|
[394] | 546 | sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way |
---|
| 547 | sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set |
---|
[331] | 548 | sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index |
---|
[394] | 549 | sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address |
---|
[331] | 550 | |
---|
| 551 | // communication between CC_RECEIVE FSM and DCACHE FSM |
---|
[394] | 552 | sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request |
---|
[549] | 553 | sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request |
---|
[394] | 554 | sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way |
---|
| 555 | sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set |
---|
[331] | 556 | sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index |
---|
[394] | 557 | sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address |
---|
[331] | 558 | |
---|
[468] | 559 | /////////////////////////////////// |
---|
| 560 | // DSPIN CLACK INTERFACE REGISTER |
---|
| 561 | /////////////////////////////////// |
---|
| 562 | sc_signal<bool> r_dspin_clack_req; |
---|
| 563 | sc_signal<uint64_t> r_dspin_clack_flit; |
---|
| 564 | |
---|
[331] | 565 | ////////////////////////////////////////////////////////////////// |
---|
| 566 | // processor, write buffer, caches , TLBs |
---|
| 567 | ////////////////////////////////////////////////////////////////// |
---|
| 568 | |
---|
| 569 | iss_t r_iss; |
---|
| 570 | MultiWriteBuffer<paddr_t> r_wbuf; |
---|
| 571 | GenericCache<paddr_t> r_icache; |
---|
| 572 | GenericCache<paddr_t> r_dcache; |
---|
| 573 | GenericTlb<paddr_t> r_itlb; |
---|
| 574 | GenericTlb<paddr_t> r_dtlb; |
---|
| 575 | |
---|
| 576 | ////////////////////////////////////////////////////////////////// |
---|
| 577 | // llsc registration buffer |
---|
| 578 | ////////////////////////////////////////////////////////////////// |
---|
| 579 | |
---|
| 580 | sc_signal<paddr_t> r_dcache_llsc_paddr; |
---|
| 581 | sc_signal<uint32_t> r_dcache_llsc_key; |
---|
| 582 | sc_signal<uint32_t> r_dcache_llsc_count; |
---|
| 583 | sc_signal<bool> r_dcache_llsc_valid; |
---|
| 584 | |
---|
| 585 | //////////////////////////////// |
---|
| 586 | // Activity counters |
---|
| 587 | //////////////////////////////// |
---|
| 588 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
---|
| 589 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
---|
| 590 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
---|
| 591 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
---|
| 592 | |
---|
| 593 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
---|
| 594 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
---|
| 595 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
---|
| 596 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
---|
| 597 | |
---|
| 598 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
---|
| 599 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
| 600 | |
---|
| 601 | // Cache activity counters |
---|
| 602 | uint32_t m_cpt_data_read; // total number of read data |
---|
| 603 | uint32_t m_cpt_data_write; // total number of write data |
---|
| 604 | uint32_t m_cpt_data_miss; // number of read miss |
---|
| 605 | uint32_t m_cpt_ins_miss; // number of instruction miss |
---|
| 606 | uint32_t m_cpt_unc_read; // number of read uncached |
---|
| 607 | uint32_t m_cpt_write_cached; // number of cached write |
---|
| 608 | uint32_t m_cpt_ins_read; // number of instruction read |
---|
| 609 | uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss |
---|
| 610 | |
---|
| 611 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
---|
| 612 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
---|
| 613 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
---|
| 614 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
---|
| 615 | |
---|
| 616 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
---|
| 617 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
---|
| 618 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
---|
| 619 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
---|
| 620 | uint32_t m_cpt_icache_unc_transaction; |
---|
| 621 | |
---|
| 622 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
---|
| 623 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
---|
| 624 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
---|
| 625 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
---|
| 626 | uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions |
---|
| 627 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
---|
| 628 | |
---|
| 629 | // TLB activity counters |
---|
| 630 | uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read |
---|
| 631 | uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss |
---|
| 632 | uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update |
---|
| 633 | uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line |
---|
| 634 | uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache |
---|
| 635 | |
---|
| 636 | uint32_t m_cpt_data_tlb_read; // number of data tlb read |
---|
| 637 | uint32_t m_cpt_data_tlb_miss; // number of data tlb miss |
---|
| 638 | uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update |
---|
| 639 | uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty |
---|
| 640 | uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache |
---|
| 641 | uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line |
---|
| 642 | uint32_t m_cpt_tlb_occup_dcache; |
---|
| 643 | |
---|
| 644 | uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss |
---|
| 645 | uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss |
---|
| 646 | uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc |
---|
| 647 | uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc |
---|
| 648 | uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty |
---|
| 649 | uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache |
---|
| 650 | uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache |
---|
| 651 | |
---|
| 652 | uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions |
---|
| 653 | uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions |
---|
| 654 | uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions |
---|
| 655 | uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions |
---|
| 656 | uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions |
---|
| 657 | uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions |
---|
| 658 | uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions |
---|
| 659 | uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions |
---|
| 660 | |
---|
| 661 | uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions |
---|
| 662 | uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions |
---|
| 663 | uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions |
---|
| 664 | uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions |
---|
| 665 | uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions |
---|
| 666 | uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions |
---|
| 667 | uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions |
---|
| 668 | uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions |
---|
| 669 | |
---|
| 670 | // coherence activity counters |
---|
| 671 | uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands |
---|
| 672 | uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands |
---|
| 673 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands |
---|
| 674 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands |
---|
| 675 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands |
---|
| 676 | |
---|
| 677 | uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets |
---|
| 678 | uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets |
---|
| 679 | uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets |
---|
| 680 | uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets |
---|
| 681 | |
---|
| 682 | uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets |
---|
| 683 | uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets |
---|
| 684 | |
---|
| 685 | uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions |
---|
| 686 | uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions |
---|
| 687 | uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions |
---|
| 688 | uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions |
---|
| 689 | |
---|
| 690 | uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate |
---|
| 691 | uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate |
---|
| 692 | |
---|
| 693 | uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate |
---|
| 694 | uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate |
---|
| 695 | |
---|
| 696 | // FSM activity counters |
---|
| 697 | uint32_t m_cpt_fsm_icache [64]; |
---|
| 698 | uint32_t m_cpt_fsm_dcache [64]; |
---|
| 699 | uint32_t m_cpt_fsm_cmd [64]; |
---|
| 700 | uint32_t m_cpt_fsm_rsp [64]; |
---|
| 701 | uint32_t m_cpt_fsm_cc_receive [64]; |
---|
| 702 | uint32_t m_cpt_fsm_cc_send [64]; |
---|
| 703 | |
---|
| 704 | uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen |
---|
[432] | 705 | bool m_monitor_ok; // used to debug cache output |
---|
| 706 | uint32_t m_monitor_base; |
---|
| 707 | uint32_t m_monitor_length; |
---|
[331] | 708 | |
---|
| 709 | protected: |
---|
| 710 | SC_HAS_PROCESS(VciCcVCacheWrapper); |
---|
| 711 | |
---|
| 712 | public: |
---|
| 713 | VciCcVCacheWrapper( |
---|
[346] | 714 | sc_module_name name, |
---|
| 715 | const int proc_id, |
---|
| 716 | const soclib::common::MappingTable &mtd, |
---|
| 717 | const soclib::common::IntTab &srcid, |
---|
| 718 | const size_t cc_global_id, |
---|
| 719 | const size_t itlb_ways, |
---|
| 720 | const size_t itlb_sets, |
---|
| 721 | const size_t dtlb_ways, |
---|
| 722 | const size_t dtlb_sets, |
---|
| 723 | const size_t icache_ways, |
---|
| 724 | const size_t icache_sets, |
---|
| 725 | const size_t icache_words, |
---|
| 726 | const size_t dcache_ways, |
---|
| 727 | const size_t dcache_sets, |
---|
| 728 | const size_t dcache_words, |
---|
| 729 | const size_t wbuf_nlines, |
---|
| 730 | const size_t wbuf_nwords, |
---|
| 731 | const size_t x_width, |
---|
| 732 | const size_t y_width, |
---|
| 733 | const uint32_t max_frozen_cycles, |
---|
| 734 | const uint32_t debug_start_cycle, |
---|
| 735 | const bool debug_ok ); |
---|
[331] | 736 | |
---|
| 737 | ~VciCcVCacheWrapper(); |
---|
| 738 | |
---|
| 739 | void print_cpi(); |
---|
| 740 | void print_stats(); |
---|
| 741 | void clear_stats(); |
---|
| 742 | void print_trace(size_t mode = 0); |
---|
| 743 | void cache_monitor(paddr_t addr); |
---|
[423] | 744 | void start_monitor(paddr_t,paddr_t); |
---|
| 745 | void stop_monitor(); |
---|
[394] | 746 | inline void iss_set_debug_mask(uint v) |
---|
| 747 | { |
---|
| 748 | r_iss.set_debug_mask(v); |
---|
[331] | 749 | } |
---|
| 750 | |
---|
| 751 | private: |
---|
| 752 | void transition(); |
---|
| 753 | void genMoore(); |
---|
| 754 | |
---|
| 755 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
---|
| 756 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
---|
| 757 | }; |
---|
| 758 | |
---|
| 759 | }} |
---|
| 760 | |
---|
| 761 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */ |
---|
| 762 | |
---|
| 763 | // Local Variables: |
---|
| 764 | // tab-width: 4 |
---|
| 765 | // c-basic-offset: 4 |
---|
| 766 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 767 | // indent-tabs-mode: nil |
---|
| 768 | // End: |
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| 769 | |
---|
| 770 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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