1 | /* -*- c++ -*- |
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2 | * |
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3 | * File : vci_cc_vcache_wrapper.h |
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4 | * Copyright (c) UPMC, Lip6, SoC |
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5 | * Authors : Alain GREINER, Yang GAO |
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6 | * Date : 27/11/2011 |
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7 | * |
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8 | * SOCLIB_LGPL_HEADER_BEGIN |
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9 | * |
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10 | * This file is part of SoCLib, GNU LGPLv2.1. |
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11 | * |
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12 | * SoCLib is free software; you can redistribute it and/or modify it |
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13 | * under the terms of the GNU Lesser General Public License as published |
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14 | * by the Free Software Foundation; version 2.1 of the License. |
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15 | * |
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16 | * SoCLib is distributed in the hope that it will be useful, but |
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17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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19 | * Lesser General Public License for more details. |
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20 | * |
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21 | * You should have received a copy of the GNU Lesser General Public |
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22 | * License along with SoCLib; if not, write to the Free Software |
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23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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24 | * 02110-1301 USA |
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25 | * |
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26 | * SOCLIB_LGPL_HEADER_END |
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27 | * |
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28 | * Maintainers: cesar.fuguet-tortolero@lip6.fr |
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29 | * alexandre.joannou@lip6.fr |
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30 | */ |
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31 | |
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32 | #ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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33 | #define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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34 | |
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35 | #include <inttypes.h> |
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36 | #include <systemc> |
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37 | #include "caba_base_module.h" |
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38 | #include "multi_write_buffer.h" |
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39 | #include "generic_fifo.h" |
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40 | #include "generic_tlb.h" |
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41 | #include "generic_cache.h" |
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42 | #include "vci_initiator.h" |
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43 | #include "dspin_interface.h" |
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44 | #include "dspin_dhccp_param.h" |
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45 | #include "mapping_table.h" |
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46 | #include "static_assert.h" |
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47 | #include "iss2.h" |
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48 | |
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49 | #define LLSC_TIMEOUT 10000 |
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50 | |
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51 | namespace soclib { |
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52 | namespace caba { |
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53 | |
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54 | using namespace sc_core; |
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55 | |
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56 | //////////////////////////////////////////// |
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57 | template<typename vci_param, typename iss_t> |
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58 | class VciCcVCacheWrapper |
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59 | //////////////////////////////////////////// |
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60 | : public soclib::caba::BaseModule |
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61 | { |
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62 | typedef uint32_t vaddr_t; |
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63 | typedef uint32_t tag_t; |
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64 | typedef uint32_t type_t; |
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65 | typedef typename iss_t::DataOperationType data_op_t; |
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66 | |
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67 | typedef typename vci_param::addr_t paddr_t; |
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68 | typedef typename vci_param::data_t vci_data_t; |
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69 | typedef typename vci_param::be_t vci_be_t; |
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70 | typedef typename vci_param::srcid_t vci_srcid_t; |
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71 | typedef typename vci_param::trdid_t vci_trdid_t; |
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72 | typedef typename vci_param::pktid_t vci_pktid_t; |
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73 | typedef typename vci_param::plen_t vci_plen_t; |
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74 | |
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75 | enum icache_fsm_state_e { |
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76 | ICACHE_IDLE, |
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77 | // handling XTN processor requests |
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78 | ICACHE_XTN_TLB_FLUSH, |
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79 | ICACHE_XTN_CACHE_FLUSH, |
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80 | ICACHE_XTN_CACHE_FLUSH_GO, |
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81 | ICACHE_XTN_TLB_INVAL, |
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82 | ICACHE_XTN_CACHE_INVAL_VA, |
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83 | ICACHE_XTN_CACHE_INVAL_PA, |
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84 | ICACHE_XTN_CACHE_INVAL_GO, |
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85 | // handling tlb miss |
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86 | ICACHE_TLB_WAIT, |
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87 | // handling cache miss |
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88 | ICACHE_MISS_SELECT, |
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89 | ICACHE_MISS_CLEAN, |
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90 | ICACHE_MISS_WAIT, |
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91 | ICACHE_MISS_DATA_UPDT, |
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92 | ICACHE_MISS_DIR_UPDT, |
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93 | // handling unc read |
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94 | ICACHE_UNC_WAIT, |
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95 | // handling coherence requests |
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96 | ICACHE_CC_CHECK, |
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97 | ICACHE_CC_INVAL, |
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98 | ICACHE_CC_UPDT, |
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99 | ICACHE_CC_BROADCAST, |
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100 | ICACHE_CC_SEND_WAIT, |
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101 | }; |
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102 | |
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103 | enum dcache_fsm_state_e { |
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104 | DCACHE_IDLE, |
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105 | // handling itlb & dtlb miss |
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106 | DCACHE_TLB_MISS, |
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107 | DCACHE_TLB_PTE1_GET, |
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108 | DCACHE_TLB_PTE1_SELECT, |
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109 | DCACHE_TLB_PTE1_UPDT, |
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110 | DCACHE_TLB_PTE2_GET, |
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111 | DCACHE_TLB_PTE2_SELECT, |
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112 | DCACHE_TLB_PTE2_UPDT, |
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113 | DCACHE_TLB_LR_UPDT, |
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114 | DCACHE_TLB_LR_WAIT, |
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115 | DCACHE_TLB_RETURN, |
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116 | // handling processor XTN requests |
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117 | DCACHE_XTN_SWITCH, |
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118 | DCACHE_XTN_SYNC, |
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119 | DCACHE_XTN_IC_INVAL_VA, |
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120 | DCACHE_XTN_IC_FLUSH, |
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121 | DCACHE_XTN_IC_INVAL_PA, |
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122 | DCACHE_XTN_IT_INVAL, |
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123 | DCACHE_XTN_DC_FLUSH, |
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124 | DCACHE_XTN_DC_FLUSH_GO, |
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125 | DCACHE_XTN_DC_INVAL_VA, |
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126 | DCACHE_XTN_DC_INVAL_PA, |
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127 | DCACHE_XTN_DC_INVAL_END, |
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128 | DCACHE_XTN_DC_INVAL_GO, |
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129 | DCACHE_XTN_DT_INVAL, |
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130 | //handling dirty bit update |
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131 | DCACHE_DIRTY_GET_PTE, |
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132 | DCACHE_DIRTY_WAIT, |
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133 | // handling processor miss requests |
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134 | DCACHE_MISS_SELECT, |
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135 | DCACHE_MISS_CLEAN, |
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136 | DCACHE_MISS_WAIT, |
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137 | DCACHE_MISS_DATA_UPDT, |
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138 | DCACHE_MISS_DIR_UPDT, |
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139 | // handling processor unc, ll and sc requests |
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140 | DCACHE_UNC_WAIT, |
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141 | DCACHE_LL_WAIT, |
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142 | DCACHE_SC_WAIT, |
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143 | // handling coherence requests |
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144 | DCACHE_CC_CHECK, |
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145 | DCACHE_CC_INVAL, |
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146 | DCACHE_CC_UPDT, |
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147 | DCACHE_CC_BROADCAST, |
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148 | DCACHE_CC_SEND_WAIT, |
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149 | // handling TLB inval (after a coherence or XTN request) |
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150 | DCACHE_INVAL_TLB_SCAN, |
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151 | }; |
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152 | |
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153 | enum cmd_fsm_state_e { |
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154 | CMD_IDLE, |
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155 | CMD_INS_MISS, |
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156 | CMD_INS_UNC, |
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157 | CMD_DATA_MISS, |
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158 | CMD_DATA_UNC, |
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159 | CMD_DATA_WRITE, |
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160 | CMD_DATA_LL, |
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161 | CMD_DATA_SC, |
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162 | CMD_DATA_CAS, |
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163 | }; |
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164 | |
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165 | enum rsp_fsm_state_e { |
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166 | RSP_IDLE, |
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167 | RSP_INS_MISS, |
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168 | RSP_INS_UNC, |
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169 | RSP_DATA_MISS, |
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170 | RSP_DATA_UNC, |
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171 | RSP_DATA_LL, |
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172 | RSP_DATA_WRITE, |
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173 | }; |
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174 | |
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175 | enum cc_receive_fsm_state_e { |
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176 | CC_RECEIVE_IDLE, |
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177 | CC_RECEIVE_CLACK, |
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178 | CC_RECEIVE_BRDCAST_HEADER, |
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179 | CC_RECEIVE_BRDCAST_NLINE, |
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180 | CC_RECEIVE_INVAL_HEADER, |
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181 | CC_RECEIVE_INVAL_NLINE, |
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182 | CC_RECEIVE_UPDT_HEADER, |
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183 | CC_RECEIVE_UPDT_NLINE, |
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184 | CC_RECEIVE_UPDT_DATA, |
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185 | }; |
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186 | |
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187 | enum cc_send_fsm_state_e { |
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188 | CC_SEND_IDLE, |
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189 | CC_SEND_CLEANUP_1, |
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190 | CC_SEND_CLEANUP_2, |
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191 | CC_SEND_MULTI_ACK, |
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192 | }; |
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193 | |
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194 | /* transaction type, pktid field */ |
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195 | enum transaction_type_e |
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196 | { |
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197 | // b3 unused |
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198 | // b2 READ / NOT READ |
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199 | // if READ |
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200 | // b1 DATA / INS |
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201 | // b0 UNC / MISS |
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202 | // else |
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203 | // b1 accÚs table llsc type SW / other |
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204 | // b2 WRITE/CAS/LL/SC |
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205 | TYPE_READ_DATA_UNC = 0x0, |
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206 | TYPE_READ_DATA_MISS = 0x1, |
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207 | TYPE_READ_INS_UNC = 0x2, |
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208 | TYPE_READ_INS_MISS = 0x3, |
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209 | TYPE_WRITE = 0x4, |
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210 | TYPE_CAS = 0x5, |
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211 | TYPE_LL = 0x6, |
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212 | TYPE_SC = 0x7 |
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213 | }; |
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214 | |
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215 | /* SC return values */ |
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216 | enum sc_status_type_e |
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217 | { |
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218 | SC_SUCCESS = 0x00000000, |
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219 | SC_FAIL = 0x00000001 |
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220 | }; |
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221 | |
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222 | // cc_send_type |
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223 | typedef enum { |
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224 | CC_TYPE_CLEANUP, |
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225 | CC_TYPE_MULTI_ACK, |
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226 | } cc_send_t; |
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227 | |
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228 | // cc_receive_type |
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229 | typedef enum { |
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230 | CC_TYPE_CLACK, |
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231 | CC_TYPE_BRDCAST, |
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232 | CC_TYPE_INVAL, |
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233 | CC_TYPE_UPDT, |
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234 | } cc_receive_t; |
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235 | |
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236 | // TLB Mode : ITLB / DTLB / ICACHE / DCACHE |
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237 | enum { |
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238 | INS_TLB_MASK = 0x8, |
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239 | DATA_TLB_MASK = 0x4, |
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240 | INS_CACHE_MASK = 0x2, |
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241 | DATA_CACHE_MASK = 0x1, |
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242 | }; |
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243 | |
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244 | // Error Type |
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245 | enum mmu_error_type_e |
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246 | { |
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247 | MMU_NONE = 0x0000, // None |
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248 | MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 |
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249 | MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 |
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250 | MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode |
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251 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page |
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252 | MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write & undefined external access |
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253 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write & Bus Error accessing PT1 |
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254 | MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 |
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255 | MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access |
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256 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 |
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257 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 |
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258 | MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode |
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259 | MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page |
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260 | MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access |
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261 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 |
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262 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 |
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263 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access |
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264 | }; |
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265 | |
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266 | // miss types for data cache |
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267 | enum dcache_miss_type_e |
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268 | { |
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269 | PTE1_MISS, |
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270 | PTE2_MISS, |
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271 | PROC_MISS, |
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272 | }; |
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273 | |
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274 | enum transaction_type_d_e |
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275 | { |
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276 | // b0 : 1 if cached |
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277 | // b1 : 1 if instruction |
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278 | TYPE_DATA_UNC = 0x0, |
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279 | TYPE_DATA_MISS = 0x1, |
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280 | TYPE_INS_UNC = 0x2, |
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281 | TYPE_INS_MISS = 0x3, |
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282 | }; |
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283 | |
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284 | public: |
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285 | sc_in<bool> p_clk; |
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286 | sc_in<bool> p_resetn; |
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287 | sc_in<bool> p_irq[iss_t::n_irq]; |
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288 | soclib::caba::VciInitiator<vci_param> p_vci; |
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289 | soclib::caba::DspinInput <40> p_dspin_in; |
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290 | soclib::caba::DspinOutput<33> p_dspin_out; |
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291 | |
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292 | private: |
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293 | |
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294 | // STRUCTURAL PARAMETERS |
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295 | soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; |
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296 | |
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297 | const vci_srcid_t m_srcid; |
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298 | const size_t m_cc_global_id; |
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299 | const size_t m_nline_width; |
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300 | const size_t m_itlb_ways; |
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301 | const size_t m_itlb_sets; |
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302 | const size_t m_dtlb_ways; |
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303 | const size_t m_dtlb_sets; |
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304 | const size_t m_icache_ways; |
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305 | const size_t m_icache_sets; |
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306 | const paddr_t m_icache_yzmask; |
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307 | const size_t m_icache_words; |
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308 | const size_t m_dcache_ways; |
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309 | const size_t m_dcache_sets; |
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310 | const paddr_t m_dcache_yzmask; |
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311 | const size_t m_dcache_words; |
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312 | const size_t m_x_width; |
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313 | const size_t m_y_width; |
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314 | const size_t m_proc_id; |
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315 | const uint32_t m_max_frozen_cycles; |
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316 | const size_t m_paddr_nbits; |
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317 | uint32_t m_debug_start_cycle; |
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318 | bool m_debug_ok; |
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319 | |
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320 | //////////////////////////////////////// |
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321 | // Communication with processor ISS |
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322 | //////////////////////////////////////// |
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323 | typename iss_t::InstructionRequest m_ireq; |
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324 | typename iss_t::InstructionResponse m_irsp; |
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325 | typename iss_t::DataRequest m_dreq; |
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326 | typename iss_t::DataResponse m_drsp; |
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327 | |
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328 | ///////////////////////////////////////////// |
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329 | // debug variables (for each FSM) |
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330 | ///////////////////////////////////////////// |
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331 | bool m_debug_previous_hit; |
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332 | bool m_idebug_previous_hit; |
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333 | bool m_debug_dcache_fsm; |
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334 | bool m_debug_icache_fsm; |
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335 | bool m_debug_inval_itlb_fsm; |
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336 | bool m_debug_inval_dtlb_fsm; |
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337 | |
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338 | /////////////////////////////// |
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339 | // Software visible REGISTERS |
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340 | /////////////////////////////// |
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341 | sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register |
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342 | sc_signal<uint32_t> r_mmu_mode; // mmu mode register |
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343 | sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low |
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344 | sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight |
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345 | sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address |
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346 | sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address |
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347 | sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type |
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348 | sc_signal<uint32_t> r_mmu_detr; // mmu data error type |
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349 | uint32_t r_mmu_params; // read-only |
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350 | uint32_t r_mmu_release; // read_only |
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351 | |
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352 | |
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353 | ////////////////////////////// |
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354 | // ICACHE FSM REGISTERS |
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355 | ////////////////////////////// |
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356 | sc_signal<int> r_icache_fsm; // state register |
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357 | sc_signal<int> r_icache_fsm_save; // return state for coherence op |
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358 | sc_signal<paddr_t> r_icache_vci_paddr; // physical address |
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359 | sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor |
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360 | |
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361 | // icache miss handling |
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362 | sc_signal<size_t> r_icache_miss_way; // selected way for cache update |
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363 | sc_signal<size_t> r_icache_miss_set; // selected set for cache update |
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364 | sc_signal<size_t> r_icache_miss_word; // word index ( cache update) |
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365 | sc_signal<bool> r_icache_miss_inval; // coherence request matching a miss |
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366 | sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge |
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367 | |
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368 | // coherence request handling |
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369 | sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval |
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370 | sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval |
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371 | sc_signal<size_t> r_icache_cc_word; // word counter for cc update |
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372 | sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing |
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373 | |
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374 | // icache flush handling |
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375 | sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush |
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376 | |
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377 | // communication between ICACHE FSM and VCI_CMD FSM |
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378 | sc_signal<bool> r_icache_miss_req; // cached read miss |
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379 | sc_signal<bool> r_icache_unc_req; // uncached read miss |
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380 | |
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381 | // communication between ICACHE FSM and DCACHE FSM |
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382 | sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache) |
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383 | sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error |
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384 | |
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385 | // communication between ICACHE FSM and CC_SEND FSM |
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386 | sc_signal<bool> r_icache_cc_send_req; // ICACHE cc_send request |
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387 | sc_signal<cc_send_t> r_icache_cc_send_type; // ICACHE cc_send request type |
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388 | sc_signal<paddr_t> r_icache_cc_send_nline; // ICACHE cc_send nline |
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389 | sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way |
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390 | sc_signal<size_t> r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index |
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391 | |
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392 | /////////////////////////////// |
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393 | // DCACHE FSM REGISTERS |
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394 | /////////////////////////////// |
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395 | sc_signal<int> r_dcache_fsm; // state register |
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396 | sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence op |
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397 | sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op |
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398 | // registers written in P0 stage (used in P1 stage) |
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399 | sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage |
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400 | sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage |
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401 | sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) |
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402 | sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) |
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403 | sc_signal<vci_be_t> r_dcache_save_be; // byte enable (from proc) |
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404 | sc_signal<paddr_t> r_dcache_save_paddr; // physical address |
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405 | sc_signal<bool> r_dcache_save_cacheable; // address cacheable |
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406 | sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) |
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407 | sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) |
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408 | sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache) |
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409 | // registers used by the Dirty bit sub-fsm |
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410 | sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address |
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411 | sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache |
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412 | sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache |
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413 | |
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414 | // communication between DCACHE FSM and VCI_CMD FSM |
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415 | sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command |
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416 | sc_signal<bool> r_dcache_vci_miss_req; // read miss request |
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417 | sc_signal<bool> r_dcache_vci_unc_req; // uncacheable read request |
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418 | sc_signal<bool> r_dcache_vci_unc_be; // uncacheable read byte enable |
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419 | sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS |
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420 | sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS |
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421 | sc_signal<uint32_t> r_dcache_vci_cas_new; // new data value for a CAS |
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422 | sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL |
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423 | sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC |
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424 | sc_signal<vci_data_t> r_dcache_vci_sc_data; // SC data (command) |
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425 | |
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426 | // register used for XTN inval |
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427 | sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) |
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428 | sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) |
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429 | |
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430 | // write buffer state extension |
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431 | sc_signal<bool> r_dcache_pending_unc_write; // pending uncacheable write in WBUF |
---|
432 | |
---|
433 | // handling dcache miss |
---|
434 | sc_signal<int> r_dcache_miss_type; // depending on the requester |
---|
435 | sc_signal<size_t> r_dcache_miss_word; // word index for cache update |
---|
436 | sc_signal<size_t> r_dcache_miss_way; // selected way for cache update |
---|
437 | sc_signal<size_t> r_dcache_miss_set; // selected set for cache update |
---|
438 | sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss |
---|
439 | sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge |
---|
440 | |
---|
441 | // handling coherence requests |
---|
442 | sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval |
---|
443 | sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval |
---|
444 | sc_signal<size_t> r_dcache_cc_word; // word counter for cc update |
---|
445 | sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing |
---|
446 | |
---|
447 | // dcache flush handling |
---|
448 | sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush |
---|
449 | |
---|
450 | // ll response handling |
---|
451 | sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp |
---|
452 | |
---|
453 | // used by the TLB miss sub-fsm |
---|
454 | sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss |
---|
455 | sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) |
---|
456 | sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte |
---|
457 | sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 |
---|
458 | sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 |
---|
459 | sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache |
---|
460 | sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache |
---|
461 | sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache |
---|
462 | sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb |
---|
463 | sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb |
---|
464 | |
---|
465 | // ITLB and DTLB invalidation |
---|
466 | sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index |
---|
467 | sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter |
---|
468 | |
---|
469 | // communication between DCACHE FSM and ICACHE FSM |
---|
470 | sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor) |
---|
471 | sc_signal<int> r_dcache_xtn_opcode; // xtn request type |
---|
472 | |
---|
473 | // communication between DCACHE FSM and CC_SEND FSM |
---|
474 | sc_signal<bool> r_dcache_cc_send_req; // DCACHE cc_send request |
---|
475 | sc_signal<cc_send_t> r_dcache_cc_send_type; // DCACHE cc_send request type |
---|
476 | sc_signal<paddr_t> r_dcache_cc_send_nline; // DCACHE cc_send nline |
---|
477 | sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way |
---|
478 | sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index |
---|
479 | |
---|
480 | // dcache directory extension |
---|
481 | bool *r_dcache_in_tlb; // copy exist in dtlb or itlb |
---|
482 | bool *r_dcache_contains_ptd; // cache line contains a PTD |
---|
483 | |
---|
484 | /////////////////////////////////// |
---|
485 | // VCI_CMD FSM REGISTERS |
---|
486 | /////////////////////////////////// |
---|
487 | sc_signal<int> r_vci_cmd_fsm; |
---|
488 | sc_signal<size_t> r_vci_cmd_min; // used for write bursts |
---|
489 | sc_signal<size_t> r_vci_cmd_max; // used for write bursts |
---|
490 | sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts |
---|
491 | sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss |
---|
492 | |
---|
493 | /////////////////////////////////// |
---|
494 | // VCI_RSP FSM REGISTERS |
---|
495 | /////////////////////////////////// |
---|
496 | sc_signal<int> r_vci_rsp_fsm; |
---|
497 | sc_signal<size_t> r_vci_rsp_cpt; |
---|
498 | sc_signal<bool> r_vci_rsp_ins_error; |
---|
499 | sc_signal<bool> r_vci_rsp_data_error; |
---|
500 | GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM |
---|
501 | GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM |
---|
502 | |
---|
503 | /////////////////////////////////// |
---|
504 | // CC_SEND FSM REGISTER |
---|
505 | /////////////////////////////////// |
---|
506 | sc_signal<int> r_cc_send_fsm; // state register |
---|
507 | sc_signal<bool> r_cc_send_last_client; // round robin flip-flop : 0 dcache / 1 icache |
---|
508 | |
---|
509 | /////////////////////////////////// |
---|
510 | // CC_RECEIVE FSM REGISTER |
---|
511 | /////////////////////////////////// |
---|
512 | sc_signal<int> r_cc_receive_fsm; // state register |
---|
513 | sc_signal<bool> r_cc_receive_data_ins; // request concerning : 0 dcache / 1 icache |
---|
514 | |
---|
515 | // communication cc updt FIFO between CC_RECEIVE FSM and ICACHE/DCACHE FSM |
---|
516 | sc_signal<size_t> r_cc_receive_word_idx; // word index |
---|
517 | GenericFifo<uint32_t> r_cc_receive_updt_fifo_be; |
---|
518 | GenericFifo<uint32_t> r_cc_receive_updt_fifo_data; |
---|
519 | GenericFifo<bool> r_cc_receive_updt_fifo_eop; |
---|
520 | |
---|
521 | // communication between CC_RECEIVE FSM and ICACHE FSM |
---|
522 | sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request |
---|
523 | sc_signal<cc_receive_t> r_cc_receive_icache_type; // cc_receive type of coherence request |
---|
524 | sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way |
---|
525 | sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set |
---|
526 | sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index |
---|
527 | sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address |
---|
528 | |
---|
529 | // communication between CC_RECEIVE FSM and DCACHE FSM |
---|
530 | sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request |
---|
531 | sc_signal<cc_receive_t> r_cc_receive_dcache_type; // cc_receive type of coherence request |
---|
532 | sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way |
---|
533 | sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set |
---|
534 | sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index |
---|
535 | sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address |
---|
536 | |
---|
537 | ////////////////////////////////////////////////////////////////// |
---|
538 | // processor, write buffer, caches , TLBs |
---|
539 | ////////////////////////////////////////////////////////////////// |
---|
540 | |
---|
541 | iss_t r_iss; |
---|
542 | MultiWriteBuffer<paddr_t> r_wbuf; |
---|
543 | GenericCache<paddr_t> r_icache; |
---|
544 | GenericCache<paddr_t> r_dcache; |
---|
545 | GenericTlb<paddr_t> r_itlb; |
---|
546 | GenericTlb<paddr_t> r_dtlb; |
---|
547 | |
---|
548 | ////////////////////////////////////////////////////////////////// |
---|
549 | // llsc registration buffer |
---|
550 | ////////////////////////////////////////////////////////////////// |
---|
551 | |
---|
552 | sc_signal<paddr_t> r_dcache_llsc_paddr; |
---|
553 | sc_signal<uint32_t> r_dcache_llsc_key; |
---|
554 | sc_signal<uint32_t> r_dcache_llsc_count; |
---|
555 | sc_signal<bool> r_dcache_llsc_valid; |
---|
556 | |
---|
557 | //////////////////////////////// |
---|
558 | // Activity counters |
---|
559 | //////////////////////////////// |
---|
560 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
---|
561 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
---|
562 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
---|
563 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
---|
564 | |
---|
565 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
---|
566 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
---|
567 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
---|
568 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
---|
569 | |
---|
570 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
---|
571 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
572 | |
---|
573 | // Cache activity counters |
---|
574 | uint32_t m_cpt_data_read; // total number of read data |
---|
575 | uint32_t m_cpt_data_write; // total number of write data |
---|
576 | uint32_t m_cpt_data_miss; // number of read miss |
---|
577 | uint32_t m_cpt_ins_miss; // number of instruction miss |
---|
578 | uint32_t m_cpt_unc_read; // number of read uncached |
---|
579 | uint32_t m_cpt_write_cached; // number of cached write |
---|
580 | uint32_t m_cpt_ins_read; // number of instruction read |
---|
581 | uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss |
---|
582 | |
---|
583 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
---|
584 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
---|
585 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
---|
586 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
---|
587 | |
---|
588 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
---|
589 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
---|
590 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
---|
591 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
---|
592 | uint32_t m_cpt_icache_unc_transaction; |
---|
593 | |
---|
594 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
---|
595 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
---|
596 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
---|
597 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
---|
598 | uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions |
---|
599 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
---|
600 | |
---|
601 | // TLB activity counters |
---|
602 | uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read |
---|
603 | uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss |
---|
604 | uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update |
---|
605 | uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line |
---|
606 | uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache |
---|
607 | |
---|
608 | uint32_t m_cpt_data_tlb_read; // number of data tlb read |
---|
609 | uint32_t m_cpt_data_tlb_miss; // number of data tlb miss |
---|
610 | uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update |
---|
611 | uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty |
---|
612 | uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache |
---|
613 | uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line |
---|
614 | uint32_t m_cpt_tlb_occup_dcache; |
---|
615 | |
---|
616 | uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss |
---|
617 | uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss |
---|
618 | uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc |
---|
619 | uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc |
---|
620 | uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty |
---|
621 | uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache |
---|
622 | uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache |
---|
623 | |
---|
624 | uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions |
---|
625 | uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions |
---|
626 | uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions |
---|
627 | uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions |
---|
628 | uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions |
---|
629 | uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions |
---|
630 | uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions |
---|
631 | uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions |
---|
632 | |
---|
633 | uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions |
---|
634 | uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions |
---|
635 | uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions |
---|
636 | uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions |
---|
637 | uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions |
---|
638 | uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions |
---|
639 | uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions |
---|
640 | uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions |
---|
641 | |
---|
642 | // coherence activity counters |
---|
643 | uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands |
---|
644 | uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands |
---|
645 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands |
---|
646 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands |
---|
647 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands |
---|
648 | |
---|
649 | uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets |
---|
650 | uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets |
---|
651 | uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets |
---|
652 | uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets |
---|
653 | |
---|
654 | uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets |
---|
655 | uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets |
---|
656 | |
---|
657 | uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions |
---|
658 | uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions |
---|
659 | uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions |
---|
660 | uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions |
---|
661 | |
---|
662 | uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate |
---|
663 | uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate |
---|
664 | |
---|
665 | uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate |
---|
666 | uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate |
---|
667 | |
---|
668 | // FSM activity counters |
---|
669 | uint32_t m_cpt_fsm_icache [64]; |
---|
670 | uint32_t m_cpt_fsm_dcache [64]; |
---|
671 | uint32_t m_cpt_fsm_cmd [64]; |
---|
672 | uint32_t m_cpt_fsm_rsp [64]; |
---|
673 | uint32_t m_cpt_fsm_cc_receive [64]; |
---|
674 | uint32_t m_cpt_fsm_cc_send [64]; |
---|
675 | |
---|
676 | uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen |
---|
677 | |
---|
678 | protected: |
---|
679 | SC_HAS_PROCESS(VciCcVCacheWrapper); |
---|
680 | |
---|
681 | public: |
---|
682 | VciCcVCacheWrapper( |
---|
683 | sc_module_name name, |
---|
684 | const int proc_id, |
---|
685 | const soclib::common::MappingTable &mtd, |
---|
686 | const soclib::common::IntTab &srcid, |
---|
687 | const size_t cc_global_id, |
---|
688 | const size_t itlb_ways, |
---|
689 | const size_t itlb_sets, |
---|
690 | const size_t dtlb_ways, |
---|
691 | const size_t dtlb_sets, |
---|
692 | const size_t icache_ways, |
---|
693 | const size_t icache_sets, |
---|
694 | const size_t icache_words, |
---|
695 | const size_t dcache_ways, |
---|
696 | const size_t dcache_sets, |
---|
697 | const size_t dcache_words, |
---|
698 | const size_t wbuf_nlines, |
---|
699 | const size_t wbuf_nwords, |
---|
700 | const size_t x_width, |
---|
701 | const size_t y_width, |
---|
702 | const uint32_t max_frozen_cycles, |
---|
703 | const uint32_t debug_start_cycle, |
---|
704 | const bool debug_ok ); |
---|
705 | |
---|
706 | ~VciCcVCacheWrapper(); |
---|
707 | |
---|
708 | void print_cpi(); |
---|
709 | void print_stats(); |
---|
710 | void clear_stats(); |
---|
711 | void print_trace(size_t mode = 0); |
---|
712 | void cache_monitor(paddr_t addr); |
---|
713 | inline void iss_set_debug_mask(uint v) { |
---|
714 | r_iss.set_debug_mask(v); |
---|
715 | } |
---|
716 | |
---|
717 | private: |
---|
718 | void transition(); |
---|
719 | void genMoore(); |
---|
720 | |
---|
721 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
---|
722 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
---|
723 | }; |
---|
724 | |
---|
725 | }} |
---|
726 | |
---|
727 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */ |
---|
728 | |
---|
729 | // Local Variables: |
---|
730 | // tab-width: 4 |
---|
731 | // c-basic-offset: 4 |
---|
732 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
733 | // indent-tabs-mode: nil |
---|
734 | // End: |
---|
735 | |
---|
736 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|