Context Navigation

source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 1057

Last change on this file since 1057 was 1047, checked in by alain, 8 years ago
Improve the debug features regarding frozen cycles.
File size: 244.6 KB

Rev	Line
[331]	1	/* -- c++ --
	2	* File : vci_cc_vcache_wrapper.cpp
	3	* Copyright (c) UPMC, Lip6, SoC
	4	* Authors : Alain GREINER, Yang GAO
	5	*
	6	* SOCLIB_LGPL_HEADER_BEGIN
	7	*
	8	* This file is part of SoCLib, GNU LGPLv2.1.
	9	*
	10	* SoCLib is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU Lesser General Public License as published
	12	* by the Free Software Foundation; version 2.1 of the License.
	13	*
	14	* SoCLib is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* Lesser General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU Lesser General Public
	20	* License along with SoCLib; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	22	* 02110-1301 USA
	23	*
	24	* SOCLIB_LGPL_HEADER_END
	25	*
	26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
	27	* alexandre.joannou@lip6.fr
	28	*/
	29
	30	#include <cassert>
[752]	31	#include <signal.h>
	32
[331]	33	#include "arithmetics.h"
[351]	34	#include "../include/vci_cc_vcache_wrapper.h"
[331]	35
[789]	36	#define DEBUG_DCACHE 1
	37	#define DEBUG_ICACHE 1
	38	#define DEBUG_CMD 0
[331]	39
	40	namespace soclib {
	41	namespace caba {
	42
	43	namespace {
[789]	44	const char * icache_fsm_state_str[] = {
[331]	45	"ICACHE_IDLE",
	46
	47	"ICACHE_XTN_TLB_FLUSH",
	48	"ICACHE_XTN_CACHE_FLUSH",
	49	"ICACHE_XTN_CACHE_FLUSH_GO",
	50	"ICACHE_XTN_TLB_INVAL",
	51	"ICACHE_XTN_CACHE_INVAL_VA",
	52	"ICACHE_XTN_CACHE_INVAL_PA",
	53	"ICACHE_XTN_CACHE_INVAL_GO",
	54
	55	"ICACHE_TLB_WAIT",
	56
	57	"ICACHE_MISS_SELECT",
	58	"ICACHE_MISS_CLEAN",
	59	"ICACHE_MISS_WAIT",
	60	"ICACHE_MISS_DATA_UPDT",
	61	"ICACHE_MISS_DIR_UPDT",
	62
	63	"ICACHE_UNC_WAIT",
	64
	65	"ICACHE_CC_CHECK",
[468]	66	"ICACHE_CC_UPDT",
[331]	67	"ICACHE_CC_INVAL",
	68	};
	69
[789]	70	const char * dcache_fsm_state_str[] = {
[331]	71	"DCACHE_IDLE",
	72
	73	"DCACHE_TLB_MISS",
	74	"DCACHE_TLB_PTE1_GET",
	75	"DCACHE_TLB_PTE1_SELECT",
	76	"DCACHE_TLB_PTE1_UPDT",
	77	"DCACHE_TLB_PTE2_GET",
	78	"DCACHE_TLB_PTE2_SELECT",
	79	"DCACHE_TLB_PTE2_UPDT",
	80	"DCACHE_TLB_LR_UPDT",
	81	"DCACHE_TLB_LR_WAIT",
	82	"DCACHE_TLB_RETURN",
	83
	84	"DCACHE_XTN_SWITCH",
	85	"DCACHE_XTN_SYNC",
	86	"DCACHE_XTN_IC_INVAL_VA",
	87	"DCACHE_XTN_IC_FLUSH",
	88	"DCACHE_XTN_IC_INVAL_PA",
[721]	89	"DCACHE_XTN_IC_PADDR_EXT",
[331]	90	"DCACHE_XTN_IT_INVAL",
	91	"DCACHE_XTN_DC_FLUSH",
	92	"DCACHE_XTN_DC_FLUSH_GO",
	93	"DCACHE_XTN_DC_INVAL_VA",
	94	"DCACHE_XTN_DC_INVAL_PA",
	95	"DCACHE_XTN_DC_INVAL_END",
	96	"DCACHE_XTN_DC_INVAL_GO",
	97	"DCACHE_XTN_DT_INVAL",
	98
[384]	99	"DCACHE_DIRTY_GET_PTE",
[331]	100	"DCACHE_DIRTY_WAIT",
	101
	102	"DCACHE_MISS_SELECT",
	103	"DCACHE_MISS_CLEAN",
	104	"DCACHE_MISS_WAIT",
	105	"DCACHE_MISS_DATA_UPDT",
	106	"DCACHE_MISS_DIR_UPDT",
	107
	108	"DCACHE_UNC_WAIT",
	109	"DCACHE_LL_WAIT",
	110	"DCACHE_SC_WAIT",
	111
	112	"DCACHE_CC_CHECK",
[468]	113	"DCACHE_CC_UPDT",
[331]	114	"DCACHE_CC_INVAL",
	115
	116	"DCACHE_INVAL_TLB_SCAN",
	117	};
	118
[789]	119	const char * cmd_fsm_state_str[] = {
[331]	120	"CMD_IDLE",
	121	"CMD_INS_MISS",
	122	"CMD_INS_UNC",
	123	"CMD_DATA_MISS",
[616]	124	"CMD_DATA_UNC_READ",
	125	"CMD_DATA_UNC_WRITE",
[331]	126	"CMD_DATA_WRITE",
	127	"CMD_DATA_LL",
	128	"CMD_DATA_SC",
	129	"CMD_DATA_CAS",
	130	};
	131
[789]	132	const char * vci_pktid_type_str[] = {
[616]	133	"TYPE_DATA_UNC",
[816]	134	"TYPE_READ_DATA_MISS",
	135	"TYPE_READ_INS_UNC",
[423]	136	"TYPE_READ_INS_MISS",
	137	"TYPE_WRITE",
	138	"TYPE_CAS",
	139	"TYPE_LL",
	140	"TYPE_SC",
	141	};
	142
[789]	143	const char * vci_cmd_type_str[] = {
[423]	144	"NOP or STORE_COND",
	145	"READ",
	146	"WRITE",
	147	"LOCKED_READ"
	148	};
	149
[789]	150	const char * rsp_fsm_state_str[] = {
[331]	151	"RSP_IDLE",
	152	"RSP_INS_MISS",
	153	"RSP_INS_UNC",
	154	"RSP_DATA_MISS",
	155	"RSP_DATA_UNC",
	156	"RSP_DATA_LL",
	157	"RSP_DATA_WRITE",
	158	};
	159
[789]	160	const char * cc_receive_fsm_state_str[] = {
[331]	161	"CC_RECEIVE_IDLE",
	162	"CC_RECEIVE_BRDCAST_HEADER",
	163	"CC_RECEIVE_BRDCAST_NLINE",
[468]	164	"CC_RECEIVE_INS_INVAL_HEADER",
	165	"CC_RECEIVE_INS_INVAL_NLINE",
	166	"CC_RECEIVE_INS_UPDT_HEADER",
	167	"CC_RECEIVE_INS_UPDT_NLINE",
	168	"CC_RECEIVE_INS_UPDT_DATA",
	169	"CC_RECEIVE_DATA_INVAL_HEADER",
	170	"CC_RECEIVE_DATA_INVAL_NLINE",
	171	"CC_RECEIVE_DATA_UPDT_HEADER",
	172	"CC_RECEIVE_DATA_UPDT_NLINE",
	173	"CC_RECEIVE_DATA_UPDT_DATA",
[331]	174	};
	175
[789]	176	const char * cc_send_fsm_state_str[] = {
[331]	177	"CC_SEND_IDLE",
	178	"CC_SEND_CLEANUP_1",
	179	"CC_SEND_CLEANUP_2",
	180	"CC_SEND_MULTI_ACK",
	181	};
	182	}
	183
[386]	184	#define tmpl(...) \
	185	template<typename vci_param, \
	186	size_t dspin_in_width, \
	187	size_t dspin_out_width, \
	188	typename iss_t> __VA_ARGS__ \
	189	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
[331]	190
[346]	191	using namespace soclib::common;
[331]	192
	193	/////////////////////////////////
	194	tmpl(/**/)::VciCcVCacheWrapper(
[789]	195	sc_module_name name,
	196	const int proc_id,
	197	const MappingTable &mtd,
	198	const IntTab &srcid,
	199	const size_t cc_global_id,
	200	const size_t itlb_ways,
	201	const size_t itlb_sets,
	202	const size_t dtlb_ways,
	203	const size_t dtlb_sets,
	204	const size_t icache_ways,
	205	const size_t icache_sets,
	206	const size_t icache_words,
	207	const size_t dcache_ways,
	208	const size_t dcache_sets,
	209	const size_t dcache_words,
	210	const size_t wbuf_nlines,
	211	const size_t wbuf_nwords,
	212	const size_t x_width,
	213	const size_t y_width,
	214	const uint32_t max_frozen_cycles,
	215	const uint32_t debug_start_cycle,
	216	const bool debug_ok)
[331]	217	: soclib::caba::BaseModule(name),
	218
[346]	219	p_clk("p_clk"),
	220	p_resetn("p_resetn"),
	221	p_vci("p_vci"),
[468]	222	p_dspin_m2p("p_dspin_m2p"),
	223	p_dspin_p2m("p_dspin_p2m"),
	224	p_dspin_clack("p_dspin_clack"),
[331]	225
[789]	226	m_cacheability_table( mtd.getCacheabilityTable()),
	227	m_srcid(mtd.indexForId(srcid)),
	228	m_cc_global_id(cc_global_id),
	229	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
	230	m_itlb_ways(itlb_ways),
	231	m_itlb_sets(itlb_sets),
	232	m_dtlb_ways(dtlb_ways),
	233	m_dtlb_sets(dtlb_sets),
	234	m_icache_ways(icache_ways),
	235	m_icache_sets(icache_sets),
	236	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
	237	m_icache_words(icache_words),
	238	m_dcache_ways(dcache_ways),
	239	m_dcache_sets(dcache_sets),
	240	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
	241	m_dcache_words(dcache_words),
	242	m_x_width(x_width),
	243	m_y_width(y_width),
	244	m_proc_id(proc_id),
	245	m_max_frozen_cycles(max_frozen_cycles),
	246	m_paddr_nbits(vci_param::N),
	247	m_debug_start_cycle(debug_start_cycle),
	248	m_debug_ok(debug_ok),
[721]	249	m_dcache_paddr_ext_reset(0),
	250	m_icache_paddr_ext_reset(0),
[331]	251
	252	r_mmu_ptpr("r_mmu_ptpr"),
	253	r_mmu_mode("r_mmu_mode"),
	254	r_mmu_word_lo("r_mmu_word_lo"),
	255	r_mmu_word_hi("r_mmu_word_hi"),
	256	r_mmu_ibvar("r_mmu_ibvar"),
	257	r_mmu_dbvar("r_mmu_dbvar"),
	258	r_mmu_ietr("r_mmu_ietr"),
	259	r_mmu_detr("r_mmu_detr"),
	260
	261	r_icache_fsm("r_icache_fsm"),
	262	r_icache_fsm_save("r_icache_fsm_save"),
	263	r_icache_vci_paddr("r_icache_vci_paddr"),
	264	r_icache_vaddr_save("r_icache_vaddr_save"),
	265
	266	r_icache_miss_way("r_icache_miss_way"),
	267	r_icache_miss_set("r_icache_miss_set"),
	268	r_icache_miss_word("r_icache_miss_word"),
	269	r_icache_miss_inval("r_icache_miss_inval"),
	270	r_icache_miss_clack("r_icache_miss_clack"),
	271
	272	r_icache_cc_way("r_icache_cc_way"),
	273	r_icache_cc_set("r_icache_cc_set"),
	274	r_icache_cc_word("r_icache_cc_word"),
	275	r_icache_cc_need_write("r_icache_cc_need_write"),
	276
	277	r_icache_flush_count("r_icache_flush_count"),
	278
	279	r_icache_miss_req("r_icache_miss_req"),
	280	r_icache_unc_req("r_icache_unc_req"),
	281
	282	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
	283	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
	284
[487]	285	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
	286	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
	287
[331]	288	r_icache_cc_send_req("r_icache_cc_send_req"),
	289	r_icache_cc_send_type("r_icache_cc_send_type"),
	290	r_icache_cc_send_nline("r_icache_cc_send_nline"),
	291	r_icache_cc_send_way("r_icache_cc_send_way"),
	292	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
	293
	294	r_dcache_fsm("r_dcache_fsm"),
	295	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
	296	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
	297
	298	r_dcache_wbuf_req("r_dcache_wbuf_req"),
	299	r_dcache_updt_req("r_dcache_updt_req"),
	300	r_dcache_save_vaddr("r_dcache_save_vaddr"),
	301	r_dcache_save_wdata("r_dcache_save_wdata"),
	302	r_dcache_save_be("r_dcache_save_be"),
	303	r_dcache_save_paddr("r_dcache_save_paddr"),
	304	r_dcache_save_cache_way("r_dcache_save_cache_way"),
	305	r_dcache_save_cache_set("r_dcache_save_cache_set"),
	306	r_dcache_save_cache_word("r_dcache_save_cache_word"),
	307
	308	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
	309	r_dcache_dirty_way("r_dcache_dirty_way"),
	310	r_dcache_dirty_set("r_dcache_dirty_set"),
	311
	312	r_dcache_vci_paddr("r_dcache_vci_paddr"),
[616]	313	r_dcache_vci_wdata("r_dcache_vci_wdata"),
[331]	314	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
	315	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
[627]	316	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
[616]	317	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
[331]	318	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
	319	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
	320	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
	321	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
	322	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
	323	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
	324
	325	r_dcache_xtn_way("r_dcache_xtn_way"),
	326	r_dcache_xtn_set("r_dcache_xtn_set"),
	327
	328	r_dcache_miss_type("r_dcache_miss_type"),
	329	r_dcache_miss_word("r_dcache_miss_word"),
	330	r_dcache_miss_way("r_dcache_miss_way"),
	331	r_dcache_miss_set("r_dcache_miss_set"),
	332	r_dcache_miss_inval("r_dcache_miss_inval"),
	333
	334	r_dcache_cc_way("r_dcache_cc_way"),
	335	r_dcache_cc_set("r_dcache_cc_set"),
	336	r_dcache_cc_word("r_dcache_cc_word"),
	337	r_dcache_cc_need_write("r_dcache_cc_need_write"),
	338
	339	r_dcache_flush_count("r_dcache_flush_count"),
	340
	341	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
	342
	343	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
	344	r_dcache_tlb_ins("r_dcache_tlb_ins"),
	345	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
	346	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
	347	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
	348	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
	349	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
	350	r_dcache_tlb_way("r_dcache_tlb_way"),
	351	r_dcache_tlb_set("r_dcache_tlb_set"),
	352
	353	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
	354	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
	355
	356	r_dcache_xtn_req("r_dcache_xtn_req"),
	357	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
	358
[487]	359	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
	360	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
[816]	361
[331]	362	r_dcache_cc_send_req("r_dcache_cc_send_req"),
	363	r_dcache_cc_send_type("r_dcache_cc_send_type"),
	364	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
	365	r_dcache_cc_send_way("r_dcache_cc_send_way"),
	366	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
	367
	368	r_vci_cmd_fsm("r_vci_cmd_fsm"),
	369	r_vci_cmd_min("r_vci_cmd_min"),
	370	r_vci_cmd_max("r_vci_cmd_max"),
	371	r_vci_cmd_cpt("r_vci_cmd_cpt"),
	372	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
	373
	374	r_vci_rsp_fsm("r_vci_rsp_fsm"),
	375	r_vci_rsp_cpt("r_vci_rsp_cpt"),
	376	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
	377	r_vci_rsp_data_error("r_vci_rsp_data_error"),
[789]	378	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
	379	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
[331]	380
	381	r_cc_send_fsm("r_cc_send_fsm"),
	382	r_cc_send_last_client("r_cc_send_last_client"),
	383
	384	r_cc_receive_fsm("r_cc_receive_fsm"),
	385	r_cc_receive_data_ins("r_cc_receive_data_ins"),
	386	r_cc_receive_word_idx("r_cc_receive_word_idx"),
[789]	387	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
	388	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
	389	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
[331]	390
	391	r_cc_receive_icache_req("r_cc_receive_icache_req"),
	392	r_cc_receive_icache_type("r_cc_receive_icache_type"),
	393	r_cc_receive_icache_way("r_cc_receive_icache_way"),
	394	r_cc_receive_icache_set("r_cc_receive_icache_set"),
	395	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
	396	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
	397
	398	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
	399	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
	400	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
	401	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
	402	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
	403	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
	404
	405	r_iss(this->name(), proc_id),
	406	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
	407	r_icache("icache", icache_ways, icache_sets, icache_words),
	408	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
	409	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
	410	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
	411	{
[421]	412	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
	413
[789]	414	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
[331]	415	"Need more PLEN bits.");
	416
[789]	417	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
[331]	418	"Need more TRDID bits.");
	419
[789]	420	assert((icache_words == dcache_words) and
[331]	421	"icache_words and dcache_words parameters must be equal");
	422
[789]	423	assert((itlb_sets == dtlb_sets) and
[331]	424	"itlb_sets and dtlb_sets parameters must be etqual");
	425
[789]	426	assert((itlb_ways == dtlb_ways) and
[331]	427	"itlb_ways and dtlb_ways parameters must be etqual");
	428
[789]	429	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
	430	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
	431	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
	432	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
	433	(uint32_log2(m_icache_words << 2));
[331]	434
[789]	435	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
[331]	436
[789]	437	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
	438	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
[331]	439
	440	SC_METHOD(transition);
	441	dont_initialize();
	442	sensitive << p_clk.pos();
	443
	444	SC_METHOD(genMoore);
	445	dont_initialize();
	446	sensitive << p_clk.neg();
	447
	448	typename iss_t::CacheInfo cache_info;
	449	cache_info.has_mmu = true;
[789]	450	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
[331]	451	cache_info.icache_assoc = icache_ways;
	452	cache_info.icache_n_lines = icache_sets;
[789]	453	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
[331]	454	cache_info.dcache_assoc = dcache_ways;
	455	cache_info.dcache_n_lines = dcache_sets;
	456	r_iss.setCacheInfo(cache_info);
	457	}
	458
	459	/////////////////////////////////////
	460	tmpl(/**/)::~VciCcVCacheWrapper()
	461	/////////////////////////////////////
	462	{
	463	delete [] r_dcache_in_tlb;
	464	delete [] r_dcache_contains_ptd;
	465	}
	466
	467	////////////////////////
	468	tmpl(void)::print_cpi()
	469	////////////////////////
	470	{
	471	std::cout << name() << " CPI = "
	472	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
	473	}
	474
	475	////////////////////////////////////
	476	tmpl(void)::print_trace(size_t mode)
	477	////////////////////////////////////
	478	{
	479	// b0 : write buffer trace
[740]	480	// b1 : dump processor registers
[331]	481	// b2 : dcache trace
	482	// b3 : icache trace
	483	// b4 : dtlb trace
	484	// b5 : itlb trace
[740]	485	// b6 : SR (ISS register 32)
[331]	486
	487	std::cout << std::dec << "PROC " << name() << std::endl;
	488
	489	std::cout << " " << m_ireq << std::endl;
	490	std::cout << " " << m_irsp << std::endl;
	491	std::cout << " " << m_dreq << std::endl;
	492	std::cout << " " << m_drsp << std::endl;
	493
	494	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
	495	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
	496	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
	497	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
	498	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
[394]	499	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
	500	<< " \| MMU = " << r_mmu_mode.read();
[711]	501
[789]	502	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
	503	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
[331]	504	std::cout << std::endl;
	505
[789]	506	if (mode & 0x01)
[331]	507	{
[789]	508	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
	509	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
	510	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
	511	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
[711]	512
[789]	513	r_wbuf.printTrace((mode >> 1) & 1);
[331]	514	}
[789]	515	if (mode & 0x02)
[740]	516	{
	517	r_iss.dump();
	518	}
[789]	519	if (mode & 0x04)
[331]	520	{
	521	std::cout << " Data Cache" << std::endl;
	522	r_dcache.printTrace();
	523	}
[789]	524	if (mode & 0x08)
[331]	525	{
	526	std::cout << " Instruction Cache" << std::endl;
	527	r_icache.printTrace();
	528	}
[789]	529	if (mode & 0x10)
[331]	530	{
	531	std::cout << " Data TLB" << std::endl;
	532	r_dtlb.printTrace();
	533	}
[789]	534	if (mode & 0x20)
[331]	535	{
	536	std::cout << " Instruction TLB" << std::endl;
	537	r_itlb.printTrace();
	538	}
[789]	539	if (mode & 0x40)
[740]	540	{
[789]	541	uint32_t status = r_iss.debugGetRegisterValue(32);
[740]	542	std::cout << name();
[789]	543	if (status != m_previous_status ) std::cout << " NEW ";
[740]	544	std::cout << " status = " << std::hex << status << " " << std::endl;
	545	m_previous_status = status;
	546	}
[331]	547	}
	548
	549	//////////////////////////////////////////
[789]	550	tmpl(void)::cache_monitor(paddr_t addr)
[331]	551	//////////////////////////////////////////
	552	{
[789]	553	bool cache_hit;
	554	size_t cache_way = 0;
	555	size_t cache_set = 0;
	556	size_t cache_word = 0;
	557	uint32_t cache_rdata = 0;
[394]	558
[789]	559	cache_hit = r_dcache.read_neutral(addr,
	560	&cache_rdata,
	561	&cache_way,
	562	&cache_set,
	563	&cache_word);
[394]	564
[789]	565	if (cache_hit != m_debug_previous_d_hit)
[331]	566	{
[394]	567	std::cout << "Monitor PROC " << name()
	568	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
[816]	569	<< " / HIT = " << cache_hit
[394]	570	<< " / PADDR = " << std::hex << addr
[816]	571	<< " / DATA = " << cache_rdata
[394]	572	<< " / WAY = " << cache_way << std::endl;
[789]	573	m_debug_previous_d_hit = cache_hit;
[331]	574	}
[394]	575
[789]	576	cache_hit = r_icache.read_neutral(addr,
	577	&cache_rdata,
	578	&cache_way,
	579	&cache_set,
	580	&cache_word);
[394]	581
[789]	582	if (cache_hit != m_debug_previous_i_hit)
[331]	583	{
[394]	584	std::cout << "Monitor PROC " << name()
	585	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
[816]	586	<< " / HIT = " << cache_hit
[394]	587	<< " / PADDR = " << std::hex << addr
[816]	588	<< " / DATA = " << cache_rdata
[394]	589	<< " / WAY = " << cache_way << std::endl;
[789]	590	m_debug_previous_i_hit = cache_hit;
[331]	591	}
	592	}
	593
[1047]	594	/////////////////////////////////
	595	tmpl(void)::print_frozen_stats()
	596	/////////////////////////////////
	597	{
	598	if ( m_cpt_frozen_events )
	599	{
	600	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
	601	std::cout << name()
	602	<< " : FROZEN EVENTS = " << m_cpt_frozen_events
	603	<< " / AVERAGE LENGTH = " << m_cpt_frozen_cost/(m_cpt_frozen_events*1000)
	604	<< " Kcycles / CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl;
	605	}
	606	}
	607
	608
[331]	609	/*
	610	////////////////////////
	611	tmpl(void)::print_stats()
	612	////////////////////////
	613	{
	614	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
	615	std::cout << name() << std::endl
	616	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
	617	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
	618	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
	619	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
	620	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
	621	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
	622	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
	623	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
	624	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
	625	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
	626	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
	627	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
	628	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
	629	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
	630	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
	631	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
	632	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
	633	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
	634	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
	635	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
	636	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
	637	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
	638	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
	639	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
	640	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
	641	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
	642	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
	643	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
	644	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
	645	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
	646	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
	647	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
	648	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
	649	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
	650	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
	651	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
	652	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
	653	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
	654	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
	655	}
	656
	657	////////////////////////
	658	tmpl(void)::clear_stats()
	659	////////////////////////
	660	{
	661	m_cpt_dcache_data_read = 0;
	662	m_cpt_dcache_data_write = 0;
	663	m_cpt_dcache_dir_read = 0;
	664	m_cpt_dcache_dir_write = 0;
	665	m_cpt_icache_data_read = 0;
	666	m_cpt_icache_data_write = 0;
	667	m_cpt_icache_dir_read = 0;
	668	m_cpt_icache_dir_write = 0;
	669
	670	m_cpt_frz_cycles = 0;
	671	m_cpt_dcache_frz_cycles = 0;
	672	m_cpt_total_cycles = 0;
	673
	674	m_cpt_read = 0;
	675	m_cpt_write = 0;
	676	m_cpt_data_miss = 0;
	677	m_cpt_ins_miss = 0;
	678	m_cpt_unc_read = 0;
	679	m_cpt_write_cached = 0;
	680	m_cpt_ins_read = 0;
	681
	682	m_cost_write_frz = 0;
	683	m_cost_data_miss_frz = 0;
	684	m_cost_unc_read_frz = 0;
	685	m_cost_ins_miss_frz = 0;
	686
	687	m_cpt_imiss_transaction = 0;
	688	m_cpt_dmiss_transaction = 0;
	689	m_cpt_unc_transaction = 0;
	690	m_cpt_write_transaction = 0;
	691	m_cpt_icache_unc_transaction = 0;
	692
	693	m_cost_imiss_transaction = 0;
	694	m_cost_dmiss_transaction = 0;
	695	m_cost_unc_transaction = 0;
	696	m_cost_write_transaction = 0;
	697	m_cost_icache_unc_transaction = 0;
	698	m_length_write_transaction = 0;
	699
	700	m_cpt_ins_tlb_read = 0;
	701	m_cpt_ins_tlb_miss = 0;
	702	m_cpt_ins_tlb_update_acc = 0;
	703
	704	m_cpt_data_tlb_read = 0;
	705	m_cpt_data_tlb_miss = 0;
	706	m_cpt_data_tlb_update_acc = 0;
	707	m_cpt_data_tlb_update_dirty = 0;
	708	m_cpt_ins_tlb_hit_dcache = 0;
	709	m_cpt_data_tlb_hit_dcache = 0;
	710	m_cpt_ins_tlb_occup_cache = 0;
	711	m_cpt_data_tlb_occup_cache = 0;
	712
	713	m_cost_ins_tlb_miss_frz = 0;
	714	m_cost_data_tlb_miss_frz = 0;
	715	m_cost_ins_tlb_update_acc_frz = 0;
	716	m_cost_data_tlb_update_acc_frz = 0;
	717	m_cost_data_tlb_update_dirty_frz = 0;
	718	m_cost_ins_tlb_occup_cache_frz = 0;
	719	m_cost_data_tlb_occup_cache_frz = 0;
	720
	721	m_cpt_itlbmiss_transaction = 0;
	722	m_cpt_itlb_ll_transaction = 0;
	723	m_cpt_itlb_sc_transaction = 0;
	724	m_cpt_dtlbmiss_transaction = 0;
	725	m_cpt_dtlb_ll_transaction = 0;
	726	m_cpt_dtlb_sc_transaction = 0;
	727	m_cpt_dtlb_ll_dirty_transaction = 0;
	728	m_cpt_dtlb_sc_dirty_transaction = 0;
	729
	730	m_cost_itlbmiss_transaction = 0;
	731	m_cost_itlb_ll_transaction = 0;
	732	m_cost_itlb_sc_transaction = 0;
	733	m_cost_dtlbmiss_transaction = 0;
	734	m_cost_dtlb_ll_transaction = 0;
	735	m_cost_dtlb_sc_transaction = 0;
	736	m_cost_dtlb_ll_dirty_transaction = 0;
	737	m_cost_dtlb_sc_dirty_transaction = 0;
	738
	739	m_cpt_cc_update_data = 0;
	740	m_cpt_cc_inval_ins = 0;
	741	m_cpt_cc_inval_data = 0;
	742	m_cpt_cc_broadcast = 0;
	743
	744	m_cost_updt_data_frz = 0;
	745	m_cost_inval_ins_frz = 0;
	746	m_cost_inval_data_frz = 0;
	747	m_cost_broadcast_frz = 0;
	748
	749	m_cpt_cc_cleanup_data = 0;
	750	m_cpt_cc_cleanup_ins = 0;
	751	}
	752
	753	*/
	754
	755	/////////////////////////
	756	tmpl(void)::transition()
	757	/////////////////////////
	758	{
[789]	759	if (not p_resetn.read())
[331]	760	{
	761	r_iss.reset();
	762	r_wbuf.reset();
	763	r_icache.reset();
	764	r_dcache.reset();
	765	r_itlb.reset();
	766	r_dtlb.reset();
	767
[789]	768	r_dcache_fsm = DCACHE_IDLE;
	769	r_icache_fsm = ICACHE_IDLE;
	770	r_vci_cmd_fsm = CMD_IDLE;
	771	r_vci_rsp_fsm = RSP_IDLE;
	772	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	773	r_cc_send_fsm = CC_SEND_IDLE;
[331]	774
[394]	775	// reset data physical address extension
[721]	776	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
[394]	777
[721]	778	// reset inst physical address extension
	779	r_icache_paddr_ext = m_icache_paddr_ext_reset;
	780
[331]	781	// reset dcache directory extension
[789]	782	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
[331]	783	{
[789]	784	r_dcache_in_tlb[i] = false;
[331]	785	r_dcache_contains_ptd[i] = false;
	786	}
	787
	788	// Response FIFOs and cleanup buffer
	789	r_vci_rsp_fifo_icache.init();
	790	r_vci_rsp_fifo_dcache.init();
	791
	792	// ICACHE & DCACHE activated
[394]	793	// ITLB & DTLB desactivated
[331]	794	r_mmu_mode = 0x3;
	795
[789]	796	// No request from ICACHE FSM to CMD FSM
[331]	797	r_icache_miss_req = false;
	798	r_icache_unc_req = false;
	799
	800	// No request from ICACHE_FSM to DCACHE FSM
	801	r_icache_tlb_miss_req = false;
	802
	803	// No request from ICACHE_FSM to CC_SEND FSM
	804	r_icache_cc_send_req = false;
[487]	805	r_icache_cleanup_victim_req = false;
[331]	806
[468]	807	r_icache_clack_req = false;
	808
[331]	809	// No pending write in pipeline
	810	r_dcache_wbuf_req = false;
	811	r_dcache_updt_req = false;
	812
	813	// No request from DCACHE_FSM to CMD_FSM
	814	r_dcache_vci_miss_req = false;
	815	r_dcache_vci_unc_req = false;
	816	r_dcache_vci_cas_req = false;
	817	r_dcache_vci_ll_req = false;
	818	r_dcache_vci_sc_req = false;
	819
	820	// No processor XTN request pending
	821	r_dcache_xtn_req = false;
	822
	823	// No request from DCACHE FSM to CC_SEND FSM
[789]	824	r_dcache_cc_send_req = false;
[487]	825	r_dcache_cleanup_victim_req = false;
[331]	826
[468]	827	r_dcache_clack_req = false;
	828
[331]	829	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
	830	r_cc_receive_icache_req = false;
	831	r_cc_receive_dcache_req = false;
	832
	833	// last cc_send client was dcache
	834	r_cc_send_last_client = false;
	835
	836	// No pending cleanup after a replacement
	837	r_icache_miss_clack = false;
	838	r_dcache_miss_clack = false;
	839
	840	// No signalisation of a coherence request matching a pending miss
	841	r_icache_miss_inval = false;
	842	r_dcache_miss_inval = false;
	843
[468]	844	r_dspin_clack_req = false;
	845
[331]	846	// No signalisation of errors
	847	r_vci_rsp_ins_error = false;
	848	r_vci_rsp_data_error = false;
	849
	850	// Debug variables
[394]	851	m_debug_previous_i_hit = false;
	852	m_debug_previous_d_hit = false;
[789]	853	m_debug_icache_fsm = false;
	854	m_debug_dcache_fsm = false;
	855	m_debug_cmd_fsm = false;
[331]	856
	857	// activity counters
	858	m_cpt_dcache_data_read = 0;
	859	m_cpt_dcache_data_write = 0;
	860	m_cpt_dcache_dir_read = 0;
	861	m_cpt_dcache_dir_write = 0;
	862	m_cpt_icache_data_read = 0;
	863	m_cpt_icache_data_write = 0;
	864	m_cpt_icache_dir_read = 0;
	865	m_cpt_icache_dir_write = 0;
	866
	867	m_cpt_frz_cycles = 0;
	868	m_cpt_total_cycles = 0;
	869	m_cpt_stop_simulation = 0;
[1047]	870	m_cpt_frozen_events = 0;
	871	m_cpt_frozen_cost = 0;
[331]	872
	873	m_cpt_data_miss = 0;
	874	m_cpt_ins_miss = 0;
	875	m_cpt_unc_read = 0;
	876	m_cpt_write_cached = 0;
	877	m_cpt_ins_read = 0;
	878
	879	m_cost_write_frz = 0;
	880	m_cost_data_miss_frz = 0;
	881	m_cost_unc_read_frz = 0;
	882	m_cost_ins_miss_frz = 0;
	883
[1047]	884	m_cpt_imiss_transaction = 0;
	885	m_cpt_dmiss_transaction = 0;
	886	m_cpt_unc_transaction = 0;
	887	m_cpt_write_transaction = 0;
	888	m_cpt_icache_unc_transaction = 0;
[331]	889
	890	m_cost_imiss_transaction = 0;
	891	m_cost_dmiss_transaction = 0;
	892	m_cost_unc_transaction = 0;
	893	m_cost_write_transaction = 0;
	894	m_cost_icache_unc_transaction = 0;
	895	m_length_write_transaction = 0;
	896
	897	m_cpt_ins_tlb_read = 0;
	898	m_cpt_ins_tlb_miss = 0;
	899	m_cpt_ins_tlb_update_acc = 0;
	900
	901	m_cpt_data_tlb_read = 0;
	902	m_cpt_data_tlb_miss = 0;
	903	m_cpt_data_tlb_update_acc = 0;
	904	m_cpt_data_tlb_update_dirty = 0;
	905	m_cpt_ins_tlb_hit_dcache = 0;
	906	m_cpt_data_tlb_hit_dcache = 0;
	907	m_cpt_ins_tlb_occup_cache = 0;
	908	m_cpt_data_tlb_occup_cache = 0;
	909
	910	m_cost_ins_tlb_miss_frz = 0;
	911	m_cost_data_tlb_miss_frz = 0;
	912	m_cost_ins_tlb_update_acc_frz = 0;
	913	m_cost_data_tlb_update_acc_frz = 0;
	914	m_cost_data_tlb_update_dirty_frz = 0;
	915	m_cost_ins_tlb_occup_cache_frz = 0;
	916	m_cost_data_tlb_occup_cache_frz = 0;
	917
[789]	918	m_cpt_ins_tlb_inval = 0;
	919	m_cpt_data_tlb_inval = 0;
	920	m_cost_ins_tlb_inval_frz = 0;
	921	m_cost_data_tlb_inval_frz = 0;
[331]	922
	923	m_cpt_cc_broadcast = 0;
	924
[789]	925	m_cost_updt_data_frz = 0;
	926	m_cost_inval_ins_frz = 0;
	927	m_cost_inval_data_frz = 0;
	928	m_cost_broadcast_frz = 0;
[331]	929
[789]	930	m_cpt_cc_cleanup_data = 0;
	931	m_cpt_cc_cleanup_ins = 0;
[331]	932
	933	m_cpt_itlbmiss_transaction = 0;
	934	m_cpt_itlb_ll_transaction = 0;
	935	m_cpt_itlb_sc_transaction = 0;
	936	m_cpt_dtlbmiss_transaction = 0;
	937	m_cpt_dtlb_ll_transaction = 0;
	938	m_cpt_dtlb_sc_transaction = 0;
	939	m_cpt_dtlb_ll_dirty_transaction = 0;
	940	m_cpt_dtlb_sc_dirty_transaction = 0;
	941
	942	m_cost_itlbmiss_transaction = 0;
	943	m_cost_itlb_ll_transaction = 0;
	944	m_cost_itlb_sc_transaction = 0;
	945	m_cost_dtlbmiss_transaction = 0;
	946	m_cost_dtlb_ll_transaction = 0;
	947	m_cost_dtlb_sc_transaction = 0;
	948	m_cost_dtlb_ll_dirty_transaction = 0;
	949	m_cost_dtlb_sc_dirty_transaction = 0;
	950	/*
	951	m_cpt_dcache_frz_cycles = 0;
[789]	952	m_cpt_read = 0;
	953	m_cpt_write = 0;
	954	m_cpt_cc_update_data = 0;
	955	m_cpt_cc_inval_ins = 0;
	956	m_cpt_cc_inval_data = 0;
[331]	957	*/
	958
[789]	959	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
	960	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
	961	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
	962	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
[331]	963
	964	// init the llsc reservation buffer
	965	r_dcache_llsc_valid = false;
[423]	966	m_monitor_ok = false;
[331]	967
	968	return;
	969	}
	970
	971	// Response FIFOs default values
[789]	972	bool vci_rsp_fifo_icache_get = false;
	973	bool vci_rsp_fifo_icache_put = false;
	974	uint32_t vci_rsp_fifo_icache_data = 0;
[331]	975
[789]	976	bool vci_rsp_fifo_dcache_get = false;
	977	bool vci_rsp_fifo_dcache_put = false;
	978	uint32_t vci_rsp_fifo_dcache_data = 0;
[331]	979
	980	// updt fifo
[789]	981	bool cc_receive_updt_fifo_get = false;
	982	bool cc_receive_updt_fifo_put = false;
	983	uint32_t cc_receive_updt_fifo_be = 0;
	984	uint32_t cc_receive_updt_fifo_data = 0;
	985	bool cc_receive_updt_fifo_eop = false;
[331]	986
	987	#ifdef INSTRUMENTATION
[789]	988	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
	989	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
	990	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
	991	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
	992	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
	993	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
[331]	994	#endif
	995
	996	m_cpt_total_cycles++;
	997
[668]	998	m_debug_icache_fsm = m_debug_icache_fsm \|\|
	999	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
	1000	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
	1001	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
	1002	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
	1003	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
[331]	1004
	1005	/////////////////////////////////////////////////////////////////////
	1006	// Get data and instruction requests from processor
	1007	///////////////////////////////////////////////////////////////////////
	1008
	1009	r_iss.getRequests(m_ireq, m_dreq);
	1010
	1011	////////////////////////////////////////////////////////////////////////////////////
	1012	// ICACHE_FSM
	1013	//
	1014	// 1/ Coherence operations
	1015	// They are handled as interrupts generated by the CC_RECEIVE FSM.
	1016	// - There is a coherence request when r_tgt_icache_req is set.
	1017	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
	1018	// - There is a cleanup ack request when r_cleanup_icache_req is set.
	1019	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
	1020	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
	1021	// - For both types of requests, actions associated to the pre-empted state
	1022	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
	1023	// or CC_CLACK) to execute the requested coherence operation, and returns
	1024	// to the pre-empted state.
	1025	//
	1026	// 2/ Processor requests
	1027	// They are taken in IDLE state only. In case of cache miss, or uncacheable
	1028	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
	1029	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
	1030	// flip-flops are reset when the transaction starts.
	1031	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
	1032	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
	1033	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
	1034	// The availability of the missing cache line is signaled by the response fifo,
	1035	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
	1036	// and ICACHE_MISS_DIR_UPDT states.
	1037	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
	1038	// to wait the response from the RSP FSM, through the response fifo.
	1039	// The missing instruction is directly returned to processor in this state.
	1040	//
	1041	// 3/ TLB miss
	1042	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
	1043	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
	1044	// register, and goes to the ICACHE_TLB_WAIT state.
	1045	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
	1046	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
	1047	// to signal the completion.
	1048	//
	1049	// 4/ XTN requests
	1050	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
	1051	// using the r_dcache_xtn_req flip-flop.
	1052	// The request opcode and the address to be invalidated are transmitted
	1053	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
	1054	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
	1055	// is completed.
	1056	//
	1057	// 5/ Error Handling
	1058	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
	1059	// in a cache miss or uncacheable read VCI transaction. Nothing is written
	1060	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
	1061	////////////////////////////////////////////////////////////////////////////////////////
	1062
	1063	// default value for m_irsp
[789]	1064	m_irsp.valid = false;
	1065	m_irsp.error = false;
[331]	1066	m_irsp.instruction = 0;
	1067
[789]	1068	switch (r_icache_fsm.read())
[331]	1069	{
	1070	/////////////////
[789]	1071	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
[331]	1072	// and coherence requests with a fixed priority:
	1073	// 1/ Coherence requests => ICACHE_CC_CHECK
	1074	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
	1075	// 3/ tlb miss => ICACHE_TLB_WAIT
	1076	// 4/ cacheable read miss => ICACHE_MISS_SELECT
	1077	// 5/ uncacheable read miss => ICACHE_UNC_REQ
	1078	{
[468]	1079	// coherence clack interrupt
[789]	1080	if (r_icache_clack_req.read())
[468]	1081	{
	1082	r_icache_fsm = ICACHE_CC_CHECK;
	1083	r_icache_fsm_save = r_icache_fsm.read();
	1084	break;
	1085	}
	1086
[331]	1087	// coherence interrupt
[789]	1088	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1089	{
	1090	r_icache_fsm = ICACHE_CC_CHECK;
	1091	r_icache_fsm_save = r_icache_fsm.read();
	1092	break;
	1093	}
	1094
	1095	// XTN requests sent by DCACHE FSM
[721]	1096	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
	1097	// because they require access to icache or itlb, that are already accessed
[789]	1098	if (r_dcache_xtn_req.read())
[331]	1099	{
[789]	1100	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
[331]	1101	{
[789]	1102	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
[331]	1103	}
[789]	1104	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
[331]	1105	{
	1106	r_icache_flush_count = 0;
[789]	1107	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
[331]	1108	}
[789]	1109	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
[331]	1110	{
[789]	1111	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
[331]	1112	}
[789]	1113	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
[331]	1114	{
[789]	1115	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
[331]	1116	}
[789]	1117	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
[331]	1118	{
[970]	1119	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
	1120	((uint64_t)r_mmu_word_lo.read());
	1121
	1122	r_icache_vci_paddr = (paddr_t)pa;
[721]	1123	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
[331]	1124	}
[789]	1125	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
[721]	1126	{
[816]	1127	r_icache_paddr_ext = r_dcache_save_wdata.read();
[721]	1128	r_dcache_xtn_req = false;
	1129	}
[331]	1130	else
	1131	{
[789]	1132	assert(false and
[331]	1133	"undefined XTN request received by ICACHE FSM");
	1134	}
	1135	break;
	1136	} // end if xtn_req
	1137
	1138	// processor request
[789]	1139	if (m_ireq.valid )
[331]	1140	{
[789]	1141	bool cacheable;
	1142	paddr_t paddr;
	1143	bool tlb_hit = false;
	1144	pte_info_t tlb_flags;
	1145	size_t tlb_way;
	1146	size_t tlb_set;
	1147	paddr_t tlb_nline;
	1148	uint32_t cache_inst = 0;
	1149	size_t cache_way;
	1150	size_t cache_set;
	1151	size_t cache_word;
	1152	int cache_state = CACHE_SLOT_STATE_EMPTY;
[331]	1153
	1154	// We register processor request
	1155	r_icache_vaddr_save = m_ireq.addr;
[752]	1156	paddr = (paddr_t) m_ireq.addr;
[331]	1157
	1158	// sytematic itlb access (if activated)
[789]	1159	if (r_mmu_mode.read() & INS_TLB_MASK)
[331]	1160	{
	1161
	1162	#ifdef INSTRUMENTATION
[789]	1163	m_cpt_itlb_read++;
[331]	1164	#endif
[789]	1165	tlb_hit = r_itlb.translate(m_ireq.addr,
	1166	&paddr,
	1167	&tlb_flags,
	1168	&tlb_nline, // unused
	1169	&tlb_way, // unused
	1170	&tlb_set); // unused
[331]	1171	}
[752]	1172	else if (vci_param::N > 32)
[331]	1173	{
[752]	1174	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
[331]	1175	}
	1176
	1177	// systematic icache access (if activated)
[789]	1178	if (r_mmu_mode.read() & INS_CACHE_MASK)
[331]	1179	{
	1180
	1181
	1182	#ifdef INSTRUMENTATION
[789]	1183	m_cpt_icache_data_read++;
	1184	m_cpt_icache_dir_read++;
[331]	1185	#endif
[789]	1186	r_icache.read(paddr,
	1187	&cache_inst,
	1188	&cache_way,
	1189	&cache_set,
	1190	&cache_word,
	1191	&cache_state);
[331]	1192	}
	1193
	1194	// We compute cacheability and check access rights:
	1195	// - If MMU activated : cacheability is defined by the C bit in the PTE,
	1196	// and the access rights are defined by the U and X bits in the PTE.
	1197	// - If MMU not activated : cacheability is defined by the segment table,
	1198	// and there is no access rights checking
	1199
[789]	1200	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
[331]	1201	{
	1202	// cacheability
[789]	1203	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
	1204	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
[331]	1205	}
[789]	1206	else // itlb activated
[331]	1207	{
[789]	1208	if (tlb_hit) // ITLB hit
[331]	1209	{
	1210	// cacheability
[789]	1211	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
[331]	1212	else cacheable = tlb_flags.c;
	1213
	1214	// access rights checking
[789]	1215	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
[331]	1216	{
[809]	1217
	1218	#if DEBUG_ICACHE
	1219	if ( m_debug_icache_fsm )
[816]	1220	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
[809]	1221	<< " : PADDR = " << std::hex << paddr << std::endl;
	1222	#endif
	1223	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
	1224	r_mmu_ibvar = m_ireq.addr;
	1225	m_irsp.valid = true;
	1226	m_irsp.error = true;
	1227	m_irsp.instruction = 0;
[331]	1228	break;
	1229	}
[789]	1230	else if (not tlb_flags.x)
[331]	1231	{
[809]	1232
	1233	#if DEBUG_ICACHE
	1234	if ( m_debug_icache_fsm )
[816]	1235	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
[809]	1236	<< " : PADDR = " << std::hex << paddr << std::endl;
	1237	#endif
	1238	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
	1239	r_mmu_ibvar = m_ireq.addr;
	1240	m_irsp.valid = true;
	1241	m_irsp.error = true;
	1242	m_irsp.instruction = 0;
[331]	1243	break;
	1244	}
	1245	}
[789]	1246	else // ITLB miss
[331]	1247	{
	1248
	1249	#ifdef INSTRUMENTATION
[789]	1250	m_cpt_itlb_miss++;
[331]	1251	#endif
	1252	r_icache_fsm = ICACHE_TLB_WAIT;
	1253	r_icache_tlb_miss_req = true;
	1254	break;
	1255	}
	1256	} // end if itlb activated
	1257
	1258	// physical address registration
[789]	1259	r_icache_vci_paddr = paddr;
[331]	1260
	1261	// Finally, we send the response to processor, and compute next state
[789]	1262	if (cacheable)
[331]	1263	{
[789]	1264	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
[331]	1265	{
	1266
	1267	#ifdef INSTRUMENTATION
[789]	1268	m_cpt_icache_miss++;
[331]	1269	#endif
	1270	// we request a VCI transaction
[789]	1271	r_icache_fsm = ICACHE_MISS_SELECT;
[386]	1272	#if DEBUG_ICACHE
[789]	1273	if (m_debug_icache_fsm)
[816]	1274	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
[789]	1275	<< " : PADDR = " << std::hex << paddr << std::endl;
[386]	1276	#endif
	1277	r_icache_miss_req = true;
[331]	1278	}
[789]	1279	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
[331]	1280	{
	1281	// stalled until cleanup is acknowledged
[789]	1282	r_icache_fsm = ICACHE_IDLE;
[331]	1283	}
[789]	1284	else // cache hit
[331]	1285	{
	1286
	1287	#ifdef INSTRUMENTATION
[789]	1288	m_cpt_ins_read++;
[331]	1289	#endif
	1290	// return instruction to processor
	1291	m_irsp.valid = true;
	1292	m_irsp.instruction = cache_inst;
	1293	r_icache_fsm = ICACHE_IDLE;
[386]	1294	#if DEBUG_ICACHE
[789]	1295	if (m_debug_icache_fsm)
[816]	1296	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
[789]	1297	<< " : PADDR = " << std::hex << paddr
	1298	<< " / INST = " << cache_inst << std::endl;
[386]	1299	#endif
[331]	1300	}
	1301	}
[789]	1302	else // non cacheable read
[331]	1303	{
[789]	1304	r_icache_unc_req = true;
	1305	r_icache_fsm = ICACHE_UNC_WAIT;
[386]	1306
	1307	#if DEBUG_ICACHE
[789]	1308	if (m_debug_icache_fsm)
	1309	{
	1310	std::cout << " <PROC " << name()
[816]	1311	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
[789]	1312	<< " : PADDR = " << std::hex << paddr << std::endl;
	1313	}
[386]	1314	#endif
[331]	1315	}
	1316	} // end if m_ireq.valid
	1317	break;
	1318	}
	1319	/////////////////////
[789]	1320	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
[331]	1321	// the itlb is udated by the DCACHE FSM, as well as the
	1322	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
	1323	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
	1324	// reset the r_icache_tlb_miss_req flip-flop
	1325	// external coherence request are accepted in this state.
	1326	{
[468]	1327	// coherence clack interrupt
[789]	1328	if (r_icache_clack_req.read())
[468]	1329	{
	1330	r_icache_fsm = ICACHE_CC_CHECK;
	1331	r_icache_fsm_save = r_icache_fsm.read();
	1332	break;
	1333	}
	1334
[331]	1335	// coherence interrupt
[789]	1336	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1337	{
	1338	r_icache_fsm = ICACHE_CC_CHECK;
	1339	r_icache_fsm_save = r_icache_fsm.read();
	1340	break;
	1341	}
	1342
[789]	1343	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
[331]	1344
	1345	// DCACHE FSM signals response by reseting the request flip-flop
[789]	1346	if (not r_icache_tlb_miss_req.read())
[331]	1347	{
[789]	1348	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
[331]	1349	{
	1350	r_icache_tlb_rsp_error = false;
[789]	1351	m_irsp.error = true;
	1352	m_irsp.valid = true;
	1353	r_icache_fsm = ICACHE_IDLE;
[331]	1354	}
[789]	1355	else // tlb updated : return to IDLE state
[331]	1356	{
	1357	r_icache_fsm = ICACHE_IDLE;
	1358	}
	1359	}
	1360	break;
	1361	}
	1362	//////////////////////////
[789]	1363	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
[331]	1364	{
	1365	r_itlb.flush();
[789]	1366	r_dcache_xtn_req = false;
	1367	r_icache_fsm = ICACHE_IDLE;
[331]	1368	break;
	1369	}
	1370	////////////////////////////
[789]	1371	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
[331]	1372	// r_icache_flush_count as a slot counter,
[789]	1373	// looping in this state until all slots are visited.
[331]	1374	// It can require two cycles per slot:
	1375	// We test here the slot state, and make the actual inval
	1376	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
[789]	1377	// A cleanup request is generated for each valid line
[331]	1378	{
[468]	1379	// coherence clack interrupt
[789]	1380	if (r_icache_clack_req.read())
[468]	1381	{
	1382	r_icache_fsm = ICACHE_CC_CHECK;
	1383	r_icache_fsm_save = r_icache_fsm.read();
	1384	break;
	1385	}
	1386
[384]	1387	// coherence request (from CC_RECEIVE FSM)
[789]	1388	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[384]	1389	{
	1390	r_icache_fsm = ICACHE_CC_CHECK;
	1391	r_icache_fsm_save = r_icache_fsm.read();
	1392	break;
	1393	}
	1394
[789]	1395	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
[331]	1396	{
[789]	1397	int state;
	1398	paddr_t tag;
[836]	1399	size_t way = r_icache_flush_count.read() / m_icache_sets;
	1400	size_t set = r_icache_flush_count.read() % m_icache_sets;
[331]	1401
[1041]	1402	if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways)) // last slot
	1403	{
	1404	r_dcache_xtn_req = false;
	1405	m_drsp.valid = true;
	1406	r_icache_fsm = ICACHE_IDLE;
	1407	break;
	1408	}
	1409
	1410
[331]	1411	#ifdef INSTRUMENTATION
[789]	1412	m_cpt_icache_dir_read++;
[331]	1413	#endif
[789]	1414	r_icache.read_dir(way,
	1415	set,
	1416	&tag,
	1417	&state);
[331]	1418
[789]	1419	if (state == CACHE_SLOT_STATE_VALID) // inval required
[331]	1420	{
	1421	// request cleanup
	1422	r_icache_cc_send_req = true;
[384]	1423	r_icache_cc_send_nline = tag * m_icache_sets + set;
[331]	1424	r_icache_cc_send_way = way;
	1425	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	1426
	1427	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
[789]	1428	r_icache_miss_way = way;
	1429	r_icache_miss_set = set;
	1430	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
[331]	1431	}
[1041]	1432	else {
	1433	// saturation counter, to have the same last slot condition
	1434	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
[331]	1435	r_icache_flush_count = r_icache_flush_count.read() + 1;
	1436	}
	1437	}
	1438	break;
	1439	}
	1440	///////////////////////////////
[789]	1441	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
[331]	1442	{
[789]	1443	size_t way = r_icache_miss_way.read();
	1444	size_t set = r_icache_miss_set.read();
[331]	1445
	1446	#ifdef INSTRUMENTATION
[789]	1447	m_cpt_icache_dir_write++;
[331]	1448	#endif
	1449
[789]	1450	r_icache.write_dir(way,
	1451	set,
	1452	CACHE_SLOT_STATE_ZOMBI);
[331]	1453
[1041]	1454	if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways - 1)) // last slot
[331]	1455	{
[789]	1456	r_icache_fsm = ICACHE_IDLE;
[1041]	1457	break;
[331]	1458	}
[1041]	1459	r_icache_flush_count = r_icache_flush_count.read() + 1;
	1460	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
[331]	1461	break;
	1462	}
	1463
	1464	//////////////////////////
[789]	1465	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
	1466	// stored in the r_dcache_save_wdata register
[331]	1467	{
	1468	r_itlb.inval(r_dcache_save_wdata.read());
[789]	1469	r_dcache_xtn_req = false;
	1470	r_icache_fsm = ICACHE_IDLE;
[331]	1471	break;
	1472	}
	1473	///////////////////////////////
[789]	1474	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
[331]	1475	// requires 3 cycles (in case of hit on itlb and icache).
[789]	1476	// In this state, access TLB to translate virtual address
	1477	// stored in the r_dcache_save_wdata register.
[331]	1478	{
[789]	1479	paddr_t paddr;
	1480	bool hit;
[331]	1481
	1482	// read physical address in TLB when MMU activated
[789]	1483	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
[331]	1484	{
	1485
	1486	#ifdef INSTRUMENTATION
[789]	1487	m_cpt_itlb_read++;
[331]	1488	#endif
[789]	1489	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
[331]	1490	}
[789]	1491	else // itlb not activated
[331]	1492	{
[789]	1493	paddr = (paddr_t) r_dcache_save_wdata.read();
	1494	hit = true;
[331]	1495	}
	1496
[789]	1497	if (hit) // continue the selective inval process
[331]	1498	{
[789]	1499	r_icache_vci_paddr = paddr;
	1500	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
[331]	1501	}
[789]	1502	else // miss : send a request to DCACHE FSM
[331]	1503	{
	1504
	1505	#ifdef INSTRUMENTATION
[789]	1506	m_cpt_itlb_miss++;
[331]	1507	#endif
	1508	r_icache_tlb_miss_req = true;
[789]	1509	r_icache_vaddr_save = r_dcache_save_wdata.read();
[331]	1510	r_icache_fsm = ICACHE_TLB_WAIT;
	1511	}
	1512	break;
	1513	}
	1514	///////////////////////////////
[789]	1515	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
[331]	1516	// require 2 cycles. In this state, we read directory
	1517	// with address stored in r_icache_vci_paddr register.
	1518	{
[789]	1519	int state;
	1520	size_t way;
	1521	size_t set;
	1522	size_t word;
[331]	1523
	1524	#ifdef INSTRUMENTATION
[789]	1525	m_cpt_icache_dir_read++;
[331]	1526	#endif
	1527	r_icache.read_dir(r_icache_vci_paddr.read(),
	1528	&state,
	1529	&way,
	1530	&set,
	1531	&word);
	1532
[789]	1533	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
[331]	1534	{
	1535	r_icache_miss_way = way;
	1536	r_icache_miss_set = set;
	1537	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
	1538	}
[789]	1539	else // miss : acknowlege the XTN request and return
[331]	1540	{
	1541	r_dcache_xtn_req = false;
	1542	r_icache_fsm = ICACHE_IDLE;
	1543	}
	1544	break;
	1545	}
	1546	///////////////////////////////
	1547	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
	1548	{
[789]	1549	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
[331]	1550	{
	1551
	1552	#ifdef INSTRUMENTATION
[789]	1553	m_cpt_icache_dir_write++;
[331]	1554	#endif
[789]	1555	r_icache.write_dir(r_icache_miss_way.read(),
	1556	r_icache_miss_set.read(),
	1557	CACHE_SLOT_STATE_ZOMBI);
[331]	1558
	1559	// request cleanup
	1560	r_icache_cc_send_req = true;
[789]	1561	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
[331]	1562	r_icache_cc_send_way = r_icache_miss_way.read();
	1563	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	1564
	1565	// acknowledge the XTN request and return
[789]	1566	r_dcache_xtn_req = false;
	1567	r_icache_fsm = ICACHE_IDLE;
[331]	1568	}
	1569	break;
	1570	}
	1571	////////////////////////
	1572	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
	1573	// Waiting in this state if no slot available.
[816]	1574	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
	1575	// we send the cleanup request in this state.
[487]	1576	// If not, a r_icache_cleanup_victim_req flip-flop is
	1577	// utilized for saving this cleanup request, and it will be sent later
[816]	1578	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
[487]	1579	// The r_icache_miss_clack flip-flop is set
[331]	1580	// when a cleanup is required
	1581	{
	1582	if (m_ireq.valid) m_cost_ins_miss_frz++;
	1583
[468]	1584	// coherence clack interrupt
[789]	1585	if (r_icache_clack_req.read())
[468]	1586	{
	1587	r_icache_fsm = ICACHE_CC_CHECK;
	1588	r_icache_fsm_save = r_icache_fsm.read();
	1589	break;
	1590	}
	1591
[331]	1592	// coherence interrupt
[789]	1593	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1594	{
	1595	r_icache_fsm = ICACHE_CC_CHECK;
	1596	r_icache_fsm_save = r_icache_fsm.read();
	1597	break;
	1598	}
	1599
	1600
[789]	1601	bool found;
	1602	bool cleanup;
	1603	size_t way;
	1604	size_t set;
	1605	paddr_t victim;
[487]	1606
[331]	1607	#ifdef INSTRUMENTATION
[789]	1608	m_cpt_icache_dir_read++;
[331]	1609	#endif
[487]	1610	r_icache.read_select(r_icache_vci_paddr.read(),
	1611	&victim,
	1612	&way,
	1613	&set,
	1614	&found,
[789]	1615	&cleanup);
	1616	if (not found)
[487]	1617	{
	1618	break;
	1619	}
	1620	else
	1621	{
[789]	1622	r_icache_miss_way = way;
	1623	r_icache_miss_set = set;
[487]	1624
[789]	1625	if (cleanup)
[331]	1626	{
[789]	1627	if (not r_icache_cc_send_req.read())
[331]	1628	{
[789]	1629	r_icache_cc_send_req = true;
	1630	r_icache_cc_send_nline = victim;
	1631	r_icache_cc_send_way = way;
[816]	1632	r_icache_cc_send_type = CC_TYPE_CLEANUP;
[331]	1633	}
	1634	else
	1635	{
[487]	1636	r_icache_cleanup_victim_req = true;
	1637	r_icache_cleanup_victim_nline = victim;
[331]	1638	}
	1639
[789]	1640	r_icache_miss_clack = true;
	1641	r_icache_fsm = ICACHE_MISS_CLEAN;
[487]	1642	}
	1643	else
	1644	{
[789]	1645	r_icache_fsm = ICACHE_MISS_WAIT;
[487]	1646	}
	1647
[331]	1648	#if DEBUG_ICACHE
[789]	1649	if (m_debug_icache_fsm)
	1650	{
	1651	std::cout << " <PROC " << name()
	1652	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
	1653	<< " / WAY = " << way
	1654	<< " / SET = " << set;
	1655	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
	1656	else std::cout << std::endl;
	1657	}
[331]	1658	#endif
	1659	}
	1660	break;
	1661	}
	1662	///////////////////////
[789]	1663	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
[331]	1664	{
	1665	if (m_ireq.valid) m_cost_ins_miss_frz++;
	1666
	1667	#ifdef INSTRUMENTATION
[789]	1668	m_cpt_icache_dir_write++;
[331]	1669	#endif
[789]	1670	r_icache.write_dir(r_icache_miss_way.read(),
	1671	r_icache_miss_set.read(),
	1672	CACHE_SLOT_STATE_ZOMBI);
[331]	1673	#if DEBUG_ICACHE
[789]	1674	if (m_debug_icache_fsm)
	1675	{
	1676	std::cout << " <PROC " << name()
	1677	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
	1678	<< " / WAY = " << r_icache_miss_way.read()
	1679	<< " / SET = " << r_icache_miss_set.read() << std::endl;
	1680	}
[331]	1681	#endif
	1682
	1683	r_icache_fsm = ICACHE_MISS_WAIT;
	1684	break;
	1685	}
	1686	//////////////////////
[789]	1687	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
[331]	1688	{
	1689	if (m_ireq.valid) m_cost_ins_miss_frz++;
	1690
[487]	1691	// send cleanup victim request
[789]	1692	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
[487]	1693	{
	1694	r_icache_cc_send_req = true;
	1695	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
	1696	r_icache_cc_send_way = r_icache_miss_way;
[816]	1697	r_icache_cc_send_type = CC_TYPE_CLEANUP;
[487]	1698	r_icache_cleanup_victim_req = false;
[816]	1699	}
[468]	1700
[488]	1701	// coherence clack interrupt
[789]	1702	if (r_icache_clack_req.read())
[488]	1703	{
	1704	r_icache_fsm = ICACHE_CC_CHECK;
	1705	r_icache_fsm_save = r_icache_fsm.read();
	1706	break;
	1707	}
[816]	1708
[331]	1709	// coherence interrupt
[789]	1710	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
[331]	1711	{
	1712	r_icache_fsm = ICACHE_CC_CHECK;
	1713	r_icache_fsm_save = r_icache_fsm.read();
	1714	break;
	1715	}
	1716
[789]	1717	if (r_vci_rsp_ins_error.read()) // bus error
[331]	1718	{
	1719	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
	1720	r_mmu_ibvar = r_icache_vaddr_save.read();
	1721	m_irsp.valid = true;
	1722	m_irsp.error = true;
	1723	r_vci_rsp_ins_error = false;
	1724	r_icache_fsm = ICACHE_IDLE;
	1725	}
[789]	1726	else if (r_vci_rsp_fifo_icache.rok()) // response available
[331]	1727	{
	1728	r_icache_miss_word = 0;
	1729	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
	1730	}
	1731	break;
	1732	}
	1733	///////////////////////////
[789]	1734	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
[331]	1735	{
[789]	1736	if (m_ireq.valid) m_cost_ins_miss_frz++;
[331]	1737
[789]	1738	if (r_vci_rsp_fifo_icache.rok()) // response available
[331]	1739	{
	1740
	1741	#ifdef INSTRUMENTATION
[789]	1742	m_cpt_icache_data_write++;
[331]	1743	#endif
[789]	1744	r_icache.write(r_icache_miss_way.read(),
	1745	r_icache_miss_set.read(),
	1746	r_icache_miss_word.read(),
	1747	r_vci_rsp_fifo_icache.read());
[331]	1748	#if DEBUG_ICACHE
[789]	1749	if (m_debug_icache_fsm)
	1750	{
	1751	std::cout << " <PROC " << name()
	1752	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
	1753	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
	1754	<< " WAY = " << r_icache_miss_way.read()
	1755	<< " SET = " << r_icache_miss_set.read()
	1756	<< " WORD = " << r_icache_miss_word.read() << std::endl;
	1757	}
[331]	1758	#endif
	1759	vci_rsp_fifo_icache_get = true;
	1760	r_icache_miss_word = r_icache_miss_word.read() + 1;
	1761
[789]	1762	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
[331]	1763	{
	1764	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
	1765	}
	1766	}
	1767	break;
	1768	}
	1769	//////////////////////////
[789]	1770	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
[331]	1771	// and the cleanup ack has not been received,
	1772	// as indicated by r_icache_miss_clack.
	1773	// - If no matching coherence request (r_icache_miss_inval)
	1774	// switch directory slot to VALID state.
	1775	// - If matching coherence request, switch directory slot
	1776	// to ZOMBI state, and send a cleanup request.
	1777	{
[789]	1778	if (m_ireq.valid ) m_cost_ins_miss_frz++;
[331]	1779
[487]	1780	// send cleanup victim request
[789]	1781	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
[487]	1782	{
	1783	r_icache_cc_send_req = true;
	1784	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
	1785	r_icache_cc_send_way = r_icache_miss_way;
[816]	1786	r_icache_cc_send_type = CC_TYPE_CLEANUP;
[487]	1787	r_icache_cleanup_victim_req = false;
[816]	1788	}
[487]	1789
[488]	1790	// coherence clack interrupt
[789]	1791	if (r_icache_clack_req.read())
[488]	1792	{
	1793	r_icache_fsm = ICACHE_CC_CHECK;
	1794	r_icache_fsm_save = r_icache_fsm.read();
	1795	break;
	1796	}
	1797
[331]	1798	// coherence interrupt
[789]	1799	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
[331]	1800	{
	1801	r_icache_fsm = ICACHE_CC_CHECK;
	1802	r_icache_fsm_save = r_icache_fsm.read();
	1803	break;
	1804	}
	1805
[789]	1806	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
[331]	1807	{
[789]	1808	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
[331]	1809	{
[789]	1810	if (not r_icache_cc_send_req.read())
[331]	1811	{
	1812	r_icache_miss_inval = false;
	1813	// request cleanup
	1814	r_icache_cc_send_req = true;
[789]	1815	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
[331]	1816	r_icache_cc_send_way = r_icache_miss_way.read();
	1817	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	1818
	1819	#ifdef INSTRUMENTATION
[789]	1820	m_cpt_icache_dir_write++;
[331]	1821	#endif
[789]	1822	r_icache.write_dir(r_icache_vci_paddr.read(),
	1823	r_icache_miss_way.read(),
	1824	r_icache_miss_set.read(),
	1825	CACHE_SLOT_STATE_ZOMBI);
[331]	1826	#if DEBUG_ICACHE
[789]	1827	if (m_debug_icache_fsm)
	1828	{
	1829	std::cout << " <PROC " << name()
	1830	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
	1831	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
	1832	<< " WAY = " << std::dec << r_icache_miss_way.read()
	1833	<< " SET = " << r_icache_miss_set.read() << std::endl;
	1834	}
[331]	1835	#endif
	1836	}
	1837	else
	1838	break;
	1839	}
[789]	1840	else // Switch slot to VALID state
[331]	1841	{
	1842
	1843	#ifdef INSTRUMENTATION
[789]	1844	m_cpt_icache_dir_write++;
[331]	1845	#endif
[789]	1846	r_icache.write_dir(r_icache_vci_paddr.read(),
	1847	r_icache_miss_way.read(),
	1848	r_icache_miss_set.read(),
	1849	CACHE_SLOT_STATE_VALID);
[331]	1850	#if DEBUG_ICACHE
[789]	1851	if (m_debug_icache_fsm)
	1852	{
	1853	std::cout << " <PROC " << name()
	1854	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
	1855	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
	1856	<< " WAY = " << std::dec << r_icache_miss_way.read()
	1857	<< " SET = " << r_icache_miss_set.read() << std::endl;
	1858	}
[331]	1859	#endif
	1860	}
	1861
	1862	r_icache_fsm = ICACHE_IDLE;
	1863	}
	1864	break;
	1865	}
	1866	////////////////////
[789]	1867	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
[331]	1868	{
[468]	1869	// coherence clack interrupt
[789]	1870	if (r_icache_clack_req.read())
[468]	1871	{
[789]	1872	r_icache_fsm = ICACHE_CC_CHECK;
[468]	1873	r_icache_fsm_save = r_icache_fsm.read();
	1874	break;
	1875	}
	1876
[331]	1877	// coherence interrupt
[789]	1878	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1879	{
[789]	1880	r_icache_fsm = ICACHE_CC_CHECK;
[331]	1881	r_icache_fsm_save = r_icache_fsm.read();
	1882	break;
	1883	}
	1884
[789]	1885	if (r_vci_rsp_ins_error.read()) // bus error
[331]	1886	{
	1887	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
	1888	r_mmu_ibvar = m_ireq.addr;
	1889	r_vci_rsp_ins_error = false;
	1890	m_irsp.valid = true;
	1891	m_irsp.error = true;
	1892	r_icache_fsm = ICACHE_IDLE;
	1893	}
[789]	1894	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
[331]	1895	{
	1896	vci_rsp_fifo_icache_get = true;
	1897	r_icache_fsm = ICACHE_IDLE;
[789]	1898	if (m_ireq.valid and
	1899	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
[331]	1900	{
	1901	m_irsp.valid = true;
	1902	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
	1903	}
	1904	}
	1905	break;
	1906	}
	1907	/////////////////////
[789]	1908	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
	1909	// handling coherence requests.
	1910	// if there is a matching pending miss, it is
	1911	// signaled in the r_icache_miss_inval flip-flop.
	1912	// The return state is defined in r_icache_fsm_save.
[331]	1913	{
[789]	1914	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
	1915	paddr_t mask = ~((m_icache_words << 2) - 1);
[331]	1916
[484]	1917	// CLACK handler
	1918	// We switch the directory slot to EMPTY state
	1919	// and reset r_icache_miss_clack if the cleanup ack
	1920	// is matching a pending miss.
[789]	1921	if (r_icache_clack_req.read())
[484]	1922	{
[331]	1923
[789]	1924	if (m_ireq.valid) m_cost_ins_miss_frz++;
[484]	1925
	1926	#ifdef INSTRUMENTATION
[789]	1927	m_cpt_icache_dir_write++;
[484]	1928	#endif
[789]	1929	r_icache.write_dir(0,
	1930	r_icache_clack_way.read(),
	1931	r_icache_clack_set.read(),
	1932	CACHE_SLOT_STATE_EMPTY);
[484]	1933
[789]	1934	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
	1935	(r_icache_miss_way.read() == r_icache_clack_way.read()))
[484]	1936	{
	1937	r_icache_miss_clack = false;
	1938	}
	1939
	1940	r_icache_clack_req = false;
	1941
	1942	// return to cc_save state
	1943	r_icache_fsm = r_icache_fsm_save.read();
	1944
	1945	#if DEBUG_ICACHE
[789]	1946	if (m_debug_icache_fsm)
	1947	{
	1948	std::cout << " <PROC " << name()
	1949	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
	1950	<< " set = " << r_icache_clack_set.read()
	1951	<< " / way = " << r_icache_clack_way.read() << std::endl;
	1952	}
[484]	1953	#endif
	1954
	1955	break;
	1956	}
	1957
[789]	1958	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
[487]	1959
[468]	1960	// Match between MISS address and CC address
	1961	if (r_cc_receive_icache_req.read() and
[789]	1962	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
	1963	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
[468]	1964	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
[789]	1965	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
[331]	1966	{
	1967	// signaling the matching
[789]	1968	r_icache_miss_inval = true;
[331]	1969
	1970	// in case of update, go to CC_UPDT
	1971	// JUST TO POP THE FIFO
	1972	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
	1973	{
[789]	1974	r_icache_fsm = ICACHE_CC_UPDT;
	1975	r_icache_cc_word = r_cc_receive_word_idx.read();
[468]	1976
[331]	1977	// just pop the fifo , don't write in icache
	1978	r_icache_cc_need_write = false;
	1979	}
	1980	// the request is dealt with
	1981	else
	1982	{
	1983	r_cc_receive_icache_req = false;
[789]	1984	r_icache_fsm = r_icache_fsm_save.read();
[331]	1985	}
	1986	#if DEBUG_ICACHE
[789]	1987	if (m_debug_icache_fsm)
	1988	{
	1989	std::cout << " <PROC " << name()
	1990	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
	1991	<< " PADDR = " << std::hex << paddr << std::endl;
	1992	}
[331]	1993	#endif
	1994	}
[468]	1995
	1996	// CC request handler
	1997
[789]	1998	int state = 0;
	1999	size_t way = 0;
	2000	size_t set = 0;
	2001	size_t word = 0;
[468]	2002
[331]	2003	#ifdef INSTRUMENTATION
[789]	2004	m_cpt_icache_dir_read++;
[331]	2005	#endif
[468]	2006	r_icache.read_dir(paddr,
	2007	&state,
	2008	&way,
	2009	&set,
	2010	&word);
	2011
	2012	r_icache_cc_way = way;
	2013	r_icache_cc_set = set;
	2014
[789]	2015	if (state == CACHE_SLOT_STATE_VALID) // hit
[331]	2016	{
[468]	2017	// need to update the cache state
	2018	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
	2019	{
	2020	r_icache_cc_need_write = true;
[789]	2021	r_icache_fsm = ICACHE_CC_UPDT;
	2022	r_icache_cc_word = r_cc_receive_word_idx.read();
[468]	2023	}
[789]	2024	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
[468]	2025	{
[789]	2026	r_icache_fsm = ICACHE_CC_INVAL;
[468]	2027	}
[331]	2028	}
[468]	2029	else // miss
[331]	2030	{
[468]	2031	// multicast acknowledgement required in case of update
[789]	2032	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
[468]	2033	{
[789]	2034	r_icache_fsm = ICACHE_CC_UPDT;
	2035	r_icache_cc_word = r_cc_receive_word_idx.read();
[331]	2036
[468]	2037	// just pop the fifo , don't write in icache
	2038	r_icache_cc_need_write = false;
	2039	}
	2040	else // No response needed
	2041	{
	2042	r_cc_receive_icache_req = false;
[789]	2043	r_icache_fsm = r_icache_fsm_save.read();
[468]	2044	}
[331]	2045	}
	2046	break;
	2047	}
[468]	2048	/////////////////////
[789]	2049	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
[331]	2050	{
[468]	2051	assert (not r_icache_cc_send_req.read() &&
	2052	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
	2053	"must not be set");
[331]	2054
[468]	2055	#ifdef INSTRUMENTATION
[789]	2056	m_cpt_icache_dir_read++;
[468]	2057	#endif
	2058
[816]	2059	// Switch slot state to ZOMBI and send CLEANUP command
[789]	2060	r_icache.write_dir(r_icache_cc_way.read(),
	2061	r_icache_cc_set.read(),
	2062	CACHE_SLOT_STATE_ZOMBI);
[468]	2063
	2064	// coherence request completed
	2065	r_icache_cc_send_req = true;
	2066	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
	2067	r_icache_cc_send_way = r_icache_cc_way.read();
	2068	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	2069
[789]	2070	r_icache_fsm = r_icache_fsm_save.read();
[468]	2071
[331]	2072	#if DEBUG_ICACHE
[789]	2073	if (m_debug_icache_fsm)
	2074	{
	2075	std::cout << " <PROC " << name()
	2076	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
	2077	<< " set = " << r_icache_cc_set.read()
	2078	<< " / way = " << r_icache_cc_way.read() << std::endl;
	2079	}
[331]	2080	#endif
	2081
[468]	2082	break;
	2083	}
	2084	////////////////////
[789]	2085	case ICACHE_CC_UPDT: // hit update : write one word per cycle
[468]	2086	{
	2087	assert (not r_icache_cc_send_req.read() &&
	2088	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
	2089	"must not be set");
	2090
[789]	2091	if (not r_cc_receive_updt_fifo_be.rok()) break;
[468]	2092
	2093
[789]	2094	size_t word = r_icache_cc_word.read();
	2095	size_t way = r_icache_cc_way.read();
	2096	size_t set = r_icache_cc_set.read();
[331]	2097
[468]	2098	if (r_icache_cc_need_write.read())
[331]	2099	{
[789]	2100	r_icache.write(way,
	2101	set,
	2102	word,
	2103	r_cc_receive_updt_fifo_data.read(),
	2104	r_cc_receive_updt_fifo_be.read());
[331]	2105
[789]	2106	r_icache_cc_word = word + 1;
[331]	2107
[468]	2108	#ifdef INSTRUMENTATION
[789]	2109	m_cpt_icache_data_write++;
[468]	2110	#endif
[331]	2111
	2112	#if DEBUG_ICACHE
[789]	2113	if (m_debug_icache_fsm)
	2114	{
	2115	std::cout << " <PROC " << name()
	2116	<< " ICACHE_CC_UPDT> Write one word "
	2117	<< " set = " << r_icache_cc_set.read()
	2118	<< " / way = " << r_icache_cc_way.read()
	2119	<< " / word = " << r_icache_cc_word.read() << std::endl;
	2120	}
[331]	2121	#endif
[468]	2122	}
[331]	2123
[789]	2124	if (r_cc_receive_updt_fifo_eop.read()) // last word
[331]	2125	{
	2126	// no need to write in the cache anymore
[789]	2127	r_icache_cc_need_write = false;
[331]	2128
	2129	// coherence request completed
[789]	2130	r_cc_receive_icache_req = false;
[331]	2131
[468]	2132	// request multicast acknowledgement
	2133	r_icache_cc_send_req = true;
	2134	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
	2135	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
	2136	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
	2137
[789]	2138	r_icache_fsm = r_icache_fsm_save.read();
[331]	2139	}
[468]	2140	//consume fifo if not eop
[789]	2141	cc_receive_updt_fifo_get = true;
[468]	2142
[331]	2143	break;
	2144	}
[468]	2145
[331]	2146	} // end switch r_icache_fsm
	2147
	2148	////////////////////////////////////////////////////////////////////////////////////
	2149	// DCACHE FSM
	2150	//
	2151	// 1/ Coherence operations
	2152	// They are handled as interrupts generated by the CC_RECEIVE FSM.
	2153	// - There is a coherence request when r_tgt_dcache_req is set.
	2154	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
	2155	// and SC_WAIT states.
	2156	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
	2157	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
	2158	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
	2159	// - For both types of requests, actions associated to the pre-empted state
	2160	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
	2161	// or CC_CLACK) to execute the requested coherence operation, and returns
	2162	// to the pre-empted state.
	2163	//
	2164	// 2/ TLB miss
	2165	// The page tables are generally cacheable.
	2166	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
	2167	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
	2168	// this sub-fsm implement the table-walk...
	2169	//
	2170	// 3/ processor requests
	2171	// Processor requests are taken in IDLE state only.
	2172	// The IDLE state implements a two stages pipe-line to handle write bursts:
	2173	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
	2174	// - The registration in wbuf and the dcache update is done in stage P1
	2175	// (if the processor request is a write).
	2176	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
	2177	// the operations that must be done in P1 stage, and the access type
	2178	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
	2179	// READ requests are delayed if a cache update is requested.
	2180	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
	2181	// that is done (before handling the processor request) by a dedicated sub-fsm.
	2182	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
	2183	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
	2184	//
	2185	// 4/ Atomic instructions LL/SC
	2186	// The LL/SC address are non cacheable (systematic access to memory).
	2187	// The llsc buffer contains a registration for an active LL/SC operation
	2188	// (with an address, a registration key, an aging counter and a valid bit).
	2189	// - LL requests from the processor are transmitted as a one flit VCI command
	2190	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
	2191	// be 8 as the response is 2 flits long (data and registration key)
	2192	// - SC requests from the processor are systematically transmitted to the
	2193	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
	2194	// as PKTID value). The first flit contains the registration key, the second
	2195	// flit contains the data to write in case of success.
	2196	// The cache is not updated, as this is done in case of success by the
	2197	// coherence transaction.
	2198	//
	2199	// 5/ Non cacheable access:
	2200	// This component implement a strong order between non cacheable access
	2201	// (read or write) : A new non cacheable VCI transaction starts only when
[616]	2202	// the previous non cacheable transaction is completed. After send the VCI
	2203	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
	2204	// So the processor is blocked until the respone arrives in CACHE L1.
[331]	2205	//
	2206	// 6/ Error handling:
	2207	// When the MMU is not activated, Read Bus Errors are synchronous events,
[816]	2208	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
	2209	// but some Write Bus Errors are asynchronous events when the request is cacheable access
[616]	2210	// (processor is not frozen).
	2211	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
[331]	2212	// r_vci_rsp_data_error flip-flop, without writing any data in the
	2213	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
	2214	// by the DCACHE FSM.
[816]	2215	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
[616]	2216	// the asynchronous error using the setWriteBerr() method.
[331]	2217	// When the MMU is activated bus error are rare events, as the MMU
	2218	// checks the physical address before the VCI transaction starts.
	2219	////////////////////////////////////////////////////////////////////////////////////////
	2220
	2221	// default value for m_drsp
	2222	m_drsp.valid = false;
	2223	m_drsp.error = false;
	2224	m_drsp.rdata = 0;
	2225
[789]	2226	switch (r_dcache_fsm.read())
[331]	2227	{
	2228	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
	2229	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
	2230	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
	2231	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
	2232	// 4) XTN request (processor) => DCACHE_XTN_*
	2233	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
	2234	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
	2235	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
[816]	2236	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
[331]	2237	// 9) LL access (processor) => DCACHE_LL_WAIT
	2238	// 10) SC access (processor) => DCACHE_SC_WAIT
	2239	//
	2240	// There is a fixed priority to handle requests to DCACHE:
	2241	// 1/ the ITLB/DTLB invalidate requests
	2242	// 2/ the coherence requests,
	2243	// 3/ the processor requests (including DTLB miss),
	2244	// 4/ the ITLB miss requests,
	2245	// The address space processor request are handled as follows:
	2246	// - WRITE request is blocked if the Dirty bit mus be set.
	2247	// If DTLB hit, the P1 stage is activated (writes WBUF, and
	2248	// updates DCACHE if DCACHE hit) & processor request acknowledged.
	2249	// - READ request generate a simultaneouss access to DCACHE.DATA
	2250	// and DCACHE.DIR, but is delayed if DCACHE update required.
	2251	//
	2252	// There is 4 configurations defining the access type to
	2253	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
	2254	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
	2255	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
	2256	// 0 / 0 / NOP / NOP / NOP /
	2257	// 0 / 1 / NOP / NOP / WRITE /
	2258	// 1 / 0 / READ / READ / NOP /
	2259	// 1 / 1 / READ / READ / WRITE /
	2260	// Those two registers are set at each cycle from the 3 signals
	2261	// updt_request, wbuf_request, wbuf_write_miss.
	2262	{
[789]	2263	paddr_t paddr;
	2264	pte_info_t tlb_flags;
	2265	size_t tlb_way;
	2266	size_t tlb_set;
	2267	paddr_t tlb_nline = 0;
	2268	size_t cache_way;
	2269	size_t cache_set;
	2270	size_t cache_word;
	2271	uint32_t cache_rdata = 0;
	2272	bool tlb_hit = false;
	2273	int cache_state = CACHE_SLOT_STATE_EMPTY;
[331]	2274
[789]	2275	bool tlb_inval_required = false; // request TLB inval after cache update
	2276	bool wbuf_write_miss = false; // miss a WBUF write request
	2277	bool updt_request = false; // request DCACHE update in P1 stage
	2278	bool wbuf_request = false; // request WBUF write in P1 stage
[331]	2279
[789]	2280	// physical address computation : systematic DTLB access if activated
[752]	2281	paddr = (paddr_t) m_dreq.addr;
[789]	2282	if (m_dreq.valid)
[331]	2283	{
[789]	2284	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
[331]	2285	{
[789]	2286	tlb_hit = r_dtlb.translate(m_dreq.addr,
	2287	&paddr,
	2288	&tlb_flags,
	2289	&tlb_nline,
	2290	&tlb_way,
	2291	&tlb_set);
[331]	2292	#ifdef INSTRUMENTATION
[789]	2293	m_cpt_dtlb_read++;
[331]	2294	#endif
	2295	}
[789]	2296	else // identity mapping
[331]	2297	{
[394]	2298	// we take into account the paddr extension
[816]	2299	if (vci_param::N > 32)
[789]	2300	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
[331]	2301	}
	2302	} // end physical address computation
	2303
	2304	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
[789]	2305	if (r_mmu_mode.read() & DATA_CACHE_MASK)
[331]	2306	{
[752]	2307
[789]	2308	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
[331]	2309	{
[789]	2310	r_dcache.read_dir(paddr,
	2311	&cache_state,
	2312	&cache_way,
	2313	&cache_set,
	2314	&cache_word);
[331]	2315
[789]	2316	r_dcache.write(r_dcache_save_cache_way.read(),
	2317	r_dcache_save_cache_set.read(),
	2318	r_dcache_save_cache_word.read(),
	2319	r_dcache_save_wdata.read(),
	2320	r_dcache_save_be.read());
[331]	2321	#ifdef INSTRUMENTATION
[789]	2322	m_cpt_dcache_dir_read++;
	2323	m_cpt_dcache_data_write++;
[331]	2324	#endif
	2325	}
[789]	2326	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
[331]	2327	{
[789]	2328	r_dcache.read(paddr,
	2329	&cache_rdata,
	2330	&cache_way,
	2331	&cache_set,
	2332	&cache_word,
	2333	&cache_state);
[366]	2334
[331]	2335	#ifdef INSTRUMENTATION
[789]	2336	m_cpt_dcache_dir_read++;
	2337	m_cpt_dcache_data_read++;
[331]	2338	#endif
	2339	}
[789]	2340	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
[331]	2341	{
[789]	2342	r_dcache.write(r_dcache_save_cache_way.read(),
	2343	r_dcache_save_cache_set.read(),
	2344	r_dcache_save_cache_word.read(),
	2345	r_dcache_save_wdata.read(),
	2346	r_dcache_save_be.read());
[331]	2347	#ifdef INSTRUMENTATION
[789]	2348	m_cpt_dcache_data_write++;
[331]	2349	#endif
	2350	}
	2351	} // end dcache access
	2352
	2353	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
[789]	2354	if (r_dcache_updt_req.read())
[331]	2355	{
	2356	size_t way = r_dcache_save_cache_way.read();
	2357	size_t set = r_dcache_save_cache_set.read();
	2358
[789]	2359	if (r_dcache_in_tlb[way * m_dcache_sets + set])
[331]	2360	{
[789]	2361	tlb_inval_required = true;
	2362	r_dcache_tlb_inval_set = 0;
	2363	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
	2364	(uint32_log2(m_dcache_words << 2));
	2365	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[331]	2366	}
[789]	2367	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
[331]	2368	{
	2369	r_itlb.reset();
	2370	r_dtlb.reset();
[789]	2371	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	2372	}
	2373
	2374	#if DEBUG_DCACHE
[789]	2375	if (m_debug_dcache_fsm)
	2376	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2377	<< " Cache update in P1 stage" << std::dec
	2378	<< " / WAY = " << r_dcache_save_cache_way.read()
	2379	<< " / SET = " << r_dcache_save_cache_set.read()
	2380	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
	2381	<< " / WDATA = " << r_dcache_save_wdata.read()
	2382	<< " / BE = " << r_dcache_save_be.read() << std::endl;
[331]	2383	#endif
	2384	} // end test TLB inval
	2385
	2386	// Try WBUF update in P1 stage
	2387	// Miss if the write request is non cacheable, and there is a pending
	2388	// non cacheable write, or if the write buffer is full.
[789]	2389	if (r_dcache_wbuf_req.read())
[331]	2390	{
[789]	2391	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
	2392	r_dcache_save_be.read(),
	2393	r_dcache_save_wdata.read(),
	2394	true);
[331]	2395	#ifdef INSTRUMENTATION
[789]	2396	m_cpt_wbuf_write++;
[331]	2397	#endif
[789]	2398	if (not wok ) // miss if write buffer full
[616]	2399	{
	2400	wbuf_write_miss = true;
[331]	2401	}
	2402	} // end WBUF update
	2403
	2404	// Computing the response to processor,
	2405	// and the next value for r_dcache_fsm
	2406
	2407	// itlb/dtlb invalidation self-request
[789]	2408	if (tlb_inval_required)
[331]	2409	{
	2410	r_dcache_fsm_scan_save = r_dcache_fsm.read();
	2411	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
	2412	}
	2413
[468]	2414	// coherence clack request (from DSPIN CLACK)
[789]	2415	else if (r_dcache_clack_req.read())
[468]	2416	{
	2417	r_dcache_fsm = DCACHE_CC_CHECK;
	2418	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	2419	}
[331]	2420	// coherence request (from CC_RECEIVE FSM)
[789]	2421	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	2422	{
	2423	r_dcache_fsm = DCACHE_CC_CHECK;
	2424	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	2425	}
	2426
	2427	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
	2428	// we don't take the processor request, and registers
	2429	// are frozen in case of wbuf_write_miss
[789]	2430	else if (m_dreq.valid and not wbuf_write_miss)
[331]	2431	{
	2432	// register processor request and DCACHE response
	2433	r_dcache_save_vaddr = m_dreq.addr;
	2434	r_dcache_save_be = m_dreq.be;
	2435	r_dcache_save_wdata = m_dreq.wdata;
	2436	r_dcache_save_paddr = paddr;
	2437	r_dcache_save_cache_way = cache_way;
	2438	r_dcache_save_cache_set = cache_set;
	2439	r_dcache_save_cache_word = cache_word;
	2440
	2441	// READ XTN requests from processor
	2442	// They are executed in this DCACHE_IDLE state.
	2443	// The processor must not be in user mode
	2444	if (m_dreq.type == iss_t::XTN_READ)
	2445	{
[836]	2446	int xtn_opcode = (int) m_dreq.addr / 4;
[331]	2447
	2448	// checking processor mode:
	2449	if (m_dreq.mode == iss_t::MODE_USER)
	2450	{
	2451	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
	2452	r_mmu_dbvar = m_dreq.addr;
	2453	m_drsp.valid = true;
	2454	m_drsp.error = true;
	2455	m_drsp.rdata = 0;
	2456	r_dcache_fsm = DCACHE_IDLE;
	2457	}
	2458	else
	2459	{
[789]	2460	switch (xtn_opcode)
[331]	2461	{
	2462	case iss_t::XTN_INS_ERROR_TYPE:
	2463	m_drsp.rdata = r_mmu_ietr.read();
	2464	m_drsp.valid = true;
	2465	m_drsp.error = false;
	2466	break;
	2467
	2468	case iss_t::XTN_DATA_ERROR_TYPE:
	2469	m_drsp.rdata = r_mmu_detr.read();
	2470	m_drsp.valid = true;
	2471	m_drsp.error = false;
	2472	break;
	2473
	2474	case iss_t::XTN_INS_BAD_VADDR:
	2475	m_drsp.rdata = r_mmu_ibvar.read();
	2476	m_drsp.valid = true;
	2477	m_drsp.error = false;
	2478	break;
	2479
	2480	case iss_t::XTN_DATA_BAD_VADDR:
	2481	m_drsp.rdata = r_mmu_dbvar.read();
	2482	m_drsp.valid = true;
	2483	m_drsp.error = false;
	2484	break;
	2485
	2486	case iss_t::XTN_PTPR:
	2487	m_drsp.rdata = r_mmu_ptpr.read();
	2488	m_drsp.valid = true;
	2489	m_drsp.error = false;
	2490	break;
	2491
	2492	case iss_t::XTN_TLB_MODE:
	2493	m_drsp.rdata = r_mmu_mode.read();
	2494	m_drsp.valid = true;
	2495	m_drsp.error = false;
	2496	break;
	2497
	2498	case iss_t::XTN_MMU_PARAMS:
	2499	m_drsp.rdata = r_mmu_params;
	2500	m_drsp.valid = true;
	2501	m_drsp.error = false;
	2502	break;
	2503
	2504	case iss_t::XTN_MMU_RELEASE:
	2505	m_drsp.rdata = r_mmu_release;
	2506	m_drsp.valid = true;
	2507	m_drsp.error = false;
	2508	break;
	2509
	2510	case iss_t::XTN_MMU_WORD_LO:
	2511	m_drsp.rdata = r_mmu_word_lo.read();
	2512	m_drsp.valid = true;
	2513	m_drsp.error = false;
	2514	break;
	2515
	2516	case iss_t::XTN_MMU_WORD_HI:
	2517	m_drsp.rdata = r_mmu_word_hi.read();
	2518	m_drsp.valid = true;
	2519	m_drsp.error = false;
	2520	break;
	2521
[394]	2522	case iss_t::XTN_DATA_PADDR_EXT:
	2523	m_drsp.rdata = r_dcache_paddr_ext.read();
	2524	m_drsp.valid = true;
	2525	m_drsp.error = false;
	2526	break;
	2527
[721]	2528	case iss_t::XTN_INST_PADDR_EXT:
	2529	m_drsp.rdata = r_icache_paddr_ext.read();
	2530	m_drsp.valid = true;
	2531	m_drsp.error = false;
	2532	break;
	2533
[331]	2534	default:
[789]	2535	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
[331]	2536	r_mmu_dbvar = m_dreq.addr;
	2537	m_drsp.valid = true;
	2538	m_drsp.error = true;
	2539	m_drsp.rdata = 0;
	2540	break;
	2541	} // end switch xtn_opcode
	2542	} // end else
	2543	} // end if XTN_READ
	2544
	2545	// Handling WRITE XTN requests from processor.
	2546	// They are not executed in this DCACHE_IDLE state
	2547	// if they require access to the caches or the TLBs
	2548	// that are already accessed.
	2549	// Caches can be invalidated or flushed in user mode,
	2550	// and the sync instruction can be executed in user mode
	2551	else if (m_dreq.type == iss_t::XTN_WRITE)
	2552	{
[789]	2553	int xtn_opcode = (int)m_dreq.addr / 4;
[331]	2554	r_dcache_xtn_opcode = xtn_opcode;
	2555
	2556	// checking processor mode:
[789]	2557	if ((m_dreq.mode == iss_t::MODE_USER) &&
[366]	2558	(xtn_opcode != iss_t::XTN_SYNC) &&
[331]	2559	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
	2560	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
	2561	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
[789]	2562	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
[331]	2563	{
	2564	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
	2565	r_mmu_dbvar = m_dreq.addr;
	2566	m_drsp.valid = true;
	2567	m_drsp.error = true;
	2568	m_drsp.rdata = 0;
	2569	r_dcache_fsm = DCACHE_IDLE;
	2570	}
	2571	else
	2572	{
[789]	2573	switch (xtn_opcode)
[331]	2574	{
[789]	2575	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
[331]	2576	r_dcache_xtn_req = true;
	2577	r_dcache_fsm = DCACHE_XTN_SWITCH;
	2578	break;
	2579
[789]	2580	case iss_t::XTN_TLB_MODE: // no cache or tlb access
	2581	r_mmu_mode = m_dreq.wdata;
	2582	m_drsp.valid = true;
	2583	r_dcache_fsm = DCACHE_IDLE;
[331]	2584	break;
	2585
[789]	2586	case iss_t::XTN_DTLB_INVAL: // dtlb access
	2587	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
[331]	2588	break;
	2589
[789]	2590	case iss_t::XTN_ITLB_INVAL: // itlb access
[331]	2591	r_dcache_xtn_req = true;
	2592	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
	2593	break;
	2594
[789]	2595	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
	2596	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
[331]	2597	break;
	2598
[789]	2599	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
[970]	2600	{
	2601	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
	2602	((uint64_t)r_mmu_word_lo.read());
	2603
	2604	r_dcache_save_paddr = (paddr_t)pa;
[789]	2605	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
[331]	2606	break;
[970]	2607	}
[789]	2608	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
[331]	2609	r_dcache_flush_count = 0;
[789]	2610	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
[331]	2611	break;
	2612
[789]	2613	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
[331]	2614	r_dcache_xtn_req = true;
	2615	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
	2616	break;
	2617
[789]	2618	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
[331]	2619	r_dcache_xtn_req = true;
	2620	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
	2621	break;
	2622
[789]	2623	case iss_t::XTN_ICACHE_FLUSH: // icache access
[331]	2624	r_dcache_xtn_req = true;
	2625	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
	2626	break;
	2627
[789]	2628	case iss_t::XTN_SYNC: // wait until write buffer empty
	2629	r_dcache_fsm = DCACHE_XTN_SYNC;
[331]	2630	break;
	2631
[789]	2632	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
	2633	r_mmu_word_lo = m_dreq.wdata;
	2634	m_drsp.valid = true;
	2635	r_dcache_fsm = DCACHE_IDLE;
[331]	2636	break;
	2637
[789]	2638	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
	2639	r_mmu_word_hi = m_dreq.wdata;
	2640	m_drsp.valid = true;
	2641	r_dcache_fsm = DCACHE_IDLE;
[331]	2642	break;
	2643
[789]	2644	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
[331]	2645	r_dcache_llsc_valid = false;
[789]	2646	m_drsp.valid = true;
	2647	r_dcache_fsm = DCACHE_IDLE;
[331]	2648	break;
	2649
[789]	2650	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
[394]	2651	r_dcache_paddr_ext = m_dreq.wdata;
	2652	m_drsp.valid = true;
	2653	r_dcache_fsm = DCACHE_IDLE;
	2654	break;
	2655
[789]	2656	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
[721]	2657	r_dcache_xtn_req = true;
	2658	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
	2659	break;
	2660
[789]	2661	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
	2662	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
	2663	m_drsp.valid = true;
	2664	r_dcache_fsm = DCACHE_IDLE;
[721]	2665	break;
[331]	2666
[668]	2667	case iss_t::XTN_DEBUG_MASK: // debug mask
	2668	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
	2669	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
	2670	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
	2671	m_drsp.valid = true;
	2672	r_dcache_fsm = DCACHE_IDLE;
	2673	break;
	2674
[331]	2675	default:
	2676	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
	2677	r_mmu_dbvar = m_dreq.addr;
	2678	m_drsp.valid = true;
	2679	m_drsp.error = true;
	2680	r_dcache_fsm = DCACHE_IDLE;
	2681	break;
	2682	} // end switch xtn_opcode
	2683	} // end else
	2684	} // end if XTN_WRITE
	2685
	2686	// Handling processor requests to address space (READ/WRITE/LL/SC)
	2687	// The dtlb and dcache can be activated or not.
	2688	// We compute the cacheability, and check processor request validity:
	2689	// - If DTLB not activated : cacheability is defined by the segment table,
	2690	// and there is no access rights checking.
	2691	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
	2692	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
	2693	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
	2694	else
	2695	{
[789]	2696	bool valid_req;
	2697	bool cacheable;
[331]	2698
[789]	2699	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
[331]	2700	{
[789]	2701	valid_req = true;
[331]	2702
[789]	2703	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
[549]	2704	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
[331]	2705	}
[789]	2706	else // dtlb activated
[331]	2707	{
[789]	2708	if (tlb_hit) // tlb hit
[331]	2709	{
	2710	// cacheability
[789]	2711	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
[331]	2712	else cacheable = tlb_flags.c;
	2713
	2714	// access rights checking
[789]	2715	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
[331]	2716	{
[789]	2717	if ((m_dreq.type == iss_t::DATA_READ) or
	2718	(m_dreq.type == iss_t::DATA_LL))
[331]	2719	{
	2720	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
	2721	}
	2722	else
	2723	{
	2724	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
	2725	}
	2726	valid_req = false;
	2727	r_mmu_dbvar = m_dreq.addr;
	2728	m_drsp.valid = true;
	2729	m_drsp.error = true;
	2730	m_drsp.rdata = 0;
	2731	#if DEBUG_DCACHE
[789]	2732	if (m_debug_dcache_fsm)
	2733	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2734	<< " HIT in dtlb, but privilege violation" << std::endl;
[331]	2735	#endif
	2736	}
[789]	2737	else if (not tlb_flags.w and
[331]	2738	((m_dreq.type == iss_t::DATA_WRITE) or
[789]	2739	(m_dreq.type == iss_t::DATA_SC)))
[331]	2740	{
	2741	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
	2742	valid_req = false;
	2743	r_mmu_dbvar = m_dreq.addr;
	2744	m_drsp.valid = true;
	2745	m_drsp.error = true;
	2746	m_drsp.rdata = 0;
	2747	#if DEBUG_DCACHE
[789]	2748	if (m_debug_dcache_fsm)
	2749	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2750	<< " HIT in dtlb, but writable violation" << std::endl;
[331]	2751	#endif
	2752	}
	2753	else
	2754	{
[789]	2755	valid_req = true;
[331]	2756	}
	2757	}
[789]	2758	else // tlb miss
[331]	2759	{
[789]	2760	valid_req = false;
	2761	r_dcache_tlb_vaddr = m_dreq.addr;
	2762	r_dcache_tlb_ins = false;
	2763	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	2764	}
	2765	} // end DTLB activated
	2766
[789]	2767	if (valid_req) // processor request is valid (after MMU check)
[331]	2768	{
	2769	// READ request
	2770	// The read requests are taken only if there is no cache update.
	2771	// We request a VCI transaction to CMD FSM if miss or uncachable
[366]	2772
[789]	2773	if (((m_dreq.type == iss_t::DATA_READ))
	2774	and not r_dcache_updt_req.read())
[331]	2775	{
[789]	2776	if (cacheable) // cacheable read
[331]	2777	{
[789]	2778	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
[331]	2779	{
	2780	#ifdef INSTRUMENTATION
[789]	2781	m_cpt_dcache_miss++;
[331]	2782	#endif
	2783	// request a VCI DMISS transaction
	2784	r_dcache_vci_paddr = paddr;
	2785	r_dcache_vci_miss_req = true;
	2786	r_dcache_miss_type = PROC_MISS;
	2787	r_dcache_fsm = DCACHE_MISS_SELECT;
	2788	#if DEBUG_DCACHE
[789]	2789	if (m_debug_dcache_fsm)
	2790	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
[816]	2791	<< " READ MISS in dcache"
[789]	2792	<< " / PADDR = " << std::hex << paddr << std::endl;
[331]	2793	#endif
	2794	}
[789]	2795	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
[331]	2796	{
	2797	// stalled until cleanup is acknowledged
	2798	r_dcache_fsm = DCACHE_IDLE;
[394]	2799	#if DEBUG_DCACHE
[789]	2800	if (m_debug_dcache_fsm)
	2801	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2802	<< " Pending cleanup, stalled until cleanup acknowledge"
	2803	<< " / PADDR = " << std::hex << paddr << std::endl;
[394]	2804	#endif
[331]	2805	}
	2806	else // cache hit
	2807	{
	2808	#ifdef INSTRUMENTATION
[789]	2809	m_cpt_data_read++;
[331]	2810	#endif
	2811	// returns data to processor
[789]	2812	m_drsp.valid = true;
	2813	m_drsp.error = false;
	2814	m_drsp.rdata = cache_rdata;
[331]	2815	#if DEBUG_DCACHE
[789]	2816	if (m_debug_dcache_fsm)
	2817	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
[816]	2818	<< " READ HIT in dcache"
	2819	<< " : PADDR = " << std::hex << paddr
[789]	2820	<< " / DATA = " << std::hex << cache_rdata << std::endl;
[331]	2821	#endif
	2822	}
	2823	}
[789]	2824	else // uncacheable read
[331]	2825	{
[789]	2826	r_dcache_vci_paddr = paddr;
	2827	r_dcache_vci_unc_be = m_dreq.be;
	2828	r_dcache_vci_unc_write = false;
	2829	r_dcache_vci_unc_req = true;
	2830	r_dcache_fsm = DCACHE_UNC_WAIT;
[331]	2831	#if DEBUG_DCACHE
[789]	2832	if (m_debug_dcache_fsm)
	2833	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
[816]	2834	<< " READ UNCACHEABLE in dcache"
[789]	2835	<< " / PADDR = " << std::hex << paddr << std::endl;
[331]	2836	#endif
	2837	}
	2838	} // end READ
	2839
	2840	// LL request (non cachable)
	2841	// We request a VCI LL transaction to CMD FSM and register
	2842	// the LL/SC operation in llsc buffer.
	2843	else if (m_dreq.type == iss_t::DATA_LL)
	2844	{
	2845	// register paddr in LLSC buffer
	2846	r_dcache_llsc_paddr = paddr;
	2847	r_dcache_llsc_count = LLSC_TIMEOUT;
	2848	r_dcache_llsc_valid = true;
	2849
	2850	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
	2851	r_dcache_vci_ll_req = true;
	2852	r_dcache_vci_paddr = paddr;
	2853	r_dcache_ll_rsp_count = 0;
	2854	r_dcache_fsm = DCACHE_LL_WAIT;
	2855
	2856	}// end LL
	2857
	2858	// WRITE request:
	2859	// If the TLB is activated and the PTE Dirty bit is not set, we stall
	2860	// the processor and set the Dirty bit before handling the write request,
	2861	// going to the DCACHE_DIRTY_GT_PTE state.
	2862	// If we don't need to set the Dirty bit, we can acknowledge
	2863	// the processor request, as the write arguments (including the
	2864	// physical address) are registered in r_dcache_save registers,
	2865	// and the write will be done in the P1 pipeline stage.
[789]	2866	else if (m_dreq.type == iss_t::DATA_WRITE)
[331]	2867	{
[789]	2868	if ((r_mmu_mode.read() & DATA_TLB_MASK)
	2869	and not tlb_flags.d) // Dirty bit must be set
[331]	2870	{
	2871	// The PTE physical address is obtained from the nline value (dtlb),
	2872	// and from the virtual address (word index)
[789]	2873	if (tlb_flags.b ) // PTE1
[331]	2874	{
[789]	2875	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
	2876	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
[331]	2877	}
[789]	2878	else // PTE2
[331]	2879	{
[789]	2880	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
	2881	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
[331]	2882	}
[789]	2883	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
[331]	2884	}
[789]	2885	else // Write request accepted
[331]	2886	{
	2887	#ifdef INSTRUMENTATION
[789]	2888	m_cpt_data_write++;
[331]	2889	#endif
	2890	// cleaning llsc buffer if address matching
[789]	2891	if (paddr == r_dcache_llsc_paddr.read())
[331]	2892	r_dcache_llsc_valid = false;
	2893
[816]	2894	if (not cacheable) // uncacheable write
	2895	{
[789]	2896	r_dcache_vci_paddr = paddr;
	2897	r_dcache_vci_wdata = m_dreq.wdata;
	2898	r_dcache_vci_unc_write = true;
	2899	r_dcache_vci_unc_be = m_dreq.be;
	2900	r_dcache_vci_unc_req = true;
	2901	r_dcache_fsm = DCACHE_UNC_WAIT;
[892]	2902
	2903	#if DEBUG_DCACHE
	2904	if (m_debug_dcache_fsm)
	2905	{
	2906	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2907	<< " Request WRITE UNCACHEABLE" << std::hex
	2908	<< " / VADDR = " << m_dreq.addr
	2909	<< " / PADDR = " << paddr
	2910	<< std::dec << std::endl;
	2911	}
	2912	#endif
[616]	2913	}
	2914	else
	2915	{
	2916	// response to processor
[789]	2917	m_drsp.valid = true;
[616]	2918	// activating P1 stage
	2919	wbuf_request = true;
	2920	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
[892]	2921
	2922	#if DEBUG_DCACHE
	2923	if (m_debug_dcache_fsm)
	2924	{
	2925	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2926	<< " Request WBUF WRITE" << std::hex
	2927	<< " / VADDR = " << m_dreq.addr
	2928	<< " / PADDR = " << paddr
	2929	<< std::dec << std::endl;
	2930	}
	2931	#endif
[616]	2932	}
[331]	2933	}
	2934	} // end WRITE
	2935
	2936	// SC request:
	2937	// If the TLB is activated and the PTE Dirty bit is not set, we stall
	2938	// the processor and set the Dirty bit before handling the write request,
	2939	// going to the DCACHE_DIRTY_GT_PTE state.
	2940	// If we don't need to set the Dirty bit, we test the llsc buffer:
	2941	// If failure, we send a negative response to processor.
	2942	// If success, we request a SC transaction to CMD FSM and go
	2943	// to DCACHE_SC_WAIT state.
	2944	// We don't check a possible write hit in dcache, as the cache update
	2945	// is done by the coherence transaction induced by the SC...
[789]	2946	else if (m_dreq.type == iss_t::DATA_SC)
[331]	2947	{
[789]	2948	if ((r_mmu_mode.read() & DATA_TLB_MASK)
	2949	and not tlb_flags.d) // Dirty bit must be set
[331]	2950	{
	2951	// The PTE physical address is obtained from the nline value (dtlb),
	2952	// and the word index (virtual address)
[789]	2953	if (tlb_flags.b) // PTE1
[331]	2954	{
[789]	2955	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
	2956	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
[331]	2957	}
[789]	2958	else // PTE2
[331]	2959	{
[789]	2960	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
	2961	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
[331]	2962	}
[789]	2963	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
[331]	2964	m_drsp.valid = false;
	2965	m_drsp.error = false;
	2966	m_drsp.rdata = 0;
	2967	}
[789]	2968	else // SC request accepted
[331]	2969	{
	2970	#ifdef INSTRUMENTATION
[789]	2971	m_cpt_data_sc++;
[331]	2972	#endif
	2973	// checking local success
[789]	2974	if (r_dcache_llsc_valid.read() and
	2975	(r_dcache_llsc_paddr.read() == paddr)) // local success
[331]	2976	{
	2977	// request an SC CMD and go to DCACHE_SC_WAIT state
	2978	r_dcache_vci_paddr = paddr;
	2979	r_dcache_vci_sc_req = true;
	2980	r_dcache_vci_sc_data = m_dreq.wdata;
	2981	r_dcache_fsm = DCACHE_SC_WAIT;
	2982	}
[789]	2983	else // local fail
[331]	2984	{
[789]	2985	m_drsp.valid = true;
	2986	m_drsp.error = false;
	2987	m_drsp.rdata = 0x1;
[331]	2988	}
	2989	}
	2990	} // end SC
	2991	} // end valid_req
	2992	} // end if read/write/ll/sc request
	2993	} // end processor request
	2994
	2995	// itlb miss request
[836]	2996	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
[331]	2997	{
	2998	r_dcache_tlb_ins = true;
	2999	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
	3000	r_dcache_fsm = DCACHE_TLB_MISS;
	3001	}
	3002
	3003	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
	3004	r_dcache_updt_req = updt_request;
	3005	r_dcache_wbuf_req = wbuf_request or
	3006	(r_dcache_wbuf_req.read() and wbuf_write_miss);
	3007	break;
	3008	}
	3009	/////////////////////
	3010	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
	3011	// Input arguments are:
	3012	// - r_dcache_tlb_vaddr
	3013	// - r_dcache_tlb_ins (true when itlb miss)
	3014	// The sub-fsm access the dcache to find the missing TLB entry,
	3015	// and activates the cache miss procedure in case of miss.
	3016	// It bypass the first level page table access if possible.
	3017	// It uses atomic access to update the R/L access bits
	3018	// in the page table if required.
	3019	// It directly updates the itlb or dtlb, and writes into the
	3020	// r_mmu_ins_* or r_mmu_data* error reporting registers.
	3021	{
[789]	3022	uint32_t ptba = 0;
	3023	bool bypass;
	3024	paddr_t pte_paddr;
[331]	3025
	3026	// evaluate bypass in order to skip first level page table access
[789]	3027	if (r_dcache_tlb_ins.read()) // itlb miss
[331]	3028	{
	3029	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
	3030	}
[789]	3031	else // dtlb miss
[331]	3032	{
	3033	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
	3034	}
	3035
[789]	3036	if (not bypass) // Try to read PTE1/PTD1 in dcache
[331]	3037	{
[789]	3038	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
	3039	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
[331]	3040	r_dcache_tlb_paddr = pte_paddr;
	3041	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
	3042	}
[789]	3043	else // Try to read PTE2 in dcache
[331]	3044	{
[789]	3045	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
	3046	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
[331]	3047	r_dcache_tlb_paddr = pte_paddr;
	3048	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
	3049	}
	3050
	3051	#if DEBUG_DCACHE
[789]	3052	if (m_debug_dcache_fsm)
	3053	{
	3054	if (r_dcache_tlb_ins.read())
	3055	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
	3056	else
	3057	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
	3058	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
	3059	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
	3060	<< " / BYPASS = " << bypass
	3061	<< " / PTE_ADR = " << pte_paddr << std::endl;
	3062	}
[331]	3063	#endif
	3064
	3065	break;
	3066	}
	3067	/////////////////////////
[789]	3068	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
[331]	3069	{
[468]	3070	// coherence clack request (from DSPIN CLACK)
[789]	3071	if (r_dcache_clack_req.read())
[468]	3072	{
	3073	r_dcache_fsm = DCACHE_CC_CHECK;
	3074	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3075	break;
	3076	}
	3077
[341]	3078	// coherence request (from CC_RECEIVE FSM)
[789]	3079	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[341]	3080	{
	3081	r_dcache_fsm = DCACHE_CC_CHECK;
	3082	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3083	break;
	3084	}
	3085
[789]	3086	uint32_t entry;
	3087	size_t way;
	3088	size_t set;
	3089	size_t word;
	3090	int cache_state;
	3091	r_dcache.read(r_dcache_tlb_paddr.read(),
	3092	&entry,
	3093	&way,
	3094	&set,
	3095	&word,
	3096	&cache_state);
[331]	3097	#ifdef INSTRUMENTATION
[789]	3098	m_cpt_dcache_data_read++;
	3099	m_cpt_dcache_dir_read++;
[331]	3100	#endif
[789]	3101	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
[331]	3102	{
[789]	3103	if (not (entry & PTE_V_MASK)) // unmapped
[331]	3104	{
[789]	3105	if (r_dcache_tlb_ins.read())
[331]	3106	{
	3107	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
	3108	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	3109	r_icache_tlb_miss_req = false;
	3110	r_icache_tlb_rsp_error = true;
	3111	}
	3112	else
	3113	{
[789]	3114	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
	3115	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	3116	m_drsp.valid = true;
	3117	m_drsp.error = true;
[331]	3118	}
[789]	3119	r_dcache_fsm = DCACHE_IDLE;
[331]	3120
	3121	#if DEBUG_DCACHE
[789]	3122	if (m_debug_dcache_fsm)
	3123	{
[816]	3124	std::cout << " <PROC " << name()
[789]	3125	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
	3126	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
	3127	<< std::dec << " / way = " << way
	3128	<< std::dec << " / set = " << set
	3129	<< std::dec << " / word = " << word
	3130	<< std::hex << " / PTE1 = " << entry << std::endl;
	3131	}
[331]	3132	#endif
	3133
	3134	}
[836]	3135	else if (entry & PTE_T_MASK) // PTD : me must access PT2
[331]	3136	{
	3137	// mark the cache line ac containing a PTD
[789]	3138	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
[331]	3139
	3140	// register bypass
[789]	3141	if (r_dcache_tlb_ins.read()) // itlb
[331]	3142	{
	3143	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
	3144	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
[789]	3145	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
[331]	3146	}
[789]	3147	else // dtlb
[331]	3148	{
	3149	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
	3150	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
[789]	3151	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
[331]	3152	}
	3153	r_dcache_tlb_paddr =
[789]	3154	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
[331]	3155	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
[789]	3156	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
[331]	3157
	3158	#if DEBUG_DCACHE
[789]	3159	if (m_debug_dcache_fsm)
	3160	{
[816]	3161	std::cout << " <PROC " << name()
[789]	3162	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
	3163	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
	3164	<< std::dec << " / way = " << way
	3165	<< std::dec << " / set = " << set
	3166	<< std::dec << " / word = " << word
	3167	<< std::hex << " / PTD = " << entry << std::endl;
	3168	}
[331]	3169	#endif
	3170	}
[789]	3171	else // PTE1 : we must update the TLB
[331]	3172	{
[789]	3173	r_dcache_in_tlb[m_icache_sets * way + set] = true;
[331]	3174	r_dcache_tlb_pte_flags = entry;
	3175	r_dcache_tlb_cache_way = way;
	3176	r_dcache_tlb_cache_set = set;
	3177	r_dcache_tlb_cache_word = word;
	3178	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
	3179
	3180	#if DEBUG_DCACHE
[789]	3181	if (m_debug_dcache_fsm)
	3182	{
[816]	3183	std::cout << " <PROC " << name()
[789]	3184	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
	3185	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
	3186	<< std::dec << " / way = " << way
	3187	<< std::dec << " / set = " << set
	3188	<< std::dec << " / word = " << word
	3189	<< std::hex << " / PTE1 = " << entry << std::endl;
	3190	}
[331]	3191	#endif
	3192	}
	3193	}
[789]	3194	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
[338]	3195	{
	3196	// stalled until cleanup is acknowledged
[789]	3197	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
[338]	3198	}
[789]	3199	else // we must load the missing cache line in dcache
[331]	3200	{
[789]	3201	r_dcache_vci_miss_req = true;
	3202	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
	3203	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
	3204	r_dcache_miss_type = PTE1_MISS;
	3205	r_dcache_fsm = DCACHE_MISS_SELECT;
[331]	3206
	3207	#if DEBUG_DCACHE
[789]	3208	if (m_debug_dcache_fsm)
	3209	{
[816]	3210	std::cout << " <PROC " << name()
[789]	3211	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
	3212	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
	3213	}
[331]	3214	#endif
	3215	}
	3216	break;
	3217	}
	3218	////////////////////////////
[789]	3219	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
[331]	3220	{
[789]	3221	size_t way;
	3222	size_t set;
[331]	3223
[789]	3224	if (r_dcache_tlb_ins.read())
[331]	3225	{
[789]	3226	r_itlb.select(r_dcache_tlb_vaddr.read(),
	3227	true, // PTE1
	3228	&way,
	3229	&set);
[331]	3230	#ifdef INSTRUMENTATION
[789]	3231	m_cpt_itlb_read++;
[331]	3232	#endif
	3233	}
	3234	else
	3235	{
[789]	3236	r_dtlb.select(r_dcache_tlb_vaddr.read(),
	3237	true, // PTE1
	3238	&way,
	3239	&set);
[331]	3240	#ifdef INSTRUMENTATION
[789]	3241	m_cpt_dtlb_read++;
[331]	3242	#endif
	3243	}
	3244	r_dcache_tlb_way = way;
	3245	r_dcache_tlb_set = set;
	3246	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
	3247
	3248	#if DEBUG_DCACHE
[789]	3249	if (m_debug_dcache_fsm)
	3250	{
	3251	if (r_dcache_tlb_ins.read())
[816]	3252	std::cout << " <PROC " << name()
[789]	3253	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
	3254	else
[816]	3255	std::cout << " <PROC " << name()
[789]	3256	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
	3257	std::cout << " way = " << std::dec << way
	3258	<< " / set = " << set << std::endl;
	3259	}
[331]	3260	#endif
	3261	break;
	3262	}
	3263	//////////////////////////
[789]	3264	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
[331]	3265	// - if L/R bit already set, exit the sub-fsm.
	3266	// - if not, we update the page table but we dont write
	3267	// neither in DCACHE, nor in TLB, as this will be done by
	3268	// the coherence mechanism.
	3269	{
[789]	3270	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
	3271	uint32_t pte = r_dcache_tlb_pte_flags.read();
	3272	bool pt_updt = false;
	3273	bool local = true;
[331]	3274
	3275	// We should compute the access locality:
	3276	// The PPN MSB bits define the destination cluster index.
[346]	3277	// The m_srcid MSB bits define the source cluster index.
[331]	3278	// The number of bits to compare depends on the number of clusters,
	3279	// and can be obtained in the mapping table.
	3280	// As long as this computation is not done, all access are local.
	3281
[789]	3282	if (local) // local access
[331]	3283	{
[789]	3284	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
[331]	3285	{
	3286	pt_updt = true;
[789]	3287	r_dcache_vci_cas_old = pte;
	3288	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
[331]	3289	pte = pte \| PTE_L_MASK;
	3290	r_dcache_tlb_pte_flags = pte;
	3291	}
	3292	}
[789]	3293	else // remote access
[331]	3294	{
[789]	3295	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
[331]	3296	{
	3297	pt_updt = true;
[789]	3298	r_dcache_vci_cas_old = pte;
	3299	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
[331]	3300	pte = pte \| PTE_R_MASK;
	3301	r_dcache_tlb_pte_flags = pte;
	3302	}
	3303	}
	3304
[789]	3305	if (not pt_updt) // update TLB and return
[331]	3306	{
[789]	3307	if (r_dcache_tlb_ins.read())
[331]	3308	{
[789]	3309	r_itlb.write(true, // 2M page
	3310	pte,
	3311	0, // argument unused for a PTE1
	3312	r_dcache_tlb_vaddr.read(),
	3313	r_dcache_tlb_way.read(),
	3314	r_dcache_tlb_set.read(),
	3315	nline);
[331]	3316	#ifdef INSTRUMENTATION
[789]	3317	m_cpt_itlb_write++;
[331]	3318	#endif
	3319
	3320	#if DEBUG_DCACHE
[789]	3321	if (m_debug_dcache_fsm)
	3322	{
[816]	3323	std::cout << " <PROC " << name()
[789]	3324	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
	3325	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3326	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3327	r_itlb.printTrace();
	3328	}
[331]	3329	#endif
	3330	}
	3331	else
	3332	{
[789]	3333	r_dtlb.write(true, // 2M page
	3334	pte,
	3335	0, // argument unused for a PTE1
	3336	r_dcache_tlb_vaddr.read(),
	3337	r_dcache_tlb_way.read(),
	3338	r_dcache_tlb_set.read(),
	3339	nline);
[331]	3340	#ifdef INSTRUMENTATION
[789]	3341	m_cpt_dtlb_write++;
[331]	3342	#endif
	3343
	3344	#if DEBUG_DCACHE
[789]	3345	if (m_debug_dcache_fsm)
	3346	{
[816]	3347	std::cout << " <PROC " << name()
[789]	3348	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
	3349	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3350	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3351	r_dtlb.printTrace();
	3352	}
[331]	3353	#endif
	3354	}
	3355	r_dcache_fsm = DCACHE_TLB_RETURN;
	3356	}
	3357	else // update page table but not TLB
	3358	{
	3359	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
	3360
	3361	#if DEBUG_DCACHE
[789]	3362	if (m_debug_dcache_fsm)
	3363	{
[816]	3364	std::cout << " <PROC " << name()
[789]	3365	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
	3366	<< std::endl;
	3367	}
[331]	3368	#endif
	3369	}
	3370	break;
	3371	}
	3372	/////////////////////////
[789]	3373	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
[331]	3374	{
[468]	3375	// coherence clack request (from DSPIN CLACK)
[789]	3376	if (r_dcache_clack_req.read())
[468]	3377	{
	3378	r_dcache_fsm = DCACHE_CC_CHECK;
	3379	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3380	break;
	3381	}
	3382
[341]	3383	// coherence request (from CC_RECEIVE FSM)
[789]	3384	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[341]	3385	{
	3386	r_dcache_fsm = DCACHE_CC_CHECK;
	3387	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3388	break;
	3389	}
	3390
[789]	3391	uint32_t pte_flags;
	3392	uint32_t pte_ppn;
	3393	size_t way;
	3394	size_t set;
	3395	size_t word;
	3396	int cache_state;
[331]	3397
[789]	3398	r_dcache.read(r_dcache_tlb_paddr.read(),
	3399	&pte_flags,
	3400	&pte_ppn,
	3401	&way,
	3402	&set,
	3403	&word,
	3404	&cache_state);
[331]	3405	#ifdef INSTRUMENTATION
[789]	3406	m_cpt_dcache_data_read++;
	3407	m_cpt_dcache_dir_read++;
[331]	3408	#endif
[789]	3409	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
[331]	3410	{
[789]	3411	if (not (pte_flags & PTE_V_MASK)) // unmapped
[331]	3412	{
[789]	3413	if (r_dcache_tlb_ins.read())
[331]	3414	{
	3415	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
	3416	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	3417	r_icache_tlb_miss_req = false;
	3418	r_icache_tlb_rsp_error = true;
	3419	}
	3420	else
	3421	{
[789]	3422	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
	3423	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	3424	m_drsp.valid = true;
	3425	m_drsp.error = true;
[331]	3426	}
[789]	3427	r_dcache_fsm = DCACHE_IDLE;
[331]	3428
	3429	#if DEBUG_DCACHE
[789]	3430	if (m_debug_dcache_fsm)
	3431	{
	3432	std::cout << " <PROC " << name()
	3433	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
	3434	<< " PTE_FLAGS = " << std::hex << pte_flags
	3435	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
	3436	}
[331]	3437	#endif
	3438	}
[789]	3439	else // mapped : we must update the TLB
[331]	3440	{
[789]	3441	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
[331]	3442	r_dcache_tlb_pte_flags = pte_flags;
	3443	r_dcache_tlb_pte_ppn = pte_ppn;
	3444	r_dcache_tlb_cache_way = way;
	3445	r_dcache_tlb_cache_set = set;
	3446	r_dcache_tlb_cache_word = word;
	3447	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
	3448
	3449	#if DEBUG_DCACHE
[789]	3450	if (m_debug_dcache_fsm)
	3451	{
[816]	3452	std::cout << " <PROC " << name()
[789]	3453	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
	3454	<< " PTE_FLAGS = " << std::hex << pte_flags
	3455	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
	3456	}
[331]	3457	#endif
	3458	}
	3459	}
[789]	3460	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
[338]	3461	{
	3462	// stalled until cleanup is acknowledged
	3463	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
[386]	3464
	3465	#if DEBUG_DCACHE
[789]	3466	if (m_debug_dcache_fsm)
	3467	{
[816]	3468	std::cout << " <PROC " << name()
[789]	3469	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
	3470	<< std::endl;
	3471	}
[386]	3472	#endif
[338]	3473	}
[331]	3474	else // we must load the missing cache line in dcache
	3475	{
	3476	r_dcache_fsm = DCACHE_MISS_SELECT;
	3477	r_dcache_vci_miss_req = true;
	3478	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
	3479	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
	3480	r_dcache_miss_type = PTE2_MISS;
	3481
	3482	#if DEBUG_DCACHE
[789]	3483	if (m_debug_dcache_fsm)
	3484	{
	3485	std::cout << " <PROC " << name()
	3486	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
	3487	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
	3488	}
[331]	3489	#endif
	3490	}
	3491	break;
	3492	}
	3493	////////////////////////////
	3494	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
	3495	{
	3496	size_t way;
	3497	size_t set;
	3498
[789]	3499	if (r_dcache_tlb_ins.read())
[331]	3500	{
[789]	3501	r_itlb.select(r_dcache_tlb_vaddr.read(),
	3502	false, // PTE2
	3503	&way,
	3504	&set);
[331]	3505	#ifdef INSTRUMENTATION
[789]	3506	m_cpt_itlb_read++;
[331]	3507	#endif
	3508	}
	3509	else
	3510	{
[789]	3511	r_dtlb.select(r_dcache_tlb_vaddr.read(),
	3512	false, // PTE2
	3513	&way,
	3514	&set);
[331]	3515	#ifdef INSTRUMENTATION
[789]	3516	m_cpt_dtlb_read++;
[331]	3517	#endif
	3518	}
	3519
	3520	#if DEBUG_DCACHE
[789]	3521	if (m_debug_dcache_fsm)
	3522	{
	3523	if (r_dcache_tlb_ins.read())
	3524	std::cout << " <PROC " << name()
	3525	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
	3526	else
	3527	std::cout << " <PROC " << name()
	3528	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
	3529	std::cout << " way = " << std::dec << way
	3530	<< " / set = " << set << std::endl;
	3531	}
[331]	3532	#endif
	3533	r_dcache_tlb_way = way;
	3534	r_dcache_tlb_set = set;
	3535	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
	3536	break;
	3537	}
	3538	//////////////////////////
[789]	3539	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
[331]	3540	// - if L/R bit already set, exit the sub-fsm.
	3541	// - if not, we update the page table but we dont write
	3542	// neither in DCACHE, nor in TLB, as this will be done by
	3543	// the coherence mechanism.
	3544	{
[789]	3545	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
	3546	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
	3547	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
	3548	bool pt_updt = false;
	3549	bool local = true;
[331]	3550
	3551	// We should compute the access locality:
	3552	// The PPN MSB bits define the destination cluster index.
[346]	3553	// The m_srcid MSB bits define the source cluster index.
[331]	3554	// The number of bits to compare depends on the number of clusters,
	3555	// and can be obtained in the mapping table.
	3556	// As long as this computation is not done, all access are local.
	3557
[789]	3558	if (local) // local access
[331]	3559	{
[789]	3560	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
[331]	3561	{
	3562	pt_updt = true;
[355]	3563	r_dcache_vci_cas_old = pte_flags;
	3564	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
[331]	3565	pte_flags = pte_flags \| PTE_L_MASK;
[789]	3566	r_dcache_tlb_pte_flags = pte_flags;
[331]	3567	}
	3568	}
	3569	else // remote access
	3570	{
[789]	3571	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
[331]	3572	{
	3573	pt_updt = true;
[355]	3574	r_dcache_vci_cas_old = pte_flags;
	3575	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
[331]	3576	pte_flags = pte_flags \| PTE_R_MASK;
[789]	3577	r_dcache_tlb_pte_flags = pte_flags;
[331]	3578	}
	3579	}
	3580
[789]	3581	if (not pt_updt) // update TLB
[331]	3582	{
[789]	3583	if (r_dcache_tlb_ins.read())
[331]	3584	{
[789]	3585	r_itlb.write( false, // 4K page
[331]	3586	pte_flags,
	3587	pte_ppn,
	3588	r_dcache_tlb_vaddr.read(),
	3589	r_dcache_tlb_way.read(),
	3590	r_dcache_tlb_set.read(),
	3591	nline );
	3592	#ifdef INSTRUMENTATION
[789]	3593	m_cpt_itlb_write++;
[331]	3594	#endif
	3595
	3596	#if DEBUG_DCACHE
[789]	3597	if (m_debug_dcache_fsm)
	3598	{
	3599	std::cout << " <PROC " << name()
	3600	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
	3601	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3602	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3603	r_itlb.printTrace();
	3604	}
[331]	3605	#endif
	3606	}
	3607	else
	3608	{
[789]	3609	r_dtlb.write(false, // 4K page
	3610	pte_flags,
	3611	pte_ppn,
	3612	r_dcache_tlb_vaddr.read(),
	3613	r_dcache_tlb_way.read(),
	3614	r_dcache_tlb_set.read(),
	3615	nline);
[331]	3616	#ifdef INSTRUMENTATION
[789]	3617	m_cpt_dtlb_write++;
[331]	3618	#endif
	3619
	3620	#if DEBUG_DCACHE
[789]	3621	if (m_debug_dcache_fsm)
	3622	{
	3623	std::cout << " <PROC " << name()
	3624	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
	3625	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3626	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3627	r_dtlb.printTrace();
	3628	}
[331]	3629	#endif
	3630
	3631	}
	3632	r_dcache_fsm = DCACHE_TLB_RETURN;
	3633	}
	3634	else // update page table but not TLB
	3635	{
[789]	3636	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
[331]	3637
	3638	#if DEBUG_DCACHE
[789]	3639	if (m_debug_dcache_fsm)
	3640	{
	3641	std::cout << " <PROC " << name()
	3642	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
	3643	}
[331]	3644	#endif
	3645	}
	3646	break;
	3647	}
	3648	////////////////////////
	3649	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
	3650	{
	3651	#if DEBUG_DCACHE
[789]	3652	if (m_debug_dcache_fsm)
	3653	{
	3654	std::cout << " <PROC " << name()
	3655	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
	3656	}
[331]	3657	#endif
	3658	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
	3659	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
	3660
	3661	// checking llsc reservation buffer
[789]	3662	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
[331]	3663	r_dcache_llsc_valid = false;
	3664
	3665	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
	3666	r_dcache_vci_cas_req = true;
[789]	3667	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
[331]	3668	break;
	3669	}
	3670	////////////////////////
[789]	3671	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
[331]	3672	// We consume the response in rsp FIFO,
	3673	// and exit the sub-fsm, but we don't
	3674	// analyse the response, because we don't
	3675	// care if the L/R bit update is not done.
	3676	// We must take the coherence requests because
	3677	// there is a risk of dead-lock
	3678
	3679	{
[468]	3680	// coherence clack request (from DSPIN CLACK)
[789]	3681	if (r_dcache_clack_req.read())
[468]	3682	{
	3683	r_dcache_fsm = DCACHE_CC_CHECK;
	3684	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3685	break;
	3686	}
	3687
[331]	3688	// coherence request (from CC_RECEIVE FSM)
[789]	3689	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	3690	{
	3691	r_dcache_fsm = DCACHE_CC_CHECK;
	3692	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3693	break;
	3694	}
	3695
[789]	3696	if (r_vci_rsp_data_error.read()) // bus error
[331]	3697	{
	3698	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
	3699	std::cout << "This should not happen in this state" << std::endl;
	3700	exit(0);
	3701	}
[789]	3702	else if (r_vci_rsp_fifo_dcache.rok()) // response available
[506]	3703	{
[331]	3704	#if DEBUG_DCACHE
[789]	3705	if (m_debug_dcache_fsm)
	3706	{
	3707	std::cout << " <PROC " << name()
	3708	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
	3709	}
[331]	3710	#endif
	3711	vci_rsp_fifo_dcache_get = true;
[789]	3712	r_dcache_fsm = DCACHE_TLB_RETURN;
[331]	3713	}
	3714	break;
	3715	}
	3716	///////////////////////
[789]	3717	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
[331]	3718	{
	3719	#if DEBUG_DCACHE
[789]	3720	if (m_debug_dcache_fsm)
	3721	{
	3722	std::cout << " <PROC " << name()
	3723	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
	3724	}
[331]	3725	#endif
[789]	3726	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
[331]	3727	r_dcache_fsm = DCACHE_IDLE;
	3728	break;
	3729	}
	3730	///////////////////////
[789]	3731	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
[331]	3732	// and both itlb and dtlb must be flushed.
	3733	// Caution : the itlb miss requests must be taken
	3734	// to avoid dead-lock in case of simultaneous ITLB miss
[521]	3735	// Caution : the clack and cc requests must be taken
	3736	// to avoid dead-lock
[331]	3737	{
[521]	3738	// coherence clack request (from DSPIN CLACK)
[789]	3739	if (r_dcache_clack_req.read())
[521]	3740	{
	3741	r_dcache_fsm = DCACHE_CC_CHECK;
	3742	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3743	break;
	3744	}
	3745
	3746	// coherence request (from CC_RECEIVE FSM)
[789]	3747	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[521]	3748	{
	3749	r_dcache_fsm = DCACHE_CC_CHECK;
	3750	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3751	break;
	3752	}
	3753
[331]	3754	// itlb miss request
[789]	3755	if (r_icache_tlb_miss_req.read())
[331]	3756	{
[789]	3757	r_dcache_tlb_ins = true;
	3758	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
	3759	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	3760	break;
	3761	}
	3762
[789]	3763	if (not r_dcache_xtn_req.read())
[331]	3764	{
	3765	r_dtlb.flush();
	3766	r_mmu_ptpr = m_dreq.wdata;
	3767	r_dcache_fsm = DCACHE_IDLE;
	3768	m_drsp.valid = true;
	3769	}
	3770	break;
	3771	}
	3772	/////////////////////
[789]	3773	case DCACHE_XTN_SYNC: // waiting until write buffer empty
	3774	// The coherence request must be taken
	3775	// as there is a risk of dead-lock
[331]	3776	{
[468]	3777	// coherence clack request (from DSPIN CLACK)
[789]	3778	if (r_dcache_clack_req.read())
[468]	3779	{
	3780	r_dcache_fsm = DCACHE_CC_CHECK;
	3781	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3782	break;
	3783	}
	3784
[331]	3785	// coherence request (from CC_RECEIVE FSM)
[789]	3786	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	3787	{
	3788	r_dcache_fsm = DCACHE_CC_CHECK;
	3789	r_dcache_fsm_cc_save = r_dcache_fsm.read();
[468]	3790	break;
[331]	3791	}
	3792
[789]	3793	if (r_wbuf.empty())
[331]	3794	{
[789]	3795	m_drsp.valid = true;
[331]	3796	r_dcache_fsm = DCACHE_IDLE;
	3797	}
	3798	break;
	3799	}
	3800	////////////////////////
[721]	3801	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
	3802	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
	3803	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
	3804	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
	3805	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
	3806
[331]	3807	{
[468]	3808	// coherence clack request (from DSPIN CLACK)
[789]	3809	if (r_dcache_clack_req.read())
[468]	3810	{
	3811	r_dcache_fsm = DCACHE_CC_CHECK;
	3812	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3813	break;
	3814	}
	3815
[331]	3816	// coherence request (from CC_RECEIVE FSM)
[789]	3817	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	3818	{
	3819	r_dcache_fsm = DCACHE_CC_CHECK;
	3820	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3821	break;
	3822	}
	3823
	3824	// itlb miss request
[789]	3825	if (r_icache_tlb_miss_req.read())
[331]	3826	{
[789]	3827	r_dcache_tlb_ins = true;
	3828	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
	3829	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	3830	break;
	3831	}
	3832
	3833	// test if XTN request to icache completed
[789]	3834	if (not r_dcache_xtn_req.read())
[331]	3835	{
	3836	r_dcache_fsm = DCACHE_IDLE;
	3837	m_drsp.valid = true;
	3838	}
	3839	break;
	3840	}
	3841	/////////////////////////
[789]	3842	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
[331]	3843	// r_dcache_flush_count as a slot counter,
	3844	// looping in this state until all slots have been visited.
	3845	// It can require two cycles per slot:
	3846	// We test here the slot state, and make the actual inval
	3847	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
	3848	// A cleanup request is generated for each valid line.
	3849	// returns to IDLE and flush TLBs when last slot
	3850	{
[468]	3851	// coherence clack request (from DSPIN CLACK)
[789]	3852	if (r_dcache_clack_req.read())
[468]	3853	{
	3854	r_dcache_fsm = DCACHE_CC_CHECK;
	3855	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3856	break;
	3857	}
	3858
[384]	3859	// coherence request (from CC_RECEIVE FSM)
[789]	3860	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[384]	3861	{
	3862	r_dcache_fsm = DCACHE_CC_CHECK;
	3863	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3864	break;
	3865	}
	3866
[789]	3867	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
[331]	3868	{
[789]	3869	int state;
	3870	paddr_t tag;
[836]	3871	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
	3872	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
[331]	3873
	3874	#ifdef INSTRUMENTATION
[789]	3875	m_cpt_dcache_dir_read++;
[331]	3876	#endif
[789]	3877	r_dcache.read_dir(way,
	3878	set,
	3879	&tag,
	3880	&state);
[331]	3881
[789]	3882	if (state == CACHE_SLOT_STATE_VALID) // inval required
[331]	3883	{
	3884	// request cleanup
	3885	r_dcache_cc_send_req = true;
[384]	3886	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
[331]	3887	r_dcache_cc_send_way = way;
	3888	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	3889
	3890	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
[789]	3891	r_dcache_miss_way = way;
	3892	r_dcache_miss_set = set;
	3893	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
[331]	3894	}
[789]	3895	else if (r_dcache_flush_count.read() ==
	3896	(m_dcache_sets*m_dcache_ways - 1)) // last slot
[331]	3897	{
	3898	r_dtlb.reset();
	3899	r_itlb.reset();
	3900	r_dcache_fsm = DCACHE_IDLE;
	3901	m_drsp.valid = true;
	3902	}
	3903
	3904	// saturation counter
[789]	3905	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
[331]	3906	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
	3907	}
	3908	break;
	3909	}
	3910	////////////////////////////
	3911	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
	3912	// and reset directory extension.
	3913	// returns to IDLE and flush TLBs when last slot
	3914	{
	3915	size_t way = r_dcache_miss_way.read();
	3916	size_t set = r_dcache_miss_set.read();
	3917
[789]	3918	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
	3919	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
[331]	3920
	3921	#ifdef INSTRUMENTATION
[789]	3922	m_cpt_dcache_dir_write++;
[331]	3923	#endif
[789]	3924	r_dcache.write_dir(way,
	3925	set,
	3926	CACHE_SLOT_STATE_ZOMBI);
[331]	3927
[789]	3928	if (r_dcache_flush_count.read() ==
	3929	(m_dcache_sets*m_dcache_ways - 1)) // last slot
[331]	3930	{
	3931	r_dtlb.reset();
	3932	r_itlb.reset();
	3933	r_dcache_fsm = DCACHE_IDLE;
	3934	m_drsp.valid = true;
	3935	}
	3936	else
	3937	{
	3938	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
	3939	}
	3940	break;
	3941	}
	3942	/////////////////////////
[789]	3943	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
[331]	3944	{
	3945	r_dtlb.inval(r_dcache_save_wdata.read());
[789]	3946	r_dcache_fsm = DCACHE_IDLE;
	3947	m_drsp.valid = true;
[331]	3948	break;
	3949	}
	3950	////////////////////////////
	3951	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
	3952	// requires 3 cycles: access tlb, read cache, inval cache
[789]	3953	// we compute the physical address in this state
[331]	3954	{
	3955	paddr_t paddr;
[789]	3956	bool hit;
[331]	3957
[789]	3958	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
[331]	3959	{
	3960
	3961	#ifdef INSTRUMENTATION
[789]	3962	m_cpt_dtlb_read++;
[331]	3963	#endif
[789]	3964	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
	3965	&paddr);
[331]	3966	}
[789]	3967	else // dtlb not activated
[331]	3968	{
	3969	paddr = (paddr_t)r_dcache_save_wdata.read();
[816]	3970	if (vci_param::N > 32)
[487]	3971	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
[789]	3972	hit = true;
[331]	3973	}
	3974
[789]	3975	if (hit) // tlb hit
[331]	3976	{
	3977	r_dcache_save_paddr = paddr;
[789]	3978	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
[331]	3979	}
[789]	3980	else // tlb miss
	3981	{
[331]	3982
	3983	#ifdef INSTRUMENTATION
[789]	3984	m_cpt_dtlb_miss++;
[331]	3985	#endif
[789]	3986	r_dcache_tlb_ins = false; // dtlb
	3987	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
	3988	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	3989	}
	3990
	3991	#if DEBUG_DCACHE
[789]	3992	if (m_debug_dcache_fsm)
	3993	{
	3994	std::cout << " <PROC " << name()
	3995	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
	3996	<< " / VADDR = " << r_dcache_save_wdata.read()
	3997	<< " / PADDR = " << paddr << std::endl;
	3998	}
[331]	3999	#endif
	4000
	4001	break;
	4002	}
	4003	////////////////////////////
	4004	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
	4005	// requires 2 cycles: read cache / inval cache
	4006	// In this state we read dcache.
	4007	{
[789]	4008	size_t way;
	4009	size_t set;
	4010	size_t word;
	4011	int state;
[331]	4012
	4013	#ifdef INSTRUMENTATION
[789]	4014	m_cpt_dcache_dir_read++;
[331]	4015	#endif
[789]	4016	r_dcache.read_dir(r_dcache_save_paddr.read(),
	4017	&state,
	4018	&way,
	4019	&set,
	4020	&word);
[331]	4021
[789]	4022	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
[331]	4023	{
	4024	r_dcache_xtn_way = way;
	4025	r_dcache_xtn_set = set;
[789]	4026	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
[331]	4027	}
[789]	4028	else // miss : nothing to do
[331]	4029	{
[789]	4030	r_dcache_fsm = DCACHE_IDLE;
	4031	m_drsp.valid = true;
[331]	4032	}
	4033
	4034	#if DEBUG_DCACHE
[789]	4035	if (m_debug_dcache_fsm)
	4036	{
	4037	std::cout << " <PROC " << name()
	4038	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
	4039	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
	4040	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
	4041	<< " / SET = " << set
	4042	<< " / WAY = " << way << std::endl;
	4043	}
[331]	4044	#endif
	4045	break;
	4046	}
	4047	////////////////////////////
	4048	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
[789]	4049	// Blocked if previous cleanup not completed
[331]	4050	// Test if itlb or dtlb inval is required
	4051	{
[789]	4052	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
[331]	4053	{
[789]	4054	size_t way = r_dcache_xtn_way.read();
	4055	size_t set = r_dcache_xtn_set.read();
	4056	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
[331]	4057
	4058	#ifdef INSTRUMENTATION
[789]	4059	m_cpt_dcache_dir_write++;
[331]	4060	#endif
[789]	4061	r_dcache.write_dir(way,
	4062	set,
	4063	CACHE_SLOT_STATE_ZOMBI);
[331]	4064
	4065	// request cleanup
	4066	r_dcache_cc_send_req = true;
	4067	r_dcache_cc_send_nline = nline;
	4068	r_dcache_cc_send_way = way;
	4069	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	4070
	4071	// possible itlb & dtlb invalidate
[789]	4072	if (r_dcache_in_tlb[way * m_dcache_sets + set])
[331]	4073	{
	4074	r_dcache_tlb_inval_line = nline;
	4075	r_dcache_tlb_inval_set = 0;
	4076	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
	4077	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[789]	4078	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[331]	4079	}
[789]	4080	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
[331]	4081	{
	4082	r_itlb.reset();
	4083	r_dtlb.reset();
[789]	4084	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	4085	r_dcache_fsm = DCACHE_IDLE;
	4086	m_drsp.valid = true;
	4087	}
	4088	else
	4089	{
	4090	r_dcache_fsm = DCACHE_IDLE;
	4091	m_drsp.valid = true;
	4092	}
	4093
	4094	#if DEBUG_DCACHE
[789]	4095	if (m_debug_dcache_fsm)
	4096	{
	4097	std::cout << " <PROC " << name()
	4098	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
	4099	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
	4100	}
[331]	4101	#endif
[789]	4102	}
[331]	4103	break;
	4104	}
	4105	//////////////////////////////
[789]	4106	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
[331]	4107	{
	4108	r_dcache_fsm = DCACHE_IDLE;
	4109	m_drsp.valid = true;
	4110	break;
	4111	}
	4112	////////////////////////
[487]	4113	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
	4114	// Waiting in this state if no slot available.
[816]	4115	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
	4116	// we send the cleanup request in this state.
[487]	4117	// If not, a r_icache_cleanup_victim_req flip-flop is
	4118	// utilized for saving this cleanup request, and it will be sent later
[816]	4119	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
[487]	4120	// The r_icache_miss_clack flip-flop is set
	4121	// when a cleanup is required
[331]	4122	{
[789]	4123	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4124
[468]	4125	// coherence clack request (from DSPIN CLACK)
[789]	4126	if (r_dcache_clack_req.read())
[468]	4127	{
	4128	r_dcache_fsm = DCACHE_CC_CHECK;
	4129	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4130	break;
	4131	}
	4132
[331]	4133	// coherence request (from CC_RECEIVE FSM)
[789]	4134	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4135	{
	4136	r_dcache_fsm = DCACHE_CC_CHECK;
	4137	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4138	break;
	4139	}
	4140
[789]	4141	bool found = false;
	4142	bool cleanup = false;
	4143	size_t way = 0;
	4144	size_t set = 0;
	4145	paddr_t victim = 0;
[331]	4146
	4147	#ifdef INSTRUMENTATION
[789]	4148	m_cpt_dcache_dir_read++;
[331]	4149	#endif
[789]	4150	r_dcache.read_select(r_dcache_save_paddr.read(),
	4151	&victim,
	4152	&way,
	4153	&set,
	4154	&found,
	4155	&cleanup);
[355]	4156
[789]	4157	if (not found)
[487]	4158	{
	4159	break;
	4160	}
	4161	else
	4162	{
	4163	r_dcache_miss_way = way;
	4164	r_dcache_miss_set = set;
	4165
[789]	4166	if (cleanup)
[331]	4167	{
[789]	4168	if (not r_dcache_cc_send_req.read())
[487]	4169	{
[789]	4170	r_dcache_cc_send_req = true;
	4171	r_dcache_cc_send_nline = victim;
	4172	r_dcache_cc_send_way = way;
[816]	4173	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
[331]	4174
	4175	}
	4176	else
	4177	{
[487]	4178	r_dcache_cleanup_victim_req = true;
	4179	r_dcache_cleanup_victim_nline = victim;
[331]	4180	}
	4181
[789]	4182	r_dcache_miss_clack = true;
	4183	r_dcache_fsm = DCACHE_MISS_CLEAN;
[487]	4184	}
	4185	else
	4186	{
[789]	4187	r_dcache_fsm = DCACHE_MISS_WAIT;
[487]	4188	}
	4189
[331]	4190	#if DEBUG_DCACHE
[789]	4191	if (m_debug_dcache_fsm)
	4192	{
	4193	std::cout << " <PROC " << name()
	4194	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
	4195	<< " / WAY = " << way
	4196	<< " / SET = " << set
	4197	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
	4198	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
	4199	else std::cout << std::endl;
	4200	}
[331]	4201	#endif
[487]	4202	} // end found
[331]	4203	break;
	4204	}
	4205	///////////////////////
[789]	4206	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
[331]	4207	// and possibly request itlb or dtlb invalidate
	4208	{
[789]	4209	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4210
[789]	4211	size_t way = r_dcache_miss_way.read();
	4212	size_t set = r_dcache_miss_set.read();
[331]	4213
	4214	#ifdef INSTRUMENTATION
[789]	4215	m_cpt_dcache_dir_read++;
[331]	4216	#endif
[789]	4217	r_dcache.write_dir(way,
	4218	set,
	4219	CACHE_SLOT_STATE_ZOMBI);
[331]	4220	#if DEBUG_DCACHE
[789]	4221	if (m_debug_dcache_fsm)
	4222	{
	4223	std::cout << " <PROC " << name()
	4224	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
	4225	<< " / way = " << way
	4226	<< " / set = " << set << std::endl;
	4227	}
[331]	4228	#endif
	4229	// if selective itlb & dtlb invalidate are required
	4230	// the miss response is not handled before invalidate completed
[789]	4231	if (r_dcache_in_tlb[way * m_dcache_sets + set])
[331]	4232	{
[789]	4233	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[532]	4234
[789]	4235	if (not r_dcache_cleanup_victim_req.read())
	4236	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
[532]	4237	else
	4238	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
	4239
[789]	4240	r_dcache_tlb_inval_set = 0;
	4241	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
	4242	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[331]	4243	}
[789]	4244	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
[331]	4245	{
	4246	r_itlb.reset();
	4247	r_dtlb.reset();
[789]	4248	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	4249	r_dcache_fsm = DCACHE_MISS_WAIT;
	4250	}
	4251	else
	4252	{
	4253	r_dcache_fsm = DCACHE_MISS_WAIT;
	4254	}
	4255	break;
	4256	}
	4257	//////////////////////
[789]	4258	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
[331]	4259	// This state is in charge of error signaling
	4260	// There is 5 types of error depending on the requester
	4261	{
[789]	4262	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4263
[487]	4264	// send cleanup victim request
[789]	4265	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
[487]	4266	{
	4267	r_dcache_cc_send_req = true;
	4268	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
	4269	r_dcache_cc_send_way = r_dcache_miss_way;
[816]	4270	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
[487]	4271	r_dcache_cleanup_victim_req = false;
[816]	4272	}
[487]	4273
[488]	4274	// coherence clack request (from DSPIN CLACK)
[789]	4275	if (r_dcache_clack_req.read())
[488]	4276	{
	4277	r_dcache_fsm = DCACHE_CC_CHECK;
	4278	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4279	break;
	4280	}
	4281
[331]	4282	// coherence request (from CC_RECEIVE FSM)
[816]	4283	if (r_cc_receive_dcache_req.read() and
	4284	not r_dcache_cc_send_req.read() and
[711]	4285	not r_dcache_cleanup_victim_req.read())
[331]	4286	{
	4287	r_dcache_fsm = DCACHE_CC_CHECK;
	4288	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4289	break;
	4290	}
	4291
[789]	4292	if (r_vci_rsp_data_error.read()) // bus error
[331]	4293	{
[789]	4294	switch (r_dcache_miss_type.read())
[331]	4295	{
	4296	case PROC_MISS:
	4297	{
[789]	4298	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
	4299	r_mmu_dbvar = r_dcache_save_vaddr.read();
	4300	m_drsp.valid = true;
	4301	m_drsp.error = true;
	4302	r_dcache_fsm = DCACHE_IDLE;
[331]	4303	break;
	4304	}
	4305	case PTE1_MISS:
	4306	{
[789]	4307	if (r_dcache_tlb_ins.read())
[331]	4308	{
[789]	4309	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
	4310	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	4311	r_icache_tlb_miss_req = false;
	4312	r_icache_tlb_rsp_error = true;
[331]	4313	}
	4314	else
	4315	{
[789]	4316	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
	4317	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	4318	m_drsp.valid = true;
	4319	m_drsp.error = true;
[331]	4320	}
[789]	4321	r_dcache_fsm = DCACHE_IDLE;
[331]	4322	break;
	4323	}
	4324	case PTE2_MISS:
	4325	{
[789]	4326	if (r_dcache_tlb_ins.read())
[331]	4327	{
[789]	4328	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
	4329	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	4330	r_icache_tlb_miss_req = false;
	4331	r_icache_tlb_rsp_error = true;
[331]	4332	}
	4333	else
	4334	{
[789]	4335	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
	4336	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	4337	m_drsp.valid = true;
	4338	m_drsp.error = true;
[331]	4339	}
[789]	4340	r_dcache_fsm = DCACHE_IDLE;
[331]	4341	break;
	4342	}
	4343	} // end switch type
	4344	r_vci_rsp_data_error = false;
	4345	}
[789]	4346	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
[331]	4347	{
	4348	r_dcache_miss_word = 0;
[789]	4349	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
[331]	4350	}
	4351	break;
	4352	}
	4353	//////////////////////////
[789]	4354	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
[331]	4355	{
[789]	4356	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4357
[789]	4358	if (r_vci_rsp_fifo_dcache.rok()) // one word available
[331]	4359	{
	4360	#ifdef INSTRUMENTATION
[789]	4361	m_cpt_dcache_data_write++;
[331]	4362	#endif
[789]	4363	r_dcache.write(r_dcache_miss_way.read(),
	4364	r_dcache_miss_set.read(),
	4365	r_dcache_miss_word.read(),
	4366	r_vci_rsp_fifo_dcache.read());
[331]	4367	#if DEBUG_DCACHE
[789]	4368	if (m_debug_dcache_fsm)
	4369	{
	4370	std::cout << " <PROC " << name()
	4371	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
	4372	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
	4373	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
	4374	<< " / SET = " << r_dcache_miss_set.read()
	4375	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
	4376	}
[331]	4377	#endif
	4378	vci_rsp_fifo_dcache_get = true;
	4379	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
	4380
[789]	4381	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
[331]	4382	{
	4383	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
	4384	}
	4385	}
	4386	break;
	4387	}
	4388	//////////////////////////
	4389	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
	4390	// and the cleanup ack has not been received,
	4391	// as indicated by the r_dcache_miss clack.
	4392	// - If no matching coherence request (r_dcache_inval_miss)
	4393	// switch directory slot to VALID state.
	4394	// - If matching coherence request, switch directory slot
	4395	// to ZOMBI state, and send a cleanup request.
	4396	{
[789]	4397	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4398
[487]	4399	// send cleanup victim request
[789]	4400	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
[487]	4401	{
	4402	r_dcache_cc_send_req = true;
	4403	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
	4404	r_dcache_cc_send_way = r_dcache_miss_way;
[816]	4405	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
[487]	4406	r_dcache_cleanup_victim_req = false;
[816]	4407	}
[487]	4408
[488]	4409	// coherence clack request (from DSPIN CLACK)
[789]	4410	if (r_dcache_clack_req.read())
[488]	4411	{
	4412	r_dcache_fsm = DCACHE_CC_CHECK;
	4413	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4414	break;
	4415	}
	4416
[331]	4417	// coherence request (from CC_RECEIVE FSM)
[816]	4418	if (r_cc_receive_dcache_req.read() and
	4419	not r_dcache_cc_send_req.read() and
[789]	4420	not r_dcache_cleanup_victim_req.read())
[331]	4421	{
	4422	r_dcache_fsm = DCACHE_CC_CHECK;
	4423	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4424	break;
	4425	}
	4426
[789]	4427	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
[331]	4428	{
[789]	4429	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
[331]	4430	{
[789]	4431	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
[331]	4432	{
	4433	r_dcache_miss_inval = false;
	4434	// request cleanup
	4435	r_dcache_cc_send_req = true;
[789]	4436	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
[331]	4437	r_dcache_cc_send_way = r_dcache_miss_way.read();
	4438	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	4439
	4440	#ifdef INSTRUMENTATION
[789]	4441	m_cpt_dcache_dir_write++;
[331]	4442	#endif
	4443	r_dcache.write_dir( r_dcache_save_paddr.read(),
	4444	r_dcache_miss_way.read(),
	4445	r_dcache_miss_set.read(),
	4446	CACHE_SLOT_STATE_ZOMBI );
	4447	#if DEBUG_DCACHE
[789]	4448	if (m_debug_dcache_fsm)
	4449	std::cout << " <PROC " << name()
	4450	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
	4451	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
	4452	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
	4453	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
[331]	4454	#endif
	4455	}
	4456	else
	4457	break;
	4458	}
	4459	else // switch slot to VALID state
	4460	{
	4461
	4462	#ifdef INSTRUMENTATION
[789]	4463	m_cpt_dcache_dir_write++;
[331]	4464	#endif
[789]	4465	r_dcache.write_dir(r_dcache_save_paddr.read(),
	4466	r_dcache_miss_way.read(),
	4467	r_dcache_miss_set.read(),
	4468	CACHE_SLOT_STATE_VALID);
[331]	4469
	4470	#if DEBUG_DCACHE
[789]	4471	if (m_debug_dcache_fsm)
	4472	std::cout << " <PROC " << name()
	4473	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
	4474	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
	4475	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
	4476	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
[331]	4477	#endif
	4478	// reset directory extension
	4479	size_t way = r_dcache_miss_way.read();
	4480	size_t set = r_dcache_miss_set.read();
[789]	4481	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
	4482	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	4483	}
[836]	4484	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
	4485	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
	4486	else r_dcache_fsm = DCACHE_IDLE;
[331]	4487	}
	4488	break;
	4489	}
	4490	/////////////////////
[816]	4491	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
[331]	4492	{
[468]	4493	// coherence clack request (from DSPIN CLACK)
[789]	4494	if (r_dcache_clack_req.read())
[468]	4495	{
	4496	r_dcache_fsm = DCACHE_CC_CHECK;
	4497	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4498	break;
	4499	}
	4500
[331]	4501	// coherence request (from CC_RECEIVE FSM)
[789]	4502	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4503	{
	4504	r_dcache_fsm = DCACHE_CC_CHECK;
	4505	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4506	break;
	4507	}
	4508
[789]	4509	if (r_vci_rsp_data_error.read()) // bus error
[331]	4510	{
[789]	4511	if (r_dcache_vci_unc_write.read())
	4512	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
[616]	4513	else
[789]	4514	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
[816]	4515
[331]	4516	r_mmu_dbvar = m_dreq.addr;
	4517	r_vci_rsp_data_error = false;
	4518	m_drsp.error = true;
	4519	m_drsp.valid = true;
	4520	r_dcache_fsm = DCACHE_IDLE;
	4521	break;
	4522	}
[789]	4523	else if (r_vci_rsp_fifo_dcache.rok()) // data available
	4524	{
[331]	4525	// consume data
	4526	vci_rsp_fifo_dcache_get = true;
	4527	r_dcache_fsm = DCACHE_IDLE;
	4528
	4529	// acknowledge the processor request if it has not been modified
[789]	4530	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
[331]	4531	{
[789]	4532	m_drsp.valid = true;
	4533	m_drsp.error = false;
	4534	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
[331]	4535	}
[789]	4536	}
[331]	4537	break;
	4538	}
	4539	/////////////////////
	4540	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
	4541	{
[468]	4542	// coherence clack request (from DSPIN CLACK)
[789]	4543	if (r_dcache_clack_req.read())
[468]	4544	{
	4545	r_dcache_fsm = DCACHE_CC_CHECK;
	4546	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4547	break;
	4548	}
	4549
[331]	4550	// coherence request (from CC_RECEIVE FSM)
[789]	4551	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4552	{
	4553	r_dcache_fsm = DCACHE_CC_CHECK;
	4554	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4555	break;
	4556	}
	4557
[789]	4558	if (r_vci_rsp_data_error.read()) // bus error
[331]	4559	{
	4560	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
	4561	r_mmu_dbvar = m_dreq.addr;
	4562	r_vci_rsp_data_error = false;
	4563	m_drsp.error = true;
	4564	m_drsp.valid = true;
	4565	r_dcache_fsm = DCACHE_IDLE;
	4566	break;
	4567	}
[789]	4568	else if (r_vci_rsp_fifo_dcache.rok()) // data available
	4569	{
[331]	4570	// consume data
	4571	vci_rsp_fifo_dcache_get = true;
	4572
[789]	4573	if (r_dcache_ll_rsp_count.read() == 0) // first flit
[331]	4574	{
	4575	// set key value in llsc reservation buffer
	4576	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
[789]	4577	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
[331]	4578	}
	4579	else // last flit
	4580	{
	4581	// acknowledge the processor request if it has not been modified
[789]	4582	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
[331]	4583	{
[789]	4584	m_drsp.valid = true;
	4585	m_drsp.error = false;
	4586	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
[331]	4587	}
	4588	r_dcache_fsm = DCACHE_IDLE;
	4589	}
[789]	4590	}
[331]	4591	break;
	4592	}
	4593	////////////////////
[789]	4594	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
[331]	4595	{
[468]	4596	// coherence clack request (from DSPIN CLACK)
[789]	4597	if (r_dcache_clack_req.read())
[468]	4598	{
	4599	r_dcache_fsm = DCACHE_CC_CHECK;
	4600	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4601	break;
	4602	}
	4603
[331]	4604	// coherence request (from CC_RECEIVE FSM)
[789]	4605	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4606	{
	4607	r_dcache_fsm = DCACHE_CC_CHECK;
	4608	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4609	break;
	4610	}
	4611
[789]	4612	if (r_vci_rsp_data_error.read()) // bus error
[331]	4613	{
	4614	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
	4615	r_mmu_dbvar = m_dreq.addr;
	4616	r_vci_rsp_data_error = false;
	4617	m_drsp.error = true;
	4618	m_drsp.valid = true;
	4619	r_dcache_fsm = DCACHE_IDLE;
	4620	break;
	4621	}
[789]	4622	else if (r_vci_rsp_fifo_dcache.rok()) // response available
	4623	{
[331]	4624	// consume response
	4625	vci_rsp_fifo_dcache_get = true;
	4626	m_drsp.valid = true;
	4627	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
	4628	r_dcache_fsm = DCACHE_IDLE;
[789]	4629	}
[331]	4630	break;
	4631	}
	4632	//////////////////////////
[789]	4633	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
	4634	// before handling a processor WRITE or SC request
	4635	// Input argument is r_dcache_dirty_paddr
	4636	// In this first state, we get PTE value in dcache
	4637	// and post a CAS request to CMD FSM
[331]	4638	{
	4639	// get PTE in dcache
	4640	uint32_t pte;
	4641	size_t way;
	4642	size_t set;
[468]	4643	size_t word; // unused
[331]	4644	int state;
	4645
	4646	#ifdef INSTRUMENTATION
[789]	4647	m_cpt_dcache_data_read++;
	4648	m_cpt_dcache_dir_read++;
[331]	4649	#endif
[789]	4650	r_dcache.read(r_dcache_dirty_paddr.read(),
	4651	&pte,
	4652	&way,
	4653	&set,
	4654	&word,
	4655	&state);
[331]	4656
	4657	assert( (state == CACHE_SLOT_STATE_VALID) and
	4658	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
	4659
	4660	// request CAS transaction to CMD_FSM
[789]	4661	r_dcache_dirty_way = way;
	4662	r_dcache_dirty_set = set;
[331]	4663
	4664	// check llsc reservation buffer
[789]	4665	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
[331]	4666	r_dcache_llsc_valid = false;
	4667
	4668	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
	4669	r_dcache_vci_cas_req = true;
	4670	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
	4671	r_dcache_vci_cas_old = pte;
	4672	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
	4673	r_dcache_fsm = DCACHE_DIRTY_WAIT;
	4674
	4675	#if DEBUG_DCACHE
[789]	4676	if (m_debug_dcache_fsm)
	4677	{
	4678	std::cout << " <PROC " << name()
	4679	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
	4680	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
	4681	<< " / PTE_VALUE = " << pte << std::dec
	4682	<< " / SET = " << set
	4683	<< " / WAY = " << way << std::endl;
	4684	}
[331]	4685	#endif
	4686	break;
	4687	}
	4688	///////////////////////
[789]	4689	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
	4690	// and return to IDLE state when response is received.
	4691	// we don't care if the CAS is a failure:
	4692	// - if the CAS is a success, the coherence mechanism
	4693	// updates the local copy.
	4694	// - if the CAS is a failure, we just retry the write.
[331]	4695	{
[468]	4696	// coherence clack request (from DSPIN CLACK)
[789]	4697	if (r_dcache_clack_req.read())
[468]	4698	{
	4699	r_dcache_fsm = DCACHE_CC_CHECK;
	4700	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4701	break;
	4702	}
	4703
[331]	4704	// coherence request (from CC_RECEIVE FSM)
[789]	4705	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4706	{
	4707	r_dcache_fsm = DCACHE_CC_CHECK;
	4708	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4709	break;
	4710	}
	4711
[789]	4712	if (r_vci_rsp_data_error.read()) // bus error
[331]	4713	{
	4714	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
	4715	std::cout << "This should not happen in this state" << std::endl;
	4716	exit(0);
	4717	}
[789]	4718	else if (r_vci_rsp_fifo_dcache.rok()) // response available
[331]	4719	{
	4720	vci_rsp_fifo_dcache_get = true;
	4721	r_dcache_fsm = DCACHE_IDLE;
	4722
	4723	#if DEBUG_DCACHE
[789]	4724	if (m_debug_dcache_fsm)
	4725	{
	4726	std::cout << " <PROC " << name()
	4727	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
	4728	}
[331]	4729	#endif
	4730	}
	4731	break;
	4732	}
	4733	/////////////////////
	4734	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
	4735	// handling coherence requests for DCACHE.
	4736	// If there is a matching pending miss on the modified cache
	4737	// line this is signaled in the r_dcache_miss inval flip-flop.
	4738	// If the updated (or invalidated) cache line has copies in TLBs
	4739	// these TLB copies are invalidated.
	4740	// The return state is defined in r_dcache_fsm_cc_save
	4741	{
[789]	4742	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
	4743	paddr_t mask = ~((m_dcache_words << 2) - 1);
[331]	4744
[484]	4745	// CLACK handler
	4746	// We switch the directory slot to EMPTY state and reset
	4747	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
[789]	4748	if (r_dcache_clack_req.read())
[484]	4749	{
[789]	4750	if (m_dreq.valid ) m_cost_data_miss_frz++;
[331]	4751
[484]	4752	#ifdef INSTRUMENTATION
[789]	4753	m_cpt_dcache_dir_write++;
[484]	4754	#endif
[789]	4755	r_dcache.write_dir(0,
	4756	r_dcache_clack_way.read(),
	4757	r_dcache_clack_set.read(),
	4758	CACHE_SLOT_STATE_EMPTY);
[484]	4759
[789]	4760	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
	4761	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
[484]	4762	{
	4763	r_dcache_miss_clack = false;
	4764	}
	4765
	4766	r_dcache_clack_req = false;
	4767
	4768	// return to cc_save state
	4769	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
	4770
	4771	#if DEBUG_DCACHE
[789]	4772	if (m_debug_dcache_fsm)
	4773	{
	4774	std::cout << " <PROC " << name()
	4775	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
	4776	<< " Switch slot to EMPTY state : "
	4777	<< " set = " << r_dcache_clack_set.read()
	4778	<< " / way = " << r_dcache_clack_way.read() << std::endl;
	4779	}
[484]	4780	#endif
	4781	break;
	4782	}
	4783
[836]	4784	assert(not r_dcache_cc_send_req.read() and
	4785	"CC_SEND must be available in DCACHE_CC_CHECK");
[487]	4786
[468]	4787	// Match between MISS address and CC address
[816]	4788	if (r_cc_receive_dcache_req.read() and
[789]	4789	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
	4790	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
[468]	4791	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
	4792	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
[331]	4793	{
	4794	// signaling matching
	4795	r_dcache_miss_inval = true;
	4796
	4797	// in case of update, go to CC_UPDT
	4798	// JUST TO POP THE FIFO
	4799	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
	4800	{
[789]	4801	r_dcache_fsm = DCACHE_CC_UPDT;
	4802	r_dcache_cc_word = r_cc_receive_word_idx.read();
[468]	4803
[331]	4804	// just pop the fifo , don't write in icache
	4805	r_dcache_cc_need_write = false;
	4806	}
	4807	// the request is dealt with
	4808	else
	4809	{
	4810	r_cc_receive_dcache_req = false;
[468]	4811	r_dcache_fsm = r_dcache_fsm_cc_save.read();
[331]	4812	}
	4813
	4814	#if DEBUG_DCACHE
[789]	4815	if (m_debug_dcache_fsm)
	4816	{
	4817	std::cout << " <PROC " << name()
	4818	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
	4819	<< " PADDR = " << std::hex << paddr << std::endl;
	4820	}
[331]	4821	#endif
[468]	4822	}
[331]	4823
[468]	4824	// CC request handler
[816]	4825
[468]	4826	int state = 0;
	4827	size_t way = 0;
	4828	size_t set = 0;
	4829	size_t word = 0;
	4830
[331]	4831	#ifdef INSTRUMENTATION
[789]	4832	m_cpt_dcache_dir_read++;
[331]	4833	#endif
[789]	4834	r_dcache.read_dir(paddr,
	4835	&state,
	4836	&way,
	4837	&set,
	4838	&word); // unused
[331]	4839
[468]	4840	r_dcache_cc_way = way;
	4841	r_dcache_cc_set = set;
[331]	4842
[789]	4843	if (state == CACHE_SLOT_STATE_VALID) // hit
[468]	4844	{
	4845	// need to update the cache state
	4846	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
[331]	4847	{
	4848	r_dcache_cc_need_write = true;
[468]	4849	r_dcache_fsm = DCACHE_CC_UPDT;
	4850	r_dcache_cc_word = r_cc_receive_word_idx.read();
[331]	4851	}
[789]	4852	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
[331]	4853	{
[789]	4854	r_dcache_fsm = DCACHE_CC_INVAL;
[331]	4855	}
[468]	4856	}
	4857	else // miss
	4858	{
	4859	// multicast acknowledgement required in case of update
[789]	4860	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
[468]	4861	{
[789]	4862	r_dcache_fsm = DCACHE_CC_UPDT;
	4863	r_dcache_cc_word = r_cc_receive_word_idx.read();
[331]	4864
[468]	4865	// just pop the fifo , don't write in icache
	4866	r_dcache_cc_need_write = false;
	4867	}
	4868	else // No response needed
	4869	{
	4870	r_cc_receive_dcache_req = false;
[789]	4871	r_dcache_fsm = r_dcache_fsm_cc_save.read();
[468]	4872	}
	4873	}
	4874
[331]	4875	#if DEBUG_DCACHE
[789]	4876	if (m_debug_dcache_fsm)
	4877	{
	4878	std::cout << " <PROC " << name()
	4879	<< " DCACHE_CC_CHECK> Coherence request received:"
	4880	<< " PADDR = " << std::hex << paddr
	4881	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
	4882	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
	4883	}
[331]	4884	#endif
[468]	4885
[331]	4886	break;
	4887	}
	4888	/////////////////////
[468]	4889	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
	4890	// CLEANUP after possible invalidation of copies in
	4891	// TLBs
[331]	4892	{
[789]	4893	size_t way = r_dcache_cc_way.read();
	4894	size_t set = r_dcache_cc_set.read();
[331]	4895
[789]	4896	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
[331]	4897	{
[789]	4898	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
	4899	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
	4900	r_dcache_tlb_inval_set = 0;
	4901	r_dcache_fsm_scan_save = r_dcache_fsm.read();
	4902	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[468]	4903	break;
	4904	}
[331]	4905
[789]	4906	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
[468]	4907	{
	4908	r_itlb.reset();
	4909	r_dtlb.reset();
[789]	4910	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[468]	4911
[331]	4912	#if DEBUG_DCACHE
[789]	4913	if (m_debug_dcache_fsm)
	4914	{
	4915	std::cout << " <PROC " << name()
	4916	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
	4917	}
[331]	4918	#endif
[468]	4919	}
[331]	4920
[789]	4921	assert(not r_dcache_cc_send_req.read() &&
[468]	4922	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
	4923	"must not be set");
[331]	4924
[816]	4925	// Switch slot state to ZOMBI and send CLEANUP command
[789]	4926	r_dcache.write_dir(way,
	4927	set,
	4928	CACHE_SLOT_STATE_ZOMBI);
[331]	4929
[468]	4930	// coherence request completed
	4931	r_cc_receive_dcache_req = false;
	4932	r_dcache_cc_send_req = true;
	4933	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
	4934	r_dcache_cc_send_way = r_dcache_cc_way.read();
	4935	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	4936	r_dcache_fsm = r_dcache_fsm_cc_save.read();
	4937
[331]	4938	#if DEBUG_DCACHE
[789]	4939	if (m_debug_dcache_fsm)
	4940	{
	4941	std::cout << " <PROC " << name()
	4942	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
	4943	<< " / WAY = " << way
	4944	<< " / SET = " << set << std::endl;
	4945	}
[331]	4946	#endif
	4947	break;
	4948	}
	4949	///////////////////
[789]	4950	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
	4951	// after possible invalidation of copies in TLBs
[331]	4952	{
[789]	4953	size_t word = r_dcache_cc_word.read();
	4954	size_t way = r_dcache_cc_way.read();
	4955	size_t set = r_dcache_cc_set.read();
[331]	4956
[789]	4957	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
[331]	4958	{
[789]	4959	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[468]	4960	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
	4961	r_dcache_tlb_inval_set = 0;
	4962	r_dcache_fsm_scan_save = r_dcache_fsm.read();
	4963	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[331]	4964
[468]	4965	break;
	4966	}
[331]	4967
[789]	4968	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
[468]	4969	{
	4970	r_itlb.reset();
	4971	r_dtlb.reset();
[789]	4972	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[468]	4973
[331]	4974	#if DEBUG_DCACHE
[789]	4975	if (m_debug_dcache_fsm)
	4976	{
	4977	std::cout << " <PROC " << name()
	4978	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
	4979	}
[331]	4980	#endif
[468]	4981	}
[331]	4982
[468]	4983	assert (not r_dcache_cc_send_req.read() &&
	4984	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
	4985	"must not be set");
[816]	4986
[789]	4987	if (not r_cc_receive_updt_fifo_be.rok()) break;
[468]	4988
	4989	if (r_dcache_cc_need_write.read())
	4990	{
[816]	4991
[331]	4992	#ifdef INSTRUMENTATION
[789]	4993	m_cpt_dcache_data_write++;
[331]	4994	#endif
[789]	4995	r_dcache.write(way,
	4996	set,
	4997	word,
	4998	r_cc_receive_updt_fifo_data.read(),
	4999	r_cc_receive_updt_fifo_be.read());
[331]	5000
[468]	5001	r_dcache_cc_word = word + 1;
[331]	5002
	5003	#if DEBUG_DCACHE
[789]	5004	if (m_debug_dcache_fsm)
	5005	{
	5006	std::cout << " <PROC " << name()
	5007	<< " DCACHE_CC_UPDT> Write one word" << std::dec
	5008	<< " / WAY = " << way
	5009	<< " / SET = " << set
	5010	<< " / WORD = " << word
	5011	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
	5012	}
[331]	5013	#endif
	5014	}
	5015
[789]	5016	if (r_cc_receive_updt_fifo_eop.read()) // last word
[331]	5017	{
[468]	5018	// no need to write in the cache anymore
	5019	r_dcache_cc_need_write = false;
[331]	5020
[468]	5021	// coherence request completed
	5022	r_cc_receive_dcache_req = false;
[331]	5023
[468]	5024	// request multicast acknowledgement
	5025	r_dcache_cc_send_req = true;
	5026	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
	5027	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
	5028	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
	5029	r_dcache_fsm = r_dcache_fsm_cc_save.read();
[331]	5030	}
	5031
[468]	5032	//consume fifo if not eop
	5033	cc_receive_updt_fifo_get = true;
	5034
[331]	5035	break;
	5036	}
	5037	///////////////////////////
[789]	5038	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
	5039	// It makes assumption: m_itlb_sets == m_dtlb_sets
	5040	// All ways are handled in parallel.
	5041	// We enter this state when a DCACHE line is modified,
	5042	// and there is a copy in itlb or dtlb.
	5043	// It can be caused by:
	5044	// - a coherence inval or updt transaction,
	5045	// - a line inval caused by a cache miss
	5046	// - a processor XTN inval request,
	5047	// - a WRITE hit,
	5048	// - a Dirty bit update
	5049	// Input arguments are:
	5050	// - r_dcache_tlb_inval_line
	5051	// - r_dcache_tlb_inval_set
	5052	// - r_dcache_fsm_scan_save
[331]	5053	{
[789]	5054	paddr_t line = r_dcache_tlb_inval_line.read();
	5055	size_t set = r_dcache_tlb_inval_set.read();
	5056	size_t way;
	5057	bool ok;
[331]	5058
[789]	5059	for (way = 0; way < m_itlb_ways; way++)
[331]	5060	{
[789]	5061	ok = r_itlb.inval(line, way, set);
[331]	5062
	5063	#if DEBUG_DCACHE
[789]	5064	if (m_debug_dcache_fsm and ok)
	5065	{
	5066	std::cout << " <PROC " << name()
	5067	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
	5068	<< " line = " << line << std::dec
	5069	<< " / set = " << set
	5070	<< " / way = " << way << std::endl;
	5071	}
[331]	5072	#endif
	5073	}
	5074
[789]	5075	for (way = 0; way < m_dtlb_ways; way++)
[331]	5076	{
[789]	5077	ok = r_dtlb.inval( line, way, set);
[331]	5078
	5079	#if DEBUG_DCACHE
[789]	5080	if (m_debug_dcache_fsm and ok)
	5081	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
	5082	<< " Invalidate DTLB entry" << std::hex
	5083	<< " / line = " << line << std::dec
	5084	<< " / set = " << set
	5085	<< " / way = " << way << std::endl;
[331]	5086	#endif
	5087	}
	5088
	5089	// return to the calling state when TLB inval completed
[789]	5090	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
[331]	5091	{
	5092	r_dcache_fsm = r_dcache_fsm_scan_save.read();
	5093	}
	5094	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
	5095	break;
	5096	}
	5097	} // end switch r_dcache_fsm
	5098
[1047]	5099	///////////////// wbuf update //////////////////////////////////////////////////////////
[331]	5100	r_wbuf.update();
	5101
[1047]	5102	///////////////// llsc update //////////////////////////////////////////////////////////
[331]	5103	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
	5104	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
	5105
[1047]	5106	//////////////// test processor frozen /////////////////////////////////////////////////
	5107	// 1) The m_cpt_frz_cycles counter defining the total number of cache related frozen
	5108	// cycles is incremented.
	5109	// 2) If the processor is continuously frozen for more than (m_max_frozen_cycles / 20),
	5110	// a warning is issued, and the two m_cpt_frozen_events & m_cpt_frozen_cost counters
	5111	// are incremented to evaluate the frequency and cost of pahological transactions.
	5112	// 3) If the processor is continuously frozen for more than (m_max_frozen_cycles),
	5113	// the simulation is stopped, with an error message.
	5114	////////////////////////////////////////////////////////////////////////////////////////
	5115
	5116	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid)) // frozen
[331]	5117	{
[1047]	5118	m_cpt_frz_cycles++; // total number of frozen cycles
	5119	m_cpt_stop_simulation++; // number of continuously frozen cycles
	5120	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
[331]	5121	{
	5122	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
	5123	<< " stop at cycle " << m_cpt_total_cycles << std::endl
	5124	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
	5125	<< std::endl;
	5126	r_iss.dump();
[896]	5127	r_wbuf.printTrace();
	5128	raise(SIGINT);
[331]	5129	}
	5130	}
[1047]	5131	else // processor not frozen
[331]	5132	{
[1047]	5133	if ( m_cpt_stop_simulation > (m_max_frozen_cycles/20) )
	5134	{
	5135	m_cpt_frozen_events++;
	5136	m_cpt_frozen_cost += m_cpt_stop_simulation;
	5137	std::cout << std::dec << "WARNING : Proc " << name()
	5138	<< " frozen from cycle " << (m_cpt_total_cycles - m_cpt_stop_simulation)
	5139	<< " for " << (m_cpt_stop_simulation / 1000) << " Kcyles" << std::endl;
	5140	}
[331]	5141	m_cpt_stop_simulation = 0;
	5142	}
	5143
	5144	/////////// execute one iss cycle /////////////////////////////////
	5145	{
[789]	5146	uint32_t it = 0;
	5147	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
	5148	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
[331]	5149	}
	5150
	5151	////////////////////////////////////////////////////////////////////////////
	5152	// The VCI_CMD FSM controls the following ressources:
	5153	// - r_vci_cmd_fsm
	5154	// - r_vci_cmd_min
	5155	// - r_vci_cmd_max
	5156	// - r_vci_cmd_cpt
	5157	// - r_vci_cmd_imiss_prio
	5158	// - wbuf (reset)
	5159	// - r_icache_miss_req (reset)
	5160	// - r_icache_unc_req (reset)
	5161	// - r_dcache_vci_miss_req (reset)
	5162	// - r_dcache_vci_unc_req (reset)
	5163	// - r_dcache_vci_ll_req (reset)
	5164	// - r_dcache_vci_sc_req (reset in case of local sc fail)
	5165	// - r_dcache_vci_cas_req (reset)
	5166	//
	5167	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
	5168	// There are 8 request types, with the following priorities :
	5169	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
	5170	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
	5171	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
	5172	// 4 - Instruction Uncachable : r_icache_unc_req
	5173	// 5 - Data Write : r_wbuf.rok()
	5174	// 6 - Data Linked Load : r_dcache_vci_ll_req
	5175	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
	5176	// 8 - Compare And Swap : r_dcache_vci_cas_req
	5177	//
	5178	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
	5179	// and the VCI_RSP_FSM are fully desynchronized.
	5180	//
	5181	// VCI formats:
	5182	// According to the VCI advanced specification, all read requests packets
	5183	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
	5184	// are one word packets.
	5185	// For write burst packets, all words are in the same cache line,
	5186	// and addresses must be contiguous (the BE field is 0 in case of "holes").
	5187	// The sc command packet implements actually a compare-and-swap mechanism
	5188	// and the packet contains two flits.
	5189	////////////////////////////////////////////////////////////////////////////////////
	5190
[423]	5191
[789]	5192	switch (r_vci_cmd_fsm.read())
[331]	5193	{
	5194	//////////////
	5195	case CMD_IDLE:
	5196	{
[394]	5197	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
[331]	5198	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
	5199	// to check a possible pending write on the same cache line.
	5200	// As there is only one possible access per cycle to write buffer, we implement
	5201	// a round-robin priority between DCACHE and ICACHE for this access,
	5202	// using the r_vci_cmd_imiss_prio flip-flop.
	5203
[789]	5204	size_t wbuf_min;
	5205	size_t wbuf_max;
[331]	5206
	5207	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
[789]	5208	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[331]	5209
[789]	5210	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
	5211	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[331]	5212
[789]	5213	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
	5214	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[616]	5215
[789]	5216	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
	5217	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[616]	5218
[331]	5219	bool icache_miss_req = r_icache_miss_req.read() and
[789]	5220	(not (r_dcache_vci_miss_req.read() or
	5221	r_dcache_vci_ll_req.read() or
	5222	r_dcache_vci_cas_req.read() or
	5223	r_dcache_vci_sc_req.read()) or
	5224	r_vci_cmd_imiss_prio.read());
[331]	5225
[616]	5226	// 1 - Data unc write
[789]	5227	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
[331]	5228	{
[616]	5229	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
	5230	r_dcache_vci_unc_req = false;
	5231	}
	5232	// 2 data read miss
[789]	5233	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[616]	5234	{
[331]	5235	r_vci_cmd_fsm = CMD_DATA_MISS;
	5236	r_dcache_vci_miss_req = false;
	5237	r_vci_cmd_imiss_prio = true;
	5238	}
[616]	5239	// 3 - Data Read Uncachable
[789]	5240	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
[331]	5241	{
[616]	5242	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
[331]	5243	r_dcache_vci_unc_req = false;
	5244	}
[616]	5245	// 4 - Data Linked Load
[789]	5246	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[331]	5247	{
[616]	5248	r_vci_cmd_fsm = CMD_DATA_LL;
	5249	r_dcache_vci_ll_req = false;
	5250	r_vci_cmd_imiss_prio = true;
[331]	5251	}
[616]	5252	// 5 - Instruction Miss
[789]	5253	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
[331]	5254	{
	5255	r_vci_cmd_fsm = CMD_INS_MISS;
	5256	r_icache_miss_req = false;
	5257	r_vci_cmd_imiss_prio = false;
	5258	}
[616]	5259	// 6 - Instruction Uncachable
[789]	5260	else if (r_icache_unc_req.read())
[331]	5261	{
[789]	5262	r_vci_cmd_fsm = CMD_INS_UNC;
	5263	r_icache_unc_req = false;
[331]	5264	}
[616]	5265	// 7 - Data Write
[789]	5266	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
[331]	5267	{
[789]	5268	r_vci_cmd_fsm = CMD_DATA_WRITE;
	5269	r_vci_cmd_cpt = wbuf_min;
	5270	r_vci_cmd_min = wbuf_min;
	5271	r_vci_cmd_max = wbuf_max;
[331]	5272	}
[616]	5273	// 8 - Data Store Conditionnal
[789]	5274	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[331]	5275	{
[789]	5276	r_vci_cmd_fsm = CMD_DATA_SC;
	5277	r_dcache_vci_sc_req = false;
	5278	r_vci_cmd_imiss_prio = true;
	5279	r_vci_cmd_cpt = 0;
[331]	5280	}
[616]	5281	// 9 - Compare And Swap
[789]	5282	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[331]	5283	{
[789]	5284	r_vci_cmd_fsm = CMD_DATA_CAS;
	5285	r_dcache_vci_cas_req = false;
	5286	r_vci_cmd_imiss_prio = true;
	5287	r_vci_cmd_cpt = 0;
[331]	5288	}
[394]	5289
	5290	#if DEBUG_CMD
[789]	5291	if (m_debug_cmd_fsm )
	5292	{
	5293	std::cout << " <PROC " << name() << " CMD_IDLE>"
	5294	<< " / dmiss_req = " << dcache_miss_req
	5295	<< " / imiss_req = " << icache_miss_req
	5296	<< std::endl;
	5297	}
[394]	5298	#endif
[331]	5299	break;
	5300	}
	5301	////////////////////
	5302	case CMD_DATA_WRITE:
	5303	{
[789]	5304	if (p_vci.cmdack.read())
[331]	5305	{
	5306	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
	5307	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
	5308	{
[789]	5309	r_vci_cmd_fsm = CMD_IDLE;
	5310	r_wbuf.sent();
[331]	5311	}
	5312	}
	5313	break;
	5314	}
	5315	/////////////////
	5316	case CMD_DATA_SC:
	5317	case CMD_DATA_CAS:
	5318	{
	5319	// The CAS and SC VCI commands contain two flits
[789]	5320	if (p_vci.cmdack.read())
[331]	5321	{
	5322	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
	5323	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
	5324	}
	5325	break;
	5326	}
	5327	//////////////////
	5328	case CMD_INS_MISS:
	5329	case CMD_INS_UNC:
	5330	case CMD_DATA_MISS:
[616]	5331	case CMD_DATA_UNC_READ:
	5332	case CMD_DATA_UNC_WRITE:
[331]	5333	case CMD_DATA_LL:
	5334	{
	5335	// all read VCI commands contain one single flit
[789]	5336	if (p_vci.cmdack.read()) {
[423]	5337	r_vci_cmd_fsm = CMD_IDLE;
	5338	}
[331]	5339	break;
	5340	}
	5341
	5342	} // end switch r_vci_cmd_fsm
	5343
	5344	//////////////////////////////////////////////////////////////////////////
	5345	// The VCI_RSP FSM controls the following ressources:
	5346	// - r_vci_rsp_fsm:
	5347	// - r_vci_rsp_fifo_icache (push)
	5348	// - r_vci_rsp_fifo_dcache (push)
	5349	// - r_vci_rsp_data_error (set)
	5350	// - r_vci_rsp_ins_error (set)
	5351	// - r_vci_rsp_cpt
	5352	// - r_dcache_vci_sc_req (reset when SC response recieved)
	5353	//
	5354	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
	5355	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
	5356	// to identify the transactions.
	5357	//
	5358	// VCI vormat:
	5359	// This component checks the response packet length and accepts only
	5360	// single word packets for write response packets.
	5361	//
	5362	// Error handling:
	5363	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
	5364	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
	5365	// flip_flop and the error is signaled by the DCACHE FSM.
	5366	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
	5367	// flip_flop and the error is signaled by the ICACHE FSM.
	5368	// In case of Cleanup Error, the simulation stops with an error message...
	5369	//////////////////////////////////////////////////////////////////////////
	5370
[789]	5371	switch (r_vci_rsp_fsm.read())
[331]	5372	{
	5373	//////////////
	5374	case RSP_IDLE:
	5375	{
[789]	5376	if (p_vci.rspval.read())
[331]	5377	{
	5378	r_vci_rsp_cpt = 0;
	5379
[789]	5380	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
[331]	5381	{
	5382	r_vci_rsp_fsm = RSP_DATA_UNC;
	5383	}
[789]	5384	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
[331]	5385	{
	5386	r_vci_rsp_fsm = RSP_DATA_MISS;
	5387	}
[789]	5388	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
[331]	5389	{
	5390	r_vci_rsp_fsm = RSP_INS_UNC;
	5391	}
[789]	5392	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
[331]	5393	{
	5394	r_vci_rsp_fsm = RSP_INS_MISS;
	5395	}
[789]	5396	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
[331]	5397	{
	5398	r_vci_rsp_fsm = RSP_DATA_WRITE;
	5399	}
[789]	5400	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
[331]	5401	{
	5402	r_vci_rsp_fsm = RSP_DATA_UNC;
	5403	}
[789]	5404	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
[331]	5405	{
	5406	r_vci_rsp_fsm = RSP_DATA_LL;
	5407	}
[789]	5408	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
[331]	5409	{
	5410	r_vci_rsp_fsm = RSP_DATA_UNC;
	5411	}
	5412	else
	5413	{
	5414	assert(false and "Unexpected VCI response");
	5415	}
	5416	}
	5417	break;
	5418	}
	5419	//////////////////
	5420	case RSP_INS_MISS:
	5421	{
[789]	5422	if (p_vci.rspval.read())
[331]	5423	{
[789]	5424	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5425	{
	5426	r_vci_rsp_ins_error = true;
[789]	5427	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
[331]	5428	}
	5429	else // no error reported
	5430	{
[789]	5431	if (r_vci_rsp_fifo_icache.wok())
[331]	5432	{
[789]	5433	if (r_vci_rsp_cpt.read() >= m_icache_words)
[473]	5434	{
	5435	std::cout << "ERROR in VCI_CC_VCACHE " << name()
	5436	<< " VCI response packet too long "
	5437	<< " for instruction miss" << std::endl;
	5438	exit(0);
	5439	}
[789]	5440	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
	5441	vci_rsp_fifo_icache_put = true,
	5442	vci_rsp_fifo_icache_data = p_vci.rdata.read();
	5443	if (p_vci.reop.read())
[331]	5444	{
[789]	5445	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
[473]	5446	{
	5447	std::cout << "ERROR in VCI_CC_VCACHE " << name()
[816]	5448	<< " VCI response packet too short"
[473]	5449	<< " for instruction miss" << std::endl;
	5450	exit(0);
	5451	}
[789]	5452	r_vci_rsp_fsm = RSP_IDLE;
[331]	5453	}
	5454	}
	5455	}
	5456	}
	5457	break;
	5458	}
	5459	/////////////////
	5460	case RSP_INS_UNC:
	5461	{
[789]	5462	if (p_vci.rspval.read())
[331]	5463	{
[789]	5464	assert(p_vci.reop.read() and
[331]	5465	"illegal VCI response packet for uncachable instruction");
	5466
[789]	5467	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5468	{
	5469	r_vci_rsp_ins_error = true;
	5470	r_vci_rsp_fsm = RSP_IDLE;
	5471	}
	5472	else // no error reported
	5473	{
[789]	5474	if (r_vci_rsp_fifo_icache.wok())
[331]	5475	{
[789]	5476	vci_rsp_fifo_icache_put = true;
	5477	vci_rsp_fifo_icache_data = p_vci.rdata.read();
[331]	5478	r_vci_rsp_fsm = RSP_IDLE;
	5479	}
	5480	}
	5481	}
	5482	break;
	5483	}
	5484	///////////////////
	5485	case RSP_DATA_MISS:
	5486	{
[789]	5487	if (p_vci.rspval.read())
[331]	5488	{
[789]	5489	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5490	{
	5491	r_vci_rsp_data_error = true;
[789]	5492	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
[331]	5493	}
	5494	else // no error reported
	5495	{
[789]	5496	if (r_vci_rsp_fifo_dcache.wok())
[331]	5497	{
[789]	5498	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
[331]	5499	"The VCI response packet for data miss is too long");
	5500
[789]	5501	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
	5502	vci_rsp_fifo_dcache_put = true,
	5503	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
	5504	if (p_vci.reop.read())
[331]	5505	{
[789]	5506	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
[331]	5507	"The VCI response packet for data miss is too short");
	5508
[789]	5509	r_vci_rsp_fsm = RSP_IDLE;
[331]	5510	}
	5511	}
	5512	}
	5513	}
	5514	break;
	5515	}
	5516	//////////////////
	5517	case RSP_DATA_UNC:
	5518	{
[789]	5519	if (p_vci.rspval.read())
[331]	5520	{
[789]	5521	assert(p_vci.reop.read() and
[331]	5522	"illegal VCI response packet for uncachable read data");
	5523
[789]	5524	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5525	{
	5526	r_vci_rsp_data_error = true;
	5527	r_vci_rsp_fsm = RSP_IDLE;
	5528	}
[789]	5529	else // no error reported
[331]	5530	{
[789]	5531	if (r_vci_rsp_fifo_dcache.wok())
[331]	5532	{
[789]	5533	vci_rsp_fifo_dcache_put = true;
	5534	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
[331]	5535	r_vci_rsp_fsm = RSP_IDLE;
	5536	}
	5537	}
	5538	}
	5539	break;
	5540	}
[434]	5541	/////////////////
[331]	5542	case RSP_DATA_LL:
	5543	{
[789]	5544	if (p_vci.rspval.read())
[331]	5545	{
[789]	5546	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5547	{
	5548	r_vci_rsp_data_error = true;
	5549	r_vci_rsp_fsm = RSP_IDLE;
[434]	5550	break;
[331]	5551	}
	5552	if (r_vci_rsp_cpt.read() == 0) //first flit
	5553	{
[789]	5554	if (r_vci_rsp_fifo_dcache.wok())
[331]	5555	{
[346]	5556	assert(!p_vci.reop.read() &&
[331]	5557	"illegal VCI response packet for LL");
	5558	vci_rsp_fifo_dcache_put = true;
[346]	5559	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
[331]	5560	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
	5561	}
	5562	break;
	5563	}
	5564	else // last flit
	5565	{
[789]	5566	if (r_vci_rsp_fifo_dcache.wok())
[331]	5567	{
[346]	5568	assert(p_vci.reop.read() &&
[331]	5569	"illegal VCI response packet for LL");
	5570	vci_rsp_fifo_dcache_put = true;
[346]	5571	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
[331]	5572	r_vci_rsp_fsm = RSP_IDLE;
	5573	}
	5574	break;
	5575	}
	5576	}
	5577	break;
	5578	}
	5579	////////////////////
	5580	case RSP_DATA_WRITE:
	5581	{
[346]	5582	if (p_vci.rspval.read())
[331]	5583	{
[789]	5584	assert(p_vci.reop.read() and
[331]	5585	"a VCI response packet must contain one flit for a write transaction");
	5586
	5587	r_vci_rsp_fsm = RSP_IDLE;
[789]	5588	uint32_t wbuf_index = p_vci.rtrdid.read();
[616]	5589	r_wbuf.completed(wbuf_index);
[789]	5590	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
[331]	5591	}
	5592	break;
	5593	}
	5594	} // end switch r_vci_rsp_fsm
	5595
	5596	/////////////////////////////////////////////////////////////////////////////////////
	5597	// The CC_SEND FSM is in charge of sending cleanups and the multicast
	5598	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
	5599	// and ICACHE FSM) that are served with a round-robin priority.
	5600	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
	5601	// soon as the request has been sent.
	5602	/////////////////////////////////////////////////////////////////////////////////////
[789]	5603	switch (r_cc_send_fsm.read())
[331]	5604	{
	5605	///////////////////////////
	5606	case CC_SEND_IDLE:
	5607	{
	5608	///////////////////////////////////////////////////////
	5609	// handling round robin between icache and dcache : //
	5610	// we first check for the last client and listen for //
	5611	// a request of the other, then update the client //
[386]	5612	// r_cc_send_last_client : 0 dcache / 1 icache
[331]	5613	///////////////////////////////////////////////////////
[333]	5614	bool update_last_client = r_cc_send_last_client.read();
[789]	5615	if (r_cc_send_last_client.read() == 0) // last client was dcache
[331]	5616	{
[333]	5617	if (r_icache_cc_send_req.read()) // request from icache
[331]	5618	update_last_client = 1; // update last client to icache
	5619	}
	5620	else // last client was icache
	5621	{
[333]	5622	if (r_dcache_cc_send_req.read()) // request from dcache
[331]	5623	update_last_client = 0; // update last client to dcache
	5624	}
	5625	r_cc_send_last_client = update_last_client;
	5626
	5627	// if there is an actual request
	5628	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
	5629	{
[386]	5630	// the new client is dcache and has a cleanup request
[816]	5631	if ((update_last_client == 0) and
[386]	5632	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
[331]	5633	r_cc_send_fsm = CC_SEND_CLEANUP_1;
[386]	5634	// the new client is dcache and has a multi acknowledgement request
[816]	5635	else if ((update_last_client == 0) and
[386]	5636	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
[331]	5637	r_cc_send_fsm = CC_SEND_MULTI_ACK;
[386]	5638	// the new client is icache and has a cleanup request
[816]	5639	else if ((update_last_client == 1) and
[386]	5640	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
[331]	5641	r_cc_send_fsm = CC_SEND_CLEANUP_1;
[386]	5642	// the new client is icache and has a multi acknowledgement request
[789]	5643	else if ((update_last_client == 1) and
[386]	5644	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
[331]	5645	r_cc_send_fsm = CC_SEND_MULTI_ACK;
	5646	}
	5647	break;
	5648	}
	5649	///////////////////////////
	5650	case CC_SEND_CLEANUP_1:
	5651	{
	5652	// wait for the first flit to be consumed
[468]	5653	if (p_dspin_p2m.read.read())
[331]	5654	r_cc_send_fsm = CC_SEND_CLEANUP_2;
	5655
	5656	break;
	5657	}
	5658	///////////////////////////
	5659	case CC_SEND_CLEANUP_2:
	5660	{
	5661	// wait for the second flit to be consumed
[468]	5662	if (p_dspin_p2m.read.read())
[331]	5663	{
[333]	5664	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	5665	r_dcache_cc_send_req = false; // reset dcache request
	5666	else // icache active request
	5667	r_icache_cc_send_req = false; // reset icache request
	5668
	5669	// go back to idle state
	5670	r_cc_send_fsm = CC_SEND_IDLE;
	5671	}
	5672	break;
	5673	}
	5674	///////////////////////////
	5675	case CC_SEND_MULTI_ACK:
	5676	{
	5677	// wait for the flit to be consumed
[789]	5678	if (p_dspin_p2m.read.read())
[331]	5679	{
[789]	5680	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	5681	r_dcache_cc_send_req = false; // reset dcache request
	5682	else // icache active request
	5683	r_icache_cc_send_req = false; // reset icache request
	5684	// go back to idle state
	5685	r_cc_send_fsm = CC_SEND_IDLE;
	5686	}
	5687	break;
	5688	}
	5689	} // end switch CC_SEND FSM
	5690
	5691	///////////////////////////////////////////////////////////////////////////////
[468]	5692	// CC_RECEIVE FSM
[331]	5693	// This FSM receive all coherence packets on a DSPIN40 port.
[468]	5694	// There is 5 packet types:
[331]	5695	// - CC_DATA_INVAL : DCACHE invalidate request
	5696	// - CC_DATA_UPDT : DCACHE update request (multi-words)
	5697	// - CC_INST_INVAL : ICACHE invalidate request
	5698	// - CC_INST_UPDT : ICACHE update request (multi-words)
	5699	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
	5700	//////////////////////////////////////////////////////////////////////////////
[789]	5701	switch (r_cc_receive_fsm.read())
[331]	5702	{
	5703	/////////////////////
	5704	case CC_RECEIVE_IDLE:
	5705	{
	5706	// a coherence request has arrived
[468]	5707	if (p_dspin_m2p.write.read())
[331]	5708	{
	5709	// initialize dspin received data
[468]	5710	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5711	// initialize coherence packet type
[386]	5712	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
[468]	5713	DspinDhccpParam::M2P_TYPE);
[331]	5714	// test for a broadcast
[468]	5715	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
[331]	5716	{
	5717	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
	5718	}
[468]	5719	// test for a multi updt
[816]	5720	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
[331]	5721	{
[468]	5722	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
[331]	5723	}
[468]	5724	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
[331]	5725	{
[468]	5726	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
[331]	5727	}
	5728	// test for a multi inval
[468]	5729	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
	5730	{
	5731	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
	5732	}
[331]	5733	else
	5734	{
[468]	5735	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
[331]	5736	}
	5737	}
	5738	break;
	5739	}
	5740	///////////////////////////////
	5741	case CC_RECEIVE_BRDCAST_HEADER:
	5742	{
	5743	// no actual data in the HEADER, just skip to second flit
	5744	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
	5745	break;
	5746	}
	5747	//////////////////////////////
	5748	case CC_RECEIVE_BRDCAST_NLINE:
	5749	{
	5750	// initialize dspin received data
[468]	5751	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5752	// wait for both dcache and icache to take the request
	5753	// TODO maybe we need to wait for both only to leave the state, but
	5754	// not to actually post a request to an available cache => need a
	5755	// flip_flop to check that ?
[816]	5756	if (not (r_cc_receive_icache_req.read()) and
[484]	5757	not (r_cc_receive_dcache_req.read()) and
[468]	5758	(p_dspin_m2p.write.read()))
[331]	5759	{
	5760	// request dcache to handle the BROADCAST
[468]	5761	r_cc_receive_dcache_req = true;
[789]	5762	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
[386]	5763	DspinDhccpParam::BROADCAST_NLINE);
[468]	5764	r_cc_receive_dcache_type = CC_TYPE_INVAL;
[331]	5765	// request icache to handle the BROADCAST
[468]	5766	r_cc_receive_icache_req = true;
[789]	5767	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
[386]	5768	DspinDhccpParam::BROADCAST_NLINE);
[468]	5769	r_cc_receive_icache_type = CC_TYPE_INVAL;
[331]	5770	// get back to idle state
	5771	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	5772	break;
	5773	}
	5774	// keep waiting for the caches to accept the request
	5775	break;
	5776	}
	5777	/////////////////////////////
[468]	5778	case CC_RECEIVE_DATA_INVAL_HEADER:
[331]	5779	{
[346]	5780	// sample updt tab index in the HEADER, then skip to second flit
[468]	5781	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
[331]	5782	break;
	5783	}
[468]	5784	/////////////////////////////
	5785	case CC_RECEIVE_INS_INVAL_HEADER:
	5786	{
	5787	// sample updt tab index in the HEADER, then skip to second flit
	5788	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
	5789	break;
	5790	}
[331]	5791	////////////////////////////
[468]	5792	case CC_RECEIVE_DATA_INVAL_NLINE:
[331]	5793	{
	5794	// sample nline in the second flit
[468]	5795	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5796	// for data INVAL, wait for dcache to take the request
[816]	5797	if (p_dspin_m2p.write.read() and
[789]	5798	not r_cc_receive_dcache_req.read())
[331]	5799	{
	5800	// request dcache to handle the INVAL
[468]	5801	r_cc_receive_dcache_req = true;
	5802	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
[331]	5803	r_cc_receive_dcache_type = CC_TYPE_INVAL;
	5804	// get back to idle state
	5805	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	5806	break;
	5807	}
[468]	5808	break;
	5809	}
	5810	//////////////////////////////
	5811	case CC_RECEIVE_INS_INVAL_NLINE:
	5812	{
	5813	// sample nline in the second flit
	5814	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5815	// for ins INVAL, wait for icache to take the request
[816]	5816	if (p_dspin_m2p.write.read() and
[789]	5817	not r_cc_receive_icache_req.read())
[331]	5818	{
	5819	// request icache to handle the INVAL
[468]	5820	r_cc_receive_icache_req = true;
	5821	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
[331]	5822	r_cc_receive_icache_type = CC_TYPE_INVAL;
	5823	// get back to idle state
	5824	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	5825	break;
	5826	}
[468]	5827	break;
[331]	5828	}
	5829	////////////////////////////
[468]	5830	case CC_RECEIVE_DATA_UPDT_HEADER:
[331]	5831	{
	5832	// sample updt tab index in the HEADER, than skip to second flit
[468]	5833	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5834	// for data INVAL, wait for dcache to take the request and fifo to
	5835	// be empty
[468]	5836	if (not r_cc_receive_dcache_req.read())
[331]	5837	{
[789]	5838	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
[468]	5839	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
[331]	5840	break;
	5841	}
[468]	5842	break;
	5843	}
	5844	////////////////////////////
	5845	case CC_RECEIVE_INS_UPDT_HEADER:
	5846	{
	5847	// sample updt tab index in the HEADER, than skip to second flit
	5848	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5849	// for ins INVAL, wait for icache to take the request and fifo to be
	5850	// empty
[468]	5851	if (not r_cc_receive_icache_req.read())
[331]	5852	{
[789]	5853	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
[468]	5854	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
[331]	5855	break;
	5856	}
	5857	// keep waiting for the correct cache to accept the request
	5858	break;
	5859	}
	5860	///////////////////////////
[468]	5861	case CC_RECEIVE_DATA_UPDT_NLINE:
[331]	5862	{
	5863	// sample nline and word index in the second flit
[468]	5864	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5865	// for data INVAL, wait for dcache to take the request and fifo to
	5866	// be empty
[789]	5867	if (r_cc_receive_updt_fifo_be.empty() and
	5868	p_dspin_m2p.write.read())
[331]	5869	{
[789]	5870	r_cc_receive_dcache_req = true;
	5871	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
	5872	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
	5873	r_cc_receive_dcache_type = CC_TYPE_UPDT;
[331]	5874	// get back to idle state
[468]	5875	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
[331]	5876	break;
	5877	}
[468]	5878	break;
	5879	}
	5880	////////////////////////////
	5881	case CC_RECEIVE_INS_UPDT_NLINE:
	5882	{
	5883	// sample nline and word index in the second flit
	5884	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5885	// for ins INVAL, wait for icache to take the request and fifo to be
	5886	// empty
[789]	5887	if (r_cc_receive_updt_fifo_be.empty() and
	5888	p_dspin_m2p.write.read())
[331]	5889	{
[789]	5890	r_cc_receive_icache_req = true;
	5891	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
	5892	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
	5893	r_cc_receive_icache_type = CC_TYPE_UPDT;
[331]	5894	// get back to idle state
[468]	5895	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
[331]	5896	break;
	5897	}
	5898	break;
	5899	}
	5900	//////////////////////////
[468]	5901	case CC_RECEIVE_DATA_UPDT_DATA:
[331]	5902	{
	5903	// wait for the fifo
[468]	5904	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
[331]	5905	{
[468]	5906	uint64_t receive_data = p_dspin_m2p.data.read();
	5907	bool receive_eop = p_dspin_m2p.eop.read();
[403]	5908	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
[331]	5909	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
[403]	5910	cc_receive_updt_fifo_eop = receive_eop;
[331]	5911	cc_receive_updt_fifo_put = true;
[789]	5912	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
[331]	5913	}
	5914	break;
	5915	}
[468]	5916	//////////////////////////
	5917	case CC_RECEIVE_INS_UPDT_DATA:
	5918	{
	5919	// wait for the fifo
	5920	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
	5921	{
	5922	uint64_t receive_data = p_dspin_m2p.data.read();
	5923	bool receive_eop = p_dspin_m2p.eop.read();
	5924	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
	5925	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
	5926	cc_receive_updt_fifo_eop = receive_eop;
	5927	cc_receive_updt_fifo_put = true;
[789]	5928	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
[468]	5929	}
	5930	break;
	5931	}
	5932
[331]	5933	} // end switch CC_RECEIVE FSM
	5934
[468]	5935	///////////////// DSPIN CLACK interface ///////////////
[816]	5936
[468]	5937	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
	5938	DspinDhccpParam::CLACK_TYPE);
	5939
[789]	5940	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
[468]	5941	DspinDhccpParam::CLACK_WAY);
	5942
[789]	5943	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
[468]	5944	DspinDhccpParam::CLACK_SET);
	5945
[789]	5946	bool dspin_clack_get = false;
[468]	5947	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
	5948	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
	5949
	5950	if (r_dspin_clack_req.read())
	5951	{
	5952	// CLACK DATA: Send request to DCACHE FSM
[789]	5953	if (dcache_clack_request and not r_dcache_clack_req.read())
	5954	{
[468]	5955	r_dcache_clack_req = true;
[789]	5956	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
	5957	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
[468]	5958	dspin_clack_get = true;
	5959	}
	5960
	5961	// CLACK INST: Send request to ICACHE FSM
[789]	5962	else if (icache_clack_request and not r_icache_clack_req.read())
	5963	{
[468]	5964	r_icache_clack_req = true;
	5965	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
	5966	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
	5967	dspin_clack_get = true;
	5968	}
	5969	}
	5970	else
	5971	{
	5972	dspin_clack_get = true;
	5973	}
	5974
	5975	if (dspin_clack_get)
	5976	{
	5977	r_dspin_clack_req = p_dspin_clack.write.read();
	5978	r_dspin_clack_flit = p_dspin_clack.data.read();
	5979	}
	5980
[331]	5981	///////////////// Response FIFOs update //////////////////////
	5982	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
	5983	vci_rsp_fifo_icache_put,
	5984	vci_rsp_fifo_icache_data);
	5985
	5986	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
	5987	vci_rsp_fifo_dcache_put,
	5988	vci_rsp_fifo_dcache_data);
[346]	5989
[331]	5990	///////////////// updt FIFO update //////////////////////
	5991	//TODO check this
	5992	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
	5993	cc_receive_updt_fifo_put,
	5994	cc_receive_updt_fifo_be);
	5995	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
	5996	cc_receive_updt_fifo_put,
	5997	cc_receive_updt_fifo_data);
	5998	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
	5999	cc_receive_updt_fifo_put,
	6000	cc_receive_updt_fifo_eop);
	6001
	6002	} // end transition()
	6003
	6004	///////////////////////
	6005	tmpl(void)::genMoore()
	6006	///////////////////////
	6007	{
	6008
	6009	// VCI initiator command on the direct network
	6010	// it depends on the CMD FSM state
	6011
[336]	6012	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
[789]	6013	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
[336]	6014
[346]	6015	p_vci.pktid = 0;
	6016	p_vci.srcid = m_srcid;
[816]	6017	p_vci.cons = is_sc_or_cas;
	6018	p_vci.contig = not is_sc_or_cas;
[346]	6019	p_vci.wrap = false;
	6020	p_vci.clen = 0;
	6021	p_vci.cfixed = false;
[331]	6022
[789]	6023	if (m_monitor_ok) {
	6024	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
[816]	6025	if (((p_vci.address.read()) >= m_monitor_base) and
[789]	6026	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
[423]	6027	std::cout << "CC_VCACHE Monitor " << name() << std::hex
[816]	6028	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
[423]	6029	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
	6030	<< " : address = " << p_vci.address.read()
[816]	6031	<< " / be = " << p_vci.be.read();
[789]	6032	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
[423]	6033	std::cout << " / data = " << p_vci.wdata.read();
	6034	}
	6035	std::cout << std::dec << std::endl;
	6036	}
	6037	}
	6038	}
	6039
[789]	6040	switch (r_vci_cmd_fsm.read()) {
[331]	6041
	6042	case CMD_IDLE:
[346]	6043	p_vci.cmdval = false;
	6044	p_vci.address = 0;
	6045	p_vci.wdata = 0;
	6046	p_vci.be = 0;
	6047	p_vci.trdid = 0;
	6048	p_vci.pktid = 0;
	6049	p_vci.plen = 0;
	6050	p_vci.cmd = vci_param::CMD_NOP;
	6051	p_vci.eop = false;
[331]	6052	break;
	6053
	6054	case CMD_INS_MISS:
[346]	6055	p_vci.cmdval = true;
	6056	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
	6057	p_vci.wdata = 0;
	6058	p_vci.be = 0xF;
	6059	p_vci.trdid = 0;
	6060	p_vci.pktid = TYPE_READ_INS_MISS;
[836]	6061	p_vci.plen = m_icache_words << 2;
[346]	6062	p_vci.cmd = vci_param::CMD_READ;
	6063	p_vci.eop = true;
[331]	6064	break;
	6065
	6066	case CMD_INS_UNC:
[346]	6067	p_vci.cmdval = true;
	6068	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
	6069	p_vci.wdata = 0;
	6070	p_vci.be = 0xF;
	6071	p_vci.trdid = 0;
	6072	p_vci.pktid = TYPE_READ_INS_UNC;
	6073	p_vci.plen = 4;
	6074	p_vci.cmd = vci_param::CMD_READ;
	6075	p_vci.eop = true;
[331]	6076	break;
	6077
	6078	case CMD_DATA_MISS:
[346]	6079	p_vci.cmdval = true;
	6080	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
	6081	p_vci.wdata = 0;
	6082	p_vci.be = 0xF;
	6083	p_vci.trdid = 0;
	6084	p_vci.pktid = TYPE_READ_DATA_MISS;
	6085	p_vci.plen = m_dcache_words << 2;
	6086	p_vci.cmd = vci_param::CMD_READ;
	6087	p_vci.eop = true;
[331]	6088	break;
	6089
[616]	6090	case CMD_DATA_UNC_READ:
[346]	6091	p_vci.cmdval = true;
	6092	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
	6093	p_vci.wdata = 0;
	6094	p_vci.be = r_dcache_vci_unc_be.read();
	6095	p_vci.trdid = 0;
[616]	6096	p_vci.pktid = TYPE_DATA_UNC;
[346]	6097	p_vci.plen = 4;
	6098	p_vci.cmd = vci_param::CMD_READ;
	6099	p_vci.eop = true;
[331]	6100	break;
	6101
[616]	6102	case CMD_DATA_UNC_WRITE:
	6103	p_vci.cmdval = true;
	6104	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
	6105	p_vci.wdata = r_dcache_vci_wdata.read();
	6106	p_vci.be = r_dcache_vci_unc_be.read();
	6107	p_vci.trdid = 0;
	6108	p_vci.pktid = TYPE_DATA_UNC;
	6109	p_vci.plen = 4;
	6110	p_vci.cmd = vci_param::CMD_WRITE;
	6111	p_vci.eop = true;
	6112	break;
	6113
[331]	6114	case CMD_DATA_WRITE:
[346]	6115	p_vci.cmdval = true;
	6116	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
	6117	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
	6118	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
	6119	p_vci.trdid = r_wbuf.getIndex();
	6120	p_vci.pktid = TYPE_WRITE;
	6121	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
	6122	p_vci.cmd = vci_param::CMD_WRITE;
	6123	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
[331]	6124	break;
	6125
	6126	case CMD_DATA_LL:
[346]	6127	p_vci.cmdval = true;
	6128	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
	6129	p_vci.wdata = 0;
	6130	p_vci.be = 0xF;
	6131	p_vci.trdid = 0;
	6132	p_vci.pktid = TYPE_LL;
	6133	p_vci.plen = 8;
	6134	p_vci.cmd = vci_param::CMD_LOCKED_READ;
	6135	p_vci.eop = true;
[331]	6136	break;
	6137
	6138	case CMD_DATA_SC:
[346]	6139	p_vci.cmdval = true;
	6140	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
[789]	6141	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
	6142	else p_vci.wdata = r_dcache_vci_sc_data.read();
[346]	6143	p_vci.be = 0xF;
	6144	p_vci.trdid = 0;
	6145	p_vci.pktid = TYPE_SC;
	6146	p_vci.plen = 8;
	6147	p_vci.cmd = vci_param::CMD_NOP;
	6148	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
[331]	6149	break;
	6150
	6151	case CMD_DATA_CAS:
[346]	6152	p_vci.cmdval = true;
	6153	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
[789]	6154	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
	6155	else p_vci.wdata = r_dcache_vci_cas_new.read();
[346]	6156	p_vci.be = 0xF;
	6157	p_vci.trdid = 0;
	6158	p_vci.pktid = TYPE_CAS;
	6159	p_vci.plen = 8;
	6160	p_vci.cmd = vci_param::CMD_NOP;
	6161	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
[331]	6162	break;
	6163	} // end switch r_vci_cmd_fsm
	6164
	6165	// VCI initiator response on the direct network
[346]	6166	// it depends on the VCI_RSP FSM
[331]	6167
[789]	6168	switch (r_vci_rsp_fsm.read())
[331]	6169	{
[346]	6170	case RSP_DATA_WRITE : p_vci.rspack = true; break;
	6171	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
	6172	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
	6173	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
	6174	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
	6175	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
	6176	case RSP_IDLE : p_vci.rspack = false; break;
[331]	6177	} // end switch r_vci_rsp_fsm
	6178
[346]	6179
[816]	6180	// Send coherence packets on DSPIN P2M
	6181	// it depends on the CC_SEND FSM
	6182
[331]	6183	uint64_t dspin_send_data = 0;
[789]	6184	switch (r_cc_send_fsm.read())
[331]	6185	{
[346]	6186	//////////////////
[331]	6187	case CC_SEND_IDLE:
	6188	{
[468]	6189	p_dspin_p2m.write = false;
[331]	6190	break;
	6191	}
[346]	6192	///////////////////////
[331]	6193	case CC_SEND_CLEANUP_1:
	6194	{
	6195	// initialize dspin send data
[346]	6196	DspinDhccpParam::dspin_set(dspin_send_data,
	6197	m_cc_global_id,
	6198	DspinDhccpParam::CLEANUP_SRCID);
	6199	DspinDhccpParam::dspin_set(dspin_send_data,
	6200	0,
[468]	6201	DspinDhccpParam::P2M_BC);
[346]	6202
[789]	6203	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	6204	{
[816]	6205	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
	6206	>> (m_nline_width - m_x_width - m_y_width)
[346]	6207	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[816]	6208
[331]	6209	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6210	dest,
	6211	DspinDhccpParam::CLEANUP_DEST);
[331]	6212
	6213	DspinDhccpParam::dspin_set(dspin_send_data,
[394]	6214	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
[346]	6215	DspinDhccpParam::CLEANUP_NLINE_MSB);
[331]	6216
	6217	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6218	r_dcache_cc_send_way.read(),
	6219	DspinDhccpParam::CLEANUP_WAY_INDEX);
[331]	6220
	6221	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6222	DspinDhccpParam::TYPE_CLEANUP_DATA,
[468]	6223	DspinDhccpParam::P2M_TYPE);
[331]	6224	}
[346]	6225	else // icache active request
[331]	6226	{
[816]	6227	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
	6228	>> (m_nline_width - m_x_width - m_y_width)
[346]	6229	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[331]	6230
	6231	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6232	dest,
	6233	DspinDhccpParam::CLEANUP_DEST);
[331]	6234
	6235	DspinDhccpParam::dspin_set(dspin_send_data,
[789]	6236	(r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
[346]	6237	DspinDhccpParam::CLEANUP_NLINE_MSB);
[331]	6238
	6239	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6240	r_icache_cc_send_way.read(),
	6241	DspinDhccpParam::CLEANUP_WAY_INDEX);
[331]	6242
	6243	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6244	DspinDhccpParam::TYPE_CLEANUP_INST,
[468]	6245	DspinDhccpParam::P2M_TYPE);
[331]	6246	}
	6247	// send flit
[468]	6248	p_dspin_p2m.data = dspin_send_data;
	6249	p_dspin_p2m.write = true;
	6250	p_dspin_p2m.eop = false;
[331]	6251	break;
	6252	}
[346]	6253	///////////////////////
[331]	6254	case CC_SEND_CLEANUP_2:
	6255	{
	6256	// initialize dspin send data
[346]	6257
[789]	6258	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	6259	{
	6260	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6261	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
	6262	DspinDhccpParam::CLEANUP_NLINE_LSB);
[331]	6263	}
[346]	6264	else // icache active request
[331]	6265	{
	6266	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6267	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
	6268	DspinDhccpParam::CLEANUP_NLINE_LSB);
[331]	6269	}
	6270	// send flit
[468]	6271	p_dspin_p2m.data = dspin_send_data;
	6272	p_dspin_p2m.write = true;
	6273	p_dspin_p2m.eop = true;
[331]	6274	break;
	6275	}
[346]	6276	///////////////////////
[331]	6277	case CC_SEND_MULTI_ACK:
	6278	{
	6279	// initialize dspin send data
	6280	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6281	0,
[468]	6282	DspinDhccpParam::P2M_BC);
[346]	6283	DspinDhccpParam::dspin_set(dspin_send_data,
	6284	DspinDhccpParam::TYPE_MULTI_ACK,
[468]	6285	DspinDhccpParam::P2M_TYPE);
[346]	6286
[789]	6287	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	6288	{
[816]	6289	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
	6290	>> (m_nline_width - m_x_width - m_y_width)
[346]	6291	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[816]	6292
[331]	6293	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6294	dest,
	6295	DspinDhccpParam::MULTI_ACK_DEST);
[331]	6296
	6297	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6298	r_dcache_cc_send_updt_tab_idx.read(),
	6299	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
[331]	6300	}
[346]	6301	else // icache active request
[331]	6302	{
[816]	6303	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
	6304	>> (m_nline_width - m_x_width - m_y_width)
[346]	6305	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[331]	6306
[816]	6307
[331]	6308	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6309	dest,
	6310	DspinDhccpParam::MULTI_ACK_DEST);
[331]	6311
	6312	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6313	r_icache_cc_send_updt_tab_idx.read(),
	6314	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
[331]	6315	}
	6316	// send flit
[468]	6317	p_dspin_p2m.data = dspin_send_data;
	6318	p_dspin_p2m.write = true;
	6319	p_dspin_p2m.eop = true;
[355]	6320
[331]	6321	break;
	6322	}
	6323	} // end switch CC_SEND FSM
	6324
[346]	6325	// Receive coherence packets
[816]	6326	// It depends on the CC_RECEIVE FSM
[789]	6327	switch (r_cc_receive_fsm.read())
[331]	6328	{
	6329	/////////////////////
	6330	case CC_RECEIVE_IDLE:
	6331	{
[468]	6332	p_dspin_m2p.read = false;
[331]	6333	break;
	6334	}
	6335	///////////////////////////////
	6336	case CC_RECEIVE_BRDCAST_HEADER:
	6337	{
[468]	6338	p_dspin_m2p.read = true;
[331]	6339	break;
	6340	}
	6341	//////////////////////////////
	6342	case CC_RECEIVE_BRDCAST_NLINE:
	6343	{
	6344	// TODO maybe we need to wait for both only to leave the state, but
	6345	// not to actually post a request to an available cache => need a
	6346	// flip_flop to check that ?
	6347	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
[468]	6348	p_dspin_m2p.read = true;
[331]	6349	else
[468]	6350	p_dspin_m2p.read = false;
[331]	6351	break;
	6352	}
	6353	/////////////////////////////
[468]	6354	case CC_RECEIVE_DATA_INVAL_HEADER:
	6355	case CC_RECEIVE_INS_INVAL_HEADER:
[331]	6356	{
[468]	6357	p_dspin_m2p.read = true;
[331]	6358	break;
	6359	}
	6360	////////////////////////////
[468]	6361	case CC_RECEIVE_DATA_INVAL_NLINE:
[331]	6362	{
[468]	6363	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
[331]	6364	break;
	6365	}
[468]	6366	case CC_RECEIVE_INS_INVAL_NLINE:
	6367	{
	6368	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
	6369	break;
	6370	}
	6371	///////////////////////////
	6372	case CC_RECEIVE_DATA_UPDT_HEADER:
	6373	{
	6374	if (not r_cc_receive_dcache_req.read())
	6375	p_dspin_m2p.read = true;
	6376	else
	6377	p_dspin_m2p.read = false;
	6378	break;
	6379	}
[331]	6380	////////////////////////////
[468]	6381	case CC_RECEIVE_INS_UPDT_HEADER:
[331]	6382	{
[816]	6383	if (not r_cc_receive_icache_req.read())
[468]	6384	p_dspin_m2p.read = true;
[331]	6385	else
[468]	6386	p_dspin_m2p.read = false;
[331]	6387	break;
	6388	}
	6389	///////////////////////////
[468]	6390	case CC_RECEIVE_DATA_UPDT_NLINE:
	6391	case CC_RECEIVE_INS_UPDT_NLINE:
[331]	6392	{
[789]	6393	if (r_cc_receive_updt_fifo_be.empty())
[468]	6394	p_dspin_m2p.read = true;
[331]	6395	else
[468]	6396	p_dspin_m2p.read = false;
[331]	6397	break;
	6398	}
[468]	6399	///////////////////////////
	6400	case CC_RECEIVE_DATA_UPDT_DATA:
	6401	case CC_RECEIVE_INS_UPDT_DATA:
[331]	6402	{
	6403	if (r_cc_receive_updt_fifo_be.wok())
[468]	6404	p_dspin_m2p.read = true;
[331]	6405	else
[468]	6406	p_dspin_m2p.read = false;
[331]	6407	break;
	6408	}
	6409	} // end switch CC_RECEIVE FSM
	6410
[468]	6411
	6412	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
	6413	DspinDhccpParam::CLACK_TYPE);
	6414
[789]	6415	bool dspin_clack_get = false;
[468]	6416	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
	6417	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
	6418
	6419	if (r_dspin_clack_req.read())
	6420	{
	6421	// CLACK DATA: wait if pending request to DCACHE FSM
	6422	if (dcache_clack_request and not r_dcache_clack_req.read())
	6423	{
	6424	dspin_clack_get = true;
	6425	}
	6426
	6427	// CLACK INST: wait if pending request to ICACHE FSM
	6428	else if (icache_clack_request and not r_icache_clack_req.read())
	6429	{
	6430	dspin_clack_get = true;
	6431	}
	6432	}
	6433	else
	6434	{
	6435	dspin_clack_get = true;
	6436	}
	6437
[816]	6438	p_dspin_clack.read = dspin_clack_get;
[331]	6439	} // end genMoore
	6440
[423]	6441	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
	6442	// This version of monitor print both Read and Write request
	6443	{
[789]	6444	m_monitor_ok = true;
	6445	m_monitor_base = base;
	6446	m_monitor_length = length;
[423]	6447	}
	6448
	6449	tmpl(void)::stop_monitor()
	6450	{
[789]	6451	m_monitor_ok = false;
[423]	6452	}
	6453
[331]	6454	}}
	6455
	6456	// Local Variables:
	6457	// tab-width: 4
	6458	// c-basic-offset: 4
	6459	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	6460	// indent-tabs-mode: nil
	6461	// End:
	6462
	6463	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0