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source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 991

Last change on this file since 991 was 970, checked in by cfuguet, 9 years ago

bugfix in vci_cc_vcache_wrapper: remove a wrong assert condition

Remove a wrong assert condition on the treatment of external requests (CP2) for dcache and icache physical address invalidation.

File size: 243.2 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include <signal.h>
32
33	#include "arithmetics.h"
34	#include "../include/vci_cc_vcache_wrapper.h"
35
36	#define DEBUG_DCACHE 1
37	#define DEBUG_ICACHE 1
38	#define DEBUG_CMD 0
39
40	namespace soclib {
41	namespace caba {
42
43	namespace {
44	const char * icache_fsm_state_str[] = {
45	"ICACHE_IDLE",
46
47	"ICACHE_XTN_TLB_FLUSH",
48	"ICACHE_XTN_CACHE_FLUSH",
49	"ICACHE_XTN_CACHE_FLUSH_GO",
50	"ICACHE_XTN_TLB_INVAL",
51	"ICACHE_XTN_CACHE_INVAL_VA",
52	"ICACHE_XTN_CACHE_INVAL_PA",
53	"ICACHE_XTN_CACHE_INVAL_GO",
54
55	"ICACHE_TLB_WAIT",
56
57	"ICACHE_MISS_SELECT",
58	"ICACHE_MISS_CLEAN",
59	"ICACHE_MISS_WAIT",
60	"ICACHE_MISS_DATA_UPDT",
61	"ICACHE_MISS_DIR_UPDT",
62
63	"ICACHE_UNC_WAIT",
64
65	"ICACHE_CC_CHECK",
66	"ICACHE_CC_UPDT",
67	"ICACHE_CC_INVAL",
68	};
69
70	const char * dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IC_PADDR_EXT",
90	"DCACHE_XTN_IT_INVAL",
91	"DCACHE_XTN_DC_FLUSH",
92	"DCACHE_XTN_DC_FLUSH_GO",
93	"DCACHE_XTN_DC_INVAL_VA",
94	"DCACHE_XTN_DC_INVAL_PA",
95	"DCACHE_XTN_DC_INVAL_END",
96	"DCACHE_XTN_DC_INVAL_GO",
97	"DCACHE_XTN_DT_INVAL",
98
99	"DCACHE_DIRTY_GET_PTE",
100	"DCACHE_DIRTY_WAIT",
101
102	"DCACHE_MISS_SELECT",
103	"DCACHE_MISS_CLEAN",
104	"DCACHE_MISS_WAIT",
105	"DCACHE_MISS_DATA_UPDT",
106	"DCACHE_MISS_DIR_UPDT",
107
108	"DCACHE_UNC_WAIT",
109	"DCACHE_LL_WAIT",
110	"DCACHE_SC_WAIT",
111
112	"DCACHE_CC_CHECK",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_INVAL",
115
116	"DCACHE_INVAL_TLB_SCAN",
117	};
118
119	const char * cmd_fsm_state_str[] = {
120	"CMD_IDLE",
121	"CMD_INS_MISS",
122	"CMD_INS_UNC",
123	"CMD_DATA_MISS",
124	"CMD_DATA_UNC_READ",
125	"CMD_DATA_UNC_WRITE",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char * vci_pktid_type_str[] = {
133	"TYPE_DATA_UNC",
134	"TYPE_READ_DATA_MISS",
135	"TYPE_READ_INS_UNC",
136	"TYPE_READ_INS_MISS",
137	"TYPE_WRITE",
138	"TYPE_CAS",
139	"TYPE_LL",
140	"TYPE_SC",
141	};
142
143	const char * vci_cmd_type_str[] = {
144	"NOP or STORE_COND",
145	"READ",
146	"WRITE",
147	"LOCKED_READ"
148	};
149
150	const char * rsp_fsm_state_str[] = {
151	"RSP_IDLE",
152	"RSP_INS_MISS",
153	"RSP_INS_UNC",
154	"RSP_DATA_MISS",
155	"RSP_DATA_UNC",
156	"RSP_DATA_LL",
157	"RSP_DATA_WRITE",
158	};
159
160	const char * cc_receive_fsm_state_str[] = {
161	"CC_RECEIVE_IDLE",
162	"CC_RECEIVE_BRDCAST_HEADER",
163	"CC_RECEIVE_BRDCAST_NLINE",
164	"CC_RECEIVE_INS_INVAL_HEADER",
165	"CC_RECEIVE_INS_INVAL_NLINE",
166	"CC_RECEIVE_INS_UPDT_HEADER",
167	"CC_RECEIVE_INS_UPDT_NLINE",
168	"CC_RECEIVE_INS_UPDT_DATA",
169	"CC_RECEIVE_DATA_INVAL_HEADER",
170	"CC_RECEIVE_DATA_INVAL_NLINE",
171	"CC_RECEIVE_DATA_UPDT_HEADER",
172	"CC_RECEIVE_DATA_UPDT_NLINE",
173	"CC_RECEIVE_DATA_UPDT_DATA",
174	};
175
176	const char * cc_send_fsm_state_str[] = {
177	"CC_SEND_IDLE",
178	"CC_SEND_CLEANUP_1",
179	"CC_SEND_CLEANUP_2",
180	"CC_SEND_MULTI_ACK",
181	};
182	}
183
184	#define tmpl(...) \
185	template<typename vci_param, \
186	size_t dspin_in_width, \
187	size_t dspin_out_width, \
188	typename iss_t> __VA_ARGS__ \
189	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
190
191	using namespace soclib::common;
192
193	/////////////////////////////////
194	tmpl(/**/)::VciCcVCacheWrapper(
195	sc_module_name name,
196	const int proc_id,
197	const MappingTable &mtd,
198	const IntTab &srcid,
199	const size_t cc_global_id,
200	const size_t itlb_ways,
201	const size_t itlb_sets,
202	const size_t dtlb_ways,
203	const size_t dtlb_sets,
204	const size_t icache_ways,
205	const size_t icache_sets,
206	const size_t icache_words,
207	const size_t dcache_ways,
208	const size_t dcache_sets,
209	const size_t dcache_words,
210	const size_t wbuf_nlines,
211	const size_t wbuf_nwords,
212	const size_t x_width,
213	const size_t y_width,
214	const uint32_t max_frozen_cycles,
215	const uint32_t debug_start_cycle,
216	const bool debug_ok)
217	: soclib::caba::BaseModule(name),
218
219	p_clk("p_clk"),
220	p_resetn("p_resetn"),
221	p_vci("p_vci"),
222	p_dspin_m2p("p_dspin_m2p"),
223	p_dspin_p2m("p_dspin_p2m"),
224	p_dspin_clack("p_dspin_clack"),
225
226	m_cacheability_table( mtd.getCacheabilityTable()),
227	m_srcid(mtd.indexForId(srcid)),
228	m_cc_global_id(cc_global_id),
229	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
230	m_itlb_ways(itlb_ways),
231	m_itlb_sets(itlb_sets),
232	m_dtlb_ways(dtlb_ways),
233	m_dtlb_sets(dtlb_sets),
234	m_icache_ways(icache_ways),
235	m_icache_sets(icache_sets),
236	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
237	m_icache_words(icache_words),
238	m_dcache_ways(dcache_ways),
239	m_dcache_sets(dcache_sets),
240	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
241	m_dcache_words(dcache_words),
242	m_x_width(x_width),
243	m_y_width(y_width),
244	m_proc_id(proc_id),
245	m_max_frozen_cycles(max_frozen_cycles),
246	m_paddr_nbits(vci_param::N),
247	m_debug_start_cycle(debug_start_cycle),
248	m_debug_ok(debug_ok),
249	m_dcache_paddr_ext_reset(0),
250	m_icache_paddr_ext_reset(0),
251
252	r_mmu_ptpr("r_mmu_ptpr"),
253	r_mmu_mode("r_mmu_mode"),
254	r_mmu_word_lo("r_mmu_word_lo"),
255	r_mmu_word_hi("r_mmu_word_hi"),
256	r_mmu_ibvar("r_mmu_ibvar"),
257	r_mmu_dbvar("r_mmu_dbvar"),
258	r_mmu_ietr("r_mmu_ietr"),
259	r_mmu_detr("r_mmu_detr"),
260
261	r_icache_fsm("r_icache_fsm"),
262	r_icache_fsm_save("r_icache_fsm_save"),
263	r_icache_vci_paddr("r_icache_vci_paddr"),
264	r_icache_vaddr_save("r_icache_vaddr_save"),
265
266	r_icache_miss_way("r_icache_miss_way"),
267	r_icache_miss_set("r_icache_miss_set"),
268	r_icache_miss_word("r_icache_miss_word"),
269	r_icache_miss_inval("r_icache_miss_inval"),
270	r_icache_miss_clack("r_icache_miss_clack"),
271
272	r_icache_cc_way("r_icache_cc_way"),
273	r_icache_cc_set("r_icache_cc_set"),
274	r_icache_cc_word("r_icache_cc_word"),
275	r_icache_cc_need_write("r_icache_cc_need_write"),
276
277	r_icache_flush_count("r_icache_flush_count"),
278
279	r_icache_miss_req("r_icache_miss_req"),
280	r_icache_unc_req("r_icache_unc_req"),
281
282	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
283	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
284
285	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
286	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
287
288	r_icache_cc_send_req("r_icache_cc_send_req"),
289	r_icache_cc_send_type("r_icache_cc_send_type"),
290	r_icache_cc_send_nline("r_icache_cc_send_nline"),
291	r_icache_cc_send_way("r_icache_cc_send_way"),
292	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
293
294	r_dcache_fsm("r_dcache_fsm"),
295	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
296	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
297
298	r_dcache_wbuf_req("r_dcache_wbuf_req"),
299	r_dcache_updt_req("r_dcache_updt_req"),
300	r_dcache_save_vaddr("r_dcache_save_vaddr"),
301	r_dcache_save_wdata("r_dcache_save_wdata"),
302	r_dcache_save_be("r_dcache_save_be"),
303	r_dcache_save_paddr("r_dcache_save_paddr"),
304	r_dcache_save_cache_way("r_dcache_save_cache_way"),
305	r_dcache_save_cache_set("r_dcache_save_cache_set"),
306	r_dcache_save_cache_word("r_dcache_save_cache_word"),
307
308	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
309	r_dcache_dirty_way("r_dcache_dirty_way"),
310	r_dcache_dirty_set("r_dcache_dirty_set"),
311
312	r_dcache_vci_paddr("r_dcache_vci_paddr"),
313	r_dcache_vci_wdata("r_dcache_vci_wdata"),
314	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
315	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
316	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
317	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
318	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
319	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
320	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
321	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
322	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
323	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
324
325	r_dcache_xtn_way("r_dcache_xtn_way"),
326	r_dcache_xtn_set("r_dcache_xtn_set"),
327
328	r_dcache_miss_type("r_dcache_miss_type"),
329	r_dcache_miss_word("r_dcache_miss_word"),
330	r_dcache_miss_way("r_dcache_miss_way"),
331	r_dcache_miss_set("r_dcache_miss_set"),
332	r_dcache_miss_inval("r_dcache_miss_inval"),
333
334	r_dcache_cc_way("r_dcache_cc_way"),
335	r_dcache_cc_set("r_dcache_cc_set"),
336	r_dcache_cc_word("r_dcache_cc_word"),
337	r_dcache_cc_need_write("r_dcache_cc_need_write"),
338
339	r_dcache_flush_count("r_dcache_flush_count"),
340
341	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
342
343	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
344	r_dcache_tlb_ins("r_dcache_tlb_ins"),
345	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
346	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
347	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
348	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
349	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
350	r_dcache_tlb_way("r_dcache_tlb_way"),
351	r_dcache_tlb_set("r_dcache_tlb_set"),
352
353	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
354	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
355
356	r_dcache_xtn_req("r_dcache_xtn_req"),
357	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
358
359	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
360	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
361
362	r_dcache_cc_send_req("r_dcache_cc_send_req"),
363	r_dcache_cc_send_type("r_dcache_cc_send_type"),
364	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
365	r_dcache_cc_send_way("r_dcache_cc_send_way"),
366	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
367
368	r_vci_cmd_fsm("r_vci_cmd_fsm"),
369	r_vci_cmd_min("r_vci_cmd_min"),
370	r_vci_cmd_max("r_vci_cmd_max"),
371	r_vci_cmd_cpt("r_vci_cmd_cpt"),
372	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
373
374	r_vci_rsp_fsm("r_vci_rsp_fsm"),
375	r_vci_rsp_cpt("r_vci_rsp_cpt"),
376	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
377	r_vci_rsp_data_error("r_vci_rsp_data_error"),
378	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
379	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
380
381	r_cc_send_fsm("r_cc_send_fsm"),
382	r_cc_send_last_client("r_cc_send_last_client"),
383
384	r_cc_receive_fsm("r_cc_receive_fsm"),
385	r_cc_receive_data_ins("r_cc_receive_data_ins"),
386	r_cc_receive_word_idx("r_cc_receive_word_idx"),
387	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
388	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
389	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
390
391	r_cc_receive_icache_req("r_cc_receive_icache_req"),
392	r_cc_receive_icache_type("r_cc_receive_icache_type"),
393	r_cc_receive_icache_way("r_cc_receive_icache_way"),
394	r_cc_receive_icache_set("r_cc_receive_icache_set"),
395	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
396	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
397
398	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
399	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
400	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
401	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
402	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
403	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
404
405	r_iss(this->name(), proc_id),
406	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
407	r_icache("icache", icache_ways, icache_sets, icache_words),
408	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
409	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
410	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
411	{
412	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
413
414	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
415	"Need more PLEN bits.");
416
417	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
418	"Need more TRDID bits.");
419
420	assert((icache_words == dcache_words) and
421	"icache_words and dcache_words parameters must be equal");
422
423	assert((itlb_sets == dtlb_sets) and
424	"itlb_sets and dtlb_sets parameters must be etqual");
425
426	assert((itlb_ways == dtlb_ways) and
427	"itlb_ways and dtlb_ways parameters must be etqual");
428
429	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
430	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
431	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
432	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
433	(uint32_log2(m_icache_words << 2));
434
435	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
436
437	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
438	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
439
440	SC_METHOD(transition);
441	dont_initialize();
442	sensitive << p_clk.pos();
443
444	SC_METHOD(genMoore);
445	dont_initialize();
446	sensitive << p_clk.neg();
447
448	typename iss_t::CacheInfo cache_info;
449	cache_info.has_mmu = true;
450	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
451	cache_info.icache_assoc = icache_ways;
452	cache_info.icache_n_lines = icache_sets;
453	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
454	cache_info.dcache_assoc = dcache_ways;
455	cache_info.dcache_n_lines = dcache_sets;
456	r_iss.setCacheInfo(cache_info);
457	}
458
459	/////////////////////////////////////
460	tmpl(/**/)::~VciCcVCacheWrapper()
461	/////////////////////////////////////
462	{
463	delete [] r_dcache_in_tlb;
464	delete [] r_dcache_contains_ptd;
465	}
466
467	////////////////////////
468	tmpl(void)::print_cpi()
469	////////////////////////
470	{
471	std::cout << name() << " CPI = "
472	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
473	}
474
475	////////////////////////////////////
476	tmpl(void)::print_trace(size_t mode)
477	////////////////////////////////////
478	{
479	// b0 : write buffer trace
480	// b1 : dump processor registers
481	// b2 : dcache trace
482	// b3 : icache trace
483	// b4 : dtlb trace
484	// b5 : itlb trace
485	// b6 : SR (ISS register 32)
486
487	std::cout << std::dec << "PROC " << name() << std::endl;
488
489	std::cout << " " << m_ireq << std::endl;
490	std::cout << " " << m_irsp << std::endl;
491	std::cout << " " << m_dreq << std::endl;
492	std::cout << " " << m_drsp << std::endl;
493
494	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
495	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
496	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
497	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
498	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
499	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
500	<< " \| MMU = " << r_mmu_mode.read();
501
502	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
503	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
504	std::cout << std::endl;
505
506	if (mode & 0x01)
507	{
508	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
509	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
510	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
511	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
512
513	r_wbuf.printTrace((mode >> 1) & 1);
514	}
515	if (mode & 0x02)
516	{
517	r_iss.dump();
518	}
519	if (mode & 0x04)
520	{
521	std::cout << " Data Cache" << std::endl;
522	r_dcache.printTrace();
523	}
524	if (mode & 0x08)
525	{
526	std::cout << " Instruction Cache" << std::endl;
527	r_icache.printTrace();
528	}
529	if (mode & 0x10)
530	{
531	std::cout << " Data TLB" << std::endl;
532	r_dtlb.printTrace();
533	}
534	if (mode & 0x20)
535	{
536	std::cout << " Instruction TLB" << std::endl;
537	r_itlb.printTrace();
538	}
539	if (mode & 0x40)
540	{
541	uint32_t status = r_iss.debugGetRegisterValue(32);
542	std::cout << name();
543	if (status != m_previous_status ) std::cout << " NEW ";
544	std::cout << " status = " << std::hex << status << " " << std::endl;
545	m_previous_status = status;
546	}
547	}
548
549	//////////////////////////////////////////
550	tmpl(void)::cache_monitor(paddr_t addr)
551	//////////////////////////////////////////
552	{
553	bool cache_hit;
554	size_t cache_way = 0;
555	size_t cache_set = 0;
556	size_t cache_word = 0;
557	uint32_t cache_rdata = 0;
558
559	cache_hit = r_dcache.read_neutral(addr,
560	&cache_rdata,
561	&cache_way,
562	&cache_set,
563	&cache_word);
564
565	if (cache_hit != m_debug_previous_d_hit)
566	{
567	std::cout << "Monitor PROC " << name()
568	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
569	<< " / HIT = " << cache_hit
570	<< " / PADDR = " << std::hex << addr
571	<< " / DATA = " << cache_rdata
572	<< " / WAY = " << cache_way << std::endl;
573	m_debug_previous_d_hit = cache_hit;
574	}
575
576	cache_hit = r_icache.read_neutral(addr,
577	&cache_rdata,
578	&cache_way,
579	&cache_set,
580	&cache_word);
581
582	if (cache_hit != m_debug_previous_i_hit)
583	{
584	std::cout << "Monitor PROC " << name()
585	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
586	<< " / HIT = " << cache_hit
587	<< " / PADDR = " << std::hex << addr
588	<< " / DATA = " << cache_rdata
589	<< " / WAY = " << cache_way << std::endl;
590	m_debug_previous_i_hit = cache_hit;
591	}
592	}
593
594	/*
595	////////////////////////
596	tmpl(void)::print_stats()
597	////////////////////////
598	{
599	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
600	std::cout << name() << std::endl
601	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
602	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
603	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
604	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
605	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
606	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
607	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
608	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
609	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
610	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
611	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
612	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
613	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
614	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
615	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
616	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
617	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
618	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
619	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
620	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
621	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
622	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
623	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
624	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
625	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
626	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
627	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
628	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
629	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
630	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
631	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
632	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
633	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
634	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
635	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
636	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
637	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
638	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
639	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
640	}
641
642	////////////////////////
643	tmpl(void)::clear_stats()
644	////////////////////////
645	{
646	m_cpt_dcache_data_read = 0;
647	m_cpt_dcache_data_write = 0;
648	m_cpt_dcache_dir_read = 0;
649	m_cpt_dcache_dir_write = 0;
650	m_cpt_icache_data_read = 0;
651	m_cpt_icache_data_write = 0;
652	m_cpt_icache_dir_read = 0;
653	m_cpt_icache_dir_write = 0;
654
655	m_cpt_frz_cycles = 0;
656	m_cpt_dcache_frz_cycles = 0;
657	m_cpt_total_cycles = 0;
658
659	m_cpt_read = 0;
660	m_cpt_write = 0;
661	m_cpt_data_miss = 0;
662	m_cpt_ins_miss = 0;
663	m_cpt_unc_read = 0;
664	m_cpt_write_cached = 0;
665	m_cpt_ins_read = 0;
666
667	m_cost_write_frz = 0;
668	m_cost_data_miss_frz = 0;
669	m_cost_unc_read_frz = 0;
670	m_cost_ins_miss_frz = 0;
671
672	m_cpt_imiss_transaction = 0;
673	m_cpt_dmiss_transaction = 0;
674	m_cpt_unc_transaction = 0;
675	m_cpt_write_transaction = 0;
676	m_cpt_icache_unc_transaction = 0;
677
678	m_cost_imiss_transaction = 0;
679	m_cost_dmiss_transaction = 0;
680	m_cost_unc_transaction = 0;
681	m_cost_write_transaction = 0;
682	m_cost_icache_unc_transaction = 0;
683	m_length_write_transaction = 0;
684
685	m_cpt_ins_tlb_read = 0;
686	m_cpt_ins_tlb_miss = 0;
687	m_cpt_ins_tlb_update_acc = 0;
688
689	m_cpt_data_tlb_read = 0;
690	m_cpt_data_tlb_miss = 0;
691	m_cpt_data_tlb_update_acc = 0;
692	m_cpt_data_tlb_update_dirty = 0;
693	m_cpt_ins_tlb_hit_dcache = 0;
694	m_cpt_data_tlb_hit_dcache = 0;
695	m_cpt_ins_tlb_occup_cache = 0;
696	m_cpt_data_tlb_occup_cache = 0;
697
698	m_cost_ins_tlb_miss_frz = 0;
699	m_cost_data_tlb_miss_frz = 0;
700	m_cost_ins_tlb_update_acc_frz = 0;
701	m_cost_data_tlb_update_acc_frz = 0;
702	m_cost_data_tlb_update_dirty_frz = 0;
703	m_cost_ins_tlb_occup_cache_frz = 0;
704	m_cost_data_tlb_occup_cache_frz = 0;
705
706	m_cpt_itlbmiss_transaction = 0;
707	m_cpt_itlb_ll_transaction = 0;
708	m_cpt_itlb_sc_transaction = 0;
709	m_cpt_dtlbmiss_transaction = 0;
710	m_cpt_dtlb_ll_transaction = 0;
711	m_cpt_dtlb_sc_transaction = 0;
712	m_cpt_dtlb_ll_dirty_transaction = 0;
713	m_cpt_dtlb_sc_dirty_transaction = 0;
714
715	m_cost_itlbmiss_transaction = 0;
716	m_cost_itlb_ll_transaction = 0;
717	m_cost_itlb_sc_transaction = 0;
718	m_cost_dtlbmiss_transaction = 0;
719	m_cost_dtlb_ll_transaction = 0;
720	m_cost_dtlb_sc_transaction = 0;
721	m_cost_dtlb_ll_dirty_transaction = 0;
722	m_cost_dtlb_sc_dirty_transaction = 0;
723
724	m_cpt_cc_update_data = 0;
725	m_cpt_cc_inval_ins = 0;
726	m_cpt_cc_inval_data = 0;
727	m_cpt_cc_broadcast = 0;
728
729	m_cost_updt_data_frz = 0;
730	m_cost_inval_ins_frz = 0;
731	m_cost_inval_data_frz = 0;
732	m_cost_broadcast_frz = 0;
733
734	m_cpt_cc_cleanup_data = 0;
735	m_cpt_cc_cleanup_ins = 0;
736	}
737
738	*/
739
740	/////////////////////////
741	tmpl(void)::transition()
742	/////////////////////////
743	{
744	if (not p_resetn.read())
745	{
746	r_iss.reset();
747	r_wbuf.reset();
748	r_icache.reset();
749	r_dcache.reset();
750	r_itlb.reset();
751	r_dtlb.reset();
752
753	r_dcache_fsm = DCACHE_IDLE;
754	r_icache_fsm = ICACHE_IDLE;
755	r_vci_cmd_fsm = CMD_IDLE;
756	r_vci_rsp_fsm = RSP_IDLE;
757	r_cc_receive_fsm = CC_RECEIVE_IDLE;
758	r_cc_send_fsm = CC_SEND_IDLE;
759
760	// reset data physical address extension
761	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
762
763	// reset inst physical address extension
764	r_icache_paddr_ext = m_icache_paddr_ext_reset;
765
766	// reset dcache directory extension
767	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
768	{
769	r_dcache_in_tlb[i] = false;
770	r_dcache_contains_ptd[i] = false;
771	}
772
773	// Response FIFOs and cleanup buffer
774	r_vci_rsp_fifo_icache.init();
775	r_vci_rsp_fifo_dcache.init();
776
777	// ICACHE & DCACHE activated
778	// ITLB & DTLB desactivated
779	r_mmu_mode = 0x3;
780
781	// No request from ICACHE FSM to CMD FSM
782	r_icache_miss_req = false;
783	r_icache_unc_req = false;
784
785	// No request from ICACHE_FSM to DCACHE FSM
786	r_icache_tlb_miss_req = false;
787
788	// No request from ICACHE_FSM to CC_SEND FSM
789	r_icache_cc_send_req = false;
790	r_icache_cleanup_victim_req = false;
791
792	r_icache_clack_req = false;
793
794	// No pending write in pipeline
795	r_dcache_wbuf_req = false;
796	r_dcache_updt_req = false;
797
798	// No request from DCACHE_FSM to CMD_FSM
799	r_dcache_vci_miss_req = false;
800	r_dcache_vci_unc_req = false;
801	r_dcache_vci_cas_req = false;
802	r_dcache_vci_ll_req = false;
803	r_dcache_vci_sc_req = false;
804
805	// No processor XTN request pending
806	r_dcache_xtn_req = false;
807
808	// No request from DCACHE FSM to CC_SEND FSM
809	r_dcache_cc_send_req = false;
810	r_dcache_cleanup_victim_req = false;
811
812	r_dcache_clack_req = false;
813
814	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
815	r_cc_receive_icache_req = false;
816	r_cc_receive_dcache_req = false;
817
818	// last cc_send client was dcache
819	r_cc_send_last_client = false;
820
821	// No pending cleanup after a replacement
822	r_icache_miss_clack = false;
823	r_dcache_miss_clack = false;
824
825	// No signalisation of a coherence request matching a pending miss
826	r_icache_miss_inval = false;
827	r_dcache_miss_inval = false;
828
829	r_dspin_clack_req = false;
830
831	// No signalisation of errors
832	r_vci_rsp_ins_error = false;
833	r_vci_rsp_data_error = false;
834
835	// Debug variables
836	m_debug_previous_i_hit = false;
837	m_debug_previous_d_hit = false;
838	m_debug_icache_fsm = false;
839	m_debug_dcache_fsm = false;
840	m_debug_cmd_fsm = false;
841
842	// activity counters
843	m_cpt_dcache_data_read = 0;
844	m_cpt_dcache_data_write = 0;
845	m_cpt_dcache_dir_read = 0;
846	m_cpt_dcache_dir_write = 0;
847	m_cpt_icache_data_read = 0;
848	m_cpt_icache_data_write = 0;
849	m_cpt_icache_dir_read = 0;
850	m_cpt_icache_dir_write = 0;
851
852	m_cpt_frz_cycles = 0;
853	m_cpt_total_cycles = 0;
854	m_cpt_stop_simulation = 0;
855
856	m_cpt_data_miss = 0;
857	m_cpt_ins_miss = 0;
858	m_cpt_unc_read = 0;
859	m_cpt_write_cached = 0;
860	m_cpt_ins_read = 0;
861
862	m_cost_write_frz = 0;
863	m_cost_data_miss_frz = 0;
864	m_cost_unc_read_frz = 0;
865	m_cost_ins_miss_frz = 0;
866
867	m_cpt_imiss_transaction = 0;
868	m_cpt_dmiss_transaction = 0;
869	m_cpt_unc_transaction = 0;
870	m_cpt_write_transaction = 0;
871	m_cpt_icache_unc_transaction = 0;
872
873	m_cost_imiss_transaction = 0;
874	m_cost_dmiss_transaction = 0;
875	m_cost_unc_transaction = 0;
876	m_cost_write_transaction = 0;
877	m_cost_icache_unc_transaction = 0;
878	m_length_write_transaction = 0;
879
880	m_cpt_ins_tlb_read = 0;
881	m_cpt_ins_tlb_miss = 0;
882	m_cpt_ins_tlb_update_acc = 0;
883
884	m_cpt_data_tlb_read = 0;
885	m_cpt_data_tlb_miss = 0;
886	m_cpt_data_tlb_update_acc = 0;
887	m_cpt_data_tlb_update_dirty = 0;
888	m_cpt_ins_tlb_hit_dcache = 0;
889	m_cpt_data_tlb_hit_dcache = 0;
890	m_cpt_ins_tlb_occup_cache = 0;
891	m_cpt_data_tlb_occup_cache = 0;
892
893	m_cost_ins_tlb_miss_frz = 0;
894	m_cost_data_tlb_miss_frz = 0;
895	m_cost_ins_tlb_update_acc_frz = 0;
896	m_cost_data_tlb_update_acc_frz = 0;
897	m_cost_data_tlb_update_dirty_frz = 0;
898	m_cost_ins_tlb_occup_cache_frz = 0;
899	m_cost_data_tlb_occup_cache_frz = 0;
900
901	m_cpt_ins_tlb_inval = 0;
902	m_cpt_data_tlb_inval = 0;
903	m_cost_ins_tlb_inval_frz = 0;
904	m_cost_data_tlb_inval_frz = 0;
905
906	m_cpt_cc_broadcast = 0;
907
908	m_cost_updt_data_frz = 0;
909	m_cost_inval_ins_frz = 0;
910	m_cost_inval_data_frz = 0;
911	m_cost_broadcast_frz = 0;
912
913	m_cpt_cc_cleanup_data = 0;
914	m_cpt_cc_cleanup_ins = 0;
915
916	m_cpt_itlbmiss_transaction = 0;
917	m_cpt_itlb_ll_transaction = 0;
918	m_cpt_itlb_sc_transaction = 0;
919	m_cpt_dtlbmiss_transaction = 0;
920	m_cpt_dtlb_ll_transaction = 0;
921	m_cpt_dtlb_sc_transaction = 0;
922	m_cpt_dtlb_ll_dirty_transaction = 0;
923	m_cpt_dtlb_sc_dirty_transaction = 0;
924
925	m_cost_itlbmiss_transaction = 0;
926	m_cost_itlb_ll_transaction = 0;
927	m_cost_itlb_sc_transaction = 0;
928	m_cost_dtlbmiss_transaction = 0;
929	m_cost_dtlb_ll_transaction = 0;
930	m_cost_dtlb_sc_transaction = 0;
931	m_cost_dtlb_ll_dirty_transaction = 0;
932	m_cost_dtlb_sc_dirty_transaction = 0;
933	/*
934	m_cpt_dcache_frz_cycles = 0;
935	m_cpt_read = 0;
936	m_cpt_write = 0;
937	m_cpt_cc_update_data = 0;
938	m_cpt_cc_inval_ins = 0;
939	m_cpt_cc_inval_data = 0;
940	*/
941
942	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
943	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
944	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
945	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
946
947	// init the llsc reservation buffer
948	r_dcache_llsc_valid = false;
949	m_monitor_ok = false;
950
951	return;
952	}
953
954	// Response FIFOs default values
955	bool vci_rsp_fifo_icache_get = false;
956	bool vci_rsp_fifo_icache_put = false;
957	uint32_t vci_rsp_fifo_icache_data = 0;
958
959	bool vci_rsp_fifo_dcache_get = false;
960	bool vci_rsp_fifo_dcache_put = false;
961	uint32_t vci_rsp_fifo_dcache_data = 0;
962
963	// updt fifo
964	bool cc_receive_updt_fifo_get = false;
965	bool cc_receive_updt_fifo_put = false;
966	uint32_t cc_receive_updt_fifo_be = 0;
967	uint32_t cc_receive_updt_fifo_data = 0;
968	bool cc_receive_updt_fifo_eop = false;
969
970	#ifdef INSTRUMENTATION
971	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
972	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
973	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
974	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
975	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
976	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
977	#endif
978
979	m_cpt_total_cycles++;
980
981	m_debug_icache_fsm = m_debug_icache_fsm \|\|
982	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
983	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
984	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
985	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
986	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
987
988	/////////////////////////////////////////////////////////////////////
989	// Get data and instruction requests from processor
990	///////////////////////////////////////////////////////////////////////
991
992	r_iss.getRequests(m_ireq, m_dreq);
993
994	////////////////////////////////////////////////////////////////////////////////////
995	// ICACHE_FSM
996	//
997	// 1/ Coherence operations
998	// They are handled as interrupts generated by the CC_RECEIVE FSM.
999	// - There is a coherence request when r_tgt_icache_req is set.
1000	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
1001	// - There is a cleanup ack request when r_cleanup_icache_req is set.
1002	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
1003	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
1004	// - For both types of requests, actions associated to the pre-empted state
1005	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1006	// or CC_CLACK) to execute the requested coherence operation, and returns
1007	// to the pre-empted state.
1008	//
1009	// 2/ Processor requests
1010	// They are taken in IDLE state only. In case of cache miss, or uncacheable
1011	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
1012	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
1013	// flip-flops are reset when the transaction starts.
1014	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
1015	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
1016	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
1017	// The availability of the missing cache line is signaled by the response fifo,
1018	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
1019	// and ICACHE_MISS_DIR_UPDT states.
1020	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
1021	// to wait the response from the RSP FSM, through the response fifo.
1022	// The missing instruction is directly returned to processor in this state.
1023	//
1024	// 3/ TLB miss
1025	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
1026	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
1027	// register, and goes to the ICACHE_TLB_WAIT state.
1028	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
1029	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
1030	// to signal the completion.
1031	//
1032	// 4/ XTN requests
1033	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1034	// using the r_dcache_xtn_req flip-flop.
1035	// The request opcode and the address to be invalidated are transmitted
1036	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
1037	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1038	// is completed.
1039	//
1040	// 5/ Error Handling
1041	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1042	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1043	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1044	////////////////////////////////////////////////////////////////////////////////////////
1045
1046	// default value for m_irsp
1047	m_irsp.valid = false;
1048	m_irsp.error = false;
1049	m_irsp.instruction = 0;
1050
1051	switch (r_icache_fsm.read())
1052	{
1053	/////////////////
1054	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1055	// and coherence requests with a fixed priority:
1056	// 1/ Coherence requests => ICACHE_CC_CHECK
1057	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1058	// 3/ tlb miss => ICACHE_TLB_WAIT
1059	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1060	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1061	{
1062	// coherence clack interrupt
1063	if (r_icache_clack_req.read())
1064	{
1065	r_icache_fsm = ICACHE_CC_CHECK;
1066	r_icache_fsm_save = r_icache_fsm.read();
1067	break;
1068	}
1069
1070	// coherence interrupt
1071	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1072	{
1073	r_icache_fsm = ICACHE_CC_CHECK;
1074	r_icache_fsm_save = r_icache_fsm.read();
1075	break;
1076	}
1077
1078	// XTN requests sent by DCACHE FSM
1079	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
1080	// because they require access to icache or itlb, that are already accessed
1081	if (r_dcache_xtn_req.read())
1082	{
1083	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
1084	{
1085	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1086	}
1087	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
1088	{
1089	r_icache_flush_count = 0;
1090	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1091	}
1092	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
1093	{
1094	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1095	}
1096	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
1097	{
1098	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1099	}
1100	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
1101	{
1102	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
1103	((uint64_t)r_mmu_word_lo.read());
1104
1105	r_icache_vci_paddr = (paddr_t)pa;
1106	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1107	}
1108	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
1109	{
1110	r_icache_paddr_ext = r_dcache_save_wdata.read();
1111	r_dcache_xtn_req = false;
1112	}
1113	else
1114	{
1115	assert(false and
1116	"undefined XTN request received by ICACHE FSM");
1117	}
1118	break;
1119	} // end if xtn_req
1120
1121	// processor request
1122	if (m_ireq.valid )
1123	{
1124	bool cacheable;
1125	paddr_t paddr;
1126	bool tlb_hit = false;
1127	pte_info_t tlb_flags;
1128	size_t tlb_way;
1129	size_t tlb_set;
1130	paddr_t tlb_nline;
1131	uint32_t cache_inst = 0;
1132	size_t cache_way;
1133	size_t cache_set;
1134	size_t cache_word;
1135	int cache_state = CACHE_SLOT_STATE_EMPTY;
1136
1137	// We register processor request
1138	r_icache_vaddr_save = m_ireq.addr;
1139	paddr = (paddr_t) m_ireq.addr;
1140
1141	// sytematic itlb access (if activated)
1142	if (r_mmu_mode.read() & INS_TLB_MASK)
1143	{
1144
1145	#ifdef INSTRUMENTATION
1146	m_cpt_itlb_read++;
1147	#endif
1148	tlb_hit = r_itlb.translate(m_ireq.addr,
1149	&paddr,
1150	&tlb_flags,
1151	&tlb_nline, // unused
1152	&tlb_way, // unused
1153	&tlb_set); // unused
1154	}
1155	else if (vci_param::N > 32)
1156	{
1157	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
1158	}
1159
1160	// systematic icache access (if activated)
1161	if (r_mmu_mode.read() & INS_CACHE_MASK)
1162	{
1163
1164
1165	#ifdef INSTRUMENTATION
1166	m_cpt_icache_data_read++;
1167	m_cpt_icache_dir_read++;
1168	#endif
1169	r_icache.read(paddr,
1170	&cache_inst,
1171	&cache_way,
1172	&cache_set,
1173	&cache_word,
1174	&cache_state);
1175	}
1176
1177	// We compute cacheability and check access rights:
1178	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1179	// and the access rights are defined by the U and X bits in the PTE.
1180	// - If MMU not activated : cacheability is defined by the segment table,
1181	// and there is no access rights checking
1182
1183	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
1184	{
1185	// cacheability
1186	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1187	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
1188	}
1189	else // itlb activated
1190	{
1191	if (tlb_hit) // ITLB hit
1192	{
1193	// cacheability
1194	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1195	else cacheable = tlb_flags.c;
1196
1197	// access rights checking
1198	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
1199	{
1200
1201	#if DEBUG_ICACHE
1202	if ( m_debug_icache_fsm )
1203	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
1204	<< " : PADDR = " << std::hex << paddr << std::endl;
1205	#endif
1206	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1207	r_mmu_ibvar = m_ireq.addr;
1208	m_irsp.valid = true;
1209	m_irsp.error = true;
1210	m_irsp.instruction = 0;
1211	break;
1212	}
1213	else if (not tlb_flags.x)
1214	{
1215
1216	#if DEBUG_ICACHE
1217	if ( m_debug_icache_fsm )
1218	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
1219	<< " : PADDR = " << std::hex << paddr << std::endl;
1220	#endif
1221	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1222	r_mmu_ibvar = m_ireq.addr;
1223	m_irsp.valid = true;
1224	m_irsp.error = true;
1225	m_irsp.instruction = 0;
1226	break;
1227	}
1228	}
1229	else // ITLB miss
1230	{
1231
1232	#ifdef INSTRUMENTATION
1233	m_cpt_itlb_miss++;
1234	#endif
1235	r_icache_fsm = ICACHE_TLB_WAIT;
1236	r_icache_tlb_miss_req = true;
1237	break;
1238	}
1239	} // end if itlb activated
1240
1241	// physical address registration
1242	r_icache_vci_paddr = paddr;
1243
1244	// Finally, we send the response to processor, and compute next state
1245	if (cacheable)
1246	{
1247	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1248	{
1249
1250	#ifdef INSTRUMENTATION
1251	m_cpt_icache_miss++;
1252	#endif
1253	// we request a VCI transaction
1254	r_icache_fsm = ICACHE_MISS_SELECT;
1255	#if DEBUG_ICACHE
1256	if (m_debug_icache_fsm)
1257	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1258	<< " : PADDR = " << std::hex << paddr << std::endl;
1259	#endif
1260	r_icache_miss_req = true;
1261	}
1262	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1263	{
1264	// stalled until cleanup is acknowledged
1265	r_icache_fsm = ICACHE_IDLE;
1266	}
1267	else // cache hit
1268	{
1269
1270	#ifdef INSTRUMENTATION
1271	m_cpt_ins_read++;
1272	#endif
1273	// return instruction to processor
1274	m_irsp.valid = true;
1275	m_irsp.instruction = cache_inst;
1276	r_icache_fsm = ICACHE_IDLE;
1277	#if DEBUG_ICACHE
1278	if (m_debug_icache_fsm)
1279	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1280	<< " : PADDR = " << std::hex << paddr
1281	<< " / INST = " << cache_inst << std::endl;
1282	#endif
1283	}
1284	}
1285	else // non cacheable read
1286	{
1287	r_icache_unc_req = true;
1288	r_icache_fsm = ICACHE_UNC_WAIT;
1289
1290	#if DEBUG_ICACHE
1291	if (m_debug_icache_fsm)
1292	{
1293	std::cout << " <PROC " << name()
1294	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1295	<< " : PADDR = " << std::hex << paddr << std::endl;
1296	}
1297	#endif
1298	}
1299	} // end if m_ireq.valid
1300	break;
1301	}
1302	/////////////////////
1303	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1304	// the itlb is udated by the DCACHE FSM, as well as the
1305	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1306	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1307	// reset the r_icache_tlb_miss_req flip-flop
1308	// external coherence request are accepted in this state.
1309	{
1310	// coherence clack interrupt
1311	if (r_icache_clack_req.read())
1312	{
1313	r_icache_fsm = ICACHE_CC_CHECK;
1314	r_icache_fsm_save = r_icache_fsm.read();
1315	break;
1316	}
1317
1318	// coherence interrupt
1319	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1320	{
1321	r_icache_fsm = ICACHE_CC_CHECK;
1322	r_icache_fsm_save = r_icache_fsm.read();
1323	break;
1324	}
1325
1326	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
1327
1328	// DCACHE FSM signals response by reseting the request flip-flop
1329	if (not r_icache_tlb_miss_req.read())
1330	{
1331	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
1332	{
1333	r_icache_tlb_rsp_error = false;
1334	m_irsp.error = true;
1335	m_irsp.valid = true;
1336	r_icache_fsm = ICACHE_IDLE;
1337	}
1338	else // tlb updated : return to IDLE state
1339	{
1340	r_icache_fsm = ICACHE_IDLE;
1341	}
1342	}
1343	break;
1344	}
1345	//////////////////////////
1346	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1347	{
1348	r_itlb.flush();
1349	r_dcache_xtn_req = false;
1350	r_icache_fsm = ICACHE_IDLE;
1351	break;
1352	}
1353	////////////////////////////
1354	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1355	// r_icache_flush_count as a slot counter,
1356	// looping in this state until all slots are visited.
1357	// It can require two cycles per slot:
1358	// We test here the slot state, and make the actual inval
1359	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1360	// A cleanup request is generated for each valid line
1361	{
1362	// coherence clack interrupt
1363	if (r_icache_clack_req.read())
1364	{
1365	r_icache_fsm = ICACHE_CC_CHECK;
1366	r_icache_fsm_save = r_icache_fsm.read();
1367	break;
1368	}
1369
1370	// coherence request (from CC_RECEIVE FSM)
1371	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1372	{
1373	r_icache_fsm = ICACHE_CC_CHECK;
1374	r_icache_fsm_save = r_icache_fsm.read();
1375	break;
1376	}
1377
1378	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
1379	{
1380	int state;
1381	paddr_t tag;
1382	size_t way = r_icache_flush_count.read() / m_icache_sets;
1383	size_t set = r_icache_flush_count.read() % m_icache_sets;
1384
1385	#ifdef INSTRUMENTATION
1386	m_cpt_icache_dir_read++;
1387	#endif
1388	r_icache.read_dir(way,
1389	set,
1390	&tag,
1391	&state);
1392
1393	if (state == CACHE_SLOT_STATE_VALID) // inval required
1394	{
1395	// request cleanup
1396	r_icache_cc_send_req = true;
1397	r_icache_cc_send_nline = tag * m_icache_sets + set;
1398	r_icache_cc_send_way = way;
1399	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1400
1401	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1402	r_icache_miss_way = way;
1403	r_icache_miss_set = set;
1404	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1405	}
1406	else if (r_icache_flush_count.read() ==
1407	(m_icache_sets*m_icache_ways - 1)) // last slot
1408	{
1409	r_dcache_xtn_req = false;
1410	m_drsp.valid = true;
1411	r_icache_fsm = ICACHE_IDLE;
1412	}
1413
1414	// saturation counter, to have the same last slot condition
1415	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1416	if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1))
1417	{
1418	r_icache_flush_count = r_icache_flush_count.read() + 1;
1419	}
1420	}
1421	break;
1422	}
1423	///////////////////////////////
1424	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1425	{
1426	size_t way = r_icache_miss_way.read();
1427	size_t set = r_icache_miss_set.read();
1428
1429	#ifdef INSTRUMENTATION
1430	m_cpt_icache_dir_write++;
1431	#endif
1432
1433	r_icache.write_dir(way,
1434	set,
1435	CACHE_SLOT_STATE_ZOMBI);
1436
1437	if (r_icache_flush_count.read() ==
1438	(m_icache_sets*m_icache_ways - 1)) // last slot
1439	{
1440	r_dcache_xtn_req = false;
1441	m_drsp.valid = true;
1442	r_icache_fsm = ICACHE_IDLE;
1443	}
1444	else
1445	{
1446	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1447	}
1448	break;
1449	}
1450
1451	//////////////////////////
1452	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1453	// stored in the r_dcache_save_wdata register
1454	{
1455	r_itlb.inval(r_dcache_save_wdata.read());
1456	r_dcache_xtn_req = false;
1457	r_icache_fsm = ICACHE_IDLE;
1458	break;
1459	}
1460	///////////////////////////////
1461	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1462	// requires 3 cycles (in case of hit on itlb and icache).
1463	// In this state, access TLB to translate virtual address
1464	// stored in the r_dcache_save_wdata register.
1465	{
1466	paddr_t paddr;
1467	bool hit;
1468
1469	// read physical address in TLB when MMU activated
1470	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
1471	{
1472
1473	#ifdef INSTRUMENTATION
1474	m_cpt_itlb_read++;
1475	#endif
1476	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
1477	}
1478	else // itlb not activated
1479	{
1480	paddr = (paddr_t) r_dcache_save_wdata.read();
1481	hit = true;
1482	}
1483
1484	if (hit) // continue the selective inval process
1485	{
1486	r_icache_vci_paddr = paddr;
1487	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1488	}
1489	else // miss : send a request to DCACHE FSM
1490	{
1491
1492	#ifdef INSTRUMENTATION
1493	m_cpt_itlb_miss++;
1494	#endif
1495	r_icache_tlb_miss_req = true;
1496	r_icache_vaddr_save = r_dcache_save_wdata.read();
1497	r_icache_fsm = ICACHE_TLB_WAIT;
1498	}
1499	break;
1500	}
1501	///////////////////////////////
1502	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1503	// require 2 cycles. In this state, we read directory
1504	// with address stored in r_icache_vci_paddr register.
1505	{
1506	int state;
1507	size_t way;
1508	size_t set;
1509	size_t word;
1510
1511	#ifdef INSTRUMENTATION
1512	m_cpt_icache_dir_read++;
1513	#endif
1514	r_icache.read_dir(r_icache_vci_paddr.read(),
1515	&state,
1516	&way,
1517	&set,
1518	&word);
1519
1520	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
1521	{
1522	r_icache_miss_way = way;
1523	r_icache_miss_set = set;
1524	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1525	}
1526	else // miss : acknowlege the XTN request and return
1527	{
1528	r_dcache_xtn_req = false;
1529	r_icache_fsm = ICACHE_IDLE;
1530	}
1531	break;
1532	}
1533	///////////////////////////////
1534	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1535	{
1536	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
1537	{
1538
1539	#ifdef INSTRUMENTATION
1540	m_cpt_icache_dir_write++;
1541	#endif
1542	r_icache.write_dir(r_icache_miss_way.read(),
1543	r_icache_miss_set.read(),
1544	CACHE_SLOT_STATE_ZOMBI);
1545
1546	// request cleanup
1547	r_icache_cc_send_req = true;
1548	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1549	r_icache_cc_send_way = r_icache_miss_way.read();
1550	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1551
1552	// acknowledge the XTN request and return
1553	r_dcache_xtn_req = false;
1554	r_icache_fsm = ICACHE_IDLE;
1555	}
1556	break;
1557	}
1558	////////////////////////
1559	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1560	// Waiting in this state if no slot available.
1561	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
1562	// we send the cleanup request in this state.
1563	// If not, a r_icache_cleanup_victim_req flip-flop is
1564	// utilized for saving this cleanup request, and it will be sent later
1565	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1566	// The r_icache_miss_clack flip-flop is set
1567	// when a cleanup is required
1568	{
1569	if (m_ireq.valid) m_cost_ins_miss_frz++;
1570
1571	// coherence clack interrupt
1572	if (r_icache_clack_req.read())
1573	{
1574	r_icache_fsm = ICACHE_CC_CHECK;
1575	r_icache_fsm_save = r_icache_fsm.read();
1576	break;
1577	}
1578
1579	// coherence interrupt
1580	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1581	{
1582	r_icache_fsm = ICACHE_CC_CHECK;
1583	r_icache_fsm_save = r_icache_fsm.read();
1584	break;
1585	}
1586
1587
1588	bool found;
1589	bool cleanup;
1590	size_t way;
1591	size_t set;
1592	paddr_t victim;
1593
1594	#ifdef INSTRUMENTATION
1595	m_cpt_icache_dir_read++;
1596	#endif
1597	r_icache.read_select(r_icache_vci_paddr.read(),
1598	&victim,
1599	&way,
1600	&set,
1601	&found,
1602	&cleanup);
1603	if (not found)
1604	{
1605	break;
1606	}
1607	else
1608	{
1609	r_icache_miss_way = way;
1610	r_icache_miss_set = set;
1611
1612	if (cleanup)
1613	{
1614	if (not r_icache_cc_send_req.read())
1615	{
1616	r_icache_cc_send_req = true;
1617	r_icache_cc_send_nline = victim;
1618	r_icache_cc_send_way = way;
1619	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1620	}
1621	else
1622	{
1623	r_icache_cleanup_victim_req = true;
1624	r_icache_cleanup_victim_nline = victim;
1625	}
1626
1627	r_icache_miss_clack = true;
1628	r_icache_fsm = ICACHE_MISS_CLEAN;
1629	}
1630	else
1631	{
1632	r_icache_fsm = ICACHE_MISS_WAIT;
1633	}
1634
1635	#if DEBUG_ICACHE
1636	if (m_debug_icache_fsm)
1637	{
1638	std::cout << " <PROC " << name()
1639	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1640	<< " / WAY = " << way
1641	<< " / SET = " << set;
1642	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1643	else std::cout << std::endl;
1644	}
1645	#endif
1646	}
1647	break;
1648	}
1649	///////////////////////
1650	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1651	{
1652	if (m_ireq.valid) m_cost_ins_miss_frz++;
1653
1654	#ifdef INSTRUMENTATION
1655	m_cpt_icache_dir_write++;
1656	#endif
1657	r_icache.write_dir(r_icache_miss_way.read(),
1658	r_icache_miss_set.read(),
1659	CACHE_SLOT_STATE_ZOMBI);
1660	#if DEBUG_ICACHE
1661	if (m_debug_icache_fsm)
1662	{
1663	std::cout << " <PROC " << name()
1664	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1665	<< " / WAY = " << r_icache_miss_way.read()
1666	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1667	}
1668	#endif
1669
1670	r_icache_fsm = ICACHE_MISS_WAIT;
1671	break;
1672	}
1673	//////////////////////
1674	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1675	{
1676	if (m_ireq.valid) m_cost_ins_miss_frz++;
1677
1678	// send cleanup victim request
1679	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1680	{
1681	r_icache_cc_send_req = true;
1682	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1683	r_icache_cc_send_way = r_icache_miss_way;
1684	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1685	r_icache_cleanup_victim_req = false;
1686	}
1687
1688	// coherence clack interrupt
1689	if (r_icache_clack_req.read())
1690	{
1691	r_icache_fsm = ICACHE_CC_CHECK;
1692	r_icache_fsm_save = r_icache_fsm.read();
1693	break;
1694	}
1695
1696	// coherence interrupt
1697	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1698	{
1699	r_icache_fsm = ICACHE_CC_CHECK;
1700	r_icache_fsm_save = r_icache_fsm.read();
1701	break;
1702	}
1703
1704	if (r_vci_rsp_ins_error.read()) // bus error
1705	{
1706	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1707	r_mmu_ibvar = r_icache_vaddr_save.read();
1708	m_irsp.valid = true;
1709	m_irsp.error = true;
1710	r_vci_rsp_ins_error = false;
1711	r_icache_fsm = ICACHE_IDLE;
1712	}
1713	else if (r_vci_rsp_fifo_icache.rok()) // response available
1714	{
1715	r_icache_miss_word = 0;
1716	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1717	}
1718	break;
1719	}
1720	///////////////////////////
1721	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1722	{
1723	if (m_ireq.valid) m_cost_ins_miss_frz++;
1724
1725	if (r_vci_rsp_fifo_icache.rok()) // response available
1726	{
1727
1728	#ifdef INSTRUMENTATION
1729	m_cpt_icache_data_write++;
1730	#endif
1731	r_icache.write(r_icache_miss_way.read(),
1732	r_icache_miss_set.read(),
1733	r_icache_miss_word.read(),
1734	r_vci_rsp_fifo_icache.read());
1735	#if DEBUG_ICACHE
1736	if (m_debug_icache_fsm)
1737	{
1738	std::cout << " <PROC " << name()
1739	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1740	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1741	<< " WAY = " << r_icache_miss_way.read()
1742	<< " SET = " << r_icache_miss_set.read()
1743	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1744	}
1745	#endif
1746	vci_rsp_fifo_icache_get = true;
1747	r_icache_miss_word = r_icache_miss_word.read() + 1;
1748
1749	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
1750	{
1751	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1752	}
1753	}
1754	break;
1755	}
1756	//////////////////////////
1757	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1758	// and the cleanup ack has not been received,
1759	// as indicated by r_icache_miss_clack.
1760	// - If no matching coherence request (r_icache_miss_inval)
1761	// switch directory slot to VALID state.
1762	// - If matching coherence request, switch directory slot
1763	// to ZOMBI state, and send a cleanup request.
1764	{
1765	if (m_ireq.valid ) m_cost_ins_miss_frz++;
1766
1767	// send cleanup victim request
1768	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1769	{
1770	r_icache_cc_send_req = true;
1771	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1772	r_icache_cc_send_way = r_icache_miss_way;
1773	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1774	r_icache_cleanup_victim_req = false;
1775	}
1776
1777	// coherence clack interrupt
1778	if (r_icache_clack_req.read())
1779	{
1780	r_icache_fsm = ICACHE_CC_CHECK;
1781	r_icache_fsm_save = r_icache_fsm.read();
1782	break;
1783	}
1784
1785	// coherence interrupt
1786	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1787	{
1788	r_icache_fsm = ICACHE_CC_CHECK;
1789	r_icache_fsm_save = r_icache_fsm.read();
1790	break;
1791	}
1792
1793	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
1794	{
1795	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
1796	{
1797	if (not r_icache_cc_send_req.read())
1798	{
1799	r_icache_miss_inval = false;
1800	// request cleanup
1801	r_icache_cc_send_req = true;
1802	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1803	r_icache_cc_send_way = r_icache_miss_way.read();
1804	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1805
1806	#ifdef INSTRUMENTATION
1807	m_cpt_icache_dir_write++;
1808	#endif
1809	r_icache.write_dir(r_icache_vci_paddr.read(),
1810	r_icache_miss_way.read(),
1811	r_icache_miss_set.read(),
1812	CACHE_SLOT_STATE_ZOMBI);
1813	#if DEBUG_ICACHE
1814	if (m_debug_icache_fsm)
1815	{
1816	std::cout << " <PROC " << name()
1817	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1818	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1819	<< " WAY = " << std::dec << r_icache_miss_way.read()
1820	<< " SET = " << r_icache_miss_set.read() << std::endl;
1821	}
1822	#endif
1823	}
1824	else
1825	break;
1826	}
1827	else // Switch slot to VALID state
1828	{
1829
1830	#ifdef INSTRUMENTATION
1831	m_cpt_icache_dir_write++;
1832	#endif
1833	r_icache.write_dir(r_icache_vci_paddr.read(),
1834	r_icache_miss_way.read(),
1835	r_icache_miss_set.read(),
1836	CACHE_SLOT_STATE_VALID);
1837	#if DEBUG_ICACHE
1838	if (m_debug_icache_fsm)
1839	{
1840	std::cout << " <PROC " << name()
1841	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1842	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1843	<< " WAY = " << std::dec << r_icache_miss_way.read()
1844	<< " SET = " << r_icache_miss_set.read() << std::endl;
1845	}
1846	#endif
1847	}
1848
1849	r_icache_fsm = ICACHE_IDLE;
1850	}
1851	break;
1852	}
1853	////////////////////
1854	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1855	{
1856	// coherence clack interrupt
1857	if (r_icache_clack_req.read())
1858	{
1859	r_icache_fsm = ICACHE_CC_CHECK;
1860	r_icache_fsm_save = r_icache_fsm.read();
1861	break;
1862	}
1863
1864	// coherence interrupt
1865	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1866	{
1867	r_icache_fsm = ICACHE_CC_CHECK;
1868	r_icache_fsm_save = r_icache_fsm.read();
1869	break;
1870	}
1871
1872	if (r_vci_rsp_ins_error.read()) // bus error
1873	{
1874	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1875	r_mmu_ibvar = m_ireq.addr;
1876	r_vci_rsp_ins_error = false;
1877	m_irsp.valid = true;
1878	m_irsp.error = true;
1879	r_icache_fsm = ICACHE_IDLE;
1880	}
1881	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
1882	{
1883	vci_rsp_fifo_icache_get = true;
1884	r_icache_fsm = ICACHE_IDLE;
1885	if (m_ireq.valid and
1886	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
1887	{
1888	m_irsp.valid = true;
1889	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1890	}
1891	}
1892	break;
1893	}
1894	/////////////////////
1895	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1896	// handling coherence requests.
1897	// if there is a matching pending miss, it is
1898	// signaled in the r_icache_miss_inval flip-flop.
1899	// The return state is defined in r_icache_fsm_save.
1900	{
1901	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1902	paddr_t mask = ~((m_icache_words << 2) - 1);
1903
1904	// CLACK handler
1905	// We switch the directory slot to EMPTY state
1906	// and reset r_icache_miss_clack if the cleanup ack
1907	// is matching a pending miss.
1908	if (r_icache_clack_req.read())
1909	{
1910
1911	if (m_ireq.valid) m_cost_ins_miss_frz++;
1912
1913	#ifdef INSTRUMENTATION
1914	m_cpt_icache_dir_write++;
1915	#endif
1916	r_icache.write_dir(0,
1917	r_icache_clack_way.read(),
1918	r_icache_clack_set.read(),
1919	CACHE_SLOT_STATE_EMPTY);
1920
1921	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
1922	(r_icache_miss_way.read() == r_icache_clack_way.read()))
1923	{
1924	r_icache_miss_clack = false;
1925	}
1926
1927	r_icache_clack_req = false;
1928
1929	// return to cc_save state
1930	r_icache_fsm = r_icache_fsm_save.read();
1931
1932	#if DEBUG_ICACHE
1933	if (m_debug_icache_fsm)
1934	{
1935	std::cout << " <PROC " << name()
1936	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1937	<< " set = " << r_icache_clack_set.read()
1938	<< " / way = " << r_icache_clack_way.read() << std::endl;
1939	}
1940	#endif
1941
1942	break;
1943	}
1944
1945	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
1946
1947	// Match between MISS address and CC address
1948	if (r_cc_receive_icache_req.read() and
1949	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1950	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1951	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1952	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
1953	{
1954	// signaling the matching
1955	r_icache_miss_inval = true;
1956
1957	// in case of update, go to CC_UPDT
1958	// JUST TO POP THE FIFO
1959	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1960	{
1961	r_icache_fsm = ICACHE_CC_UPDT;
1962	r_icache_cc_word = r_cc_receive_word_idx.read();
1963
1964	// just pop the fifo , don't write in icache
1965	r_icache_cc_need_write = false;
1966	}
1967	// the request is dealt with
1968	else
1969	{
1970	r_cc_receive_icache_req = false;
1971	r_icache_fsm = r_icache_fsm_save.read();
1972	}
1973	#if DEBUG_ICACHE
1974	if (m_debug_icache_fsm)
1975	{
1976	std::cout << " <PROC " << name()
1977	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1978	<< " PADDR = " << std::hex << paddr << std::endl;
1979	}
1980	#endif
1981	}
1982
1983	// CC request handler
1984
1985	int state = 0;
1986	size_t way = 0;
1987	size_t set = 0;
1988	size_t word = 0;
1989
1990	#ifdef INSTRUMENTATION
1991	m_cpt_icache_dir_read++;
1992	#endif
1993	r_icache.read_dir(paddr,
1994	&state,
1995	&way,
1996	&set,
1997	&word);
1998
1999	r_icache_cc_way = way;
2000	r_icache_cc_set = set;
2001
2002	if (state == CACHE_SLOT_STATE_VALID) // hit
2003	{
2004	// need to update the cache state
2005	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
2006	{
2007	r_icache_cc_need_write = true;
2008	r_icache_fsm = ICACHE_CC_UPDT;
2009	r_icache_cc_word = r_cc_receive_word_idx.read();
2010	}
2011	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
2012	{
2013	r_icache_fsm = ICACHE_CC_INVAL;
2014	}
2015	}
2016	else // miss
2017	{
2018	// multicast acknowledgement required in case of update
2019	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
2020	{
2021	r_icache_fsm = ICACHE_CC_UPDT;
2022	r_icache_cc_word = r_cc_receive_word_idx.read();
2023
2024	// just pop the fifo , don't write in icache
2025	r_icache_cc_need_write = false;
2026	}
2027	else // No response needed
2028	{
2029	r_cc_receive_icache_req = false;
2030	r_icache_fsm = r_icache_fsm_save.read();
2031	}
2032	}
2033	break;
2034	}
2035	/////////////////////
2036	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
2037	{
2038	assert (not r_icache_cc_send_req.read() &&
2039	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
2040	"must not be set");
2041
2042	#ifdef INSTRUMENTATION
2043	m_cpt_icache_dir_read++;
2044	#endif
2045
2046	// Switch slot state to ZOMBI and send CLEANUP command
2047	r_icache.write_dir(r_icache_cc_way.read(),
2048	r_icache_cc_set.read(),
2049	CACHE_SLOT_STATE_ZOMBI);
2050
2051	// coherence request completed
2052	r_icache_cc_send_req = true;
2053	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2054	r_icache_cc_send_way = r_icache_cc_way.read();
2055	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2056
2057	r_icache_fsm = r_icache_fsm_save.read();
2058
2059	#if DEBUG_ICACHE
2060	if (m_debug_icache_fsm)
2061	{
2062	std::cout << " <PROC " << name()
2063	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
2064	<< " set = " << r_icache_cc_set.read()
2065	<< " / way = " << r_icache_cc_way.read() << std::endl;
2066	}
2067	#endif
2068
2069	break;
2070	}
2071	////////////////////
2072	case ICACHE_CC_UPDT: // hit update : write one word per cycle
2073	{
2074	assert (not r_icache_cc_send_req.read() &&
2075	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
2076	"must not be set");
2077
2078	if (not r_cc_receive_updt_fifo_be.rok()) break;
2079
2080
2081	size_t word = r_icache_cc_word.read();
2082	size_t way = r_icache_cc_way.read();
2083	size_t set = r_icache_cc_set.read();
2084
2085	if (r_icache_cc_need_write.read())
2086	{
2087	r_icache.write(way,
2088	set,
2089	word,
2090	r_cc_receive_updt_fifo_data.read(),
2091	r_cc_receive_updt_fifo_be.read());
2092
2093	r_icache_cc_word = word + 1;
2094
2095	#ifdef INSTRUMENTATION
2096	m_cpt_icache_data_write++;
2097	#endif
2098
2099	#if DEBUG_ICACHE
2100	if (m_debug_icache_fsm)
2101	{
2102	std::cout << " <PROC " << name()
2103	<< " ICACHE_CC_UPDT> Write one word "
2104	<< " set = " << r_icache_cc_set.read()
2105	<< " / way = " << r_icache_cc_way.read()
2106	<< " / word = " << r_icache_cc_word.read() << std::endl;
2107	}
2108	#endif
2109	}
2110
2111	if (r_cc_receive_updt_fifo_eop.read()) // last word
2112	{
2113	// no need to write in the cache anymore
2114	r_icache_cc_need_write = false;
2115
2116	// coherence request completed
2117	r_cc_receive_icache_req = false;
2118
2119	// request multicast acknowledgement
2120	r_icache_cc_send_req = true;
2121	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2122	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2123	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2124
2125	r_icache_fsm = r_icache_fsm_save.read();
2126	}
2127	//consume fifo if not eop
2128	cc_receive_updt_fifo_get = true;
2129
2130	break;
2131	}
2132
2133	} // end switch r_icache_fsm
2134
2135	////////////////////////////////////////////////////////////////////////////////////
2136	// DCACHE FSM
2137	//
2138	// 1/ Coherence operations
2139	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2140	// - There is a coherence request when r_tgt_dcache_req is set.
2141	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2142	// and SC_WAIT states.
2143	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2144	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2145	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2146	// - For both types of requests, actions associated to the pre-empted state
2147	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2148	// or CC_CLACK) to execute the requested coherence operation, and returns
2149	// to the pre-empted state.
2150	//
2151	// 2/ TLB miss
2152	// The page tables are generally cacheable.
2153	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2154	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2155	// this sub-fsm implement the table-walk...
2156	//
2157	// 3/ processor requests
2158	// Processor requests are taken in IDLE state only.
2159	// The IDLE state implements a two stages pipe-line to handle write bursts:
2160	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2161	// - The registration in wbuf and the dcache update is done in stage P1
2162	// (if the processor request is a write).
2163	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2164	// the operations that must be done in P1 stage, and the access type
2165	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2166	// READ requests are delayed if a cache update is requested.
2167	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2168	// that is done (before handling the processor request) by a dedicated sub-fsm.
2169	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2170	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2171	//
2172	// 4/ Atomic instructions LL/SC
2173	// The LL/SC address are non cacheable (systematic access to memory).
2174	// The llsc buffer contains a registration for an active LL/SC operation
2175	// (with an address, a registration key, an aging counter and a valid bit).
2176	// - LL requests from the processor are transmitted as a one flit VCI command
2177	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2178	// be 8 as the response is 2 flits long (data and registration key)
2179	// - SC requests from the processor are systematically transmitted to the
2180	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2181	// as PKTID value). The first flit contains the registration key, the second
2182	// flit contains the data to write in case of success.
2183	// The cache is not updated, as this is done in case of success by the
2184	// coherence transaction.
2185	//
2186	// 5/ Non cacheable access:
2187	// This component implement a strong order between non cacheable access
2188	// (read or write) : A new non cacheable VCI transaction starts only when
2189	// the previous non cacheable transaction is completed. After send the VCI
2190	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
2191	// So the processor is blocked until the respone arrives in CACHE L1.
2192	//
2193	// 6/ Error handling:
2194	// When the MMU is not activated, Read Bus Errors are synchronous events,
2195	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
2196	// but some Write Bus Errors are asynchronous events when the request is cacheable access
2197	// (processor is not frozen).
2198	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
2199	// r_vci_rsp_data_error flip-flop, without writing any data in the
2200	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2201	// by the DCACHE FSM.
2202	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
2203	// the asynchronous error using the setWriteBerr() method.
2204	// When the MMU is activated bus error are rare events, as the MMU
2205	// checks the physical address before the VCI transaction starts.
2206	////////////////////////////////////////////////////////////////////////////////////////
2207
2208	// default value for m_drsp
2209	m_drsp.valid = false;
2210	m_drsp.error = false;
2211	m_drsp.rdata = 0;
2212
2213	switch (r_dcache_fsm.read())
2214	{
2215	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2216	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2217	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2218	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2219	// 4) XTN request (processor) => DCACHE_XTN_*
2220	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2221	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2222	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2223	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
2224	// 9) LL access (processor) => DCACHE_LL_WAIT
2225	// 10) SC access (processor) => DCACHE_SC_WAIT
2226	//
2227	// There is a fixed priority to handle requests to DCACHE:
2228	// 1/ the ITLB/DTLB invalidate requests
2229	// 2/ the coherence requests,
2230	// 3/ the processor requests (including DTLB miss),
2231	// 4/ the ITLB miss requests,
2232	// The address space processor request are handled as follows:
2233	// - WRITE request is blocked if the Dirty bit mus be set.
2234	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2235	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2236	// - READ request generate a simultaneouss access to DCACHE.DATA
2237	// and DCACHE.DIR, but is delayed if DCACHE update required.
2238	//
2239	// There is 4 configurations defining the access type to
2240	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2241	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2242	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2243	// 0 / 0 / NOP / NOP / NOP /
2244	// 0 / 1 / NOP / NOP / WRITE /
2245	// 1 / 0 / READ / READ / NOP /
2246	// 1 / 1 / READ / READ / WRITE /
2247	// Those two registers are set at each cycle from the 3 signals
2248	// updt_request, wbuf_request, wbuf_write_miss.
2249	{
2250	paddr_t paddr;
2251	pte_info_t tlb_flags;
2252	size_t tlb_way;
2253	size_t tlb_set;
2254	paddr_t tlb_nline = 0;
2255	size_t cache_way;
2256	size_t cache_set;
2257	size_t cache_word;
2258	uint32_t cache_rdata = 0;
2259	bool tlb_hit = false;
2260	int cache_state = CACHE_SLOT_STATE_EMPTY;
2261
2262	bool tlb_inval_required = false; // request TLB inval after cache update
2263	bool wbuf_write_miss = false; // miss a WBUF write request
2264	bool updt_request = false; // request DCACHE update in P1 stage
2265	bool wbuf_request = false; // request WBUF write in P1 stage
2266
2267	// physical address computation : systematic DTLB access if activated
2268	paddr = (paddr_t) m_dreq.addr;
2269	if (m_dreq.valid)
2270	{
2271	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
2272	{
2273	tlb_hit = r_dtlb.translate(m_dreq.addr,
2274	&paddr,
2275	&tlb_flags,
2276	&tlb_nline,
2277	&tlb_way,
2278	&tlb_set);
2279	#ifdef INSTRUMENTATION
2280	m_cpt_dtlb_read++;
2281	#endif
2282	}
2283	else // identity mapping
2284	{
2285	// we take into account the paddr extension
2286	if (vci_param::N > 32)
2287	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
2288	}
2289	} // end physical address computation
2290
2291	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2292	if (r_mmu_mode.read() & DATA_CACHE_MASK)
2293	{
2294
2295	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
2296	{
2297	r_dcache.read_dir(paddr,
2298	&cache_state,
2299	&cache_way,
2300	&cache_set,
2301	&cache_word);
2302
2303	r_dcache.write(r_dcache_save_cache_way.read(),
2304	r_dcache_save_cache_set.read(),
2305	r_dcache_save_cache_word.read(),
2306	r_dcache_save_wdata.read(),
2307	r_dcache_save_be.read());
2308	#ifdef INSTRUMENTATION
2309	m_cpt_dcache_dir_read++;
2310	m_cpt_dcache_data_write++;
2311	#endif
2312	}
2313	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
2314	{
2315	r_dcache.read(paddr,
2316	&cache_rdata,
2317	&cache_way,
2318	&cache_set,
2319	&cache_word,
2320	&cache_state);
2321
2322	#ifdef INSTRUMENTATION
2323	m_cpt_dcache_dir_read++;
2324	m_cpt_dcache_data_read++;
2325	#endif
2326	}
2327	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
2328	{
2329	r_dcache.write(r_dcache_save_cache_way.read(),
2330	r_dcache_save_cache_set.read(),
2331	r_dcache_save_cache_word.read(),
2332	r_dcache_save_wdata.read(),
2333	r_dcache_save_be.read());
2334	#ifdef INSTRUMENTATION
2335	m_cpt_dcache_data_write++;
2336	#endif
2337	}
2338	} // end dcache access
2339
2340	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2341	if (r_dcache_updt_req.read())
2342	{
2343	size_t way = r_dcache_save_cache_way.read();
2344	size_t set = r_dcache_save_cache_set.read();
2345
2346	if (r_dcache_in_tlb[way * m_dcache_sets + set])
2347	{
2348	tlb_inval_required = true;
2349	r_dcache_tlb_inval_set = 0;
2350	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
2351	(uint32_log2(m_dcache_words << 2));
2352	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
2353	}
2354	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
2355	{
2356	r_itlb.reset();
2357	r_dtlb.reset();
2358	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
2359	}
2360
2361	#if DEBUG_DCACHE
2362	if (m_debug_dcache_fsm)
2363	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2364	<< " Cache update in P1 stage" << std::dec
2365	<< " / WAY = " << r_dcache_save_cache_way.read()
2366	<< " / SET = " << r_dcache_save_cache_set.read()
2367	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2368	<< " / WDATA = " << r_dcache_save_wdata.read()
2369	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2370	#endif
2371	} // end test TLB inval
2372
2373	// Try WBUF update in P1 stage
2374	// Miss if the write request is non cacheable, and there is a pending
2375	// non cacheable write, or if the write buffer is full.
2376	if (r_dcache_wbuf_req.read())
2377	{
2378	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
2379	r_dcache_save_be.read(),
2380	r_dcache_save_wdata.read(),
2381	true);
2382	#ifdef INSTRUMENTATION
2383	m_cpt_wbuf_write++;
2384	#endif
2385	if (not wok ) // miss if write buffer full
2386	{
2387	wbuf_write_miss = true;
2388	}
2389	} // end WBUF update
2390
2391	// Computing the response to processor,
2392	// and the next value for r_dcache_fsm
2393
2394	// itlb/dtlb invalidation self-request
2395	if (tlb_inval_required)
2396	{
2397	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2398	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2399	}
2400
2401	// coherence clack request (from DSPIN CLACK)
2402	else if (r_dcache_clack_req.read())
2403	{
2404	r_dcache_fsm = DCACHE_CC_CHECK;
2405	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2406	}
2407	// coherence request (from CC_RECEIVE FSM)
2408	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
2409	{
2410	r_dcache_fsm = DCACHE_CC_CHECK;
2411	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2412	}
2413
2414	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2415	// we don't take the processor request, and registers
2416	// are frozen in case of wbuf_write_miss
2417	else if (m_dreq.valid and not wbuf_write_miss)
2418	{
2419	// register processor request and DCACHE response
2420	r_dcache_save_vaddr = m_dreq.addr;
2421	r_dcache_save_be = m_dreq.be;
2422	r_dcache_save_wdata = m_dreq.wdata;
2423	r_dcache_save_paddr = paddr;
2424	r_dcache_save_cache_way = cache_way;
2425	r_dcache_save_cache_set = cache_set;
2426	r_dcache_save_cache_word = cache_word;
2427
2428	// READ XTN requests from processor
2429	// They are executed in this DCACHE_IDLE state.
2430	// The processor must not be in user mode
2431	if (m_dreq.type == iss_t::XTN_READ)
2432	{
2433	int xtn_opcode = (int) m_dreq.addr / 4;
2434
2435	// checking processor mode:
2436	if (m_dreq.mode == iss_t::MODE_USER)
2437	{
2438	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2439	r_mmu_dbvar = m_dreq.addr;
2440	m_drsp.valid = true;
2441	m_drsp.error = true;
2442	m_drsp.rdata = 0;
2443	r_dcache_fsm = DCACHE_IDLE;
2444	}
2445	else
2446	{
2447	switch (xtn_opcode)
2448	{
2449	case iss_t::XTN_INS_ERROR_TYPE:
2450	m_drsp.rdata = r_mmu_ietr.read();
2451	m_drsp.valid = true;
2452	m_drsp.error = false;
2453	break;
2454
2455	case iss_t::XTN_DATA_ERROR_TYPE:
2456	m_drsp.rdata = r_mmu_detr.read();
2457	m_drsp.valid = true;
2458	m_drsp.error = false;
2459	break;
2460
2461	case iss_t::XTN_INS_BAD_VADDR:
2462	m_drsp.rdata = r_mmu_ibvar.read();
2463	m_drsp.valid = true;
2464	m_drsp.error = false;
2465	break;
2466
2467	case iss_t::XTN_DATA_BAD_VADDR:
2468	m_drsp.rdata = r_mmu_dbvar.read();
2469	m_drsp.valid = true;
2470	m_drsp.error = false;
2471	break;
2472
2473	case iss_t::XTN_PTPR:
2474	m_drsp.rdata = r_mmu_ptpr.read();
2475	m_drsp.valid = true;
2476	m_drsp.error = false;
2477	break;
2478
2479	case iss_t::XTN_TLB_MODE:
2480	m_drsp.rdata = r_mmu_mode.read();
2481	m_drsp.valid = true;
2482	m_drsp.error = false;
2483	break;
2484
2485	case iss_t::XTN_MMU_PARAMS:
2486	m_drsp.rdata = r_mmu_params;
2487	m_drsp.valid = true;
2488	m_drsp.error = false;
2489	break;
2490
2491	case iss_t::XTN_MMU_RELEASE:
2492	m_drsp.rdata = r_mmu_release;
2493	m_drsp.valid = true;
2494	m_drsp.error = false;
2495	break;
2496
2497	case iss_t::XTN_MMU_WORD_LO:
2498	m_drsp.rdata = r_mmu_word_lo.read();
2499	m_drsp.valid = true;
2500	m_drsp.error = false;
2501	break;
2502
2503	case iss_t::XTN_MMU_WORD_HI:
2504	m_drsp.rdata = r_mmu_word_hi.read();
2505	m_drsp.valid = true;
2506	m_drsp.error = false;
2507	break;
2508
2509	case iss_t::XTN_DATA_PADDR_EXT:
2510	m_drsp.rdata = r_dcache_paddr_ext.read();
2511	m_drsp.valid = true;
2512	m_drsp.error = false;
2513	break;
2514
2515	case iss_t::XTN_INST_PADDR_EXT:
2516	m_drsp.rdata = r_icache_paddr_ext.read();
2517	m_drsp.valid = true;
2518	m_drsp.error = false;
2519	break;
2520
2521	default:
2522	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2523	r_mmu_dbvar = m_dreq.addr;
2524	m_drsp.valid = true;
2525	m_drsp.error = true;
2526	m_drsp.rdata = 0;
2527	break;
2528	} // end switch xtn_opcode
2529	} // end else
2530	} // end if XTN_READ
2531
2532	// Handling WRITE XTN requests from processor.
2533	// They are not executed in this DCACHE_IDLE state
2534	// if they require access to the caches or the TLBs
2535	// that are already accessed.
2536	// Caches can be invalidated or flushed in user mode,
2537	// and the sync instruction can be executed in user mode
2538	else if (m_dreq.type == iss_t::XTN_WRITE)
2539	{
2540	int xtn_opcode = (int)m_dreq.addr / 4;
2541	r_dcache_xtn_opcode = xtn_opcode;
2542
2543	// checking processor mode:
2544	if ((m_dreq.mode == iss_t::MODE_USER) &&
2545	(xtn_opcode != iss_t::XTN_SYNC) &&
2546	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2547	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2548	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2549	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
2550	{
2551	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2552	r_mmu_dbvar = m_dreq.addr;
2553	m_drsp.valid = true;
2554	m_drsp.error = true;
2555	m_drsp.rdata = 0;
2556	r_dcache_fsm = DCACHE_IDLE;
2557	}
2558	else
2559	{
2560	switch (xtn_opcode)
2561	{
2562	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2563	r_dcache_xtn_req = true;
2564	r_dcache_fsm = DCACHE_XTN_SWITCH;
2565	break;
2566
2567	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2568	r_mmu_mode = m_dreq.wdata;
2569	m_drsp.valid = true;
2570	r_dcache_fsm = DCACHE_IDLE;
2571	break;
2572
2573	case iss_t::XTN_DTLB_INVAL: // dtlb access
2574	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2575	break;
2576
2577	case iss_t::XTN_ITLB_INVAL: // itlb access
2578	r_dcache_xtn_req = true;
2579	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2580	break;
2581
2582	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2583	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2584	break;
2585
2586	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2587	{
2588	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
2589	((uint64_t)r_mmu_word_lo.read());
2590
2591	r_dcache_save_paddr = (paddr_t)pa;
2592	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2593	break;
2594	}
2595	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2596	r_dcache_flush_count = 0;
2597	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2598	break;
2599
2600	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2601	r_dcache_xtn_req = true;
2602	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2603	break;
2604
2605	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2606	r_dcache_xtn_req = true;
2607	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2608	break;
2609
2610	case iss_t::XTN_ICACHE_FLUSH: // icache access
2611	r_dcache_xtn_req = true;
2612	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2613	break;
2614
2615	case iss_t::XTN_SYNC: // wait until write buffer empty
2616	r_dcache_fsm = DCACHE_XTN_SYNC;
2617	break;
2618
2619	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2620	r_mmu_word_lo = m_dreq.wdata;
2621	m_drsp.valid = true;
2622	r_dcache_fsm = DCACHE_IDLE;
2623	break;
2624
2625	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2626	r_mmu_word_hi = m_dreq.wdata;
2627	m_drsp.valid = true;
2628	r_dcache_fsm = DCACHE_IDLE;
2629	break;
2630
2631	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2632	r_dcache_llsc_valid = false;
2633	m_drsp.valid = true;
2634	r_dcache_fsm = DCACHE_IDLE;
2635	break;
2636
2637	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2638	r_dcache_paddr_ext = m_dreq.wdata;
2639	m_drsp.valid = true;
2640	r_dcache_fsm = DCACHE_IDLE;
2641	break;
2642
2643	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
2644	r_dcache_xtn_req = true;
2645	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
2646	break;
2647
2648	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2649	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2650	m_drsp.valid = true;
2651	r_dcache_fsm = DCACHE_IDLE;
2652	break;
2653
2654	case iss_t::XTN_DEBUG_MASK: // debug mask
2655	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2656	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2657	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2658	m_drsp.valid = true;
2659	r_dcache_fsm = DCACHE_IDLE;
2660	break;
2661
2662	default:
2663	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2664	r_mmu_dbvar = m_dreq.addr;
2665	m_drsp.valid = true;
2666	m_drsp.error = true;
2667	r_dcache_fsm = DCACHE_IDLE;
2668	break;
2669	} // end switch xtn_opcode
2670	} // end else
2671	} // end if XTN_WRITE
2672
2673	// Handling processor requests to address space (READ/WRITE/LL/SC)
2674	// The dtlb and dcache can be activated or not.
2675	// We compute the cacheability, and check processor request validity:
2676	// - If DTLB not activated : cacheability is defined by the segment table,
2677	// and there is no access rights checking.
2678	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2679	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2680	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2681	else
2682	{
2683	bool valid_req;
2684	bool cacheable;
2685
2686	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
2687	{
2688	valid_req = true;
2689
2690	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2691	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
2692	}
2693	else // dtlb activated
2694	{
2695	if (tlb_hit) // tlb hit
2696	{
2697	// cacheability
2698	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2699	else cacheable = tlb_flags.c;
2700
2701	// access rights checking
2702	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2703	{
2704	if ((m_dreq.type == iss_t::DATA_READ) or
2705	(m_dreq.type == iss_t::DATA_LL))
2706	{
2707	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2708	}
2709	else
2710	{
2711	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2712	}
2713	valid_req = false;
2714	r_mmu_dbvar = m_dreq.addr;
2715	m_drsp.valid = true;
2716	m_drsp.error = true;
2717	m_drsp.rdata = 0;
2718	#if DEBUG_DCACHE
2719	if (m_debug_dcache_fsm)
2720	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2721	<< " HIT in dtlb, but privilege violation" << std::endl;
2722	#endif
2723	}
2724	else if (not tlb_flags.w and
2725	((m_dreq.type == iss_t::DATA_WRITE) or
2726	(m_dreq.type == iss_t::DATA_SC)))
2727	{
2728	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2729	valid_req = false;
2730	r_mmu_dbvar = m_dreq.addr;
2731	m_drsp.valid = true;
2732	m_drsp.error = true;
2733	m_drsp.rdata = 0;
2734	#if DEBUG_DCACHE
2735	if (m_debug_dcache_fsm)
2736	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2737	<< " HIT in dtlb, but writable violation" << std::endl;
2738	#endif
2739	}
2740	else
2741	{
2742	valid_req = true;
2743	}
2744	}
2745	else // tlb miss
2746	{
2747	valid_req = false;
2748	r_dcache_tlb_vaddr = m_dreq.addr;
2749	r_dcache_tlb_ins = false;
2750	r_dcache_fsm = DCACHE_TLB_MISS;
2751	}
2752	} // end DTLB activated
2753
2754	if (valid_req) // processor request is valid (after MMU check)
2755	{
2756	// READ request
2757	// The read requests are taken only if there is no cache update.
2758	// We request a VCI transaction to CMD FSM if miss or uncachable
2759
2760	if (((m_dreq.type == iss_t::DATA_READ))
2761	and not r_dcache_updt_req.read())
2762	{
2763	if (cacheable) // cacheable read
2764	{
2765	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
2766	{
2767	#ifdef INSTRUMENTATION
2768	m_cpt_dcache_miss++;
2769	#endif
2770	// request a VCI DMISS transaction
2771	r_dcache_vci_paddr = paddr;
2772	r_dcache_vci_miss_req = true;
2773	r_dcache_miss_type = PROC_MISS;
2774	r_dcache_fsm = DCACHE_MISS_SELECT;
2775	#if DEBUG_DCACHE
2776	if (m_debug_dcache_fsm)
2777	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2778	<< " READ MISS in dcache"
2779	<< " / PADDR = " << std::hex << paddr << std::endl;
2780	#endif
2781	}
2782	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
2783	{
2784	// stalled until cleanup is acknowledged
2785	r_dcache_fsm = DCACHE_IDLE;
2786	#if DEBUG_DCACHE
2787	if (m_debug_dcache_fsm)
2788	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2789	<< " Pending cleanup, stalled until cleanup acknowledge"
2790	<< " / PADDR = " << std::hex << paddr << std::endl;
2791	#endif
2792	}
2793	else // cache hit
2794	{
2795	#ifdef INSTRUMENTATION
2796	m_cpt_data_read++;
2797	#endif
2798	// returns data to processor
2799	m_drsp.valid = true;
2800	m_drsp.error = false;
2801	m_drsp.rdata = cache_rdata;
2802	#if DEBUG_DCACHE
2803	if (m_debug_dcache_fsm)
2804	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2805	<< " READ HIT in dcache"
2806	<< " : PADDR = " << std::hex << paddr
2807	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2808	#endif
2809	}
2810	}
2811	else // uncacheable read
2812	{
2813	r_dcache_vci_paddr = paddr;
2814	r_dcache_vci_unc_be = m_dreq.be;
2815	r_dcache_vci_unc_write = false;
2816	r_dcache_vci_unc_req = true;
2817	r_dcache_fsm = DCACHE_UNC_WAIT;
2818	#if DEBUG_DCACHE
2819	if (m_debug_dcache_fsm)
2820	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2821	<< " READ UNCACHEABLE in dcache"
2822	<< " / PADDR = " << std::hex << paddr << std::endl;
2823	#endif
2824	}
2825	} // end READ
2826
2827	// LL request (non cachable)
2828	// We request a VCI LL transaction to CMD FSM and register
2829	// the LL/SC operation in llsc buffer.
2830	else if (m_dreq.type == iss_t::DATA_LL)
2831	{
2832	// register paddr in LLSC buffer
2833	r_dcache_llsc_paddr = paddr;
2834	r_dcache_llsc_count = LLSC_TIMEOUT;
2835	r_dcache_llsc_valid = true;
2836
2837	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2838	r_dcache_vci_ll_req = true;
2839	r_dcache_vci_paddr = paddr;
2840	r_dcache_ll_rsp_count = 0;
2841	r_dcache_fsm = DCACHE_LL_WAIT;
2842
2843	}// end LL
2844
2845	// WRITE request:
2846	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2847	// the processor and set the Dirty bit before handling the write request,
2848	// going to the DCACHE_DIRTY_GT_PTE state.
2849	// If we don't need to set the Dirty bit, we can acknowledge
2850	// the processor request, as the write arguments (including the
2851	// physical address) are registered in r_dcache_save registers,
2852	// and the write will be done in the P1 pipeline stage.
2853	else if (m_dreq.type == iss_t::DATA_WRITE)
2854	{
2855	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2856	and not tlb_flags.d) // Dirty bit must be set
2857	{
2858	// The PTE physical address is obtained from the nline value (dtlb),
2859	// and from the virtual address (word index)
2860	if (tlb_flags.b ) // PTE1
2861	{
2862	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
2863	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
2864	}
2865	else // PTE2
2866	{
2867	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2868	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2869	}
2870	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2871	}
2872	else // Write request accepted
2873	{
2874	#ifdef INSTRUMENTATION
2875	m_cpt_data_write++;
2876	#endif
2877	// cleaning llsc buffer if address matching
2878	if (paddr == r_dcache_llsc_paddr.read())
2879	r_dcache_llsc_valid = false;
2880
2881	if (not cacheable) // uncacheable write
2882	{
2883	r_dcache_vci_paddr = paddr;
2884	r_dcache_vci_wdata = m_dreq.wdata;
2885	r_dcache_vci_unc_write = true;
2886	r_dcache_vci_unc_be = m_dreq.be;
2887	r_dcache_vci_unc_req = true;
2888	r_dcache_fsm = DCACHE_UNC_WAIT;
2889
2890	#if DEBUG_DCACHE
2891	if (m_debug_dcache_fsm)
2892	{
2893	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2894	<< " Request WRITE UNCACHEABLE" << std::hex
2895	<< " / VADDR = " << m_dreq.addr
2896	<< " / PADDR = " << paddr
2897	<< std::dec << std::endl;
2898	}
2899	#endif
2900	}
2901	else
2902	{
2903	// response to processor
2904	m_drsp.valid = true;
2905	// activating P1 stage
2906	wbuf_request = true;
2907	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2908
2909	#if DEBUG_DCACHE
2910	if (m_debug_dcache_fsm)
2911	{
2912	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2913	<< " Request WBUF WRITE" << std::hex
2914	<< " / VADDR = " << m_dreq.addr
2915	<< " / PADDR = " << paddr
2916	<< std::dec << std::endl;
2917	}
2918	#endif
2919	}
2920	}
2921	} // end WRITE
2922
2923	// SC request:
2924	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2925	// the processor and set the Dirty bit before handling the write request,
2926	// going to the DCACHE_DIRTY_GT_PTE state.
2927	// If we don't need to set the Dirty bit, we test the llsc buffer:
2928	// If failure, we send a negative response to processor.
2929	// If success, we request a SC transaction to CMD FSM and go
2930	// to DCACHE_SC_WAIT state.
2931	// We don't check a possible write hit in dcache, as the cache update
2932	// is done by the coherence transaction induced by the SC...
2933	else if (m_dreq.type == iss_t::DATA_SC)
2934	{
2935	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2936	and not tlb_flags.d) // Dirty bit must be set
2937	{
2938	// The PTE physical address is obtained from the nline value (dtlb),
2939	// and the word index (virtual address)
2940	if (tlb_flags.b) // PTE1
2941	{
2942	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2943	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2944	}
2945	else // PTE2
2946	{
2947	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2948	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2949	}
2950	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2951	m_drsp.valid = false;
2952	m_drsp.error = false;
2953	m_drsp.rdata = 0;
2954	}
2955	else // SC request accepted
2956	{
2957	#ifdef INSTRUMENTATION
2958	m_cpt_data_sc++;
2959	#endif
2960	// checking local success
2961	if (r_dcache_llsc_valid.read() and
2962	(r_dcache_llsc_paddr.read() == paddr)) // local success
2963	{
2964	// request an SC CMD and go to DCACHE_SC_WAIT state
2965	r_dcache_vci_paddr = paddr;
2966	r_dcache_vci_sc_req = true;
2967	r_dcache_vci_sc_data = m_dreq.wdata;
2968	r_dcache_fsm = DCACHE_SC_WAIT;
2969	}
2970	else // local fail
2971	{
2972	m_drsp.valid = true;
2973	m_drsp.error = false;
2974	m_drsp.rdata = 0x1;
2975	}
2976	}
2977	} // end SC
2978	} // end valid_req
2979	} // end if read/write/ll/sc request
2980	} // end processor request
2981
2982	// itlb miss request
2983	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
2984	{
2985	r_dcache_tlb_ins = true;
2986	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2987	r_dcache_fsm = DCACHE_TLB_MISS;
2988	}
2989
2990	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2991	r_dcache_updt_req = updt_request;
2992	r_dcache_wbuf_req = wbuf_request or
2993	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2994	break;
2995	}
2996	/////////////////////
2997	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2998	// Input arguments are:
2999	// - r_dcache_tlb_vaddr
3000	// - r_dcache_tlb_ins (true when itlb miss)
3001	// The sub-fsm access the dcache to find the missing TLB entry,
3002	// and activates the cache miss procedure in case of miss.
3003	// It bypass the first level page table access if possible.
3004	// It uses atomic access to update the R/L access bits
3005	// in the page table if required.
3006	// It directly updates the itlb or dtlb, and writes into the
3007	// r_mmu_ins_* or r_mmu_data* error reporting registers.
3008	{
3009	uint32_t ptba = 0;
3010	bool bypass;
3011	paddr_t pte_paddr;
3012
3013	// evaluate bypass in order to skip first level page table access
3014	if (r_dcache_tlb_ins.read()) // itlb miss
3015	{
3016	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3017	}
3018	else // dtlb miss
3019	{
3020	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3021	}
3022
3023	if (not bypass) // Try to read PTE1/PTD1 in dcache
3024	{
3025	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
3026	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
3027	r_dcache_tlb_paddr = pte_paddr;
3028	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3029	}
3030	else // Try to read PTE2 in dcache
3031	{
3032	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
3033	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
3034	r_dcache_tlb_paddr = pte_paddr;
3035	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3036	}
3037
3038	#if DEBUG_DCACHE
3039	if (m_debug_dcache_fsm)
3040	{
3041	if (r_dcache_tlb_ins.read())
3042	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
3043	else
3044	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
3045	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
3046	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
3047	<< " / BYPASS = " << bypass
3048	<< " / PTE_ADR = " << pte_paddr << std::endl;
3049	}
3050	#endif
3051
3052	break;
3053	}
3054	/////////////////////////
3055	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
3056	{
3057	// coherence clack request (from DSPIN CLACK)
3058	if (r_dcache_clack_req.read())
3059	{
3060	r_dcache_fsm = DCACHE_CC_CHECK;
3061	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3062	break;
3063	}
3064
3065	// coherence request (from CC_RECEIVE FSM)
3066	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3067	{
3068	r_dcache_fsm = DCACHE_CC_CHECK;
3069	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3070	break;
3071	}
3072
3073	uint32_t entry;
3074	size_t way;
3075	size_t set;
3076	size_t word;
3077	int cache_state;
3078	r_dcache.read(r_dcache_tlb_paddr.read(),
3079	&entry,
3080	&way,
3081	&set,
3082	&word,
3083	&cache_state);
3084	#ifdef INSTRUMENTATION
3085	m_cpt_dcache_data_read++;
3086	m_cpt_dcache_dir_read++;
3087	#endif
3088	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3089	{
3090	if (not (entry & PTE_V_MASK)) // unmapped
3091	{
3092	if (r_dcache_tlb_ins.read())
3093	{
3094	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
3095	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3096	r_icache_tlb_miss_req = false;
3097	r_icache_tlb_rsp_error = true;
3098	}
3099	else
3100	{
3101	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
3102	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3103	m_drsp.valid = true;
3104	m_drsp.error = true;
3105	}
3106	r_dcache_fsm = DCACHE_IDLE;
3107
3108	#if DEBUG_DCACHE
3109	if (m_debug_dcache_fsm)
3110	{
3111	std::cout << " <PROC " << name()
3112	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
3113	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3114	<< std::dec << " / way = " << way
3115	<< std::dec << " / set = " << set
3116	<< std::dec << " / word = " << word
3117	<< std::hex << " / PTE1 = " << entry << std::endl;
3118	}
3119	#endif
3120
3121	}
3122	else if (entry & PTE_T_MASK) // PTD : me must access PT2
3123	{
3124	// mark the cache line ac containing a PTD
3125	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
3126
3127	// register bypass
3128	if (r_dcache_tlb_ins.read()) // itlb
3129	{
3130	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3131	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3132	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
3133	}
3134	else // dtlb
3135	{
3136	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3137	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3138	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
3139	}
3140	r_dcache_tlb_paddr =
3141	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
3142	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3143	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3144
3145	#if DEBUG_DCACHE
3146	if (m_debug_dcache_fsm)
3147	{
3148	std::cout << " <PROC " << name()
3149	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3150	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3151	<< std::dec << " / way = " << way
3152	<< std::dec << " / set = " << set
3153	<< std::dec << " / word = " << word
3154	<< std::hex << " / PTD = " << entry << std::endl;
3155	}
3156	#endif
3157	}
3158	else // PTE1 : we must update the TLB
3159	{
3160	r_dcache_in_tlb[m_icache_sets * way + set] = true;
3161	r_dcache_tlb_pte_flags = entry;
3162	r_dcache_tlb_cache_way = way;
3163	r_dcache_tlb_cache_set = set;
3164	r_dcache_tlb_cache_word = word;
3165	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3166
3167	#if DEBUG_DCACHE
3168	if (m_debug_dcache_fsm)
3169	{
3170	std::cout << " <PROC " << name()
3171	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3172	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3173	<< std::dec << " / way = " << way
3174	<< std::dec << " / set = " << set
3175	<< std::dec << " / word = " << word
3176	<< std::hex << " / PTE1 = " << entry << std::endl;
3177	}
3178	#endif
3179	}
3180	}
3181	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3182	{
3183	// stalled until cleanup is acknowledged
3184	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3185	}
3186	else // we must load the missing cache line in dcache
3187	{
3188	r_dcache_vci_miss_req = true;
3189	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3190	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3191	r_dcache_miss_type = PTE1_MISS;
3192	r_dcache_fsm = DCACHE_MISS_SELECT;
3193
3194	#if DEBUG_DCACHE
3195	if (m_debug_dcache_fsm)
3196	{
3197	std::cout << " <PROC " << name()
3198	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3199	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3200	}
3201	#endif
3202	}
3203	break;
3204	}
3205	////////////////////////////
3206	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3207	{
3208	size_t way;
3209	size_t set;
3210
3211	if (r_dcache_tlb_ins.read())
3212	{
3213	r_itlb.select(r_dcache_tlb_vaddr.read(),
3214	true, // PTE1
3215	&way,
3216	&set);
3217	#ifdef INSTRUMENTATION
3218	m_cpt_itlb_read++;
3219	#endif
3220	}
3221	else
3222	{
3223	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3224	true, // PTE1
3225	&way,
3226	&set);
3227	#ifdef INSTRUMENTATION
3228	m_cpt_dtlb_read++;
3229	#endif
3230	}
3231	r_dcache_tlb_way = way;
3232	r_dcache_tlb_set = set;
3233	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3234
3235	#if DEBUG_DCACHE
3236	if (m_debug_dcache_fsm)
3237	{
3238	if (r_dcache_tlb_ins.read())
3239	std::cout << " <PROC " << name()
3240	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3241	else
3242	std::cout << " <PROC " << name()
3243	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3244	std::cout << " way = " << std::dec << way
3245	<< " / set = " << set << std::endl;
3246	}
3247	#endif
3248	break;
3249	}
3250	//////////////////////////
3251	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3252	// - if L/R bit already set, exit the sub-fsm.
3253	// - if not, we update the page table but we dont write
3254	// neither in DCACHE, nor in TLB, as this will be done by
3255	// the coherence mechanism.
3256	{
3257	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3258	uint32_t pte = r_dcache_tlb_pte_flags.read();
3259	bool pt_updt = false;
3260	bool local = true;
3261
3262	// We should compute the access locality:
3263	// The PPN MSB bits define the destination cluster index.
3264	// The m_srcid MSB bits define the source cluster index.
3265	// The number of bits to compare depends on the number of clusters,
3266	// and can be obtained in the mapping table.
3267	// As long as this computation is not done, all access are local.
3268
3269	if (local) // local access
3270	{
3271	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3272	{
3273	pt_updt = true;
3274	r_dcache_vci_cas_old = pte;
3275	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3276	pte = pte \| PTE_L_MASK;
3277	r_dcache_tlb_pte_flags = pte;
3278	}
3279	}
3280	else // remote access
3281	{
3282	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3283	{
3284	pt_updt = true;
3285	r_dcache_vci_cas_old = pte;
3286	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3287	pte = pte \| PTE_R_MASK;
3288	r_dcache_tlb_pte_flags = pte;
3289	}
3290	}
3291
3292	if (not pt_updt) // update TLB and return
3293	{
3294	if (r_dcache_tlb_ins.read())
3295	{
3296	r_itlb.write(true, // 2M page
3297	pte,
3298	0, // argument unused for a PTE1
3299	r_dcache_tlb_vaddr.read(),
3300	r_dcache_tlb_way.read(),
3301	r_dcache_tlb_set.read(),
3302	nline);
3303	#ifdef INSTRUMENTATION
3304	m_cpt_itlb_write++;
3305	#endif
3306
3307	#if DEBUG_DCACHE
3308	if (m_debug_dcache_fsm)
3309	{
3310	std::cout << " <PROC " << name()
3311	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3312	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3313	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3314	r_itlb.printTrace();
3315	}
3316	#endif
3317	}
3318	else
3319	{
3320	r_dtlb.write(true, // 2M page
3321	pte,
3322	0, // argument unused for a PTE1
3323	r_dcache_tlb_vaddr.read(),
3324	r_dcache_tlb_way.read(),
3325	r_dcache_tlb_set.read(),
3326	nline);
3327	#ifdef INSTRUMENTATION
3328	m_cpt_dtlb_write++;
3329	#endif
3330
3331	#if DEBUG_DCACHE
3332	if (m_debug_dcache_fsm)
3333	{
3334	std::cout << " <PROC " << name()
3335	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3336	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3337	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3338	r_dtlb.printTrace();
3339	}
3340	#endif
3341	}
3342	r_dcache_fsm = DCACHE_TLB_RETURN;
3343	}
3344	else // update page table but not TLB
3345	{
3346	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3347
3348	#if DEBUG_DCACHE
3349	if (m_debug_dcache_fsm)
3350	{
3351	std::cout << " <PROC " << name()
3352	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3353	<< std::endl;
3354	}
3355	#endif
3356	}
3357	break;
3358	}
3359	/////////////////////////
3360	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3361	{
3362	// coherence clack request (from DSPIN CLACK)
3363	if (r_dcache_clack_req.read())
3364	{
3365	r_dcache_fsm = DCACHE_CC_CHECK;
3366	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3367	break;
3368	}
3369
3370	// coherence request (from CC_RECEIVE FSM)
3371	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3372	{
3373	r_dcache_fsm = DCACHE_CC_CHECK;
3374	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3375	break;
3376	}
3377
3378	uint32_t pte_flags;
3379	uint32_t pte_ppn;
3380	size_t way;
3381	size_t set;
3382	size_t word;
3383	int cache_state;
3384
3385	r_dcache.read(r_dcache_tlb_paddr.read(),
3386	&pte_flags,
3387	&pte_ppn,
3388	&way,
3389	&set,
3390	&word,
3391	&cache_state);
3392	#ifdef INSTRUMENTATION
3393	m_cpt_dcache_data_read++;
3394	m_cpt_dcache_dir_read++;
3395	#endif
3396	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3397	{
3398	if (not (pte_flags & PTE_V_MASK)) // unmapped
3399	{
3400	if (r_dcache_tlb_ins.read())
3401	{
3402	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3403	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3404	r_icache_tlb_miss_req = false;
3405	r_icache_tlb_rsp_error = true;
3406	}
3407	else
3408	{
3409	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3410	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3411	m_drsp.valid = true;
3412	m_drsp.error = true;
3413	}
3414	r_dcache_fsm = DCACHE_IDLE;
3415
3416	#if DEBUG_DCACHE
3417	if (m_debug_dcache_fsm)
3418	{
3419	std::cout << " <PROC " << name()
3420	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3421	<< " PTE_FLAGS = " << std::hex << pte_flags
3422	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3423	}
3424	#endif
3425	}
3426	else // mapped : we must update the TLB
3427	{
3428	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
3429	r_dcache_tlb_pte_flags = pte_flags;
3430	r_dcache_tlb_pte_ppn = pte_ppn;
3431	r_dcache_tlb_cache_way = way;
3432	r_dcache_tlb_cache_set = set;
3433	r_dcache_tlb_cache_word = word;
3434	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3435
3436	#if DEBUG_DCACHE
3437	if (m_debug_dcache_fsm)
3438	{
3439	std::cout << " <PROC " << name()
3440	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3441	<< " PTE_FLAGS = " << std::hex << pte_flags
3442	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3443	}
3444	#endif
3445	}
3446	}
3447	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3448	{
3449	// stalled until cleanup is acknowledged
3450	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3451
3452	#if DEBUG_DCACHE
3453	if (m_debug_dcache_fsm)
3454	{
3455	std::cout << " <PROC " << name()
3456	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3457	<< std::endl;
3458	}
3459	#endif
3460	}
3461	else // we must load the missing cache line in dcache
3462	{
3463	r_dcache_fsm = DCACHE_MISS_SELECT;
3464	r_dcache_vci_miss_req = true;
3465	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3466	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3467	r_dcache_miss_type = PTE2_MISS;
3468
3469	#if DEBUG_DCACHE
3470	if (m_debug_dcache_fsm)
3471	{
3472	std::cout << " <PROC " << name()
3473	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3474	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3475	}
3476	#endif
3477	}
3478	break;
3479	}
3480	////////////////////////////
3481	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3482	{
3483	size_t way;
3484	size_t set;
3485
3486	if (r_dcache_tlb_ins.read())
3487	{
3488	r_itlb.select(r_dcache_tlb_vaddr.read(),
3489	false, // PTE2
3490	&way,
3491	&set);
3492	#ifdef INSTRUMENTATION
3493	m_cpt_itlb_read++;
3494	#endif
3495	}
3496	else
3497	{
3498	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3499	false, // PTE2
3500	&way,
3501	&set);
3502	#ifdef INSTRUMENTATION
3503	m_cpt_dtlb_read++;
3504	#endif
3505	}
3506
3507	#if DEBUG_DCACHE
3508	if (m_debug_dcache_fsm)
3509	{
3510	if (r_dcache_tlb_ins.read())
3511	std::cout << " <PROC " << name()
3512	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3513	else
3514	std::cout << " <PROC " << name()
3515	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3516	std::cout << " way = " << std::dec << way
3517	<< " / set = " << set << std::endl;
3518	}
3519	#endif
3520	r_dcache_tlb_way = way;
3521	r_dcache_tlb_set = set;
3522	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3523	break;
3524	}
3525	//////////////////////////
3526	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3527	// - if L/R bit already set, exit the sub-fsm.
3528	// - if not, we update the page table but we dont write
3529	// neither in DCACHE, nor in TLB, as this will be done by
3530	// the coherence mechanism.
3531	{
3532	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3533	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3534	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3535	bool pt_updt = false;
3536	bool local = true;
3537
3538	// We should compute the access locality:
3539	// The PPN MSB bits define the destination cluster index.
3540	// The m_srcid MSB bits define the source cluster index.
3541	// The number of bits to compare depends on the number of clusters,
3542	// and can be obtained in the mapping table.
3543	// As long as this computation is not done, all access are local.
3544
3545	if (local) // local access
3546	{
3547	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3548	{
3549	pt_updt = true;
3550	r_dcache_vci_cas_old = pte_flags;
3551	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3552	pte_flags = pte_flags \| PTE_L_MASK;
3553	r_dcache_tlb_pte_flags = pte_flags;
3554	}
3555	}
3556	else // remote access
3557	{
3558	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3559	{
3560	pt_updt = true;
3561	r_dcache_vci_cas_old = pte_flags;
3562	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3563	pte_flags = pte_flags \| PTE_R_MASK;
3564	r_dcache_tlb_pte_flags = pte_flags;
3565	}
3566	}
3567
3568	if (not pt_updt) // update TLB
3569	{
3570	if (r_dcache_tlb_ins.read())
3571	{
3572	r_itlb.write( false, // 4K page
3573	pte_flags,
3574	pte_ppn,
3575	r_dcache_tlb_vaddr.read(),
3576	r_dcache_tlb_way.read(),
3577	r_dcache_tlb_set.read(),
3578	nline );
3579	#ifdef INSTRUMENTATION
3580	m_cpt_itlb_write++;
3581	#endif
3582
3583	#if DEBUG_DCACHE
3584	if (m_debug_dcache_fsm)
3585	{
3586	std::cout << " <PROC " << name()
3587	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3588	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3589	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3590	r_itlb.printTrace();
3591	}
3592	#endif
3593	}
3594	else
3595	{
3596	r_dtlb.write(false, // 4K page
3597	pte_flags,
3598	pte_ppn,
3599	r_dcache_tlb_vaddr.read(),
3600	r_dcache_tlb_way.read(),
3601	r_dcache_tlb_set.read(),
3602	nline);
3603	#ifdef INSTRUMENTATION
3604	m_cpt_dtlb_write++;
3605	#endif
3606
3607	#if DEBUG_DCACHE
3608	if (m_debug_dcache_fsm)
3609	{
3610	std::cout << " <PROC " << name()
3611	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3612	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3613	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3614	r_dtlb.printTrace();
3615	}
3616	#endif
3617
3618	}
3619	r_dcache_fsm = DCACHE_TLB_RETURN;
3620	}
3621	else // update page table but not TLB
3622	{
3623	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3624
3625	#if DEBUG_DCACHE
3626	if (m_debug_dcache_fsm)
3627	{
3628	std::cout << " <PROC " << name()
3629	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3630	}
3631	#endif
3632	}
3633	break;
3634	}
3635	////////////////////////
3636	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3637	{
3638	#if DEBUG_DCACHE
3639	if (m_debug_dcache_fsm)
3640	{
3641	std::cout << " <PROC " << name()
3642	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3643	}
3644	#endif
3645	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3646	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3647
3648	// checking llsc reservation buffer
3649	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
3650	r_dcache_llsc_valid = false;
3651
3652	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3653	r_dcache_vci_cas_req = true;
3654	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3655	break;
3656	}
3657	////////////////////////
3658	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3659	// We consume the response in rsp FIFO,
3660	// and exit the sub-fsm, but we don't
3661	// analyse the response, because we don't
3662	// care if the L/R bit update is not done.
3663	// We must take the coherence requests because
3664	// there is a risk of dead-lock
3665
3666	{
3667	// coherence clack request (from DSPIN CLACK)
3668	if (r_dcache_clack_req.read())
3669	{
3670	r_dcache_fsm = DCACHE_CC_CHECK;
3671	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3672	break;
3673	}
3674
3675	// coherence request (from CC_RECEIVE FSM)
3676	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3677	{
3678	r_dcache_fsm = DCACHE_CC_CHECK;
3679	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3680	break;
3681	}
3682
3683	if (r_vci_rsp_data_error.read()) // bus error
3684	{
3685	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3686	std::cout << "This should not happen in this state" << std::endl;
3687	exit(0);
3688	}
3689	else if (r_vci_rsp_fifo_dcache.rok()) // response available
3690	{
3691	#if DEBUG_DCACHE
3692	if (m_debug_dcache_fsm)
3693	{
3694	std::cout << " <PROC " << name()
3695	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3696	}
3697	#endif
3698	vci_rsp_fifo_dcache_get = true;
3699	r_dcache_fsm = DCACHE_TLB_RETURN;
3700	}
3701	break;
3702	}
3703	///////////////////////
3704	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3705	{
3706	#if DEBUG_DCACHE
3707	if (m_debug_dcache_fsm)
3708	{
3709	std::cout << " <PROC " << name()
3710	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3711	}
3712	#endif
3713	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
3714	r_dcache_fsm = DCACHE_IDLE;
3715	break;
3716	}
3717	///////////////////////
3718	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3719	// and both itlb and dtlb must be flushed.
3720	// Caution : the itlb miss requests must be taken
3721	// to avoid dead-lock in case of simultaneous ITLB miss
3722	// Caution : the clack and cc requests must be taken
3723	// to avoid dead-lock
3724	{
3725	// coherence clack request (from DSPIN CLACK)
3726	if (r_dcache_clack_req.read())
3727	{
3728	r_dcache_fsm = DCACHE_CC_CHECK;
3729	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3730	break;
3731	}
3732
3733	// coherence request (from CC_RECEIVE FSM)
3734	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3735	{
3736	r_dcache_fsm = DCACHE_CC_CHECK;
3737	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3738	break;
3739	}
3740
3741	// itlb miss request
3742	if (r_icache_tlb_miss_req.read())
3743	{
3744	r_dcache_tlb_ins = true;
3745	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3746	r_dcache_fsm = DCACHE_TLB_MISS;
3747	break;
3748	}
3749
3750	if (not r_dcache_xtn_req.read())
3751	{
3752	r_dtlb.flush();
3753	r_mmu_ptpr = m_dreq.wdata;
3754	r_dcache_fsm = DCACHE_IDLE;
3755	m_drsp.valid = true;
3756	}
3757	break;
3758	}
3759	/////////////////////
3760	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3761	// The coherence request must be taken
3762	// as there is a risk of dead-lock
3763	{
3764	// coherence clack request (from DSPIN CLACK)
3765	if (r_dcache_clack_req.read())
3766	{
3767	r_dcache_fsm = DCACHE_CC_CHECK;
3768	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3769	break;
3770	}
3771
3772	// coherence request (from CC_RECEIVE FSM)
3773	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3774	{
3775	r_dcache_fsm = DCACHE_CC_CHECK;
3776	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3777	break;
3778	}
3779
3780	if (r_wbuf.empty())
3781	{
3782	m_drsp.valid = true;
3783	r_dcache_fsm = DCACHE_IDLE;
3784	}
3785	break;
3786	}
3787	////////////////////////
3788	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3789	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3790	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3791	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
3792	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
3793
3794	{
3795	// coherence clack request (from DSPIN CLACK)
3796	if (r_dcache_clack_req.read())
3797	{
3798	r_dcache_fsm = DCACHE_CC_CHECK;
3799	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3800	break;
3801	}
3802
3803	// coherence request (from CC_RECEIVE FSM)
3804	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3805	{
3806	r_dcache_fsm = DCACHE_CC_CHECK;
3807	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3808	break;
3809	}
3810
3811	// itlb miss request
3812	if (r_icache_tlb_miss_req.read())
3813	{
3814	r_dcache_tlb_ins = true;
3815	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3816	r_dcache_fsm = DCACHE_TLB_MISS;
3817	break;
3818	}
3819
3820	// test if XTN request to icache completed
3821	if (not r_dcache_xtn_req.read())
3822	{
3823	r_dcache_fsm = DCACHE_IDLE;
3824	m_drsp.valid = true;
3825	}
3826	break;
3827	}
3828	/////////////////////////
3829	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3830	// r_dcache_flush_count as a slot counter,
3831	// looping in this state until all slots have been visited.
3832	// It can require two cycles per slot:
3833	// We test here the slot state, and make the actual inval
3834	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3835	// A cleanup request is generated for each valid line.
3836	// returns to IDLE and flush TLBs when last slot
3837	{
3838	// coherence clack request (from DSPIN CLACK)
3839	if (r_dcache_clack_req.read())
3840	{
3841	r_dcache_fsm = DCACHE_CC_CHECK;
3842	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3843	break;
3844	}
3845
3846	// coherence request (from CC_RECEIVE FSM)
3847	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3848	{
3849	r_dcache_fsm = DCACHE_CC_CHECK;
3850	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3851	break;
3852	}
3853
3854	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
3855	{
3856	int state;
3857	paddr_t tag;
3858	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
3859	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
3860
3861	#ifdef INSTRUMENTATION
3862	m_cpt_dcache_dir_read++;
3863	#endif
3864	r_dcache.read_dir(way,
3865	set,
3866	&tag,
3867	&state);
3868
3869	if (state == CACHE_SLOT_STATE_VALID) // inval required
3870	{
3871	// request cleanup
3872	r_dcache_cc_send_req = true;
3873	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3874	r_dcache_cc_send_way = way;
3875	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3876
3877	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3878	r_dcache_miss_way = way;
3879	r_dcache_miss_set = set;
3880	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3881	}
3882	else if (r_dcache_flush_count.read() ==
3883	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3884	{
3885	r_dtlb.reset();
3886	r_itlb.reset();
3887	r_dcache_fsm = DCACHE_IDLE;
3888	m_drsp.valid = true;
3889	}
3890
3891	// saturation counter
3892	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
3893	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3894	}
3895	break;
3896	}
3897	////////////////////////////
3898	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3899	// and reset directory extension.
3900	// returns to IDLE and flush TLBs when last slot
3901	{
3902	size_t way = r_dcache_miss_way.read();
3903	size_t set = r_dcache_miss_set.read();
3904
3905	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
3906	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
3907
3908	#ifdef INSTRUMENTATION
3909	m_cpt_dcache_dir_write++;
3910	#endif
3911	r_dcache.write_dir(way,
3912	set,
3913	CACHE_SLOT_STATE_ZOMBI);
3914
3915	if (r_dcache_flush_count.read() ==
3916	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3917	{
3918	r_dtlb.reset();
3919	r_itlb.reset();
3920	r_dcache_fsm = DCACHE_IDLE;
3921	m_drsp.valid = true;
3922	}
3923	else
3924	{
3925	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3926	}
3927	break;
3928	}
3929	/////////////////////////
3930	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3931	{
3932	r_dtlb.inval(r_dcache_save_wdata.read());
3933	r_dcache_fsm = DCACHE_IDLE;
3934	m_drsp.valid = true;
3935	break;
3936	}
3937	////////////////////////////
3938	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3939	// requires 3 cycles: access tlb, read cache, inval cache
3940	// we compute the physical address in this state
3941	{
3942	paddr_t paddr;
3943	bool hit;
3944
3945	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
3946	{
3947
3948	#ifdef INSTRUMENTATION
3949	m_cpt_dtlb_read++;
3950	#endif
3951	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
3952	&paddr);
3953	}
3954	else // dtlb not activated
3955	{
3956	paddr = (paddr_t)r_dcache_save_wdata.read();
3957	if (vci_param::N > 32)
3958	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
3959	hit = true;
3960	}
3961
3962	if (hit) // tlb hit
3963	{
3964	r_dcache_save_paddr = paddr;
3965	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3966	}
3967	else // tlb miss
3968	{
3969
3970	#ifdef INSTRUMENTATION
3971	m_cpt_dtlb_miss++;
3972	#endif
3973	r_dcache_tlb_ins = false; // dtlb
3974	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3975	r_dcache_fsm = DCACHE_TLB_MISS;
3976	}
3977
3978	#if DEBUG_DCACHE
3979	if (m_debug_dcache_fsm)
3980	{
3981	std::cout << " <PROC " << name()
3982	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3983	<< " / VADDR = " << r_dcache_save_wdata.read()
3984	<< " / PADDR = " << paddr << std::endl;
3985	}
3986	#endif
3987
3988	break;
3989	}
3990	////////////////////////////
3991	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3992	// requires 2 cycles: read cache / inval cache
3993	// In this state we read dcache.
3994	{
3995	size_t way;
3996	size_t set;
3997	size_t word;
3998	int state;
3999
4000	#ifdef INSTRUMENTATION
4001	m_cpt_dcache_dir_read++;
4002	#endif
4003	r_dcache.read_dir(r_dcache_save_paddr.read(),
4004	&state,
4005	&way,
4006	&set,
4007	&word);
4008
4009	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
4010	{
4011	r_dcache_xtn_way = way;
4012	r_dcache_xtn_set = set;
4013	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
4014	}
4015	else // miss : nothing to do
4016	{
4017	r_dcache_fsm = DCACHE_IDLE;
4018	m_drsp.valid = true;
4019	}
4020
4021	#if DEBUG_DCACHE
4022	if (m_debug_dcache_fsm)
4023	{
4024	std::cout << " <PROC " << name()
4025	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
4026	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
4027	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
4028	<< " / SET = " << set
4029	<< " / WAY = " << way << std::endl;
4030	}
4031	#endif
4032	break;
4033	}
4034	////////////////////////////
4035	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
4036	// Blocked if previous cleanup not completed
4037	// Test if itlb or dtlb inval is required
4038	{
4039	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
4040	{
4041	size_t way = r_dcache_xtn_way.read();
4042	size_t set = r_dcache_xtn_set.read();
4043	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4044
4045	#ifdef INSTRUMENTATION
4046	m_cpt_dcache_dir_write++;
4047	#endif
4048	r_dcache.write_dir(way,
4049	set,
4050	CACHE_SLOT_STATE_ZOMBI);
4051
4052	// request cleanup
4053	r_dcache_cc_send_req = true;
4054	r_dcache_cc_send_nline = nline;
4055	r_dcache_cc_send_way = way;
4056	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4057
4058	// possible itlb & dtlb invalidate
4059	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4060	{
4061	r_dcache_tlb_inval_line = nline;
4062	r_dcache_tlb_inval_set = 0;
4063	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
4064	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4065	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4066	}
4067	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4068	{
4069	r_itlb.reset();
4070	r_dtlb.reset();
4071	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4072	r_dcache_fsm = DCACHE_IDLE;
4073	m_drsp.valid = true;
4074	}
4075	else
4076	{
4077	r_dcache_fsm = DCACHE_IDLE;
4078	m_drsp.valid = true;
4079	}
4080
4081	#if DEBUG_DCACHE
4082	if (m_debug_dcache_fsm)
4083	{
4084	std::cout << " <PROC " << name()
4085	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
4086	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
4087	}
4088	#endif
4089	}
4090	break;
4091	}
4092	//////////////////////////////
4093	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
4094	{
4095	r_dcache_fsm = DCACHE_IDLE;
4096	m_drsp.valid = true;
4097	break;
4098	}
4099	////////////////////////
4100	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
4101	// Waiting in this state if no slot available.
4102	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
4103	// we send the cleanup request in this state.
4104	// If not, a r_icache_cleanup_victim_req flip-flop is
4105	// utilized for saving this cleanup request, and it will be sent later
4106	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
4107	// The r_icache_miss_clack flip-flop is set
4108	// when a cleanup is required
4109	{
4110	if (m_dreq.valid) m_cost_data_miss_frz++;
4111
4112	// coherence clack request (from DSPIN CLACK)
4113	if (r_dcache_clack_req.read())
4114	{
4115	r_dcache_fsm = DCACHE_CC_CHECK;
4116	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4117	break;
4118	}
4119
4120	// coherence request (from CC_RECEIVE FSM)
4121	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4122	{
4123	r_dcache_fsm = DCACHE_CC_CHECK;
4124	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4125	break;
4126	}
4127
4128	bool found = false;
4129	bool cleanup = false;
4130	size_t way = 0;
4131	size_t set = 0;
4132	paddr_t victim = 0;
4133
4134	#ifdef INSTRUMENTATION
4135	m_cpt_dcache_dir_read++;
4136	#endif
4137	r_dcache.read_select(r_dcache_save_paddr.read(),
4138	&victim,
4139	&way,
4140	&set,
4141	&found,
4142	&cleanup);
4143
4144	if (not found)
4145	{
4146	break;
4147	}
4148	else
4149	{
4150	r_dcache_miss_way = way;
4151	r_dcache_miss_set = set;
4152
4153	if (cleanup)
4154	{
4155	if (not r_dcache_cc_send_req.read())
4156	{
4157	r_dcache_cc_send_req = true;
4158	r_dcache_cc_send_nline = victim;
4159	r_dcache_cc_send_way = way;
4160	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4161
4162	}
4163	else
4164	{
4165	r_dcache_cleanup_victim_req = true;
4166	r_dcache_cleanup_victim_nline = victim;
4167	}
4168
4169	r_dcache_miss_clack = true;
4170	r_dcache_fsm = DCACHE_MISS_CLEAN;
4171	}
4172	else
4173	{
4174	r_dcache_fsm = DCACHE_MISS_WAIT;
4175	}
4176
4177	#if DEBUG_DCACHE
4178	if (m_debug_dcache_fsm)
4179	{
4180	std::cout << " <PROC " << name()
4181	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4182	<< " / WAY = " << way
4183	<< " / SET = " << set
4184	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4185	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4186	else std::cout << std::endl;
4187	}
4188	#endif
4189	} // end found
4190	break;
4191	}
4192	///////////////////////
4193	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4194	// and possibly request itlb or dtlb invalidate
4195	{
4196	if (m_dreq.valid) m_cost_data_miss_frz++;
4197
4198	size_t way = r_dcache_miss_way.read();
4199	size_t set = r_dcache_miss_set.read();
4200
4201	#ifdef INSTRUMENTATION
4202	m_cpt_dcache_dir_read++;
4203	#endif
4204	r_dcache.write_dir(way,
4205	set,
4206	CACHE_SLOT_STATE_ZOMBI);
4207	#if DEBUG_DCACHE
4208	if (m_debug_dcache_fsm)
4209	{
4210	std::cout << " <PROC " << name()
4211	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4212	<< " / way = " << way
4213	<< " / set = " << set << std::endl;
4214	}
4215	#endif
4216	// if selective itlb & dtlb invalidate are required
4217	// the miss response is not handled before invalidate completed
4218	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4219	{
4220	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4221
4222	if (not r_dcache_cleanup_victim_req.read())
4223	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
4224	else
4225	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
4226
4227	r_dcache_tlb_inval_set = 0;
4228	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4229	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4230	}
4231	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4232	{
4233	r_itlb.reset();
4234	r_dtlb.reset();
4235	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4236	r_dcache_fsm = DCACHE_MISS_WAIT;
4237	}
4238	else
4239	{
4240	r_dcache_fsm = DCACHE_MISS_WAIT;
4241	}
4242	break;
4243	}
4244	//////////////////////
4245	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4246	// This state is in charge of error signaling
4247	// There is 5 types of error depending on the requester
4248	{
4249	if (m_dreq.valid) m_cost_data_miss_frz++;
4250
4251	// send cleanup victim request
4252	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4253	{
4254	r_dcache_cc_send_req = true;
4255	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4256	r_dcache_cc_send_way = r_dcache_miss_way;
4257	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4258	r_dcache_cleanup_victim_req = false;
4259	}
4260
4261	// coherence clack request (from DSPIN CLACK)
4262	if (r_dcache_clack_req.read())
4263	{
4264	r_dcache_fsm = DCACHE_CC_CHECK;
4265	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4266	break;
4267	}
4268
4269	// coherence request (from CC_RECEIVE FSM)
4270	if (r_cc_receive_dcache_req.read() and
4271	not r_dcache_cc_send_req.read() and
4272	not r_dcache_cleanup_victim_req.read())
4273	{
4274	r_dcache_fsm = DCACHE_CC_CHECK;
4275	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4276	break;
4277	}
4278
4279	if (r_vci_rsp_data_error.read()) // bus error
4280	{
4281	switch (r_dcache_miss_type.read())
4282	{
4283	case PROC_MISS:
4284	{
4285	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4286	r_mmu_dbvar = r_dcache_save_vaddr.read();
4287	m_drsp.valid = true;
4288	m_drsp.error = true;
4289	r_dcache_fsm = DCACHE_IDLE;
4290	break;
4291	}
4292	case PTE1_MISS:
4293	{
4294	if (r_dcache_tlb_ins.read())
4295	{
4296	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4297	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4298	r_icache_tlb_miss_req = false;
4299	r_icache_tlb_rsp_error = true;
4300	}
4301	else
4302	{
4303	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4304	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4305	m_drsp.valid = true;
4306	m_drsp.error = true;
4307	}
4308	r_dcache_fsm = DCACHE_IDLE;
4309	break;
4310	}
4311	case PTE2_MISS:
4312	{
4313	if (r_dcache_tlb_ins.read())
4314	{
4315	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4316	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4317	r_icache_tlb_miss_req = false;
4318	r_icache_tlb_rsp_error = true;
4319	}
4320	else
4321	{
4322	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4323	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4324	m_drsp.valid = true;
4325	m_drsp.error = true;
4326	}
4327	r_dcache_fsm = DCACHE_IDLE;
4328	break;
4329	}
4330	} // end switch type
4331	r_vci_rsp_data_error = false;
4332	}
4333	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
4334	{
4335	r_dcache_miss_word = 0;
4336	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4337	}
4338	break;
4339	}
4340	//////////////////////////
4341	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4342	{
4343	if (m_dreq.valid) m_cost_data_miss_frz++;
4344
4345	if (r_vci_rsp_fifo_dcache.rok()) // one word available
4346	{
4347	#ifdef INSTRUMENTATION
4348	m_cpt_dcache_data_write++;
4349	#endif
4350	r_dcache.write(r_dcache_miss_way.read(),
4351	r_dcache_miss_set.read(),
4352	r_dcache_miss_word.read(),
4353	r_vci_rsp_fifo_dcache.read());
4354	#if DEBUG_DCACHE
4355	if (m_debug_dcache_fsm)
4356	{
4357	std::cout << " <PROC " << name()
4358	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4359	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4360	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4361	<< " / SET = " << r_dcache_miss_set.read()
4362	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4363	}
4364	#endif
4365	vci_rsp_fifo_dcache_get = true;
4366	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4367
4368	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
4369	{
4370	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4371	}
4372	}
4373	break;
4374	}
4375	//////////////////////////
4376	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4377	// and the cleanup ack has not been received,
4378	// as indicated by the r_dcache_miss clack.
4379	// - If no matching coherence request (r_dcache_inval_miss)
4380	// switch directory slot to VALID state.
4381	// - If matching coherence request, switch directory slot
4382	// to ZOMBI state, and send a cleanup request.
4383	{
4384	if (m_dreq.valid) m_cost_data_miss_frz++;
4385
4386	// send cleanup victim request
4387	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4388	{
4389	r_dcache_cc_send_req = true;
4390	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4391	r_dcache_cc_send_way = r_dcache_miss_way;
4392	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4393	r_dcache_cleanup_victim_req = false;
4394	}
4395
4396	// coherence clack request (from DSPIN CLACK)
4397	if (r_dcache_clack_req.read())
4398	{
4399	r_dcache_fsm = DCACHE_CC_CHECK;
4400	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4401	break;
4402	}
4403
4404	// coherence request (from CC_RECEIVE FSM)
4405	if (r_cc_receive_dcache_req.read() and
4406	not r_dcache_cc_send_req.read() and
4407	not r_dcache_cleanup_victim_req.read())
4408	{
4409	r_dcache_fsm = DCACHE_CC_CHECK;
4410	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4411	break;
4412	}
4413
4414	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
4415	{
4416	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
4417	{
4418	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
4419	{
4420	r_dcache_miss_inval = false;
4421	// request cleanup
4422	r_dcache_cc_send_req = true;
4423	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4424	r_dcache_cc_send_way = r_dcache_miss_way.read();
4425	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4426
4427	#ifdef INSTRUMENTATION
4428	m_cpt_dcache_dir_write++;
4429	#endif
4430	r_dcache.write_dir( r_dcache_save_paddr.read(),
4431	r_dcache_miss_way.read(),
4432	r_dcache_miss_set.read(),
4433	CACHE_SLOT_STATE_ZOMBI );
4434	#if DEBUG_DCACHE
4435	if (m_debug_dcache_fsm)
4436	std::cout << " <PROC " << name()
4437	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4438	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4439	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4440	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4441	#endif
4442	}
4443	else
4444	break;
4445	}
4446	else // switch slot to VALID state
4447	{
4448
4449	#ifdef INSTRUMENTATION
4450	m_cpt_dcache_dir_write++;
4451	#endif
4452	r_dcache.write_dir(r_dcache_save_paddr.read(),
4453	r_dcache_miss_way.read(),
4454	r_dcache_miss_set.read(),
4455	CACHE_SLOT_STATE_VALID);
4456
4457	#if DEBUG_DCACHE
4458	if (m_debug_dcache_fsm)
4459	std::cout << " <PROC " << name()
4460	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4461	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4462	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4463	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4464	#endif
4465	// reset directory extension
4466	size_t way = r_dcache_miss_way.read();
4467	size_t set = r_dcache_miss_set.read();
4468	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4469	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4470	}
4471	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4472	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4473	else r_dcache_fsm = DCACHE_IDLE;
4474	}
4475	break;
4476	}
4477	/////////////////////
4478	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
4479	{
4480	// coherence clack request (from DSPIN CLACK)
4481	if (r_dcache_clack_req.read())
4482	{
4483	r_dcache_fsm = DCACHE_CC_CHECK;
4484	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4485	break;
4486	}
4487
4488	// coherence request (from CC_RECEIVE FSM)
4489	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4490	{
4491	r_dcache_fsm = DCACHE_CC_CHECK;
4492	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4493	break;
4494	}
4495
4496	if (r_vci_rsp_data_error.read()) // bus error
4497	{
4498	if (r_dcache_vci_unc_write.read())
4499	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
4500	else
4501	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4502
4503	r_mmu_dbvar = m_dreq.addr;
4504	r_vci_rsp_data_error = false;
4505	m_drsp.error = true;
4506	m_drsp.valid = true;
4507	r_dcache_fsm = DCACHE_IDLE;
4508	break;
4509	}
4510	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4511	{
4512	// consume data
4513	vci_rsp_fifo_dcache_get = true;
4514	r_dcache_fsm = DCACHE_IDLE;
4515
4516	// acknowledge the processor request if it has not been modified
4517	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4518	{
4519	m_drsp.valid = true;
4520	m_drsp.error = false;
4521	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4522	}
4523	}
4524	break;
4525	}
4526	/////////////////////
4527	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4528	{
4529	// coherence clack request (from DSPIN CLACK)
4530	if (r_dcache_clack_req.read())
4531	{
4532	r_dcache_fsm = DCACHE_CC_CHECK;
4533	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4534	break;
4535	}
4536
4537	// coherence request (from CC_RECEIVE FSM)
4538	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4539	{
4540	r_dcache_fsm = DCACHE_CC_CHECK;
4541	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4542	break;
4543	}
4544
4545	if (r_vci_rsp_data_error.read()) // bus error
4546	{
4547	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4548	r_mmu_dbvar = m_dreq.addr;
4549	r_vci_rsp_data_error = false;
4550	m_drsp.error = true;
4551	m_drsp.valid = true;
4552	r_dcache_fsm = DCACHE_IDLE;
4553	break;
4554	}
4555	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4556	{
4557	// consume data
4558	vci_rsp_fifo_dcache_get = true;
4559
4560	if (r_dcache_ll_rsp_count.read() == 0) // first flit
4561	{
4562	// set key value in llsc reservation buffer
4563	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4564	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
4565	}
4566	else // last flit
4567	{
4568	// acknowledge the processor request if it has not been modified
4569	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4570	{
4571	m_drsp.valid = true;
4572	m_drsp.error = false;
4573	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4574	}
4575	r_dcache_fsm = DCACHE_IDLE;
4576	}
4577	}
4578	break;
4579	}
4580	////////////////////
4581	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4582	{
4583	// coherence clack request (from DSPIN CLACK)
4584	if (r_dcache_clack_req.read())
4585	{
4586	r_dcache_fsm = DCACHE_CC_CHECK;
4587	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4588	break;
4589	}
4590
4591	// coherence request (from CC_RECEIVE FSM)
4592	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4593	{
4594	r_dcache_fsm = DCACHE_CC_CHECK;
4595	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4596	break;
4597	}
4598
4599	if (r_vci_rsp_data_error.read()) // bus error
4600	{
4601	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4602	r_mmu_dbvar = m_dreq.addr;
4603	r_vci_rsp_data_error = false;
4604	m_drsp.error = true;
4605	m_drsp.valid = true;
4606	r_dcache_fsm = DCACHE_IDLE;
4607	break;
4608	}
4609	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4610	{
4611	// consume response
4612	vci_rsp_fifo_dcache_get = true;
4613	m_drsp.valid = true;
4614	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4615	r_dcache_fsm = DCACHE_IDLE;
4616	}
4617	break;
4618	}
4619	//////////////////////////
4620	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4621	// before handling a processor WRITE or SC request
4622	// Input argument is r_dcache_dirty_paddr
4623	// In this first state, we get PTE value in dcache
4624	// and post a CAS request to CMD FSM
4625	{
4626	// get PTE in dcache
4627	uint32_t pte;
4628	size_t way;
4629	size_t set;
4630	size_t word; // unused
4631	int state;
4632
4633	#ifdef INSTRUMENTATION
4634	m_cpt_dcache_data_read++;
4635	m_cpt_dcache_dir_read++;
4636	#endif
4637	r_dcache.read(r_dcache_dirty_paddr.read(),
4638	&pte,
4639	&way,
4640	&set,
4641	&word,
4642	&state);
4643
4644	assert( (state == CACHE_SLOT_STATE_VALID) and
4645	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4646
4647	// request CAS transaction to CMD_FSM
4648	r_dcache_dirty_way = way;
4649	r_dcache_dirty_set = set;
4650
4651	// check llsc reservation buffer
4652	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
4653	r_dcache_llsc_valid = false;
4654
4655	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4656	r_dcache_vci_cas_req = true;
4657	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4658	r_dcache_vci_cas_old = pte;
4659	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4660	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4661
4662	#if DEBUG_DCACHE
4663	if (m_debug_dcache_fsm)
4664	{
4665	std::cout << " <PROC " << name()
4666	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4667	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4668	<< " / PTE_VALUE = " << pte << std::dec
4669	<< " / SET = " << set
4670	<< " / WAY = " << way << std::endl;
4671	}
4672	#endif
4673	break;
4674	}
4675	///////////////////////
4676	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4677	// and return to IDLE state when response is received.
4678	// we don't care if the CAS is a failure:
4679	// - if the CAS is a success, the coherence mechanism
4680	// updates the local copy.
4681	// - if the CAS is a failure, we just retry the write.
4682	{
4683	// coherence clack request (from DSPIN CLACK)
4684	if (r_dcache_clack_req.read())
4685	{
4686	r_dcache_fsm = DCACHE_CC_CHECK;
4687	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4688	break;
4689	}
4690
4691	// coherence request (from CC_RECEIVE FSM)
4692	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4693	{
4694	r_dcache_fsm = DCACHE_CC_CHECK;
4695	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4696	break;
4697	}
4698
4699	if (r_vci_rsp_data_error.read()) // bus error
4700	{
4701	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4702	std::cout << "This should not happen in this state" << std::endl;
4703	exit(0);
4704	}
4705	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4706	{
4707	vci_rsp_fifo_dcache_get = true;
4708	r_dcache_fsm = DCACHE_IDLE;
4709
4710	#if DEBUG_DCACHE
4711	if (m_debug_dcache_fsm)
4712	{
4713	std::cout << " <PROC " << name()
4714	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4715	}
4716	#endif
4717	}
4718	break;
4719	}
4720	/////////////////////
4721	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4722	// handling coherence requests for DCACHE.
4723	// If there is a matching pending miss on the modified cache
4724	// line this is signaled in the r_dcache_miss inval flip-flop.
4725	// If the updated (or invalidated) cache line has copies in TLBs
4726	// these TLB copies are invalidated.
4727	// The return state is defined in r_dcache_fsm_cc_save
4728	{
4729	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4730	paddr_t mask = ~((m_dcache_words << 2) - 1);
4731
4732	// CLACK handler
4733	// We switch the directory slot to EMPTY state and reset
4734	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
4735	if (r_dcache_clack_req.read())
4736	{
4737	if (m_dreq.valid ) m_cost_data_miss_frz++;
4738
4739	#ifdef INSTRUMENTATION
4740	m_cpt_dcache_dir_write++;
4741	#endif
4742	r_dcache.write_dir(0,
4743	r_dcache_clack_way.read(),
4744	r_dcache_clack_set.read(),
4745	CACHE_SLOT_STATE_EMPTY);
4746
4747	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4748	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
4749	{
4750	r_dcache_miss_clack = false;
4751	}
4752
4753	r_dcache_clack_req = false;
4754
4755	// return to cc_save state
4756	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4757
4758	#if DEBUG_DCACHE
4759	if (m_debug_dcache_fsm)
4760	{
4761	std::cout << " <PROC " << name()
4762	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
4763	<< " Switch slot to EMPTY state : "
4764	<< " set = " << r_dcache_clack_set.read()
4765	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4766	}
4767	#endif
4768	break;
4769	}
4770
4771	assert(not r_dcache_cc_send_req.read() and
4772	"CC_SEND must be available in DCACHE_CC_CHECK");
4773
4774	// Match between MISS address and CC address
4775	if (r_cc_receive_dcache_req.read() and
4776	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4777	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4778	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4779	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
4780	{
4781	// signaling matching
4782	r_dcache_miss_inval = true;
4783
4784	// in case of update, go to CC_UPDT
4785	// JUST TO POP THE FIFO
4786	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4787	{
4788	r_dcache_fsm = DCACHE_CC_UPDT;
4789	r_dcache_cc_word = r_cc_receive_word_idx.read();
4790
4791	// just pop the fifo , don't write in icache
4792	r_dcache_cc_need_write = false;
4793	}
4794	// the request is dealt with
4795	else
4796	{
4797	r_cc_receive_dcache_req = false;
4798	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4799	}
4800
4801	#if DEBUG_DCACHE
4802	if (m_debug_dcache_fsm)
4803	{
4804	std::cout << " <PROC " << name()
4805	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4806	<< " PADDR = " << std::hex << paddr << std::endl;
4807	}
4808	#endif
4809	}
4810
4811	// CC request handler
4812
4813	int state = 0;
4814	size_t way = 0;
4815	size_t set = 0;
4816	size_t word = 0;
4817
4818	#ifdef INSTRUMENTATION
4819	m_cpt_dcache_dir_read++;
4820	#endif
4821	r_dcache.read_dir(paddr,
4822	&state,
4823	&way,
4824	&set,
4825	&word); // unused
4826
4827	r_dcache_cc_way = way;
4828	r_dcache_cc_set = set;
4829
4830	if (state == CACHE_SLOT_STATE_VALID) // hit
4831	{
4832	// need to update the cache state
4833	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4834	{
4835	r_dcache_cc_need_write = true;
4836	r_dcache_fsm = DCACHE_CC_UPDT;
4837	r_dcache_cc_word = r_cc_receive_word_idx.read();
4838	}
4839	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4840	{
4841	r_dcache_fsm = DCACHE_CC_INVAL;
4842	}
4843	}
4844	else // miss
4845	{
4846	// multicast acknowledgement required in case of update
4847	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4848	{
4849	r_dcache_fsm = DCACHE_CC_UPDT;
4850	r_dcache_cc_word = r_cc_receive_word_idx.read();
4851
4852	// just pop the fifo , don't write in icache
4853	r_dcache_cc_need_write = false;
4854	}
4855	else // No response needed
4856	{
4857	r_cc_receive_dcache_req = false;
4858	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4859	}
4860	}
4861
4862	#if DEBUG_DCACHE
4863	if (m_debug_dcache_fsm)
4864	{
4865	std::cout << " <PROC " << name()
4866	<< " DCACHE_CC_CHECK> Coherence request received:"
4867	<< " PADDR = " << std::hex << paddr
4868	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4869	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4870	}
4871	#endif
4872
4873	break;
4874	}
4875	/////////////////////
4876	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
4877	// CLEANUP after possible invalidation of copies in
4878	// TLBs
4879	{
4880	size_t way = r_dcache_cc_way.read();
4881	size_t set = r_dcache_cc_set.read();
4882
4883	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4884	{
4885	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4886	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4887	r_dcache_tlb_inval_set = 0;
4888	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4889	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4890	break;
4891	}
4892
4893	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4894	{
4895	r_itlb.reset();
4896	r_dtlb.reset();
4897	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4898
4899	#if DEBUG_DCACHE
4900	if (m_debug_dcache_fsm)
4901	{
4902	std::cout << " <PROC " << name()
4903	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4904	}
4905	#endif
4906	}
4907
4908	assert(not r_dcache_cc_send_req.read() &&
4909	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4910	"must not be set");
4911
4912	// Switch slot state to ZOMBI and send CLEANUP command
4913	r_dcache.write_dir(way,
4914	set,
4915	CACHE_SLOT_STATE_ZOMBI);
4916
4917	// coherence request completed
4918	r_cc_receive_dcache_req = false;
4919	r_dcache_cc_send_req = true;
4920	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4921	r_dcache_cc_send_way = r_dcache_cc_way.read();
4922	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4923	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4924
4925	#if DEBUG_DCACHE
4926	if (m_debug_dcache_fsm)
4927	{
4928	std::cout << " <PROC " << name()
4929	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4930	<< " / WAY = " << way
4931	<< " / SET = " << set << std::endl;
4932	}
4933	#endif
4934	break;
4935	}
4936	///////////////////
4937	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4938	// after possible invalidation of copies in TLBs
4939	{
4940	size_t word = r_dcache_cc_word.read();
4941	size_t way = r_dcache_cc_way.read();
4942	size_t set = r_dcache_cc_set.read();
4943
4944	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4945	{
4946	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4947	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4948	r_dcache_tlb_inval_set = 0;
4949	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4950	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4951
4952	break;
4953	}
4954
4955	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4956	{
4957	r_itlb.reset();
4958	r_dtlb.reset();
4959	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4960
4961	#if DEBUG_DCACHE
4962	if (m_debug_dcache_fsm)
4963	{
4964	std::cout << " <PROC " << name()
4965	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4966	}
4967	#endif
4968	}
4969
4970	assert (not r_dcache_cc_send_req.read() &&
4971	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4972	"must not be set");
4973
4974	if (not r_cc_receive_updt_fifo_be.rok()) break;
4975
4976	if (r_dcache_cc_need_write.read())
4977	{
4978
4979	#ifdef INSTRUMENTATION
4980	m_cpt_dcache_data_write++;
4981	#endif
4982	r_dcache.write(way,
4983	set,
4984	word,
4985	r_cc_receive_updt_fifo_data.read(),
4986	r_cc_receive_updt_fifo_be.read());
4987
4988	r_dcache_cc_word = word + 1;
4989
4990	#if DEBUG_DCACHE
4991	if (m_debug_dcache_fsm)
4992	{
4993	std::cout << " <PROC " << name()
4994	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4995	<< " / WAY = " << way
4996	<< " / SET = " << set
4997	<< " / WORD = " << word
4998	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4999	}
5000	#endif
5001	}
5002
5003	if (r_cc_receive_updt_fifo_eop.read()) // last word
5004	{
5005	// no need to write in the cache anymore
5006	r_dcache_cc_need_write = false;
5007
5008	// coherence request completed
5009	r_cc_receive_dcache_req = false;
5010
5011	// request multicast acknowledgement
5012	r_dcache_cc_send_req = true;
5013	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5014	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
5015	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
5016	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5017	}
5018
5019	//consume fifo if not eop
5020	cc_receive_updt_fifo_get = true;
5021
5022	break;
5023	}
5024	///////////////////////////
5025	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
5026	// It makes assumption: m_itlb_sets == m_dtlb_sets
5027	// All ways are handled in parallel.
5028	// We enter this state when a DCACHE line is modified,
5029	// and there is a copy in itlb or dtlb.
5030	// It can be caused by:
5031	// - a coherence inval or updt transaction,
5032	// - a line inval caused by a cache miss
5033	// - a processor XTN inval request,
5034	// - a WRITE hit,
5035	// - a Dirty bit update
5036	// Input arguments are:
5037	// - r_dcache_tlb_inval_line
5038	// - r_dcache_tlb_inval_set
5039	// - r_dcache_fsm_scan_save
5040	{
5041	paddr_t line = r_dcache_tlb_inval_line.read();
5042	size_t set = r_dcache_tlb_inval_set.read();
5043	size_t way;
5044	bool ok;
5045
5046	for (way = 0; way < m_itlb_ways; way++)
5047	{
5048	ok = r_itlb.inval(line, way, set);
5049
5050	#if DEBUG_DCACHE
5051	if (m_debug_dcache_fsm and ok)
5052	{
5053	std::cout << " <PROC " << name()
5054	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
5055	<< " line = " << line << std::dec
5056	<< " / set = " << set
5057	<< " / way = " << way << std::endl;
5058	}
5059	#endif
5060	}
5061
5062	for (way = 0; way < m_dtlb_ways; way++)
5063	{
5064	ok = r_dtlb.inval( line, way, set);
5065
5066	#if DEBUG_DCACHE
5067	if (m_debug_dcache_fsm and ok)
5068	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
5069	<< " Invalidate DTLB entry" << std::hex
5070	<< " / line = " << line << std::dec
5071	<< " / set = " << set
5072	<< " / way = " << way << std::endl;
5073	#endif
5074	}
5075
5076	// return to the calling state when TLB inval completed
5077	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
5078	{
5079	r_dcache_fsm = r_dcache_fsm_scan_save.read();
5080	}
5081	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
5082	break;
5083	}
5084	} // end switch r_dcache_fsm
5085
5086	///////////////// wbuf update ///////////////////////////////////////////////////////
5087	r_wbuf.update();
5088
5089	///////////////// llsc update ///////////////////////////////////////////////////////
5090	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
5091	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
5092
5093	//////////////// test processor frozen //////////////////////////////////////////////
5094	// The simulation exit if the number of consecutive frozen cycles
5095	// is larger than the m_max_frozen_cycles (constructor parameter)
5096	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
5097	{
5098	m_cpt_frz_cycles++; // used for instrumentation
5099	m_cpt_stop_simulation++; // used for debug
5100	if (m_cpt_stop_simulation > m_max_frozen_cycles)
5101	{
5102	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
5103	<< " stop at cycle " << m_cpt_total_cycles << std::endl
5104	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
5105	<< std::endl;
5106	r_iss.dump();
5107	r_wbuf.printTrace();
5108	raise(SIGINT);
5109	}
5110	}
5111	else
5112	{
5113	m_cpt_stop_simulation = 0;
5114	}
5115
5116	/////////// execute one iss cycle /////////////////////////////////
5117	{
5118	uint32_t it = 0;
5119	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
5120	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
5121	}
5122
5123	////////////////////////////////////////////////////////////////////////////
5124	// The VCI_CMD FSM controls the following ressources:
5125	// - r_vci_cmd_fsm
5126	// - r_vci_cmd_min
5127	// - r_vci_cmd_max
5128	// - r_vci_cmd_cpt
5129	// - r_vci_cmd_imiss_prio
5130	// - wbuf (reset)
5131	// - r_icache_miss_req (reset)
5132	// - r_icache_unc_req (reset)
5133	// - r_dcache_vci_miss_req (reset)
5134	// - r_dcache_vci_unc_req (reset)
5135	// - r_dcache_vci_ll_req (reset)
5136	// - r_dcache_vci_sc_req (reset in case of local sc fail)
5137	// - r_dcache_vci_cas_req (reset)
5138	//
5139	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
5140	// There are 8 request types, with the following priorities :
5141	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
5142	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
5143	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
5144	// 4 - Instruction Uncachable : r_icache_unc_req
5145	// 5 - Data Write : r_wbuf.rok()
5146	// 6 - Data Linked Load : r_dcache_vci_ll_req
5147	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
5148	// 8 - Compare And Swap : r_dcache_vci_cas_req
5149	//
5150	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
5151	// and the VCI_RSP_FSM are fully desynchronized.
5152	//
5153	// VCI formats:
5154	// According to the VCI advanced specification, all read requests packets
5155	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
5156	// are one word packets.
5157	// For write burst packets, all words are in the same cache line,
5158	// and addresses must be contiguous (the BE field is 0 in case of "holes").
5159	// The sc command packet implements actually a compare-and-swap mechanism
5160	// and the packet contains two flits.
5161	////////////////////////////////////////////////////////////////////////////////////
5162
5163
5164	switch (r_vci_cmd_fsm.read())
5165	{
5166	//////////////
5167	case CMD_IDLE:
5168	{
5169	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5170	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5171	// to check a possible pending write on the same cache line.
5172	// As there is only one possible access per cycle to write buffer, we implement
5173	// a round-robin priority between DCACHE and ICACHE for this access,
5174	// using the r_vci_cmd_imiss_prio flip-flop.
5175
5176	size_t wbuf_min;
5177	size_t wbuf_max;
5178
5179	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5180	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5181
5182	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5183	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5184
5185	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
5186	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5187
5188	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
5189	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5190
5191	bool icache_miss_req = r_icache_miss_req.read() and
5192	(not (r_dcache_vci_miss_req.read() or
5193	r_dcache_vci_ll_req.read() or
5194	r_dcache_vci_cas_req.read() or
5195	r_dcache_vci_sc_req.read()) or
5196	r_vci_cmd_imiss_prio.read());
5197
5198	// 1 - Data unc write
5199	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
5200	{
5201	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
5202	r_dcache_vci_unc_req = false;
5203	}
5204	// 2 data read miss
5205	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5206	{
5207	r_vci_cmd_fsm = CMD_DATA_MISS;
5208	r_dcache_vci_miss_req = false;
5209	r_vci_cmd_imiss_prio = true;
5210	}
5211	// 3 - Data Read Uncachable
5212	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
5213	{
5214	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
5215	r_dcache_vci_unc_req = false;
5216	}
5217	// 4 - Data Linked Load
5218	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5219	{
5220	r_vci_cmd_fsm = CMD_DATA_LL;
5221	r_dcache_vci_ll_req = false;
5222	r_vci_cmd_imiss_prio = true;
5223	}
5224	// 5 - Instruction Miss
5225	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
5226	{
5227	r_vci_cmd_fsm = CMD_INS_MISS;
5228	r_icache_miss_req = false;
5229	r_vci_cmd_imiss_prio = false;
5230	}
5231	// 6 - Instruction Uncachable
5232	else if (r_icache_unc_req.read())
5233	{
5234	r_vci_cmd_fsm = CMD_INS_UNC;
5235	r_icache_unc_req = false;
5236	}
5237	// 7 - Data Write
5238	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
5239	{
5240	r_vci_cmd_fsm = CMD_DATA_WRITE;
5241	r_vci_cmd_cpt = wbuf_min;
5242	r_vci_cmd_min = wbuf_min;
5243	r_vci_cmd_max = wbuf_max;
5244	}
5245	// 8 - Data Store Conditionnal
5246	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5247	{
5248	r_vci_cmd_fsm = CMD_DATA_SC;
5249	r_dcache_vci_sc_req = false;
5250	r_vci_cmd_imiss_prio = true;
5251	r_vci_cmd_cpt = 0;
5252	}
5253	// 9 - Compare And Swap
5254	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5255	{
5256	r_vci_cmd_fsm = CMD_DATA_CAS;
5257	r_dcache_vci_cas_req = false;
5258	r_vci_cmd_imiss_prio = true;
5259	r_vci_cmd_cpt = 0;
5260	}
5261
5262	#if DEBUG_CMD
5263	if (m_debug_cmd_fsm )
5264	{
5265	std::cout << " <PROC " << name() << " CMD_IDLE>"
5266	<< " / dmiss_req = " << dcache_miss_req
5267	<< " / imiss_req = " << icache_miss_req
5268	<< std::endl;
5269	}
5270	#endif
5271	break;
5272	}
5273	////////////////////
5274	case CMD_DATA_WRITE:
5275	{
5276	if (p_vci.cmdack.read())
5277	{
5278	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5279	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5280	{
5281	r_vci_cmd_fsm = CMD_IDLE;
5282	r_wbuf.sent();
5283	}
5284	}
5285	break;
5286	}
5287	/////////////////
5288	case CMD_DATA_SC:
5289	case CMD_DATA_CAS:
5290	{
5291	// The CAS and SC VCI commands contain two flits
5292	if (p_vci.cmdack.read())
5293	{
5294	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5295	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5296	}
5297	break;
5298	}
5299	//////////////////
5300	case CMD_INS_MISS:
5301	case CMD_INS_UNC:
5302	case CMD_DATA_MISS:
5303	case CMD_DATA_UNC_READ:
5304	case CMD_DATA_UNC_WRITE:
5305	case CMD_DATA_LL:
5306	{
5307	// all read VCI commands contain one single flit
5308	if (p_vci.cmdack.read()) {
5309	r_vci_cmd_fsm = CMD_IDLE;
5310	}
5311	break;
5312	}
5313
5314	} // end switch r_vci_cmd_fsm
5315
5316	//////////////////////////////////////////////////////////////////////////
5317	// The VCI_RSP FSM controls the following ressources:
5318	// - r_vci_rsp_fsm:
5319	// - r_vci_rsp_fifo_icache (push)
5320	// - r_vci_rsp_fifo_dcache (push)
5321	// - r_vci_rsp_data_error (set)
5322	// - r_vci_rsp_ins_error (set)
5323	// - r_vci_rsp_cpt
5324	// - r_dcache_vci_sc_req (reset when SC response recieved)
5325	//
5326	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5327	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5328	// to identify the transactions.
5329	//
5330	// VCI vormat:
5331	// This component checks the response packet length and accepts only
5332	// single word packets for write response packets.
5333	//
5334	// Error handling:
5335	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5336	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5337	// flip_flop and the error is signaled by the DCACHE FSM.
5338	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5339	// flip_flop and the error is signaled by the ICACHE FSM.
5340	// In case of Cleanup Error, the simulation stops with an error message...
5341	//////////////////////////////////////////////////////////////////////////
5342
5343	switch (r_vci_rsp_fsm.read())
5344	{
5345	//////////////
5346	case RSP_IDLE:
5347	{
5348	if (p_vci.rspval.read())
5349	{
5350	r_vci_rsp_cpt = 0;
5351
5352	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
5353	{
5354	r_vci_rsp_fsm = RSP_DATA_UNC;
5355	}
5356	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
5357	{
5358	r_vci_rsp_fsm = RSP_DATA_MISS;
5359	}
5360	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
5361	{
5362	r_vci_rsp_fsm = RSP_INS_UNC;
5363	}
5364	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
5365	{
5366	r_vci_rsp_fsm = RSP_INS_MISS;
5367	}
5368	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
5369	{
5370	r_vci_rsp_fsm = RSP_DATA_WRITE;
5371	}
5372	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
5373	{
5374	r_vci_rsp_fsm = RSP_DATA_UNC;
5375	}
5376	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
5377	{
5378	r_vci_rsp_fsm = RSP_DATA_LL;
5379	}
5380	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
5381	{
5382	r_vci_rsp_fsm = RSP_DATA_UNC;
5383	}
5384	else
5385	{
5386	assert(false and "Unexpected VCI response");
5387	}
5388	}
5389	break;
5390	}
5391	//////////////////
5392	case RSP_INS_MISS:
5393	{
5394	if (p_vci.rspval.read())
5395	{
5396	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5397	{
5398	r_vci_rsp_ins_error = true;
5399	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5400	}
5401	else // no error reported
5402	{
5403	if (r_vci_rsp_fifo_icache.wok())
5404	{
5405	if (r_vci_rsp_cpt.read() >= m_icache_words)
5406	{
5407	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5408	<< " VCI response packet too long "
5409	<< " for instruction miss" << std::endl;
5410	exit(0);
5411	}
5412	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5413	vci_rsp_fifo_icache_put = true,
5414	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5415	if (p_vci.reop.read())
5416	{
5417	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
5418	{
5419	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5420	<< " VCI response packet too short"
5421	<< " for instruction miss" << std::endl;
5422	exit(0);
5423	}
5424	r_vci_rsp_fsm = RSP_IDLE;
5425	}
5426	}
5427	}
5428	}
5429	break;
5430	}
5431	/////////////////
5432	case RSP_INS_UNC:
5433	{
5434	if (p_vci.rspval.read())
5435	{
5436	assert(p_vci.reop.read() and
5437	"illegal VCI response packet for uncachable instruction");
5438
5439	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5440	{
5441	r_vci_rsp_ins_error = true;
5442	r_vci_rsp_fsm = RSP_IDLE;
5443	}
5444	else // no error reported
5445	{
5446	if (r_vci_rsp_fifo_icache.wok())
5447	{
5448	vci_rsp_fifo_icache_put = true;
5449	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5450	r_vci_rsp_fsm = RSP_IDLE;
5451	}
5452	}
5453	}
5454	break;
5455	}
5456	///////////////////
5457	case RSP_DATA_MISS:
5458	{
5459	if (p_vci.rspval.read())
5460	{
5461	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5462	{
5463	r_vci_rsp_data_error = true;
5464	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5465	}
5466	else // no error reported
5467	{
5468	if (r_vci_rsp_fifo_dcache.wok())
5469	{
5470	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
5471	"The VCI response packet for data miss is too long");
5472
5473	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5474	vci_rsp_fifo_dcache_put = true,
5475	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5476	if (p_vci.reop.read())
5477	{
5478	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5479	"The VCI response packet for data miss is too short");
5480
5481	r_vci_rsp_fsm = RSP_IDLE;
5482	}
5483	}
5484	}
5485	}
5486	break;
5487	}
5488	//////////////////
5489	case RSP_DATA_UNC:
5490	{
5491	if (p_vci.rspval.read())
5492	{
5493	assert(p_vci.reop.read() and
5494	"illegal VCI response packet for uncachable read data");
5495
5496	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5497	{
5498	r_vci_rsp_data_error = true;
5499	r_vci_rsp_fsm = RSP_IDLE;
5500	}
5501	else // no error reported
5502	{
5503	if (r_vci_rsp_fifo_dcache.wok())
5504	{
5505	vci_rsp_fifo_dcache_put = true;
5506	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5507	r_vci_rsp_fsm = RSP_IDLE;
5508	}
5509	}
5510	}
5511	break;
5512	}
5513	/////////////////
5514	case RSP_DATA_LL:
5515	{
5516	if (p_vci.rspval.read())
5517	{
5518	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5519	{
5520	r_vci_rsp_data_error = true;
5521	r_vci_rsp_fsm = RSP_IDLE;
5522	break;
5523	}
5524	if (r_vci_rsp_cpt.read() == 0) //first flit
5525	{
5526	if (r_vci_rsp_fifo_dcache.wok())
5527	{
5528	assert(!p_vci.reop.read() &&
5529	"illegal VCI response packet for LL");
5530	vci_rsp_fifo_dcache_put = true;
5531	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5532	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5533	}
5534	break;
5535	}
5536	else // last flit
5537	{
5538	if (r_vci_rsp_fifo_dcache.wok())
5539	{
5540	assert(p_vci.reop.read() &&
5541	"illegal VCI response packet for LL");
5542	vci_rsp_fifo_dcache_put = true;
5543	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5544	r_vci_rsp_fsm = RSP_IDLE;
5545	}
5546	break;
5547	}
5548	}
5549	break;
5550	}
5551	////////////////////
5552	case RSP_DATA_WRITE:
5553	{
5554	if (p_vci.rspval.read())
5555	{
5556	assert(p_vci.reop.read() and
5557	"a VCI response packet must contain one flit for a write transaction");
5558
5559	r_vci_rsp_fsm = RSP_IDLE;
5560	uint32_t wbuf_index = p_vci.rtrdid.read();
5561	r_wbuf.completed(wbuf_index);
5562	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
5563	}
5564	break;
5565	}
5566	} // end switch r_vci_rsp_fsm
5567
5568	/////////////////////////////////////////////////////////////////////////////////////
5569	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5570	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5571	// and ICACHE FSM) that are served with a round-robin priority.
5572	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5573	// soon as the request has been sent.
5574	/////////////////////////////////////////////////////////////////////////////////////
5575	switch (r_cc_send_fsm.read())
5576	{
5577	///////////////////////////
5578	case CC_SEND_IDLE:
5579	{
5580	///////////////////////////////////////////////////////
5581	// handling round robin between icache and dcache : //
5582	// we first check for the last client and listen for //
5583	// a request of the other, then update the client //
5584	// r_cc_send_last_client : 0 dcache / 1 icache
5585	///////////////////////////////////////////////////////
5586	bool update_last_client = r_cc_send_last_client.read();
5587	if (r_cc_send_last_client.read() == 0) // last client was dcache
5588	{
5589	if (r_icache_cc_send_req.read()) // request from icache
5590	update_last_client = 1; // update last client to icache
5591	}
5592	else // last client was icache
5593	{
5594	if (r_dcache_cc_send_req.read()) // request from dcache
5595	update_last_client = 0; // update last client to dcache
5596	}
5597	r_cc_send_last_client = update_last_client;
5598
5599	// if there is an actual request
5600	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5601	{
5602	// the new client is dcache and has a cleanup request
5603	if ((update_last_client == 0) and
5604	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5605	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5606	// the new client is dcache and has a multi acknowledgement request
5607	else if ((update_last_client == 0) and
5608	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5609	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5610	// the new client is icache and has a cleanup request
5611	else if ((update_last_client == 1) and
5612	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5613	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5614	// the new client is icache and has a multi acknowledgement request
5615	else if ((update_last_client == 1) and
5616	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5617	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5618	}
5619	break;
5620	}
5621	///////////////////////////
5622	case CC_SEND_CLEANUP_1:
5623	{
5624	// wait for the first flit to be consumed
5625	if (p_dspin_p2m.read.read())
5626	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5627
5628	break;
5629	}
5630	///////////////////////////
5631	case CC_SEND_CLEANUP_2:
5632	{
5633	// wait for the second flit to be consumed
5634	if (p_dspin_p2m.read.read())
5635	{
5636	if (r_cc_send_last_client.read() == 0) // dcache active request
5637	r_dcache_cc_send_req = false; // reset dcache request
5638	else // icache active request
5639	r_icache_cc_send_req = false; // reset icache request
5640
5641	// go back to idle state
5642	r_cc_send_fsm = CC_SEND_IDLE;
5643	}
5644	break;
5645	}
5646	///////////////////////////
5647	case CC_SEND_MULTI_ACK:
5648	{
5649	// wait for the flit to be consumed
5650	if (p_dspin_p2m.read.read())
5651	{
5652	if (r_cc_send_last_client.read() == 0) // dcache active request
5653	r_dcache_cc_send_req = false; // reset dcache request
5654	else // icache active request
5655	r_icache_cc_send_req = false; // reset icache request
5656	// go back to idle state
5657	r_cc_send_fsm = CC_SEND_IDLE;
5658	}
5659	break;
5660	}
5661	} // end switch CC_SEND FSM
5662
5663	///////////////////////////////////////////////////////////////////////////////
5664	// CC_RECEIVE FSM
5665	// This FSM receive all coherence packets on a DSPIN40 port.
5666	// There is 5 packet types:
5667	// - CC_DATA_INVAL : DCACHE invalidate request
5668	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5669	// - CC_INST_INVAL : ICACHE invalidate request
5670	// - CC_INST_UPDT : ICACHE update request (multi-words)
5671	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5672	//////////////////////////////////////////////////////////////////////////////
5673	switch (r_cc_receive_fsm.read())
5674	{
5675	/////////////////////
5676	case CC_RECEIVE_IDLE:
5677	{
5678	// a coherence request has arrived
5679	if (p_dspin_m2p.write.read())
5680	{
5681	// initialize dspin received data
5682	uint64_t receive_data = p_dspin_m2p.data.read();
5683	// initialize coherence packet type
5684	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5685	DspinDhccpParam::M2P_TYPE);
5686	// test for a broadcast
5687	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5688	{
5689	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5690	}
5691	// test for a multi updt
5692	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5693	{
5694	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5695	}
5696	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5697	{
5698	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5699	}
5700	// test for a multi inval
5701	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5702	{
5703	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5704	}
5705	else
5706	{
5707	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5708	}
5709	}
5710	break;
5711	}
5712	///////////////////////////////
5713	case CC_RECEIVE_BRDCAST_HEADER:
5714	{
5715	// no actual data in the HEADER, just skip to second flit
5716	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5717	break;
5718	}
5719	//////////////////////////////
5720	case CC_RECEIVE_BRDCAST_NLINE:
5721	{
5722	// initialize dspin received data
5723	uint64_t receive_data = p_dspin_m2p.data.read();
5724	// wait for both dcache and icache to take the request
5725	// TODO maybe we need to wait for both only to leave the state, but
5726	// not to actually post a request to an available cache => need a
5727	// flip_flop to check that ?
5728	if (not (r_cc_receive_icache_req.read()) and
5729	not (r_cc_receive_dcache_req.read()) and
5730	(p_dspin_m2p.write.read()))
5731	{
5732	// request dcache to handle the BROADCAST
5733	r_cc_receive_dcache_req = true;
5734	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5735	DspinDhccpParam::BROADCAST_NLINE);
5736	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5737	// request icache to handle the BROADCAST
5738	r_cc_receive_icache_req = true;
5739	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5740	DspinDhccpParam::BROADCAST_NLINE);
5741	r_cc_receive_icache_type = CC_TYPE_INVAL;
5742	// get back to idle state
5743	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5744	break;
5745	}
5746	// keep waiting for the caches to accept the request
5747	break;
5748	}
5749	/////////////////////////////
5750	case CC_RECEIVE_DATA_INVAL_HEADER:
5751	{
5752	// sample updt tab index in the HEADER, then skip to second flit
5753	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5754	break;
5755	}
5756	/////////////////////////////
5757	case CC_RECEIVE_INS_INVAL_HEADER:
5758	{
5759	// sample updt tab index in the HEADER, then skip to second flit
5760	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5761	break;
5762	}
5763	////////////////////////////
5764	case CC_RECEIVE_DATA_INVAL_NLINE:
5765	{
5766	// sample nline in the second flit
5767	uint64_t receive_data = p_dspin_m2p.data.read();
5768	// for data INVAL, wait for dcache to take the request
5769	if (p_dspin_m2p.write.read() and
5770	not r_cc_receive_dcache_req.read())
5771	{
5772	// request dcache to handle the INVAL
5773	r_cc_receive_dcache_req = true;
5774	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5775	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5776	// get back to idle state
5777	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5778	break;
5779	}
5780	break;
5781	}
5782	//////////////////////////////
5783	case CC_RECEIVE_INS_INVAL_NLINE:
5784	{
5785	// sample nline in the second flit
5786	uint64_t receive_data = p_dspin_m2p.data.read();
5787	// for ins INVAL, wait for icache to take the request
5788	if (p_dspin_m2p.write.read() and
5789	not r_cc_receive_icache_req.read())
5790	{
5791	// request icache to handle the INVAL
5792	r_cc_receive_icache_req = true;
5793	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5794	r_cc_receive_icache_type = CC_TYPE_INVAL;
5795	// get back to idle state
5796	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5797	break;
5798	}
5799	break;
5800	}
5801	////////////////////////////
5802	case CC_RECEIVE_DATA_UPDT_HEADER:
5803	{
5804	// sample updt tab index in the HEADER, than skip to second flit
5805	uint64_t receive_data = p_dspin_m2p.data.read();
5806	// for data INVAL, wait for dcache to take the request and fifo to
5807	// be empty
5808	if (not r_cc_receive_dcache_req.read())
5809	{
5810	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5811	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
5812	break;
5813	}
5814	break;
5815	}
5816	////////////////////////////
5817	case CC_RECEIVE_INS_UPDT_HEADER:
5818	{
5819	// sample updt tab index in the HEADER, than skip to second flit
5820	uint64_t receive_data = p_dspin_m2p.data.read();
5821	// for ins INVAL, wait for icache to take the request and fifo to be
5822	// empty
5823	if (not r_cc_receive_icache_req.read())
5824	{
5825	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5826	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
5827	break;
5828	}
5829	// keep waiting for the correct cache to accept the request
5830	break;
5831	}
5832	///////////////////////////
5833	case CC_RECEIVE_DATA_UPDT_NLINE:
5834	{
5835	// sample nline and word index in the second flit
5836	uint64_t receive_data = p_dspin_m2p.data.read();
5837	// for data INVAL, wait for dcache to take the request and fifo to
5838	// be empty
5839	if (r_cc_receive_updt_fifo_be.empty() and
5840	p_dspin_m2p.write.read())
5841	{
5842	r_cc_receive_dcache_req = true;
5843	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5844	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5845	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5846	// get back to idle state
5847	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
5848	break;
5849	}
5850	break;
5851	}
5852	////////////////////////////
5853	case CC_RECEIVE_INS_UPDT_NLINE:
5854	{
5855	// sample nline and word index in the second flit
5856	uint64_t receive_data = p_dspin_m2p.data.read();
5857	// for ins INVAL, wait for icache to take the request and fifo to be
5858	// empty
5859	if (r_cc_receive_updt_fifo_be.empty() and
5860	p_dspin_m2p.write.read())
5861	{
5862	r_cc_receive_icache_req = true;
5863	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5864	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5865	r_cc_receive_icache_type = CC_TYPE_UPDT;
5866	// get back to idle state
5867	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
5868	break;
5869	}
5870	break;
5871	}
5872	//////////////////////////
5873	case CC_RECEIVE_DATA_UPDT_DATA:
5874	{
5875	// wait for the fifo
5876	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5877	{
5878	uint64_t receive_data = p_dspin_m2p.data.read();
5879	bool receive_eop = p_dspin_m2p.eop.read();
5880	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5881	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5882	cc_receive_updt_fifo_eop = receive_eop;
5883	cc_receive_updt_fifo_put = true;
5884	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5885	}
5886	break;
5887	}
5888	//////////////////////////
5889	case CC_RECEIVE_INS_UPDT_DATA:
5890	{
5891	// wait for the fifo
5892	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5893	{
5894	uint64_t receive_data = p_dspin_m2p.data.read();
5895	bool receive_eop = p_dspin_m2p.eop.read();
5896	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5897	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5898	cc_receive_updt_fifo_eop = receive_eop;
5899	cc_receive_updt_fifo_put = true;
5900	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5901	}
5902	break;
5903	}
5904
5905	} // end switch CC_RECEIVE FSM
5906
5907	///////////////// DSPIN CLACK interface ///////////////
5908
5909	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5910	DspinDhccpParam::CLACK_TYPE);
5911
5912	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5913	DspinDhccpParam::CLACK_WAY);
5914
5915	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5916	DspinDhccpParam::CLACK_SET);
5917
5918	bool dspin_clack_get = false;
5919	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
5920	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
5921
5922	if (r_dspin_clack_req.read())
5923	{
5924	// CLACK DATA: Send request to DCACHE FSM
5925	if (dcache_clack_request and not r_dcache_clack_req.read())
5926	{
5927	r_dcache_clack_req = true;
5928	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
5929	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
5930	dspin_clack_get = true;
5931	}
5932
5933	// CLACK INST: Send request to ICACHE FSM
5934	else if (icache_clack_request and not r_icache_clack_req.read())
5935	{
5936	r_icache_clack_req = true;
5937	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5938	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5939	dspin_clack_get = true;
5940	}
5941	}
5942	else
5943	{
5944	dspin_clack_get = true;
5945	}
5946
5947	if (dspin_clack_get)
5948	{
5949	r_dspin_clack_req = p_dspin_clack.write.read();
5950	r_dspin_clack_flit = p_dspin_clack.data.read();
5951	}
5952
5953	///////////////// Response FIFOs update //////////////////////
5954	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5955	vci_rsp_fifo_icache_put,
5956	vci_rsp_fifo_icache_data);
5957
5958	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5959	vci_rsp_fifo_dcache_put,
5960	vci_rsp_fifo_dcache_data);
5961
5962	///////////////// updt FIFO update //////////////////////
5963	//TODO check this
5964	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5965	cc_receive_updt_fifo_put,
5966	cc_receive_updt_fifo_be);
5967	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5968	cc_receive_updt_fifo_put,
5969	cc_receive_updt_fifo_data);
5970	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5971	cc_receive_updt_fifo_put,
5972	cc_receive_updt_fifo_eop);
5973
5974	} // end transition()
5975
5976	///////////////////////
5977	tmpl(void)::genMoore()
5978	///////////////////////
5979	{
5980
5981	// VCI initiator command on the direct network
5982	// it depends on the CMD FSM state
5983
5984	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5985	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
5986
5987	p_vci.pktid = 0;
5988	p_vci.srcid = m_srcid;
5989	p_vci.cons = is_sc_or_cas;
5990	p_vci.contig = not is_sc_or_cas;
5991	p_vci.wrap = false;
5992	p_vci.clen = 0;
5993	p_vci.cfixed = false;
5994
5995	if (m_monitor_ok) {
5996	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
5997	if (((p_vci.address.read()) >= m_monitor_base) and
5998	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
5999	std::cout << "CC_VCACHE Monitor " << name() << std::hex
6000	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
6001	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
6002	<< " : address = " << p_vci.address.read()
6003	<< " / be = " << p_vci.be.read();
6004	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
6005	std::cout << " / data = " << p_vci.wdata.read();
6006	}
6007	std::cout << std::dec << std::endl;
6008	}
6009	}
6010	}
6011
6012	switch (r_vci_cmd_fsm.read()) {
6013
6014	case CMD_IDLE:
6015	p_vci.cmdval = false;
6016	p_vci.address = 0;
6017	p_vci.wdata = 0;
6018	p_vci.be = 0;
6019	p_vci.trdid = 0;
6020	p_vci.pktid = 0;
6021	p_vci.plen = 0;
6022	p_vci.cmd = vci_param::CMD_NOP;
6023	p_vci.eop = false;
6024	break;
6025
6026	case CMD_INS_MISS:
6027	p_vci.cmdval = true;
6028	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
6029	p_vci.wdata = 0;
6030	p_vci.be = 0xF;
6031	p_vci.trdid = 0;
6032	p_vci.pktid = TYPE_READ_INS_MISS;
6033	p_vci.plen = m_icache_words << 2;
6034	p_vci.cmd = vci_param::CMD_READ;
6035	p_vci.eop = true;
6036	break;
6037
6038	case CMD_INS_UNC:
6039	p_vci.cmdval = true;
6040	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
6041	p_vci.wdata = 0;
6042	p_vci.be = 0xF;
6043	p_vci.trdid = 0;
6044	p_vci.pktid = TYPE_READ_INS_UNC;
6045	p_vci.plen = 4;
6046	p_vci.cmd = vci_param::CMD_READ;
6047	p_vci.eop = true;
6048	break;
6049
6050	case CMD_DATA_MISS:
6051	p_vci.cmdval = true;
6052	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
6053	p_vci.wdata = 0;
6054	p_vci.be = 0xF;
6055	p_vci.trdid = 0;
6056	p_vci.pktid = TYPE_READ_DATA_MISS;
6057	p_vci.plen = m_dcache_words << 2;
6058	p_vci.cmd = vci_param::CMD_READ;
6059	p_vci.eop = true;
6060	break;
6061
6062	case CMD_DATA_UNC_READ:
6063	p_vci.cmdval = true;
6064	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6065	p_vci.wdata = 0;
6066	p_vci.be = r_dcache_vci_unc_be.read();
6067	p_vci.trdid = 0;
6068	p_vci.pktid = TYPE_DATA_UNC;
6069	p_vci.plen = 4;
6070	p_vci.cmd = vci_param::CMD_READ;
6071	p_vci.eop = true;
6072	break;
6073
6074	case CMD_DATA_UNC_WRITE:
6075	p_vci.cmdval = true;
6076	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6077	p_vci.wdata = r_dcache_vci_wdata.read();
6078	p_vci.be = r_dcache_vci_unc_be.read();
6079	p_vci.trdid = 0;
6080	p_vci.pktid = TYPE_DATA_UNC;
6081	p_vci.plen = 4;
6082	p_vci.cmd = vci_param::CMD_WRITE;
6083	p_vci.eop = true;
6084	break;
6085
6086	case CMD_DATA_WRITE:
6087	p_vci.cmdval = true;
6088	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
6089	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
6090	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
6091	p_vci.trdid = r_wbuf.getIndex();
6092	p_vci.pktid = TYPE_WRITE;
6093	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
6094	p_vci.cmd = vci_param::CMD_WRITE;
6095	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
6096	break;
6097
6098	case CMD_DATA_LL:
6099	p_vci.cmdval = true;
6100	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6101	p_vci.wdata = 0;
6102	p_vci.be = 0xF;
6103	p_vci.trdid = 0;
6104	p_vci.pktid = TYPE_LL;
6105	p_vci.plen = 8;
6106	p_vci.cmd = vci_param::CMD_LOCKED_READ;
6107	p_vci.eop = true;
6108	break;
6109
6110	case CMD_DATA_SC:
6111	p_vci.cmdval = true;
6112	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6113	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
6114	else p_vci.wdata = r_dcache_vci_sc_data.read();
6115	p_vci.be = 0xF;
6116	p_vci.trdid = 0;
6117	p_vci.pktid = TYPE_SC;
6118	p_vci.plen = 8;
6119	p_vci.cmd = vci_param::CMD_NOP;
6120	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6121	break;
6122
6123	case CMD_DATA_CAS:
6124	p_vci.cmdval = true;
6125	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6126	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
6127	else p_vci.wdata = r_dcache_vci_cas_new.read();
6128	p_vci.be = 0xF;
6129	p_vci.trdid = 0;
6130	p_vci.pktid = TYPE_CAS;
6131	p_vci.plen = 8;
6132	p_vci.cmd = vci_param::CMD_NOP;
6133	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6134	break;
6135	} // end switch r_vci_cmd_fsm
6136
6137	// VCI initiator response on the direct network
6138	// it depends on the VCI_RSP FSM
6139
6140	switch (r_vci_rsp_fsm.read())
6141	{
6142	case RSP_DATA_WRITE : p_vci.rspack = true; break;
6143	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6144	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6145	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6146	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6147	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6148	case RSP_IDLE : p_vci.rspack = false; break;
6149	} // end switch r_vci_rsp_fsm
6150
6151
6152	// Send coherence packets on DSPIN P2M
6153	// it depends on the CC_SEND FSM
6154
6155	uint64_t dspin_send_data = 0;
6156	switch (r_cc_send_fsm.read())
6157	{
6158	//////////////////
6159	case CC_SEND_IDLE:
6160	{
6161	p_dspin_p2m.write = false;
6162	break;
6163	}
6164	///////////////////////
6165	case CC_SEND_CLEANUP_1:
6166	{
6167	// initialize dspin send data
6168	DspinDhccpParam::dspin_set(dspin_send_data,
6169	m_cc_global_id,
6170	DspinDhccpParam::CLEANUP_SRCID);
6171	DspinDhccpParam::dspin_set(dspin_send_data,
6172	0,
6173	DspinDhccpParam::P2M_BC);
6174
6175	if (r_cc_send_last_client.read() == 0) // dcache active request
6176	{
6177	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6178	>> (m_nline_width - m_x_width - m_y_width)
6179	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6180
6181	DspinDhccpParam::dspin_set(dspin_send_data,
6182	dest,
6183	DspinDhccpParam::CLEANUP_DEST);
6184
6185	DspinDhccpParam::dspin_set(dspin_send_data,
6186	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
6187	DspinDhccpParam::CLEANUP_NLINE_MSB);
6188
6189	DspinDhccpParam::dspin_set(dspin_send_data,
6190	r_dcache_cc_send_way.read(),
6191	DspinDhccpParam::CLEANUP_WAY_INDEX);
6192
6193	DspinDhccpParam::dspin_set(dspin_send_data,
6194	DspinDhccpParam::TYPE_CLEANUP_DATA,
6195	DspinDhccpParam::P2M_TYPE);
6196	}
6197	else // icache active request
6198	{
6199	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6200	>> (m_nline_width - m_x_width - m_y_width)
6201	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6202
6203	DspinDhccpParam::dspin_set(dspin_send_data,
6204	dest,
6205	DspinDhccpParam::CLEANUP_DEST);
6206
6207	DspinDhccpParam::dspin_set(dspin_send_data,
6208	(r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
6209	DspinDhccpParam::CLEANUP_NLINE_MSB);
6210
6211	DspinDhccpParam::dspin_set(dspin_send_data,
6212	r_icache_cc_send_way.read(),
6213	DspinDhccpParam::CLEANUP_WAY_INDEX);
6214
6215	DspinDhccpParam::dspin_set(dspin_send_data,
6216	DspinDhccpParam::TYPE_CLEANUP_INST,
6217	DspinDhccpParam::P2M_TYPE);
6218	}
6219	// send flit
6220	p_dspin_p2m.data = dspin_send_data;
6221	p_dspin_p2m.write = true;
6222	p_dspin_p2m.eop = false;
6223	break;
6224	}
6225	///////////////////////
6226	case CC_SEND_CLEANUP_2:
6227	{
6228	// initialize dspin send data
6229
6230	if (r_cc_send_last_client.read() == 0) // dcache active request
6231	{
6232	DspinDhccpParam::dspin_set(dspin_send_data,
6233	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6234	DspinDhccpParam::CLEANUP_NLINE_LSB);
6235	}
6236	else // icache active request
6237	{
6238	DspinDhccpParam::dspin_set(dspin_send_data,
6239	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6240	DspinDhccpParam::CLEANUP_NLINE_LSB);
6241	}
6242	// send flit
6243	p_dspin_p2m.data = dspin_send_data;
6244	p_dspin_p2m.write = true;
6245	p_dspin_p2m.eop = true;
6246	break;
6247	}
6248	///////////////////////
6249	case CC_SEND_MULTI_ACK:
6250	{
6251	// initialize dspin send data
6252	DspinDhccpParam::dspin_set(dspin_send_data,
6253	0,
6254	DspinDhccpParam::P2M_BC);
6255	DspinDhccpParam::dspin_set(dspin_send_data,
6256	DspinDhccpParam::TYPE_MULTI_ACK,
6257	DspinDhccpParam::P2M_TYPE);
6258
6259	if (r_cc_send_last_client.read() == 0) // dcache active request
6260	{
6261	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6262	>> (m_nline_width - m_x_width - m_y_width)
6263	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6264
6265	DspinDhccpParam::dspin_set(dspin_send_data,
6266	dest,
6267	DspinDhccpParam::MULTI_ACK_DEST);
6268
6269	DspinDhccpParam::dspin_set(dspin_send_data,
6270	r_dcache_cc_send_updt_tab_idx.read(),
6271	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6272	}
6273	else // icache active request
6274	{
6275	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6276	>> (m_nline_width - m_x_width - m_y_width)
6277	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6278
6279
6280	DspinDhccpParam::dspin_set(dspin_send_data,
6281	dest,
6282	DspinDhccpParam::MULTI_ACK_DEST);
6283
6284	DspinDhccpParam::dspin_set(dspin_send_data,
6285	r_icache_cc_send_updt_tab_idx.read(),
6286	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6287	}
6288	// send flit
6289	p_dspin_p2m.data = dspin_send_data;
6290	p_dspin_p2m.write = true;
6291	p_dspin_p2m.eop = true;
6292
6293	break;
6294	}
6295	} // end switch CC_SEND FSM
6296
6297	// Receive coherence packets
6298	// It depends on the CC_RECEIVE FSM
6299	switch (r_cc_receive_fsm.read())
6300	{
6301	/////////////////////
6302	case CC_RECEIVE_IDLE:
6303	{
6304	p_dspin_m2p.read = false;
6305	break;
6306	}
6307	///////////////////////////////
6308	case CC_RECEIVE_BRDCAST_HEADER:
6309	{
6310	p_dspin_m2p.read = true;
6311	break;
6312	}
6313	//////////////////////////////
6314	case CC_RECEIVE_BRDCAST_NLINE:
6315	{
6316	// TODO maybe we need to wait for both only to leave the state, but
6317	// not to actually post a request to an available cache => need a
6318	// flip_flop to check that ?
6319	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6320	p_dspin_m2p.read = true;
6321	else
6322	p_dspin_m2p.read = false;
6323	break;
6324	}
6325	/////////////////////////////
6326	case CC_RECEIVE_DATA_INVAL_HEADER:
6327	case CC_RECEIVE_INS_INVAL_HEADER:
6328	{
6329	p_dspin_m2p.read = true;
6330	break;
6331	}
6332	////////////////////////////
6333	case CC_RECEIVE_DATA_INVAL_NLINE:
6334	{
6335	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
6336	break;
6337	}
6338	case CC_RECEIVE_INS_INVAL_NLINE:
6339	{
6340	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
6341	break;
6342	}
6343	///////////////////////////
6344	case CC_RECEIVE_DATA_UPDT_HEADER:
6345	{
6346	if (not r_cc_receive_dcache_req.read())
6347	p_dspin_m2p.read = true;
6348	else
6349	p_dspin_m2p.read = false;
6350	break;
6351	}
6352	////////////////////////////
6353	case CC_RECEIVE_INS_UPDT_HEADER:
6354	{
6355	if (not r_cc_receive_icache_req.read())
6356	p_dspin_m2p.read = true;
6357	else
6358	p_dspin_m2p.read = false;
6359	break;
6360	}
6361	///////////////////////////
6362	case CC_RECEIVE_DATA_UPDT_NLINE:
6363	case CC_RECEIVE_INS_UPDT_NLINE:
6364	{
6365	if (r_cc_receive_updt_fifo_be.empty())
6366	p_dspin_m2p.read = true;
6367	else
6368	p_dspin_m2p.read = false;
6369	break;
6370	}
6371	///////////////////////////
6372	case CC_RECEIVE_DATA_UPDT_DATA:
6373	case CC_RECEIVE_INS_UPDT_DATA:
6374	{
6375	if (r_cc_receive_updt_fifo_be.wok())
6376	p_dspin_m2p.read = true;
6377	else
6378	p_dspin_m2p.read = false;
6379	break;
6380	}
6381	} // end switch CC_RECEIVE FSM
6382
6383
6384	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6385	DspinDhccpParam::CLACK_TYPE);
6386
6387	bool dspin_clack_get = false;
6388	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6389	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6390
6391	if (r_dspin_clack_req.read())
6392	{
6393	// CLACK DATA: wait if pending request to DCACHE FSM
6394	if (dcache_clack_request and not r_dcache_clack_req.read())
6395	{
6396	dspin_clack_get = true;
6397	}
6398
6399	// CLACK INST: wait if pending request to ICACHE FSM
6400	else if (icache_clack_request and not r_icache_clack_req.read())
6401	{
6402	dspin_clack_get = true;
6403	}
6404	}
6405	else
6406	{
6407	dspin_clack_get = true;
6408	}
6409
6410	p_dspin_clack.read = dspin_clack_get;
6411	} // end genMoore
6412
6413	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6414	// This version of monitor print both Read and Write request
6415	{
6416	m_monitor_ok = true;
6417	m_monitor_base = base;
6418	m_monitor_length = length;
6419	}
6420
6421	tmpl(void)::stop_monitor()
6422	{
6423	m_monitor_ok = false;
6424	}
6425
6426	}}
6427
6428	// Local Variables:
6429	// tab-width: 4
6430	// c-basic-offset: 4
6431	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6432	// indent-tabs-mode: nil
6433	// End:
6434
6435	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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