[183] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_cc_vcache_wrapper_v4.h |
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| 3 | * Copyright (c) UPMC, Lip6, SoC |
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| 4 | * Authors : Alain GREINER, Yang GAO |
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| 5 | * Date : 27/11/2011 |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | */ |
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| 27 | |
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| 28 | #ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H |
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| 29 | #define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H |
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| 30 | |
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| 31 | #include <inttypes.h> |
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| 32 | #include <systemc> |
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| 33 | #include "caba_base_module.h" |
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| 34 | #include "multi_write_buffer.h" |
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| 35 | #include "generic_fifo.h" |
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| 36 | #include "generic_tlb.h" |
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[204] | 37 | #include "generic_cache.h" |
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[183] | 38 | #include "generic_cam.h" |
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| 39 | #include "vci_initiator.h" |
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| 40 | #include "vci_target.h" |
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| 41 | #include "mapping_table.h" |
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| 42 | #include "static_assert.h" |
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| 43 | #include "iss2.h" |
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| 44 | |
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| 45 | namespace soclib { |
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| 46 | namespace caba { |
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| 47 | |
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| 48 | using namespace sc_core; |
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| 49 | |
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| 50 | //////////////////////////////////////////// |
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| 51 | template<typename vci_param, typename iss_t> |
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| 52 | class VciCcVCacheWrapperV4 |
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| 53 | //////////////////////////////////////////// |
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| 54 | : public soclib::caba::BaseModule |
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| 55 | { |
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| 56 | typedef uint32_t vaddr_t; |
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| 57 | typedef uint32_t tag_t; |
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| 58 | typedef uint32_t type_t; |
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| 59 | typedef typename iss_t::DataOperationType data_op_t; |
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| 60 | |
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| 61 | typedef typename vci_param::addr_t paddr_t; |
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| 62 | typedef typename vci_param::be_t vci_be_t; |
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| 63 | typedef typename vci_param::srcid_t vci_srcid_t; |
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| 64 | typedef typename vci_param::trdid_t vci_trdid_t; |
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| 65 | typedef typename vci_param::pktid_t vci_pktid_t; |
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| 66 | typedef typename vci_param::plen_t vci_plen_t; |
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| 67 | |
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| 68 | enum icache_fsm_state_e { |
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| 69 | ICACHE_IDLE, |
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| 70 | // handling XTN processor requests |
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| 71 | ICACHE_XTN_TLB_FLUSH, |
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| 72 | ICACHE_XTN_CACHE_FLUSH, |
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| 73 | ICACHE_XTN_TLB_INVAL, |
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| 74 | ICACHE_XTN_CACHE_INVAL_VA, |
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| 75 | ICACHE_XTN_CACHE_INVAL_PA, |
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| 76 | ICACHE_XTN_CACHE_INVAL_GO, |
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| 77 | // handling tlb miss |
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| 78 | ICACHE_TLB_WAIT, |
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| 79 | // handling cache miss |
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| 80 | ICACHE_MISS_VICTIM, |
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| 81 | ICACHE_MISS_INVAL, |
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| 82 | ICACHE_MISS_WAIT, |
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| 83 | ICACHE_MISS_UPDT, |
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| 84 | // handling unc read |
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| 85 | ICACHE_UNC_WAIT, |
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| 86 | // handling coherence requests |
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| 87 | ICACHE_CC_CHECK, |
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| 88 | ICACHE_CC_INVAL, |
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| 89 | ICACHE_CC_UPDT, |
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| 90 | }; |
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| 91 | |
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| 92 | enum dcache_fsm_state_e { |
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| 93 | DCACHE_IDLE, |
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| 94 | // handling itlb & dtlb miss |
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| 95 | DCACHE_TLB_MISS, |
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| 96 | DCACHE_TLB_PTE1_GET, |
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| 97 | DCACHE_TLB_PTE1_SELECT, |
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| 98 | DCACHE_TLB_PTE1_UPDT, |
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| 99 | DCACHE_TLB_PTE2_GET, |
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| 100 | DCACHE_TLB_PTE2_SELECT, |
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| 101 | DCACHE_TLB_PTE2_UPDT, |
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[205] | 102 | DCACHE_TLB_LR_UPDT, |
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| 103 | DCACHE_TLB_LR_WAIT, |
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[183] | 104 | DCACHE_TLB_RETURN, |
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| 105 | // handling processor XTN requests |
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| 106 | DCACHE_XTN_SWITCH, |
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| 107 | DCACHE_XTN_SYNC, |
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| 108 | DCACHE_XTN_IC_INVAL_VA, |
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| 109 | DCACHE_XTN_IC_FLUSH, |
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| 110 | DCACHE_XTN_IC_INVAL_PA, |
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| 111 | DCACHE_XTN_IT_INVAL, |
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| 112 | DCACHE_XTN_DC_FLUSH, |
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| 113 | DCACHE_XTN_DC_INVAL_VA, |
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| 114 | DCACHE_XTN_DC_INVAL_PA, |
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[204] | 115 | DCACHE_XTN_DC_INVAL_END, |
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[183] | 116 | DCACHE_XTN_DC_INVAL_GO, |
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| 117 | DCACHE_XTN_DT_INVAL, |
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[206] | 118 | //handling dirty bit update |
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| 119 | DCACHE_DIRTY_GET_PTE, |
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[205] | 120 | DCACHE_DIRTY_SC_WAIT, |
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[204] | 121 | // handling processor miss requests |
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[183] | 122 | DCACHE_MISS_VICTIM, |
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| 123 | DCACHE_MISS_INVAL, |
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| 124 | DCACHE_MISS_WAIT, |
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| 125 | DCACHE_MISS_UPDT, |
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| 126 | // handling processor unc and sc requests |
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| 127 | DCACHE_UNC_WAIT, |
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[205] | 128 | DCACHE_SC_WAIT, |
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[183] | 129 | // handling coherence requests |
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| 130 | DCACHE_CC_CHECK, |
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| 131 | DCACHE_CC_INVAL, |
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| 132 | DCACHE_CC_UPDT, |
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[204] | 133 | // handling TLB inval (after a coherence or XTN request) |
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| 134 | DCACHE_INVAL_TLB_SCAN, |
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[183] | 135 | }; |
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| 136 | |
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| 137 | enum cmd_fsm_state_e { |
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| 138 | CMD_IDLE, |
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| 139 | CMD_INS_MISS, |
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| 140 | CMD_INS_UNC, |
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| 141 | CMD_DATA_MISS, |
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| 142 | CMD_DATA_UNC, |
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| 143 | CMD_DATA_WRITE, |
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| 144 | CMD_DATA_SC, |
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| 145 | }; |
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| 146 | |
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| 147 | enum rsp_fsm_state_e { |
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| 148 | RSP_IDLE, |
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| 149 | RSP_INS_MISS, |
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| 150 | RSP_INS_UNC, |
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| 151 | RSP_DATA_MISS, |
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| 152 | RSP_DATA_UNC, |
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| 153 | RSP_DATA_WRITE, |
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| 154 | RSP_DATA_SC, |
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| 155 | }; |
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| 156 | |
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| 157 | enum cleanup_cmd_fsm_state_e { |
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| 158 | CLEANUP_DATA_IDLE, |
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| 159 | CLEANUP_DATA_GO, |
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| 160 | CLEANUP_INS_IDLE, |
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| 161 | CLEANUP_INS_GO, |
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| 162 | }; |
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| 163 | |
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| 164 | enum tgt_fsm_state_e { |
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| 165 | TGT_IDLE, |
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| 166 | TGT_UPDT_WORD, |
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| 167 | TGT_UPDT_DATA, |
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| 168 | TGT_REQ_BROADCAST, |
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| 169 | TGT_REQ_ICACHE, |
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| 170 | TGT_REQ_DCACHE, |
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| 171 | TGT_RSP_BROADCAST, |
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| 172 | TGT_RSP_ICACHE, |
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| 173 | TGT_RSP_DCACHE, |
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| 174 | }; |
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| 175 | |
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| 176 | // TLB Mode : ITLB / DTLB / ICACHE / DCACHE |
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| 177 | enum { |
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| 178 | INS_TLB_MASK = 0x8, |
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| 179 | DATA_TLB_MASK = 0x4, |
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| 180 | INS_CACHE_MASK = 0x2, |
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| 181 | DATA_CACHE_MASK = 0x1, |
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| 182 | }; |
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| 183 | |
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| 184 | // Error Type |
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| 185 | enum mmu_error_type_e |
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| 186 | { |
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| 187 | MMU_NONE = 0x0000, // None |
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| 188 | MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write access of Page fault on Page Table 1 |
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| 189 | MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write access of Page fault on Page Table 2 |
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| 190 | MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode |
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| 191 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page |
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| 192 | MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write access of undefined external access address |
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| 193 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 |
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| 194 | MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write access of Bus Error accessing Table 2 |
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| 195 | MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access |
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| 196 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 |
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| 197 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 |
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| 198 | MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read access of Protected access in user mode |
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| 199 | MMU_READ_EXEC_VIOLATION = 0x1010, // Exec access to a non exec page |
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| 200 | MMU_READ_UNDEFINED_XTN = 0x1020, // Read access of Undefined external access address |
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| 201 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access |
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| 202 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access |
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| 203 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access |
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| 204 | }; |
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| 205 | |
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| 206 | // miss types for data cache |
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| 207 | enum dcache_miss_type_e |
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| 208 | { |
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| 209 | PTE1_MISS, |
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| 210 | PTE2_MISS, |
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| 211 | PROC_MISS, |
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| 212 | }; |
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| 213 | |
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| 214 | enum transaction_type_d_e |
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| 215 | { |
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| 216 | // b0 : 1 if cached |
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| 217 | // b1 : 1 if instruction |
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| 218 | TYPE_DATA_UNC = 0x0, |
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| 219 | TYPE_DATA_MISS = 0x1, |
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| 220 | TYPE_INS_UNC = 0x2, |
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| 221 | TYPE_INS_MISS = 0x3, |
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| 222 | }; |
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| 223 | |
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| 224 | public: |
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| 225 | sc_in<bool> p_clk; |
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| 226 | sc_in<bool> p_resetn; |
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| 227 | sc_in<bool> p_irq[iss_t::n_irq]; |
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| 228 | soclib::caba::VciInitiator<vci_param> p_vci_ini_d; |
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| 229 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
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| 230 | soclib::caba::VciTarget<vci_param> p_vci_tgt_c; |
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| 231 | |
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| 232 | private: |
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| 233 | |
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| 234 | // STRUCTURAL PARAMETERS |
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| 235 | soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; |
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| 236 | const soclib::common::Segment m_segment; |
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| 237 | const vci_srcid_t m_srcid_d; |
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| 238 | const vci_srcid_t m_srcid_c; |
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| 239 | |
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| 240 | const size_t m_itlb_ways; |
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| 241 | const size_t m_itlb_sets; |
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| 242 | |
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| 243 | const size_t m_dtlb_ways; |
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| 244 | const size_t m_dtlb_sets; |
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| 245 | |
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| 246 | const size_t m_icache_ways; |
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| 247 | const size_t m_icache_sets; |
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| 248 | const paddr_t m_icache_yzmask; |
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| 249 | const size_t m_icache_words; |
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| 250 | |
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| 251 | const size_t m_dcache_ways; |
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| 252 | const size_t m_dcache_sets; |
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| 253 | const paddr_t m_dcache_yzmask; |
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| 254 | const size_t m_dcache_words; |
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| 255 | |
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[202] | 256 | const size_t m_proc_id; |
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| 257 | |
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[183] | 258 | const uint32_t m_max_frozen_cycles; |
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| 259 | |
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| 260 | const size_t m_paddr_nbits; |
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| 261 | |
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| 262 | //////////////////////////////////////// |
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[205] | 263 | // Communication with processor ISS |
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[183] | 264 | //////////////////////////////////////// |
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[205] | 265 | typename iss_t::InstructionRequest m_ireq; |
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| 266 | typename iss_t::InstructionResponse m_irsp; |
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| 267 | typename iss_t::DataRequest m_dreq; |
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| 268 | typename iss_t::DataResponse m_drsp; |
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[183] | 269 | |
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| 270 | ///////////////////////////////////////////// |
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| 271 | // debug variables (for each FSM) |
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| 272 | ///////////////////////////////////////////// |
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[206] | 273 | uint32_t m_debug_start_cycle; |
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| 274 | bool m_debug_ok; |
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| 275 | bool m_debug_previous_hit; |
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[211] | 276 | bool m_idebug_previous_hit; |
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[206] | 277 | bool m_debug_dcache_fsm; |
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| 278 | bool m_debug_icache_fsm; |
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| 279 | bool m_debug_cleanup_fsm; |
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| 280 | bool m_debug_inval_itlb_fsm; |
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| 281 | bool m_debug_inval_dtlb_fsm; |
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[183] | 282 | |
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| 283 | /////////////////////////////// |
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| 284 | // Software visible REGISTERS |
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| 285 | /////////////////////////////// |
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| 286 | sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register |
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| 287 | sc_signal<uint32_t> r_mmu_mode; // mmu mode register |
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| 288 | sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low |
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| 289 | sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight |
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| 290 | sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address |
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| 291 | sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address |
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| 292 | sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type |
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| 293 | sc_signal<uint32_t> r_mmu_detr; // mmu data error type |
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[203] | 294 | uint32_t r_mmu_params; // read-only |
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| 295 | uint32_t r_mmu_release; // read_only |
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[183] | 296 | |
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| 297 | |
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| 298 | ////////////////////////////// |
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| 299 | // ICACHE FSM REGISTERS |
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| 300 | ////////////////////////////// |
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| 301 | sc_signal<int> r_icache_fsm; // state register |
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| 302 | sc_signal<int> r_icache_fsm_save; // return state for coherence operation |
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| 303 | sc_signal<paddr_t> r_icache_vci_paddr; // physical address |
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| 304 | sc_signal<uint32_t> r_icache_vaddr_save; // virtual address requested by the processor |
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| 305 | |
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| 306 | // icache miss handling |
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| 307 | sc_signal<size_t> r_icache_miss_way; // selected way for cache update |
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| 308 | sc_signal<size_t> r_icache_miss_set; // selected set for cache update |
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| 309 | sc_signal<size_t> r_icache_miss_word; // word index for sequencial cache update |
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| 310 | sc_signal<bool> r_icache_miss_inval; // coherence request matching a pending miss |
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| 311 | |
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| 312 | // coherence request handling |
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| 313 | sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval |
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| 314 | sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval |
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| 315 | sc_signal<size_t> r_icache_cc_word; // word counter for cc update |
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| 316 | |
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| 317 | // icache flush handling |
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| 318 | sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush |
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| 319 | |
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| 320 | // communication between ICACHE FSM and VCI_CMD FSM |
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| 321 | sc_signal<bool> r_icache_miss_req; // cached read miss |
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| 322 | sc_signal<bool> r_icache_unc_req; // uncached read miss |
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| 323 | |
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| 324 | // communication between ICACHE FSM and DCACHE FSM |
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| 325 | sc_signal<bool> r_icache_tlb_miss_req; // itlb miss request (set icache/reset dcache) |
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| 326 | sc_signal<bool> r_icache_tlb_rsp_error; // itlb miss response error (written by dcache) |
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| 327 | |
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| 328 | // communication between ICACHE FSM and CLEANUP FSMs |
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| 329 | sc_signal<bool> r_icache_cleanup_req; // ins cleanup request |
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| 330 | sc_signal<paddr_t> r_icache_cleanup_line; // ins cleanup NLINE |
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| 331 | |
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| 332 | /////////////////////////////// |
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| 333 | // DCACHE FSM REGISTERS |
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| 334 | /////////////////////////////// |
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| 335 | sc_signal<int> r_dcache_fsm; // state register |
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[217] | 336 | sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence operation |
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| 337 | sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan operation |
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[183] | 338 | // registers written in P0 stage (used in P1 stage) |
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| 339 | sc_signal<bool> r_dcache_p0_valid; // P1 pipeline stage must be executed |
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| 340 | sc_signal<uint32_t> r_dcache_p0_vaddr; // virtual address (from proc) |
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| 341 | sc_signal<uint32_t> r_dcache_p0_wdata; // write data (from proc) |
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| 342 | sc_signal<vci_be_t> r_dcache_p0_be; // byte enable (from proc) |
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| 343 | sc_signal<paddr_t> r_dcache_p0_paddr; // physical address |
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| 344 | sc_signal<bool> r_dcache_p0_cacheable; // address cacheable |
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| 345 | // registers written in P1 stage (used in P2 stage) |
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| 346 | sc_signal<bool> r_dcache_p1_valid; // P2 pipeline stage must be executed |
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| 347 | sc_signal<uint32_t> r_dcache_p1_wdata; // write data (from proc) |
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| 348 | sc_signal<vci_be_t> r_dcache_p1_be; // byte enable (from proc) |
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| 349 | sc_signal<paddr_t> r_dcache_p1_paddr; // physical address |
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| 350 | sc_signal<size_t> r_dcache_p1_cache_way; // selected way (from dcache) |
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| 351 | sc_signal<size_t> r_dcache_p1_cache_set; // selected set (from dcache) |
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| 352 | sc_signal<size_t> r_dcache_p1_cache_word; // selected word (from dcache) |
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[206] | 353 | // registers used by the Dirty bit sub-fsm |
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| 354 | sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address |
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| 355 | sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache |
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| 356 | sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache |
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| 357 | |
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[183] | 358 | // communication between DCACHE FSM and VCI_CMD FSM |
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| 359 | sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command |
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| 360 | sc_signal<bool> r_dcache_vci_miss_req; // read miss request |
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| 361 | sc_signal<bool> r_dcache_vci_unc_req; // uncacheable read request |
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| 362 | sc_signal<bool> r_dcache_vci_unc_be; // uncacheable read byte enable |
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| 363 | sc_signal<bool> r_dcache_vci_sc_req; // atomic write request (Compare & swap) |
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| 364 | sc_signal<uint32_t> r_dcache_vci_sc_old; // previous data value for an atomic write |
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| 365 | sc_signal<uint32_t> r_dcache_vci_sc_new; // new data value for an atomic write |
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| 366 | |
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| 367 | // register used for XTN inval |
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| 368 | sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) |
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| 369 | sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) |
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| 370 | |
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| 371 | // write buffer state extension |
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| 372 | sc_signal<bool> r_dcache_pending_unc_write; // pending uncacheable write in WBUF |
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| 373 | |
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| 374 | // handling dcache miss |
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[205] | 375 | sc_signal<int> r_dcache_miss_type; // type of miss depending on the requester |
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[183] | 376 | sc_signal<size_t> r_dcache_miss_word; // word index for sequencial cache update |
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| 377 | sc_signal<size_t> r_dcache_miss_way; // selected way for cache update |
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| 378 | sc_signal<size_t> r_dcache_miss_set; // selected set for cache update |
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| 379 | sc_signal<bool> r_dcache_miss_inval; // coherence request matching a pending miss |
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| 380 | |
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| 381 | // handling coherence requests |
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| 382 | sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval |
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| 383 | sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval |
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| 384 | sc_signal<size_t> r_dcache_cc_word; // word counter for cc update |
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| 385 | |
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| 386 | // dcache flush handling |
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| 387 | sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush |
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| 388 | |
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| 389 | // used by the TLB miss sub-fsm |
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| 390 | sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss |
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| 391 | sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) |
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| 392 | sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte |
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| 393 | sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 |
---|
| 394 | sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 |
---|
| 395 | sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache |
---|
| 396 | sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache |
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| 397 | sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache |
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| 398 | sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb |
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| 399 | sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb |
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| 400 | |
---|
| 401 | // LL reservation handling |
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| 402 | sc_signal<bool> r_dcache_ll_valid; // valid LL reservation |
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| 403 | sc_signal<uint32_t> r_dcache_ll_data; // LL reserved data |
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| 404 | sc_signal<paddr_t> r_dcache_ll_vaddr; // LL reserved address |
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| 405 | |
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[204] | 406 | // ITLB and DTLB invalidation |
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[183] | 407 | sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index |
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[204] | 408 | sc_signal<size_t> r_dcache_tlb_inval_count; // tlb entry counter |
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[183] | 409 | |
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| 410 | // communication between DCACHE FSM and ICACHE FSM |
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| 411 | sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor) |
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| 412 | sc_signal<int> r_dcache_xtn_opcode; // xtn request type |
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| 413 | |
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| 414 | // communication between DCACHE FSM and CLEANUP FSMs |
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| 415 | sc_signal<bool> r_dcache_cleanup_req; // data cleanup request |
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| 416 | sc_signal<paddr_t> r_dcache_cleanup_line; // data cleanup NLINE |
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| 417 | |
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| 418 | // dcache directory extension |
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[206] | 419 | bool *r_dcache_in_tlb; // copy exist in dtlb or itlb |
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| 420 | bool *r_dcache_contains_ptd; // cache line contains a PTD |
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[183] | 421 | |
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| 422 | /////////////////////////////////// |
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| 423 | // VCI_CMD FSM REGISTERS |
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| 424 | /////////////////////////////////// |
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| 425 | sc_signal<int> r_vci_cmd_fsm; |
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| 426 | sc_signal<size_t> r_vci_cmd_min; // used for write bursts |
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| 427 | sc_signal<size_t> r_vci_cmd_max; // used for write bursts |
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| 428 | sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts |
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| 429 | sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss |
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| 430 | |
---|
| 431 | /////////////////////////////////// |
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| 432 | // VCI_RSP FSM REGISTERS |
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| 433 | /////////////////////////////////// |
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| 434 | sc_signal<int> r_vci_rsp_fsm; |
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| 435 | sc_signal<size_t> r_vci_rsp_cpt; |
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| 436 | sc_signal<bool> r_vci_rsp_ins_error; |
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| 437 | sc_signal<bool> r_vci_rsp_data_error; |
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| 438 | GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM |
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| 439 | GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM |
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| 440 | |
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| 441 | /////////////////////////////////// |
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| 442 | // CLEANUP FSM REGISTER |
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| 443 | /////////////////////////////////// |
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| 444 | sc_signal<int> r_cleanup_fsm; // state register |
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| 445 | sc_signal<size_t> r_cleanup_trdid; // to clear the registration buffer |
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| 446 | GenericCam<paddr_t> r_cleanup_buffer; // Registration buffer for cleanups |
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| 447 | |
---|
| 448 | /////////////////////////////////// |
---|
| 449 | // TGT FSM REGISTERS |
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| 450 | /////////////////////////////////// |
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| 451 | sc_signal<int> r_tgt_fsm; // state register |
---|
| 452 | sc_signal<paddr_t> r_tgt_paddr; // cache line physical address |
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| 453 | sc_signal<size_t> r_tgt_word_count; // word index |
---|
| 454 | sc_signal<size_t> r_tgt_word_min; // index of the first word to be updated |
---|
| 455 | sc_signal<size_t> r_tgt_word_max; // index of the last word to be updated |
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| 456 | sc_signal<bool> r_tgt_update; // update request |
---|
| 457 | sc_signal<bool> r_tgt_update_data; // update data request |
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| 458 | sc_signal<vci_srcid_t> r_tgt_srcid; |
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| 459 | sc_signal<vci_pktid_t> r_tgt_pktid; |
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| 460 | sc_signal<vci_trdid_t> r_tgt_trdid; |
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| 461 | |
---|
| 462 | // communications between TGT FSM and DCACHE/ICACHE FSMs |
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| 463 | sc_signal<bool> r_tgt_icache_req; // coherence request (set by tgt) |
---|
| 464 | sc_signal<bool> r_tgt_dcache_req; // coherence request (set by tgt) |
---|
| 465 | sc_signal<bool> r_tgt_icache_rsp; // coherence response (set by icache) |
---|
| 466 | sc_signal<bool> r_tgt_dcache_rsp; // coherence response (set by dcache) |
---|
| 467 | |
---|
| 468 | uint32_t *r_tgt_buf; // cache line word buffer |
---|
| 469 | vci_be_t *r_tgt_be; // cache line be buffer |
---|
| 470 | |
---|
| 471 | ////////////////////////////////////////////////////////////////// |
---|
| 472 | // processor, write buffer, caches , TLBs and CAM for cleanups |
---|
| 473 | ////////////////////////////////////////////////////////////////// |
---|
| 474 | iss_t r_iss; |
---|
| 475 | MultiWriteBuffer<paddr_t> r_wbuf; |
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| 476 | GenericCache<paddr_t> r_icache; |
---|
| 477 | GenericCache<paddr_t> r_dcache; |
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| 478 | GenericTlb<paddr_t> r_itlb; |
---|
| 479 | GenericTlb<paddr_t> r_dtlb; |
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| 480 | |
---|
| 481 | //////////////////////////////// |
---|
| 482 | // Activity counters |
---|
| 483 | //////////////////////////////// |
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| 484 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
---|
| 485 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
---|
| 486 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
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| 487 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
---|
| 488 | |
---|
| 489 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
---|
| 490 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
---|
| 491 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
---|
| 492 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
---|
| 493 | |
---|
| 494 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
---|
| 495 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
| 496 | |
---|
| 497 | // Cache activity counters |
---|
| 498 | uint32_t m_cpt_data_read; // total number of read data |
---|
| 499 | uint32_t m_cpt_data_write; // total number of write data |
---|
| 500 | uint32_t m_cpt_data_miss; // number of read miss |
---|
| 501 | uint32_t m_cpt_ins_miss; // number of instruction miss |
---|
| 502 | uint32_t m_cpt_unc_read; // number of read uncached |
---|
| 503 | uint32_t m_cpt_write_cached; // number of cached write |
---|
| 504 | uint32_t m_cpt_ins_read; // number of instruction read |
---|
| 505 | uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss |
---|
| 506 | |
---|
| 507 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
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| 508 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
---|
| 509 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
---|
| 510 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
---|
| 511 | |
---|
| 512 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
---|
| 513 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
---|
| 514 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
---|
| 515 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
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| 516 | uint32_t m_cpt_icache_unc_transaction; |
---|
| 517 | |
---|
| 518 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
---|
| 519 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
---|
| 520 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
---|
| 521 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
---|
| 522 | uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions |
---|
| 523 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
---|
| 524 | |
---|
| 525 | // TLB activity counters |
---|
| 526 | uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read |
---|
| 527 | uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss |
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| 528 | uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update |
---|
| 529 | uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line |
---|
| 530 | uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache |
---|
| 531 | |
---|
| 532 | uint32_t m_cpt_data_tlb_read; // number of data tlb read |
---|
| 533 | uint32_t m_cpt_data_tlb_miss; // number of data tlb miss |
---|
| 534 | uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update |
---|
| 535 | uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty |
---|
| 536 | uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache |
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| 537 | uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line |
---|
| 538 | uint32_t m_cpt_tlb_occup_dcache; |
---|
| 539 | |
---|
| 540 | uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss |
---|
| 541 | uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss |
---|
| 542 | uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc |
---|
| 543 | uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc |
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| 544 | uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty |
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| 545 | uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache |
---|
| 546 | uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache |
---|
| 547 | |
---|
| 548 | uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions |
---|
| 549 | uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions |
---|
| 550 | uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions |
---|
| 551 | uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions |
---|
| 552 | uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions |
---|
| 553 | uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions |
---|
| 554 | uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions |
---|
| 555 | uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions |
---|
| 556 | |
---|
| 557 | uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions |
---|
| 558 | uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions |
---|
| 559 | uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions |
---|
| 560 | uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions |
---|
| 561 | uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions |
---|
| 562 | uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions |
---|
| 563 | uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions |
---|
| 564 | uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions |
---|
| 565 | |
---|
| 566 | // coherence activity counters |
---|
| 567 | uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands |
---|
| 568 | uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands |
---|
| 569 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands |
---|
| 570 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands |
---|
| 571 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands |
---|
| 572 | |
---|
| 573 | uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets |
---|
| 574 | uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets |
---|
| 575 | uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets |
---|
| 576 | uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets |
---|
| 577 | |
---|
| 578 | uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets |
---|
| 579 | uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets |
---|
| 580 | |
---|
| 581 | uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions |
---|
| 582 | uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions |
---|
| 583 | uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions |
---|
| 584 | uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions |
---|
| 585 | |
---|
| 586 | uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate |
---|
| 587 | uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate |
---|
| 588 | |
---|
| 589 | uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate |
---|
| 590 | uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate |
---|
| 591 | |
---|
| 592 | // FSM activity counters |
---|
| 593 | uint32_t m_cpt_fsm_icache [64]; |
---|
| 594 | uint32_t m_cpt_fsm_dcache [64]; |
---|
| 595 | uint32_t m_cpt_fsm_cmd [64]; |
---|
| 596 | uint32_t m_cpt_fsm_rsp [64]; |
---|
| 597 | uint32_t m_cpt_fsm_tgt [64]; |
---|
| 598 | uint32_t m_cpt_fsm_cmd_cleanup[64]; |
---|
| 599 | uint32_t m_cpt_fsm_rsp_cleanup[64]; |
---|
| 600 | |
---|
| 601 | uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen |
---|
| 602 | |
---|
| 603 | protected: |
---|
| 604 | SC_HAS_PROCESS(VciCcVCacheWrapperV4); |
---|
| 605 | |
---|
| 606 | public: |
---|
| 607 | VciCcVCacheWrapperV4( |
---|
| 608 | sc_module_name insname, |
---|
| 609 | int proc_id, |
---|
| 610 | const soclib::common::MappingTable &mtp, |
---|
| 611 | const soclib::common::MappingTable &mtc, |
---|
| 612 | const soclib::common::IntTab &initiator_index_d, |
---|
| 613 | const soclib::common::IntTab &initiator_index_c, |
---|
| 614 | const soclib::common::IntTab &target_index_d, |
---|
| 615 | size_t itlb_ways, |
---|
| 616 | size_t itlb_sets, |
---|
| 617 | size_t dtlb_ways, |
---|
| 618 | size_t dtlb_sets, |
---|
| 619 | size_t icache_ways, |
---|
| 620 | size_t icache_sets, |
---|
| 621 | size_t icache_words, |
---|
| 622 | size_t dcache_ways, |
---|
| 623 | size_t dcache_sets, |
---|
| 624 | size_t dcache_words, |
---|
| 625 | size_t wbuf_nlines, |
---|
| 626 | size_t wbuf_nwords, |
---|
| 627 | uint32_t max_frozen_cycles, |
---|
| 628 | uint32_t debug_start_cycle, |
---|
| 629 | bool debug_ok); |
---|
| 630 | |
---|
| 631 | ~VciCcVCacheWrapperV4(); |
---|
| 632 | |
---|
| 633 | void print_cpi(); |
---|
| 634 | void print_stats(); |
---|
| 635 | void clear_stats(); |
---|
| 636 | void print_trace(size_t mode = 0); |
---|
| 637 | void cache_monitor(paddr_t addr); |
---|
[214] | 638 | inline void iss_set_debug_mask(uint v) { |
---|
| 639 | r_iss.set_debug_mask(v); |
---|
| 640 | } |
---|
[183] | 641 | |
---|
| 642 | private: |
---|
| 643 | void transition(); |
---|
| 644 | void genMoore(); |
---|
| 645 | |
---|
| 646 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
---|
| 647 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
---|
| 648 | }; |
---|
| 649 | |
---|
| 650 | }} |
---|
| 651 | |
---|
| 652 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ |
---|
| 653 | |
---|
| 654 | // Local Variables: |
---|
| 655 | // tab-width: 4 |
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| 656 | // c-basic-offset: 4 |
---|
| 657 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 658 | // indent-tabs-mode: nil |
---|
| 659 | // End: |
---|
| 660 | |
---|
| 661 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 662 | |
---|
| 663 | |
---|
| 664 | |
---|
| 665 | |
---|