[183] | 1 | /* -*- c++ -*- |
---|
| 2 | * File : vci_cc_vcache_wrapper_v4.h |
---|
| 3 | * Copyright (c) UPMC, Lip6, SoC |
---|
| 4 | * Authors : Alain GREINER, Yang GAO |
---|
| 5 | * Date : 27/11/2011 |
---|
| 6 | * |
---|
| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
---|
| 8 | * |
---|
| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
---|
| 10 | * |
---|
| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
---|
| 12 | * under the terms of the GNU Lesser General Public License as published |
---|
| 13 | * by the Free Software Foundation; version 2.1 of the License. |
---|
| 14 | * |
---|
| 15 | * SoCLib is distributed in the hope that it will be useful, but |
---|
| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
| 18 | * Lesser General Public License for more details. |
---|
| 19 | * |
---|
| 20 | * You should have received a copy of the GNU Lesser General Public |
---|
| 21 | * License along with SoCLib; if not, write to the Free Software |
---|
| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
---|
| 23 | * 02110-1301 USA |
---|
| 24 | * |
---|
| 25 | * SOCLIB_LGPL_HEADER_END |
---|
| 26 | */ |
---|
| 27 | |
---|
| 28 | #ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H |
---|
| 29 | #define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H |
---|
| 30 | |
---|
| 31 | #include <inttypes.h> |
---|
| 32 | #include <systemc> |
---|
| 33 | #include "caba_base_module.h" |
---|
| 34 | #include "multi_write_buffer.h" |
---|
| 35 | #include "generic_fifo.h" |
---|
| 36 | #include "generic_tlb.h" |
---|
[204] | 37 | #include "generic_cache.h" |
---|
[183] | 38 | #include "generic_cam.h" |
---|
[291] | 39 | #include "generic_llsc_local_table.h" |
---|
[183] | 40 | #include "vci_initiator.h" |
---|
| 41 | #include "vci_target.h" |
---|
| 42 | #include "mapping_table.h" |
---|
| 43 | #include "static_assert.h" |
---|
| 44 | #include "iss2.h" |
---|
| 45 | |
---|
| 46 | namespace soclib { |
---|
| 47 | namespace caba { |
---|
| 48 | |
---|
| 49 | using namespace sc_core; |
---|
| 50 | |
---|
| 51 | //////////////////////////////////////////// |
---|
| 52 | template<typename vci_param, typename iss_t> |
---|
| 53 | class VciCcVCacheWrapperV4 |
---|
| 54 | //////////////////////////////////////////// |
---|
| 55 | : public soclib::caba::BaseModule |
---|
| 56 | { |
---|
| 57 | typedef uint32_t vaddr_t; |
---|
| 58 | typedef uint32_t tag_t; |
---|
| 59 | typedef uint32_t type_t; |
---|
| 60 | typedef typename iss_t::DataOperationType data_op_t; |
---|
| 61 | |
---|
| 62 | typedef typename vci_param::addr_t paddr_t; |
---|
[291] | 63 | typedef typename vci_param::data_t vci_data_t; |
---|
[183] | 64 | typedef typename vci_param::be_t vci_be_t; |
---|
| 65 | typedef typename vci_param::srcid_t vci_srcid_t; |
---|
| 66 | typedef typename vci_param::trdid_t vci_trdid_t; |
---|
| 67 | typedef typename vci_param::pktid_t vci_pktid_t; |
---|
| 68 | typedef typename vci_param::plen_t vci_plen_t; |
---|
| 69 | |
---|
| 70 | enum icache_fsm_state_e { |
---|
| 71 | ICACHE_IDLE, |
---|
| 72 | // handling XTN processor requests |
---|
| 73 | ICACHE_XTN_TLB_FLUSH, |
---|
| 74 | ICACHE_XTN_CACHE_FLUSH, |
---|
| 75 | ICACHE_XTN_TLB_INVAL, |
---|
| 76 | ICACHE_XTN_CACHE_INVAL_VA, |
---|
| 77 | ICACHE_XTN_CACHE_INVAL_PA, |
---|
| 78 | ICACHE_XTN_CACHE_INVAL_GO, |
---|
| 79 | // handling tlb miss |
---|
| 80 | ICACHE_TLB_WAIT, |
---|
| 81 | // handling cache miss |
---|
| 82 | ICACHE_MISS_VICTIM, |
---|
| 83 | ICACHE_MISS_INVAL, |
---|
| 84 | ICACHE_MISS_WAIT, |
---|
| 85 | ICACHE_MISS_UPDT, |
---|
| 86 | // handling unc read |
---|
| 87 | ICACHE_UNC_WAIT, |
---|
| 88 | // handling coherence requests |
---|
| 89 | ICACHE_CC_CHECK, |
---|
| 90 | ICACHE_CC_INVAL, |
---|
| 91 | ICACHE_CC_UPDT, |
---|
| 92 | }; |
---|
| 93 | |
---|
| 94 | enum dcache_fsm_state_e { |
---|
| 95 | DCACHE_IDLE, |
---|
| 96 | // handling itlb & dtlb miss |
---|
| 97 | DCACHE_TLB_MISS, |
---|
| 98 | DCACHE_TLB_PTE1_GET, |
---|
| 99 | DCACHE_TLB_PTE1_SELECT, |
---|
| 100 | DCACHE_TLB_PTE1_UPDT, |
---|
| 101 | DCACHE_TLB_PTE2_GET, |
---|
| 102 | DCACHE_TLB_PTE2_SELECT, |
---|
| 103 | DCACHE_TLB_PTE2_UPDT, |
---|
[205] | 104 | DCACHE_TLB_LR_UPDT, |
---|
| 105 | DCACHE_TLB_LR_WAIT, |
---|
[183] | 106 | DCACHE_TLB_RETURN, |
---|
| 107 | // handling processor XTN requests |
---|
| 108 | DCACHE_XTN_SWITCH, |
---|
| 109 | DCACHE_XTN_SYNC, |
---|
| 110 | DCACHE_XTN_IC_INVAL_VA, |
---|
| 111 | DCACHE_XTN_IC_FLUSH, |
---|
| 112 | DCACHE_XTN_IC_INVAL_PA, |
---|
| 113 | DCACHE_XTN_IT_INVAL, |
---|
| 114 | DCACHE_XTN_DC_FLUSH, |
---|
| 115 | DCACHE_XTN_DC_INVAL_VA, |
---|
| 116 | DCACHE_XTN_DC_INVAL_PA, |
---|
[204] | 117 | DCACHE_XTN_DC_INVAL_END, |
---|
[183] | 118 | DCACHE_XTN_DC_INVAL_GO, |
---|
| 119 | DCACHE_XTN_DT_INVAL, |
---|
[206] | 120 | //handling dirty bit update |
---|
| 121 | DCACHE_DIRTY_GET_PTE, |
---|
[284] | 122 | DCACHE_DIRTY_WAIT, |
---|
[204] | 123 | // handling processor miss requests |
---|
[183] | 124 | DCACHE_MISS_VICTIM, |
---|
| 125 | DCACHE_MISS_INVAL, |
---|
| 126 | DCACHE_MISS_WAIT, |
---|
| 127 | DCACHE_MISS_UPDT, |
---|
[291] | 128 | // handling processor unc, ll and sc requests |
---|
[183] | 129 | DCACHE_UNC_WAIT, |
---|
[291] | 130 | DCACHE_LL_WAIT, |
---|
[205] | 131 | DCACHE_SC_WAIT, |
---|
[183] | 132 | // handling coherence requests |
---|
| 133 | DCACHE_CC_CHECK, |
---|
| 134 | DCACHE_CC_INVAL, |
---|
| 135 | DCACHE_CC_UPDT, |
---|
[204] | 136 | // handling TLB inval (after a coherence or XTN request) |
---|
| 137 | DCACHE_INVAL_TLB_SCAN, |
---|
[183] | 138 | }; |
---|
| 139 | |
---|
| 140 | enum cmd_fsm_state_e { |
---|
| 141 | CMD_IDLE, |
---|
| 142 | CMD_INS_MISS, |
---|
| 143 | CMD_INS_UNC, |
---|
| 144 | CMD_DATA_MISS, |
---|
| 145 | CMD_DATA_UNC, |
---|
| 146 | CMD_DATA_WRITE, |
---|
[291] | 147 | CMD_DATA_LL, |
---|
| 148 | CMD_DATA_SC, |
---|
[284] | 149 | CMD_DATA_CAS, |
---|
[183] | 150 | }; |
---|
| 151 | |
---|
| 152 | enum rsp_fsm_state_e { |
---|
| 153 | RSP_IDLE, |
---|
| 154 | RSP_INS_MISS, |
---|
| 155 | RSP_INS_UNC, |
---|
| 156 | RSP_DATA_MISS, |
---|
| 157 | RSP_DATA_UNC, |
---|
[291] | 158 | RSP_DATA_LL, |
---|
[183] | 159 | RSP_DATA_WRITE, |
---|
| 160 | }; |
---|
| 161 | |
---|
| 162 | enum cleanup_cmd_fsm_state_e { |
---|
| 163 | CLEANUP_DATA_IDLE, |
---|
| 164 | CLEANUP_DATA_GO, |
---|
| 165 | CLEANUP_INS_IDLE, |
---|
| 166 | CLEANUP_INS_GO, |
---|
| 167 | }; |
---|
| 168 | |
---|
| 169 | enum tgt_fsm_state_e { |
---|
| 170 | TGT_IDLE, |
---|
| 171 | TGT_UPDT_WORD, |
---|
| 172 | TGT_UPDT_DATA, |
---|
| 173 | TGT_REQ_BROADCAST, |
---|
| 174 | TGT_REQ_ICACHE, |
---|
| 175 | TGT_REQ_DCACHE, |
---|
| 176 | TGT_RSP_BROADCAST, |
---|
| 177 | TGT_RSP_ICACHE, |
---|
| 178 | TGT_RSP_DCACHE, |
---|
| 179 | }; |
---|
| 180 | |
---|
[284] | 181 | /* transaction type, pktid field */ |
---|
| 182 | enum transaction_type_e |
---|
| 183 | { |
---|
| 184 | // b3 unused |
---|
| 185 | // b2 READ / NOT READ |
---|
| 186 | // Si READ |
---|
| 187 | // b1 DATA / INS |
---|
| 188 | // b0 UNC / MISS |
---|
| 189 | // Si NOT READ |
---|
| 190 | // b1 accÚs table llsc type SW / other |
---|
| 191 | // b2 WRITE/CAS/LL/SC |
---|
| 192 | TYPE_READ_DATA_UNC = 0x0, |
---|
| 193 | TYPE_READ_DATA_MISS = 0x1, |
---|
| 194 | TYPE_READ_INS_UNC = 0x2, |
---|
| 195 | TYPE_READ_INS_MISS = 0x3, |
---|
| 196 | TYPE_WRITE = 0x4, |
---|
| 197 | TYPE_CAS = 0x5, |
---|
| 198 | TYPE_LL = 0x6, |
---|
| 199 | TYPE_SC = 0x7 |
---|
| 200 | }; |
---|
| 201 | |
---|
| 202 | /* SC return values */ |
---|
| 203 | enum sc_status_type_e |
---|
| 204 | { |
---|
| 205 | SC_SUCCESS = 0x00000000, |
---|
| 206 | SC_FAIL = 0x00000001 |
---|
| 207 | }; |
---|
| 208 | /* |
---|
| 209 | this is already in vci_param.h |
---|
| 210 | enum { |
---|
| 211 | STORE_COND_ATOMIC = 0, |
---|
| 212 | STORE_COND_NOT_ATOMIC = 1, |
---|
| 213 | }; |
---|
| 214 | */ |
---|
| 215 | |
---|
[183] | 216 | // TLB Mode : ITLB / DTLB / ICACHE / DCACHE |
---|
| 217 | enum { |
---|
| 218 | INS_TLB_MASK = 0x8, |
---|
| 219 | DATA_TLB_MASK = 0x4, |
---|
| 220 | INS_CACHE_MASK = 0x2, |
---|
| 221 | DATA_CACHE_MASK = 0x1, |
---|
| 222 | }; |
---|
| 223 | |
---|
| 224 | // Error Type |
---|
| 225 | enum mmu_error_type_e |
---|
| 226 | { |
---|
| 227 | MMU_NONE = 0x0000, // None |
---|
| 228 | MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write access of Page fault on Page Table 1 |
---|
| 229 | MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write access of Page fault on Page Table 2 |
---|
| 230 | MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode |
---|
| 231 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page |
---|
| 232 | MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write access of undefined external access address |
---|
| 233 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 |
---|
| 234 | MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write access of Bus Error accessing Table 2 |
---|
| 235 | MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access |
---|
| 236 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 |
---|
| 237 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 |
---|
| 238 | MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read access of Protected access in user mode |
---|
| 239 | MMU_READ_EXEC_VIOLATION = 0x1010, // Exec access to a non exec page |
---|
| 240 | MMU_READ_UNDEFINED_XTN = 0x1020, // Read access of Undefined external access address |
---|
| 241 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access |
---|
| 242 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access |
---|
| 243 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access |
---|
| 244 | }; |
---|
| 245 | |
---|
| 246 | // miss types for data cache |
---|
| 247 | enum dcache_miss_type_e |
---|
| 248 | { |
---|
| 249 | PTE1_MISS, |
---|
| 250 | PTE2_MISS, |
---|
| 251 | PROC_MISS, |
---|
| 252 | }; |
---|
| 253 | |
---|
| 254 | enum transaction_type_d_e |
---|
| 255 | { |
---|
| 256 | // b0 : 1 if cached |
---|
| 257 | // b1 : 1 if instruction |
---|
| 258 | TYPE_DATA_UNC = 0x0, |
---|
| 259 | TYPE_DATA_MISS = 0x1, |
---|
| 260 | TYPE_INS_UNC = 0x2, |
---|
| 261 | TYPE_INS_MISS = 0x3, |
---|
| 262 | }; |
---|
| 263 | |
---|
| 264 | public: |
---|
| 265 | sc_in<bool> p_clk; |
---|
| 266 | sc_in<bool> p_resetn; |
---|
| 267 | sc_in<bool> p_irq[iss_t::n_irq]; |
---|
| 268 | soclib::caba::VciInitiator<vci_param> p_vci_ini_d; |
---|
| 269 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
---|
| 270 | soclib::caba::VciTarget<vci_param> p_vci_tgt_c; |
---|
| 271 | |
---|
| 272 | private: |
---|
| 273 | |
---|
| 274 | // STRUCTURAL PARAMETERS |
---|
| 275 | soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; |
---|
| 276 | const soclib::common::Segment m_segment; |
---|
| 277 | const vci_srcid_t m_srcid_d; |
---|
| 278 | const vci_srcid_t m_srcid_c; |
---|
| 279 | |
---|
| 280 | const size_t m_itlb_ways; |
---|
| 281 | const size_t m_itlb_sets; |
---|
| 282 | |
---|
| 283 | const size_t m_dtlb_ways; |
---|
| 284 | const size_t m_dtlb_sets; |
---|
| 285 | |
---|
| 286 | const size_t m_icache_ways; |
---|
| 287 | const size_t m_icache_sets; |
---|
| 288 | const paddr_t m_icache_yzmask; |
---|
| 289 | const size_t m_icache_words; |
---|
| 290 | |
---|
| 291 | const size_t m_dcache_ways; |
---|
| 292 | const size_t m_dcache_sets; |
---|
| 293 | const paddr_t m_dcache_yzmask; |
---|
| 294 | const size_t m_dcache_words; |
---|
| 295 | |
---|
[247] | 296 | const size_t m_x_width; |
---|
| 297 | const size_t m_y_width; |
---|
| 298 | |
---|
| 299 | const size_t m_memory_cache_local_id; |
---|
| 300 | |
---|
[202] | 301 | const size_t m_proc_id; |
---|
| 302 | |
---|
[183] | 303 | const uint32_t m_max_frozen_cycles; |
---|
| 304 | |
---|
| 305 | const size_t m_paddr_nbits; |
---|
| 306 | |
---|
| 307 | //////////////////////////////////////// |
---|
[205] | 308 | // Communication with processor ISS |
---|
[183] | 309 | //////////////////////////////////////// |
---|
[205] | 310 | typename iss_t::InstructionRequest m_ireq; |
---|
| 311 | typename iss_t::InstructionResponse m_irsp; |
---|
| 312 | typename iss_t::DataRequest m_dreq; |
---|
| 313 | typename iss_t::DataResponse m_drsp; |
---|
[183] | 314 | |
---|
| 315 | ///////////////////////////////////////////// |
---|
| 316 | // debug variables (for each FSM) |
---|
| 317 | ///////////////////////////////////////////// |
---|
[206] | 318 | uint32_t m_debug_start_cycle; |
---|
| 319 | bool m_debug_ok; |
---|
| 320 | bool m_debug_previous_hit; |
---|
[211] | 321 | bool m_idebug_previous_hit; |
---|
[206] | 322 | bool m_debug_dcache_fsm; |
---|
| 323 | bool m_debug_icache_fsm; |
---|
| 324 | bool m_debug_cleanup_fsm; |
---|
| 325 | bool m_debug_inval_itlb_fsm; |
---|
| 326 | bool m_debug_inval_dtlb_fsm; |
---|
[183] | 327 | |
---|
| 328 | /////////////////////////////// |
---|
| 329 | // Software visible REGISTERS |
---|
| 330 | /////////////////////////////// |
---|
| 331 | sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register |
---|
| 332 | sc_signal<uint32_t> r_mmu_mode; // mmu mode register |
---|
| 333 | sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low |
---|
| 334 | sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight |
---|
| 335 | sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address |
---|
| 336 | sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address |
---|
| 337 | sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type |
---|
| 338 | sc_signal<uint32_t> r_mmu_detr; // mmu data error type |
---|
[203] | 339 | uint32_t r_mmu_params; // read-only |
---|
| 340 | uint32_t r_mmu_release; // read_only |
---|
[183] | 341 | |
---|
| 342 | |
---|
| 343 | ////////////////////////////// |
---|
| 344 | // ICACHE FSM REGISTERS |
---|
| 345 | ////////////////////////////// |
---|
| 346 | sc_signal<int> r_icache_fsm; // state register |
---|
| 347 | sc_signal<int> r_icache_fsm_save; // return state for coherence operation |
---|
| 348 | sc_signal<paddr_t> r_icache_vci_paddr; // physical address |
---|
| 349 | sc_signal<uint32_t> r_icache_vaddr_save; // virtual address requested by the processor |
---|
| 350 | |
---|
| 351 | // icache miss handling |
---|
| 352 | sc_signal<size_t> r_icache_miss_way; // selected way for cache update |
---|
| 353 | sc_signal<size_t> r_icache_miss_set; // selected set for cache update |
---|
| 354 | sc_signal<size_t> r_icache_miss_word; // word index for sequencial cache update |
---|
| 355 | sc_signal<bool> r_icache_miss_inval; // coherence request matching a pending miss |
---|
| 356 | |
---|
| 357 | // coherence request handling |
---|
| 358 | sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval |
---|
| 359 | sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval |
---|
| 360 | sc_signal<size_t> r_icache_cc_word; // word counter for cc update |
---|
| 361 | |
---|
| 362 | // icache flush handling |
---|
| 363 | sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush |
---|
| 364 | |
---|
| 365 | // communication between ICACHE FSM and VCI_CMD FSM |
---|
| 366 | sc_signal<bool> r_icache_miss_req; // cached read miss |
---|
| 367 | sc_signal<bool> r_icache_unc_req; // uncached read miss |
---|
| 368 | |
---|
| 369 | // communication between ICACHE FSM and DCACHE FSM |
---|
| 370 | sc_signal<bool> r_icache_tlb_miss_req; // itlb miss request (set icache/reset dcache) |
---|
| 371 | sc_signal<bool> r_icache_tlb_rsp_error; // itlb miss response error (written by dcache) |
---|
| 372 | |
---|
| 373 | // communication between ICACHE FSM and CLEANUP FSMs |
---|
| 374 | sc_signal<bool> r_icache_cleanup_req; // ins cleanup request |
---|
| 375 | sc_signal<paddr_t> r_icache_cleanup_line; // ins cleanup NLINE |
---|
| 376 | |
---|
| 377 | /////////////////////////////// |
---|
| 378 | // DCACHE FSM REGISTERS |
---|
| 379 | /////////////////////////////// |
---|
| 380 | sc_signal<int> r_dcache_fsm; // state register |
---|
[217] | 381 | sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence operation |
---|
| 382 | sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan operation |
---|
[183] | 383 | // registers written in P0 stage (used in P1 stage) |
---|
| 384 | sc_signal<bool> r_dcache_p0_valid; // P1 pipeline stage must be executed |
---|
| 385 | sc_signal<uint32_t> r_dcache_p0_vaddr; // virtual address (from proc) |
---|
| 386 | sc_signal<uint32_t> r_dcache_p0_wdata; // write data (from proc) |
---|
| 387 | sc_signal<vci_be_t> r_dcache_p0_be; // byte enable (from proc) |
---|
| 388 | sc_signal<paddr_t> r_dcache_p0_paddr; // physical address |
---|
| 389 | sc_signal<bool> r_dcache_p0_cacheable; // address cacheable |
---|
| 390 | // registers written in P1 stage (used in P2 stage) |
---|
| 391 | sc_signal<bool> r_dcache_p1_valid; // P2 pipeline stage must be executed |
---|
| 392 | sc_signal<uint32_t> r_dcache_p1_wdata; // write data (from proc) |
---|
| 393 | sc_signal<vci_be_t> r_dcache_p1_be; // byte enable (from proc) |
---|
| 394 | sc_signal<paddr_t> r_dcache_p1_paddr; // physical address |
---|
| 395 | sc_signal<size_t> r_dcache_p1_cache_way; // selected way (from dcache) |
---|
| 396 | sc_signal<size_t> r_dcache_p1_cache_set; // selected set (from dcache) |
---|
| 397 | sc_signal<size_t> r_dcache_p1_cache_word; // selected word (from dcache) |
---|
[206] | 398 | // registers used by the Dirty bit sub-fsm |
---|
| 399 | sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address |
---|
| 400 | sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache |
---|
| 401 | sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache |
---|
| 402 | |
---|
[183] | 403 | // communication between DCACHE FSM and VCI_CMD FSM |
---|
| 404 | sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command |
---|
| 405 | sc_signal<bool> r_dcache_vci_miss_req; // read miss request |
---|
| 406 | sc_signal<bool> r_dcache_vci_unc_req; // uncacheable read request |
---|
| 407 | sc_signal<bool> r_dcache_vci_unc_be; // uncacheable read byte enable |
---|
[291] | 408 | sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS |
---|
| 409 | sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for an atomic write CAS |
---|
| 410 | sc_signal<uint32_t> r_dcache_vci_cas_new; // new data value for an atomic write CAS |
---|
| 411 | sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL |
---|
| 412 | sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC |
---|
| 413 | sc_signal<vci_data_t> r_dcache_vci_sc_data; // SC data (command) |
---|
[183] | 414 | |
---|
| 415 | // register used for XTN inval |
---|
| 416 | sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) |
---|
| 417 | sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) |
---|
| 418 | |
---|
| 419 | // write buffer state extension |
---|
| 420 | sc_signal<bool> r_dcache_pending_unc_write; // pending uncacheable write in WBUF |
---|
| 421 | |
---|
| 422 | // handling dcache miss |
---|
[205] | 423 | sc_signal<int> r_dcache_miss_type; // type of miss depending on the requester |
---|
[183] | 424 | sc_signal<size_t> r_dcache_miss_word; // word index for sequencial cache update |
---|
| 425 | sc_signal<size_t> r_dcache_miss_way; // selected way for cache update |
---|
| 426 | sc_signal<size_t> r_dcache_miss_set; // selected set for cache update |
---|
| 427 | sc_signal<bool> r_dcache_miss_inval; // coherence request matching a pending miss |
---|
| 428 | |
---|
| 429 | // handling coherence requests |
---|
| 430 | sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval |
---|
| 431 | sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval |
---|
| 432 | sc_signal<size_t> r_dcache_cc_word; // word counter for cc update |
---|
| 433 | |
---|
| 434 | // dcache flush handling |
---|
| 435 | sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush |
---|
| 436 | |
---|
[291] | 437 | // ll rsp handling |
---|
| 438 | sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp |
---|
| 439 | |
---|
| 440 | // sc cmd handling |
---|
| 441 | sc_signal<vci_data_t> r_sc_key; // SC key returned by local table |
---|
| 442 | |
---|
[183] | 443 | // used by the TLB miss sub-fsm |
---|
| 444 | sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss |
---|
| 445 | sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) |
---|
| 446 | sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte |
---|
| 447 | sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 |
---|
| 448 | sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 |
---|
| 449 | sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache |
---|
| 450 | sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache |
---|
| 451 | sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache |
---|
| 452 | sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb |
---|
| 453 | sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb |
---|
| 454 | |
---|
[204] | 455 | // ITLB and DTLB invalidation |
---|
[183] | 456 | sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index |
---|
[204] | 457 | sc_signal<size_t> r_dcache_tlb_inval_count; // tlb entry counter |
---|
[183] | 458 | |
---|
| 459 | // communication between DCACHE FSM and ICACHE FSM |
---|
| 460 | sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor) |
---|
| 461 | sc_signal<int> r_dcache_xtn_opcode; // xtn request type |
---|
| 462 | |
---|
| 463 | // communication between DCACHE FSM and CLEANUP FSMs |
---|
| 464 | sc_signal<bool> r_dcache_cleanup_req; // data cleanup request |
---|
| 465 | sc_signal<paddr_t> r_dcache_cleanup_line; // data cleanup NLINE |
---|
| 466 | |
---|
| 467 | // dcache directory extension |
---|
[206] | 468 | bool *r_dcache_in_tlb; // copy exist in dtlb or itlb |
---|
| 469 | bool *r_dcache_contains_ptd; // cache line contains a PTD |
---|
[183] | 470 | |
---|
| 471 | /////////////////////////////////// |
---|
| 472 | // VCI_CMD FSM REGISTERS |
---|
| 473 | /////////////////////////////////// |
---|
| 474 | sc_signal<int> r_vci_cmd_fsm; |
---|
| 475 | sc_signal<size_t> r_vci_cmd_min; // used for write bursts |
---|
| 476 | sc_signal<size_t> r_vci_cmd_max; // used for write bursts |
---|
| 477 | sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts |
---|
| 478 | sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss |
---|
| 479 | |
---|
| 480 | /////////////////////////////////// |
---|
| 481 | // VCI_RSP FSM REGISTERS |
---|
| 482 | /////////////////////////////////// |
---|
| 483 | sc_signal<int> r_vci_rsp_fsm; |
---|
| 484 | sc_signal<size_t> r_vci_rsp_cpt; |
---|
| 485 | sc_signal<bool> r_vci_rsp_ins_error; |
---|
| 486 | sc_signal<bool> r_vci_rsp_data_error; |
---|
| 487 | GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM |
---|
| 488 | GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM |
---|
| 489 | |
---|
| 490 | /////////////////////////////////// |
---|
| 491 | // CLEANUP FSM REGISTER |
---|
| 492 | /////////////////////////////////// |
---|
| 493 | sc_signal<int> r_cleanup_fsm; // state register |
---|
| 494 | sc_signal<size_t> r_cleanup_trdid; // to clear the registration buffer |
---|
| 495 | GenericCam<paddr_t> r_cleanup_buffer; // Registration buffer for cleanups |
---|
| 496 | |
---|
| 497 | /////////////////////////////////// |
---|
| 498 | // TGT FSM REGISTERS |
---|
| 499 | /////////////////////////////////// |
---|
| 500 | sc_signal<int> r_tgt_fsm; // state register |
---|
| 501 | sc_signal<paddr_t> r_tgt_paddr; // cache line physical address |
---|
| 502 | sc_signal<size_t> r_tgt_word_count; // word index |
---|
| 503 | sc_signal<size_t> r_tgt_word_min; // index of the first word to be updated |
---|
| 504 | sc_signal<size_t> r_tgt_word_max; // index of the last word to be updated |
---|
| 505 | sc_signal<bool> r_tgt_update; // update request |
---|
| 506 | sc_signal<bool> r_tgt_update_data; // update data request |
---|
| 507 | sc_signal<vci_srcid_t> r_tgt_srcid; |
---|
| 508 | sc_signal<vci_pktid_t> r_tgt_pktid; |
---|
| 509 | sc_signal<vci_trdid_t> r_tgt_trdid; |
---|
| 510 | |
---|
| 511 | // communications between TGT FSM and DCACHE/ICACHE FSMs |
---|
| 512 | sc_signal<bool> r_tgt_icache_req; // coherence request (set by tgt) |
---|
| 513 | sc_signal<bool> r_tgt_dcache_req; // coherence request (set by tgt) |
---|
| 514 | sc_signal<bool> r_tgt_icache_rsp; // coherence response (set by icache) |
---|
| 515 | sc_signal<bool> r_tgt_dcache_rsp; // coherence response (set by dcache) |
---|
| 516 | |
---|
| 517 | uint32_t *r_tgt_buf; // cache line word buffer |
---|
| 518 | vci_be_t *r_tgt_be; // cache line be buffer |
---|
| 519 | |
---|
| 520 | ////////////////////////////////////////////////////////////////// |
---|
| 521 | // processor, write buffer, caches , TLBs and CAM for cleanups |
---|
| 522 | ////////////////////////////////////////////////////////////////// |
---|
| 523 | iss_t r_iss; |
---|
| 524 | MultiWriteBuffer<paddr_t> r_wbuf; |
---|
| 525 | GenericCache<paddr_t> r_icache; |
---|
| 526 | GenericCache<paddr_t> r_dcache; |
---|
| 527 | GenericTlb<paddr_t> r_itlb; |
---|
| 528 | GenericTlb<paddr_t> r_dtlb; |
---|
| 529 | |
---|
[291] | 530 | ////////////////////////////////////////////////////////////////// |
---|
| 531 | // llsc local registration table |
---|
| 532 | ////////////////////////////////////////////////////////////////// |
---|
| 533 | |
---|
| 534 | #define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t> |
---|
| 535 | LLSCLocalTable r_llsc_table; // The llsc local registration table |
---|
| 536 | |
---|
| 537 | typename LLSCLocalTable::in_t table_in ; // llsc local table input signals |
---|
| 538 | typename LLSCLocalTable::out_t table_out ; // llsc local table output signals |
---|
| 539 | |
---|
| 540 | #undef LLSCLocalTable |
---|
| 541 | |
---|
[183] | 542 | //////////////////////////////// |
---|
| 543 | // Activity counters |
---|
| 544 | //////////////////////////////// |
---|
| 545 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
---|
| 546 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
---|
| 547 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
---|
| 548 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
---|
| 549 | |
---|
| 550 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
---|
| 551 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
---|
| 552 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
---|
| 553 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
---|
| 554 | |
---|
| 555 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
---|
| 556 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
| 557 | |
---|
| 558 | // Cache activity counters |
---|
| 559 | uint32_t m_cpt_data_read; // total number of read data |
---|
| 560 | uint32_t m_cpt_data_write; // total number of write data |
---|
| 561 | uint32_t m_cpt_data_miss; // number of read miss |
---|
| 562 | uint32_t m_cpt_ins_miss; // number of instruction miss |
---|
| 563 | uint32_t m_cpt_unc_read; // number of read uncached |
---|
| 564 | uint32_t m_cpt_write_cached; // number of cached write |
---|
| 565 | uint32_t m_cpt_ins_read; // number of instruction read |
---|
| 566 | uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss |
---|
| 567 | |
---|
| 568 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
---|
| 569 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
---|
| 570 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
---|
| 571 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
---|
| 572 | |
---|
| 573 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
---|
| 574 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
---|
| 575 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
---|
| 576 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
---|
| 577 | uint32_t m_cpt_icache_unc_transaction; |
---|
| 578 | |
---|
| 579 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
---|
| 580 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
---|
| 581 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
---|
| 582 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
---|
| 583 | uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions |
---|
| 584 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
---|
| 585 | |
---|
| 586 | // TLB activity counters |
---|
| 587 | uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read |
---|
| 588 | uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss |
---|
| 589 | uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update |
---|
| 590 | uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line |
---|
| 591 | uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache |
---|
| 592 | |
---|
| 593 | uint32_t m_cpt_data_tlb_read; // number of data tlb read |
---|
| 594 | uint32_t m_cpt_data_tlb_miss; // number of data tlb miss |
---|
| 595 | uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update |
---|
| 596 | uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty |
---|
| 597 | uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache |
---|
| 598 | uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line |
---|
| 599 | uint32_t m_cpt_tlb_occup_dcache; |
---|
| 600 | |
---|
| 601 | uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss |
---|
| 602 | uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss |
---|
| 603 | uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc |
---|
| 604 | uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc |
---|
| 605 | uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty |
---|
| 606 | uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache |
---|
| 607 | uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache |
---|
| 608 | |
---|
| 609 | uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions |
---|
| 610 | uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions |
---|
| 611 | uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions |
---|
| 612 | uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions |
---|
| 613 | uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions |
---|
| 614 | uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions |
---|
| 615 | uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions |
---|
| 616 | uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions |
---|
| 617 | |
---|
| 618 | uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions |
---|
| 619 | uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions |
---|
| 620 | uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions |
---|
| 621 | uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions |
---|
| 622 | uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions |
---|
| 623 | uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions |
---|
| 624 | uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions |
---|
| 625 | uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions |
---|
| 626 | |
---|
| 627 | // coherence activity counters |
---|
| 628 | uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands |
---|
| 629 | uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands |
---|
| 630 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands |
---|
| 631 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands |
---|
| 632 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands |
---|
| 633 | |
---|
| 634 | uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets |
---|
| 635 | uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets |
---|
| 636 | uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets |
---|
| 637 | uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets |
---|
| 638 | |
---|
| 639 | uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets |
---|
| 640 | uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets |
---|
| 641 | |
---|
| 642 | uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions |
---|
| 643 | uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions |
---|
| 644 | uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions |
---|
| 645 | uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions |
---|
| 646 | |
---|
| 647 | uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate |
---|
| 648 | uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate |
---|
| 649 | |
---|
| 650 | uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate |
---|
| 651 | uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate |
---|
| 652 | |
---|
| 653 | // FSM activity counters |
---|
| 654 | uint32_t m_cpt_fsm_icache [64]; |
---|
| 655 | uint32_t m_cpt_fsm_dcache [64]; |
---|
| 656 | uint32_t m_cpt_fsm_cmd [64]; |
---|
| 657 | uint32_t m_cpt_fsm_rsp [64]; |
---|
| 658 | uint32_t m_cpt_fsm_tgt [64]; |
---|
| 659 | uint32_t m_cpt_fsm_cmd_cleanup[64]; |
---|
| 660 | uint32_t m_cpt_fsm_rsp_cleanup[64]; |
---|
| 661 | |
---|
| 662 | uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen |
---|
| 663 | |
---|
| 664 | protected: |
---|
| 665 | SC_HAS_PROCESS(VciCcVCacheWrapperV4); |
---|
| 666 | |
---|
| 667 | public: |
---|
| 668 | VciCcVCacheWrapperV4( |
---|
| 669 | sc_module_name insname, |
---|
| 670 | int proc_id, |
---|
| 671 | const soclib::common::MappingTable &mtp, |
---|
| 672 | const soclib::common::MappingTable &mtc, |
---|
| 673 | const soclib::common::IntTab &initiator_index_d, |
---|
| 674 | const soclib::common::IntTab &initiator_index_c, |
---|
| 675 | const soclib::common::IntTab &target_index_d, |
---|
| 676 | size_t itlb_ways, |
---|
| 677 | size_t itlb_sets, |
---|
| 678 | size_t dtlb_ways, |
---|
| 679 | size_t dtlb_sets, |
---|
| 680 | size_t icache_ways, |
---|
| 681 | size_t icache_sets, |
---|
| 682 | size_t icache_words, |
---|
| 683 | size_t dcache_ways, |
---|
| 684 | size_t dcache_sets, |
---|
| 685 | size_t dcache_words, |
---|
| 686 | size_t wbuf_nlines, |
---|
| 687 | size_t wbuf_nwords, |
---|
[247] | 688 | size_t x_width, |
---|
| 689 | size_t y_width, |
---|
| 690 | uint32_t memory_cache_local_id, |
---|
[183] | 691 | uint32_t max_frozen_cycles, |
---|
| 692 | uint32_t debug_start_cycle, |
---|
| 693 | bool debug_ok); |
---|
| 694 | |
---|
| 695 | ~VciCcVCacheWrapperV4(); |
---|
| 696 | |
---|
| 697 | void print_cpi(); |
---|
| 698 | void print_stats(); |
---|
| 699 | void clear_stats(); |
---|
| 700 | void print_trace(size_t mode = 0); |
---|
| 701 | void cache_monitor(paddr_t addr); |
---|
[214] | 702 | inline void iss_set_debug_mask(uint v) { |
---|
| 703 | r_iss.set_debug_mask(v); |
---|
| 704 | } |
---|
[183] | 705 | |
---|
| 706 | private: |
---|
| 707 | void transition(); |
---|
| 708 | void genMoore(); |
---|
| 709 | |
---|
| 710 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
---|
| 711 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
---|
| 712 | }; |
---|
| 713 | |
---|
| 714 | }} |
---|
| 715 | |
---|
| 716 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ |
---|
| 717 | |
---|
| 718 | // Local Variables: |
---|
| 719 | // tab-width: 4 |
---|
| 720 | // c-basic-offset: 4 |
---|
| 721 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 722 | // indent-tabs-mode: nil |
---|
| 723 | // End: |
---|
| 724 | |
---|
| 725 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 726 | |
---|
| 727 | |
---|
| 728 | |
---|
| 729 | |
---|