[183] | 1 | /* -*- c++ -*-C |
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| 2 | * File : vci_cc_vcache_wrapper_v4.cpp |
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| 3 | * Copyright (c) UPMC, Lip6, SoC |
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| 4 | * Authors : Alain GREINER, Yang GAO |
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| 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 7 | * |
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| 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 9 | * |
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| 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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| 13 | * |
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| 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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| 23 | * |
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| 24 | * SOCLIB_LGPL_HEADER_END |
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| 25 | */ |
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| 26 | |
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| 27 | #include <cassert> |
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| 28 | #include "arithmetics.h" |
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| 29 | #include "../include/vci_cc_vcache_wrapper_v4.h" |
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| 30 | |
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| 31 | #define DEBUG_DCACHE 1 |
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| 32 | #define DEBUG_ICACHE 1 |
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| 33 | #define DEBUG_CLEANUP 0 |
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| 34 | |
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| 35 | namespace soclib { |
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| 36 | namespace caba { |
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| 37 | |
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| 38 | namespace { |
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| 39 | const char *icache_fsm_state_str[] = { |
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| 40 | "ICACHE_IDLE", |
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| 41 | |
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| 42 | "ICACHE_XTN_TLB_FLUSH", |
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| 43 | "ICACHE_XTN_CACHE_FLUSH", |
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| 44 | "ICACHE_XTN_TLB_INVAL", |
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| 45 | "ICACHE_XTN_CACHE_INVAL_VA", |
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| 46 | "ICACHE_XTN_CACHE_INVAL_PA", |
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| 47 | "ICACHE_XTN_CACHE_INVAL_GO", |
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| 48 | |
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| 49 | "ICACHE_TLB_WAIT", |
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| 50 | |
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| 51 | "ICACHE_MISS_VICTIM", |
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| 52 | "ICACHE_MISS_INVAL", |
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| 53 | "ICACHE_MISS_WAIT", |
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| 54 | "ICACHE_MISS_UPDT", |
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| 55 | |
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| 56 | "ICACHE_UNC_WAIT", |
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| 57 | |
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| 58 | "ICACHE_CC_CHECK", |
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| 59 | "ICACHE_CC_INVAL", |
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| 60 | "ICACHE_CC_UPDT", |
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| 61 | |
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| 62 | }; |
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| 63 | const char *dcache_fsm_state_str[] = { |
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| 64 | "DCACHE_IDLE", |
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| 65 | |
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| 66 | "DCACHE_TLB_MISS", |
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| 67 | "DCACHE_TLB_PTE1_GET", |
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| 68 | "DCACHE_TLB_PTE1_SELECT", |
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| 69 | "DCACHE_TLB_PTE1_UPDT", |
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| 70 | "DCACHE_TLB_PTE2_GET", |
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| 71 | "DCACHE_TLB_PTE2_SELECT", |
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| 72 | "DCACHE_TLB_PTE2_UPDT", |
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[205] | 73 | "DCACHE_TLB_LR_UPDT", |
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| 74 | "DCACHE_TLB_LR_WAIT", |
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[183] | 75 | "DCACHE_TLB_RETURN", |
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| 76 | |
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| 77 | "DCACHE_XTN_SWITCH", |
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| 78 | "DCACHE_XTN_SYNC", |
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| 79 | "DCACHE_XTN_IC_INVAL_VA", |
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| 80 | "DCACHE_XTN_IC_FLUSH", |
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| 81 | "DCACHE_XTN_IC_INVAL_PA", |
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| 82 | "DCACHE_XTN_IT_INVAL", |
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| 83 | "DCACHE_XTN_DC_FLUSH", |
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| 84 | "DCACHE_XTN_DC_INVAL_VA", |
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| 85 | "DCACHE_XTN_DC_INVAL_PA", |
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[204] | 86 | "DCACHE_XTN_DC_INVAL_END", |
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[183] | 87 | "DCACHE_XTN_DC_INVAL_GO", |
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| 88 | "DCACHE_XTN_DT_INVAL", |
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| 89 | |
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[206] | 90 | "DCACHE_DIRTY_PTE_GET", |
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[205] | 91 | "DCACHE_DIRTY_SC_WAIT", |
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[183] | 92 | |
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| 93 | "DCACHE_MISS_VICTIM", |
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| 94 | "DCACHE_MISS_INVAL", |
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| 95 | "DCACHE_MISS_WAIT", |
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| 96 | "DCACHE_MISS_UPDT", |
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| 97 | |
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| 98 | "DCACHE_UNC_WAIT", |
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[205] | 99 | "DCACHE_SC_WAIT", |
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[183] | 100 | |
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| 101 | "DCACHE_CC_CHECK", |
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| 102 | "DCACHE_CC_INVAL", |
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| 103 | "DCACHE_CC_UPDT", |
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[204] | 104 | |
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| 105 | "DCACHE_INVAL_TLB_SCAN", |
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[183] | 106 | }; |
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| 107 | const char *cmd_fsm_state_str[] = { |
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| 108 | "CMD_IDLE", |
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| 109 | "CMD_INS_MISS", |
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| 110 | "CMD_INS_UNC", |
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| 111 | "CMD_DATA_MISS", |
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| 112 | "CMD_DATA_UNC", |
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| 113 | "CMD_DATA_WRITE", |
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| 114 | "CMD_DATA_SC", |
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| 115 | }; |
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| 116 | const char *rsp_fsm_state_str[] = { |
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| 117 | "RSP_IDLE", |
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| 118 | "RSP_INS_MISS", |
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| 119 | "RSP_INS_UNC", |
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| 120 | "RSP_DATA_MISS", |
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| 121 | "RSP_DATA_UNC", |
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| 122 | "RSP_DATA_WRITE", |
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| 123 | }; |
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| 124 | const char *cleanup_fsm_state_str[] = { |
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| 125 | "CLEANUP_DATA_IDLE", |
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| 126 | "CLEANUP_DATA_GO", |
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| 127 | "CLEANUP_INS_IDLE", |
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| 128 | "CLEANUP_INS_GO", |
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| 129 | }; |
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| 130 | const char *tgt_fsm_state_str[] = { |
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| 131 | "TGT_IDLE", |
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| 132 | "TGT_UPDT_WORD", |
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| 133 | "TGT_UPDT_DATA", |
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| 134 | "TGT_REQ_BROADCAST", |
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| 135 | "TGT_REQ_ICACHE", |
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| 136 | "TGT_REQ_DCACHE", |
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| 137 | "TGT_RSP_BROADCAST", |
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| 138 | "TGT_RSP_ICACHE", |
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| 139 | "TGT_RSP_DCACHE", |
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| 140 | }; |
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| 141 | } |
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| 142 | |
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| 143 | #define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t> |
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| 144 | |
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| 145 | using soclib::common::uint32_log2; |
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| 146 | |
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| 147 | ///////////////////////////////// |
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| 148 | tmpl(/**/)::VciCcVCacheWrapperV4( |
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| 149 | sc_module_name name, |
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| 150 | int proc_id, |
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| 151 | const soclib::common::MappingTable &mtp, |
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| 152 | const soclib::common::MappingTable &mtc, |
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| 153 | const soclib::common::IntTab &initiator_index_d, |
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| 154 | const soclib::common::IntTab &initiator_index_c, |
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| 155 | const soclib::common::IntTab &target_index_d, |
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| 156 | size_t itlb_ways, |
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| 157 | size_t itlb_sets, |
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| 158 | size_t dtlb_ways, |
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| 159 | size_t dtlb_sets, |
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| 160 | size_t icache_ways, |
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| 161 | size_t icache_sets, |
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| 162 | size_t icache_words, |
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| 163 | size_t dcache_ways, |
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| 164 | size_t dcache_sets, |
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| 165 | size_t dcache_words, |
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| 166 | size_t wbuf_nlines, |
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| 167 | size_t wbuf_nwords, |
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| 168 | uint32_t max_frozen_cycles, |
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| 169 | uint32_t debug_start_cycle, |
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| 170 | bool debug_ok) |
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| 171 | : soclib::caba::BaseModule(name), |
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| 172 | |
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| 173 | p_clk("clk"), |
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| 174 | p_resetn("resetn"), |
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| 175 | p_vci_ini_d("vci_ini_d"), |
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| 176 | p_vci_ini_c("vci_ini_c"), |
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| 177 | p_vci_tgt_c("vci_tgt_d"), |
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| 178 | |
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| 179 | m_cacheability_table(mtp.getCacheabilityTable()), |
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| 180 | m_segment(mtc.getSegment(target_index_d)), |
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| 181 | m_srcid_d(mtp.indexForId(initiator_index_d)), |
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| 182 | m_srcid_c(mtp.indexForId(initiator_index_c)), |
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| 183 | |
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| 184 | m_itlb_ways(itlb_ways), |
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| 185 | m_itlb_sets(itlb_sets), |
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| 186 | |
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| 187 | m_dtlb_ways(dtlb_ways), |
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| 188 | m_dtlb_sets(dtlb_sets), |
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| 189 | |
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| 190 | m_icache_ways(icache_ways), |
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| 191 | m_icache_sets(icache_sets), |
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| 192 | m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)), |
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| 193 | m_icache_words(icache_words), |
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| 194 | |
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| 195 | m_dcache_ways(dcache_ways), |
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| 196 | m_dcache_sets(dcache_sets), |
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| 197 | m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)), |
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| 198 | m_dcache_words(dcache_words), |
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| 199 | |
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[201] | 200 | m_proc_id(proc_id), |
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| 201 | |
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[183] | 202 | m_max_frozen_cycles(max_frozen_cycles), |
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| 203 | |
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| 204 | m_paddr_nbits(vci_param::N), |
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| 205 | |
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| 206 | m_debug_start_cycle(debug_start_cycle), |
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| 207 | m_debug_ok(debug_ok), |
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| 208 | |
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| 209 | r_mmu_ptpr("r_mmu_ptpr"), |
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| 210 | r_mmu_mode("r_mmu_mode"), |
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| 211 | r_mmu_word_lo("r_mmu_word_lo"), |
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| 212 | r_mmu_word_hi("r_mmu_word_hi"), |
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| 213 | r_mmu_ibvar("r_mmu_ibvar"), |
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| 214 | r_mmu_dbvar("r_mmu_dbvar"), |
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| 215 | r_mmu_ietr("r_mmu_ietr"), |
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| 216 | r_mmu_detr("r_mmu_detr"), |
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| 217 | |
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| 218 | r_icache_fsm("r_icache_fsm"), |
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| 219 | r_icache_fsm_save("r_icache_fsm_save"), |
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| 220 | r_icache_vci_paddr("r_icache_vci_paddr"), |
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| 221 | r_icache_vaddr_save("r_icache_vaddr_save"), |
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| 222 | |
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| 223 | r_icache_miss_way("r_icache_miss_way"), |
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| 224 | r_icache_miss_set("r_icache_miss_set"), |
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| 225 | r_icache_miss_word("r_icache_miss_word"), |
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| 226 | r_icache_miss_inval("r_icache_miss_inval"), |
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| 227 | |
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| 228 | r_icache_cc_way("r_icache_cc_way"), |
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| 229 | r_icache_cc_set("r_icache_cc_set"), |
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| 230 | r_icache_cc_word("r_icache_cc_word"), |
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| 231 | |
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| 232 | r_icache_flush_count("r_icache_flush_count"), |
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| 233 | |
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| 234 | r_icache_miss_req("r_icache_miss_req"), |
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| 235 | r_icache_unc_req("r_icache_unc_req"), |
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| 236 | |
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| 237 | r_icache_tlb_miss_req("r_icache_tlb_read_req"), |
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| 238 | r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), |
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| 239 | |
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| 240 | r_icache_cleanup_req("r_icache_cleanup_req"), |
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| 241 | r_icache_cleanup_line("r_icache_cleanup_line"), |
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| 242 | |
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| 243 | r_dcache_fsm("r_dcache_fsm"), |
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| 244 | r_dcache_fsm_save("r_dcache_fsm_save"), |
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| 245 | |
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| 246 | r_dcache_p0_valid("r_dcache_p0_valid"), |
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| 247 | r_dcache_p0_vaddr("r_dcache_p0_vaddr"), |
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| 248 | r_dcache_p0_wdata("r_dcache_p0_wdata"), |
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| 249 | r_dcache_p0_be("r_dcache_p0_be"), |
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| 250 | r_dcache_p0_paddr("r_dcache_p0_paddr"), |
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| 251 | r_dcache_p0_cacheable("r_dcache_p0_cacheable"), |
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| 252 | |
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| 253 | r_dcache_p1_valid("r_dcache_p1_valid"), |
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| 254 | r_dcache_p1_wdata("r_dcache_p1_wdata"), |
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| 255 | r_dcache_p1_be("r_dcache_p1_be"), |
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| 256 | r_dcache_p1_paddr("r_dcache_p1_paddr"), |
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| 257 | r_dcache_p1_cache_way("r_dcache_p1_cache_way"), |
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| 258 | r_dcache_p1_cache_set("r_dcache_p1_cache_set"), |
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| 259 | r_dcache_p1_cache_word("r_dcache_p1_word_save"), |
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| 260 | |
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[206] | 261 | r_dcache_dirty_paddr("r_dcache_dirty_paddr"), |
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| 262 | r_dcache_dirty_way("r_dcache_dirty_way"), |
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| 263 | r_dcache_dirty_set("r_dcache_dirty_set"), |
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[183] | 264 | |
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| 265 | r_dcache_vci_paddr("r_dcache_vci_paddr"), |
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| 266 | r_dcache_vci_miss_req("r_dcache_vci_miss_req"), |
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| 267 | r_dcache_vci_unc_req("r_dcache_vci_unc_req"), |
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| 268 | r_dcache_vci_unc_be("r_dcache_vci_unc_be"), |
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| 269 | r_dcache_vci_sc_req("r_dcache_vci_sc_req"), |
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| 270 | r_dcache_vci_sc_old("r_dcache_vci_sc_old"), |
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| 271 | r_dcache_vci_sc_new("r_dcache_vci_sc_new"), |
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| 272 | |
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| 273 | r_dcache_xtn_way("r_dcache_xtn_way"), |
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| 274 | r_dcache_xtn_set("r_dcache_xtn_set"), |
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| 275 | |
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| 276 | r_dcache_pending_unc_write("r_dcache_pending_unc_write"), |
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| 277 | |
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| 278 | r_dcache_miss_type("r_dcache_miss_type"), |
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| 279 | r_dcache_miss_word("r_dcache_miss_word"), |
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| 280 | r_dcache_miss_way("r_dcache_miss_way"), |
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| 281 | r_dcache_miss_set("r_dcache_miss_set"), |
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| 282 | r_dcache_miss_inval("r_dcache_miss_inval"), |
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| 283 | |
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| 284 | r_dcache_cc_way("r_dcache_cc_way"), |
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| 285 | r_dcache_cc_set("r_dcache_cc_set"), |
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| 286 | r_dcache_cc_word("r_dcache_cc_word"), |
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| 287 | |
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| 288 | r_dcache_flush_count("r_dcache_flush_count"), |
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| 289 | |
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| 290 | r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"), |
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| 291 | r_dcache_tlb_ins("r_dcache_tlb_ins"), |
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| 292 | r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), |
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| 293 | r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), |
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| 294 | r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), |
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| 295 | r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), |
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| 296 | r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), |
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| 297 | r_dcache_tlb_way("r_dcache_tlb_way"), |
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| 298 | r_dcache_tlb_set("r_dcache_tlb_set"), |
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| 299 | |
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| 300 | r_dcache_ll_valid("r_dcache_ll_valid"), |
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| 301 | r_dcache_ll_data("r_dcache_ll_data"), |
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| 302 | r_dcache_ll_vaddr("r_dcache_ll_vaddr"), |
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| 303 | |
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| 304 | r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"), |
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[204] | 305 | r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"), |
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[183] | 306 | |
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| 307 | r_dcache_xtn_req("r_dcache_xtn_req"), |
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| 308 | r_dcache_xtn_opcode("r_dcache_xtn_opcode"), |
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| 309 | |
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| 310 | r_dcache_cleanup_req("r_dcache_cleanup_req"), |
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| 311 | r_dcache_cleanup_line("r_dcache_cleanup_line"), |
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| 312 | |
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| 313 | r_vci_cmd_fsm("r_vci_cmd_fsm"), |
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| 314 | r_vci_cmd_min("r_vci_cmd_min"), |
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| 315 | r_vci_cmd_max("r_vci_cmd_max"), |
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| 316 | r_vci_cmd_cpt("r_vci_cmd_cpt"), |
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| 317 | r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"), |
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| 318 | |
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| 319 | r_vci_rsp_fsm("r_vci_rsp_fsm"), |
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| 320 | r_vci_rsp_cpt("r_vci_rsp_cpt"), |
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| 321 | r_vci_rsp_ins_error("r_vci_rsp_ins_error"), |
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| 322 | r_vci_rsp_data_error("r_vci_rsp_data_error"), |
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| 323 | r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth |
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| 324 | r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth |
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| 325 | |
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| 326 | r_cleanup_fsm("r_cleanup_fsm"), |
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| 327 | r_cleanup_trdid("r_cleanup_trdid"), |
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| 328 | r_cleanup_buffer(4), // up to 4 simultaneous cleanups |
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| 329 | |
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| 330 | r_tgt_fsm("r_tgt_fsm"), |
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| 331 | r_tgt_paddr("r_tgt_paddr"), |
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| 332 | r_tgt_word_count("r_tgt_word_count"), |
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| 333 | r_tgt_word_min("r_tgt_word_min"), |
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| 334 | r_tgt_word_max("r_tgt_word_max"), |
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| 335 | r_tgt_update("r_tgt_update"), |
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| 336 | r_tgt_update_data("r_tgt_update_data"), |
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| 337 | r_tgt_srcid("r_tgt_srcid"), |
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| 338 | r_tgt_pktid("r_tgt_pktid"), |
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| 339 | r_tgt_trdid("r_tgt_trdid"), |
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| 340 | |
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| 341 | r_tgt_icache_req("r_tgt_icache_req"), |
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| 342 | r_tgt_dcache_req("r_tgt_dcache_req"), |
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| 343 | r_tgt_icache_rsp("r_tgt_icache_rsp"), |
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| 344 | r_tgt_dcache_rsp("r_tgt_dcache_rsp"), |
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| 345 | |
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| 346 | r_iss(this->name(), proc_id), |
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| 347 | r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ), |
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| 348 | r_icache("icache", icache_ways, icache_sets, icache_words), |
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| 349 | r_dcache("dcache", dcache_ways, dcache_sets, dcache_words), |
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[202] | 350 | r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N), |
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| 351 | r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N) |
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[183] | 352 | { |
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| 353 | assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and |
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| 354 | "Need more PLEN bits."); |
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| 355 | |
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| 356 | assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and |
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| 357 | "Need more TRDID bits."); |
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| 358 | |
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| 359 | assert( (icache_words == dcache_words) and |
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| 360 | "icache_words and dcache_words parameters must be equal"); |
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| 361 | |
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[204] | 362 | assert( (itlb_sets == dtlb_sets) and |
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| 363 | "itlb_sets and dtlb_sets parameters must be etqual"); |
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| 364 | |
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| 365 | assert( (itlb_ways == dtlb_ways) and |
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| 366 | "itlb_ways and dtlb_ways parameters must be etqual"); |
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| 367 | |
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[198] | 368 | r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | |
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| 369 | (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | |
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| 370 | (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | |
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| 371 | (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | |
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| 372 | (uint32_log2(m_icache_words<<2)); |
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[183] | 373 | |
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[198] | 374 | r_mmu_release = (uint32_t)(1 << 16) | 0x1; |
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[183] | 375 | |
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[206] | 376 | r_tgt_buf = new uint32_t[dcache_words]; |
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| 377 | r_tgt_be = new vci_be_t[dcache_words]; |
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| 378 | r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; |
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| 379 | r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; |
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[183] | 380 | |
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| 381 | SC_METHOD(transition); |
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| 382 | dont_initialize(); |
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| 383 | sensitive << p_clk.pos(); |
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| 384 | |
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| 385 | SC_METHOD(genMoore); |
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| 386 | dont_initialize(); |
---|
| 387 | sensitive << p_clk.neg(); |
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| 388 | |
---|
| 389 | typename iss_t::CacheInfo cache_info; |
---|
| 390 | cache_info.has_mmu = true; |
---|
| 391 | cache_info.icache_line_size = icache_words*sizeof(uint32_t); |
---|
| 392 | cache_info.icache_assoc = icache_ways; |
---|
| 393 | cache_info.icache_n_lines = icache_sets; |
---|
| 394 | cache_info.dcache_line_size = dcache_words*sizeof(uint32_t); |
---|
| 395 | cache_info.dcache_assoc = dcache_ways; |
---|
| 396 | cache_info.dcache_n_lines = dcache_sets; |
---|
| 397 | r_iss.setCacheInfo(cache_info); |
---|
| 398 | } |
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| 399 | |
---|
| 400 | ///////////////////////////////////// |
---|
| 401 | tmpl(/**/)::~VciCcVCacheWrapperV4() |
---|
| 402 | ///////////////////////////////////// |
---|
| 403 | { |
---|
| 404 | delete [] r_tgt_be; |
---|
| 405 | delete [] r_tgt_buf; |
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[206] | 406 | delete [] r_dcache_in_tlb; |
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| 407 | delete [] r_dcache_contains_ptd; |
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[183] | 408 | } |
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| 409 | |
---|
| 410 | //////////////////////// |
---|
| 411 | tmpl(void)::print_cpi() |
---|
| 412 | //////////////////////// |
---|
| 413 | { |
---|
| 414 | std::cout << name() << " CPI = " |
---|
| 415 | << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ; |
---|
| 416 | } |
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| 417 | |
---|
| 418 | //////////////////////////////////// |
---|
| 419 | tmpl(void)::print_trace(size_t mode) |
---|
| 420 | //////////////////////////////////// |
---|
| 421 | { |
---|
[205] | 422 | // b0 : write buffer trace |
---|
[183] | 423 | // b1 : write buffer verbose |
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[205] | 424 | // b2 : dcache trace |
---|
| 425 | // b3 : icache trace |
---|
| 426 | // b4 : dtlb trace |
---|
| 427 | // b5 : itlb trace |
---|
[183] | 428 | |
---|
| 429 | std::cout << std::dec << "PROC " << name() << std::endl; |
---|
| 430 | |
---|
[205] | 431 | std::cout << " " << m_ireq << std::endl; |
---|
| 432 | std::cout << " " << m_irsp << std::endl; |
---|
| 433 | std::cout << " " << m_dreq << std::endl; |
---|
| 434 | std::cout << " " << m_drsp << std::endl; |
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[183] | 435 | |
---|
| 436 | std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] |
---|
| 437 | << " | " << dcache_fsm_state_str[r_dcache_fsm.read()] |
---|
| 438 | << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()] |
---|
| 439 | << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] |
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[204] | 440 | << " | " << tgt_fsm_state_str[r_tgt_fsm.read()] |
---|
| 441 | << " | " << cleanup_fsm_state_str[r_cleanup_fsm.read()]; |
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[183] | 442 | if (r_dcache_p0_valid.read() ) std::cout << " | P1_WRITE"; |
---|
| 443 | if (r_dcache_p1_valid.read() ) std::cout << " | P2_WRITE"; |
---|
| 444 | std::cout << std::endl; |
---|
| 445 | |
---|
[205] | 446 | if(mode & 0x01) |
---|
[183] | 447 | { |
---|
| 448 | r_wbuf.printTrace((mode>>1)&1); |
---|
| 449 | } |
---|
[205] | 450 | if(mode & 0x04) |
---|
[183] | 451 | { |
---|
[205] | 452 | std::cout << " Data Cache" << std::endl; |
---|
[183] | 453 | r_dcache.printTrace(); |
---|
| 454 | } |
---|
[205] | 455 | if(mode & 0x08) |
---|
[183] | 456 | { |
---|
[205] | 457 | std::cout << " Instruction Cache" << std::endl; |
---|
[183] | 458 | r_icache.printTrace(); |
---|
| 459 | } |
---|
[205] | 460 | if(mode & 0x10) |
---|
| 461 | { |
---|
| 462 | std::cout << " Data TLB" << std::endl; |
---|
| 463 | r_dtlb.printTrace(); |
---|
| 464 | } |
---|
| 465 | if(mode & 0x20) |
---|
| 466 | { |
---|
| 467 | std::cout << " Instruction TLB" << std::endl; |
---|
| 468 | r_itlb.printTrace(); |
---|
| 469 | } |
---|
[183] | 470 | } |
---|
| 471 | |
---|
| 472 | ////////////////////////////////////////// |
---|
| 473 | tmpl(void)::cache_monitor( paddr_t addr ) |
---|
| 474 | ////////////////////////////////////////// |
---|
| 475 | { |
---|
| 476 | size_t cache_way; |
---|
| 477 | size_t cache_set; |
---|
| 478 | size_t cache_word; |
---|
| 479 | uint32_t cache_rdata; |
---|
| 480 | bool cache_hit = r_dcache.read( addr, |
---|
| 481 | &cache_rdata, |
---|
| 482 | &cache_way, |
---|
| 483 | &cache_set, |
---|
| 484 | &cache_word ); |
---|
| 485 | if ( cache_hit != m_debug_previous_hit ) |
---|
| 486 | { |
---|
| 487 | std::cout << "PROC " << name() |
---|
| 488 | << " cache change at cycle " << std::dec << m_cpt_total_cycles |
---|
| 489 | << " for adresse " << std::hex << addr |
---|
| 490 | << " / HIT = " << cache_hit << std::endl; |
---|
| 491 | } |
---|
| 492 | m_debug_previous_hit = cache_hit; |
---|
| 493 | } |
---|
| 494 | |
---|
| 495 | |
---|
[198] | 496 | |
---|
| 497 | /* |
---|
[183] | 498 | //////////////////////// |
---|
| 499 | tmpl(void)::print_stats() |
---|
| 500 | //////////////////////// |
---|
| 501 | { |
---|
| 502 | float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); |
---|
[198] | 503 | std::cout << name() << std::endl |
---|
| 504 | << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl |
---|
| 505 | << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl |
---|
| 506 | << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl |
---|
| 507 | << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl |
---|
| 508 | << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl |
---|
| 509 | << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl |
---|
| 510 | << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl |
---|
| 511 | << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl |
---|
| 512 | << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl |
---|
| 513 | << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl |
---|
| 514 | << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl |
---|
| 515 | << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl |
---|
| 516 | << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl |
---|
| 517 | << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl |
---|
| 518 | << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl |
---|
| 519 | << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl |
---|
| 520 | << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl |
---|
| 521 | << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl |
---|
| 522 | << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl |
---|
| 523 | << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl |
---|
| 524 | << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl |
---|
| 525 | << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl |
---|
| 526 | << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl |
---|
| 527 | << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl |
---|
| 528 | << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl |
---|
| 529 | << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl |
---|
| 530 | << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl |
---|
| 531 | << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl |
---|
| 532 | << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl |
---|
| 533 | << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl |
---|
| 534 | << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl |
---|
| 535 | << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl |
---|
| 536 | << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl |
---|
| 537 | << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl |
---|
| 538 | << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl |
---|
| 539 | << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl |
---|
| 540 | << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl |
---|
| 541 | << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl |
---|
| 542 | << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; |
---|
[183] | 543 | } |
---|
| 544 | |
---|
| 545 | //////////////////////// |
---|
| 546 | tmpl(void)::clear_stats() |
---|
| 547 | //////////////////////// |
---|
| 548 | { |
---|
| 549 | m_cpt_dcache_data_read = 0; |
---|
| 550 | m_cpt_dcache_data_write = 0; |
---|
| 551 | m_cpt_dcache_dir_read = 0; |
---|
| 552 | m_cpt_dcache_dir_write = 0; |
---|
| 553 | m_cpt_icache_data_read = 0; |
---|
| 554 | m_cpt_icache_data_write = 0; |
---|
| 555 | m_cpt_icache_dir_read = 0; |
---|
| 556 | m_cpt_icache_dir_write = 0; |
---|
| 557 | |
---|
| 558 | m_cpt_frz_cycles = 0; |
---|
| 559 | m_cpt_dcache_frz_cycles = 0; |
---|
| 560 | m_cpt_total_cycles = 0; |
---|
| 561 | |
---|
[198] | 562 | m_cpt_read = 0; |
---|
| 563 | m_cpt_write = 0; |
---|
[183] | 564 | m_cpt_data_miss = 0; |
---|
| 565 | m_cpt_ins_miss = 0; |
---|
| 566 | m_cpt_unc_read = 0; |
---|
| 567 | m_cpt_write_cached = 0; |
---|
| 568 | m_cpt_ins_read = 0; |
---|
| 569 | |
---|
| 570 | m_cost_write_frz = 0; |
---|
| 571 | m_cost_data_miss_frz = 0; |
---|
| 572 | m_cost_unc_read_frz = 0; |
---|
| 573 | m_cost_ins_miss_frz = 0; |
---|
| 574 | |
---|
| 575 | m_cpt_imiss_transaction = 0; |
---|
| 576 | m_cpt_dmiss_transaction = 0; |
---|
| 577 | m_cpt_unc_transaction = 0; |
---|
| 578 | m_cpt_write_transaction = 0; |
---|
| 579 | m_cpt_icache_unc_transaction = 0; |
---|
| 580 | |
---|
| 581 | m_cost_imiss_transaction = 0; |
---|
| 582 | m_cost_dmiss_transaction = 0; |
---|
| 583 | m_cost_unc_transaction = 0; |
---|
| 584 | m_cost_write_transaction = 0; |
---|
| 585 | m_cost_icache_unc_transaction = 0; |
---|
| 586 | m_length_write_transaction = 0; |
---|
| 587 | |
---|
| 588 | m_cpt_ins_tlb_read = 0; |
---|
| 589 | m_cpt_ins_tlb_miss = 0; |
---|
| 590 | m_cpt_ins_tlb_update_acc = 0; |
---|
[198] | 591 | |
---|
[183] | 592 | m_cpt_data_tlb_read = 0; |
---|
| 593 | m_cpt_data_tlb_miss = 0; |
---|
| 594 | m_cpt_data_tlb_update_acc = 0; |
---|
| 595 | m_cpt_data_tlb_update_dirty = 0; |
---|
[198] | 596 | m_cpt_ins_tlb_hit_dcache = 0; |
---|
[183] | 597 | m_cpt_data_tlb_hit_dcache = 0; |
---|
[198] | 598 | m_cpt_ins_tlb_occup_cache = 0; |
---|
[183] | 599 | m_cpt_data_tlb_occup_cache = 0; |
---|
| 600 | |
---|
| 601 | m_cost_ins_tlb_miss_frz = 0; |
---|
| 602 | m_cost_data_tlb_miss_frz = 0; |
---|
| 603 | m_cost_ins_tlb_update_acc_frz = 0; |
---|
| 604 | m_cost_data_tlb_update_acc_frz = 0; |
---|
| 605 | m_cost_data_tlb_update_dirty_frz = 0; |
---|
| 606 | m_cost_ins_tlb_occup_cache_frz = 0; |
---|
| 607 | m_cost_data_tlb_occup_cache_frz = 0; |
---|
| 608 | |
---|
| 609 | m_cpt_itlbmiss_transaction = 0; |
---|
| 610 | m_cpt_itlb_ll_transaction = 0; |
---|
| 611 | m_cpt_itlb_sc_transaction = 0; |
---|
| 612 | m_cpt_dtlbmiss_transaction = 0; |
---|
| 613 | m_cpt_dtlb_ll_transaction = 0; |
---|
| 614 | m_cpt_dtlb_sc_transaction = 0; |
---|
| 615 | m_cpt_dtlb_ll_dirty_transaction = 0; |
---|
| 616 | m_cpt_dtlb_sc_dirty_transaction = 0; |
---|
| 617 | |
---|
| 618 | m_cost_itlbmiss_transaction = 0; |
---|
| 619 | m_cost_itlb_ll_transaction = 0; |
---|
| 620 | m_cost_itlb_sc_transaction = 0; |
---|
| 621 | m_cost_dtlbmiss_transaction = 0; |
---|
| 622 | m_cost_dtlb_ll_transaction = 0; |
---|
| 623 | m_cost_dtlb_sc_transaction = 0; |
---|
| 624 | m_cost_dtlb_ll_dirty_transaction = 0; |
---|
| 625 | m_cost_dtlb_sc_dirty_transaction = 0; |
---|
| 626 | |
---|
[198] | 627 | m_cpt_cc_update_data = 0; |
---|
| 628 | m_cpt_cc_inval_ins = 0; |
---|
| 629 | m_cpt_cc_inval_data = 0; |
---|
| 630 | m_cpt_cc_broadcast = 0; |
---|
[183] | 631 | |
---|
| 632 | m_cost_updt_data_frz = 0; |
---|
| 633 | m_cost_inval_ins_frz = 0; |
---|
| 634 | m_cost_inval_data_frz = 0; |
---|
| 635 | m_cost_broadcast_frz = 0; |
---|
| 636 | |
---|
| 637 | m_cpt_cc_cleanup_data = 0; |
---|
| 638 | m_cpt_cc_cleanup_ins = 0; |
---|
| 639 | } |
---|
| 640 | |
---|
[198] | 641 | */ |
---|
[183] | 642 | |
---|
| 643 | ///////////////////////// |
---|
| 644 | tmpl(void)::transition() |
---|
| 645 | ///////////////////////// |
---|
| 646 | { |
---|
| 647 | if ( not p_resetn.read() ) |
---|
| 648 | { |
---|
| 649 | r_iss.reset(); |
---|
| 650 | r_wbuf.reset(); |
---|
| 651 | r_icache.reset(); |
---|
| 652 | r_dcache.reset(); |
---|
| 653 | r_itlb.reset(); |
---|
| 654 | r_dtlb.reset(); |
---|
| 655 | |
---|
| 656 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 657 | r_icache_fsm = ICACHE_IDLE; |
---|
| 658 | r_vci_cmd_fsm = CMD_IDLE; |
---|
| 659 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 660 | r_tgt_fsm = TGT_IDLE; |
---|
| 661 | r_cleanup_fsm = CLEANUP_DATA_IDLE; |
---|
| 662 | |
---|
[206] | 663 | // reset dcache directory extension |
---|
| 664 | for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) |
---|
| 665 | { |
---|
| 666 | r_dcache_in_tlb[i] = false; |
---|
| 667 | r_dcache_contains_ptd[i] = false; |
---|
| 668 | } |
---|
[183] | 669 | |
---|
| 670 | // Response FIFOs and cleanup buffer |
---|
| 671 | r_vci_rsp_fifo_icache.init(); |
---|
| 672 | r_vci_rsp_fifo_dcache.init(); |
---|
| 673 | r_cleanup_buffer.reset(); |
---|
| 674 | |
---|
| 675 | // ICACHE & DCACHE activated |
---|
| 676 | r_mmu_mode = 0x3; |
---|
| 677 | |
---|
[198] | 678 | // No request from ICACHE FSM to CMD FSM |
---|
[183] | 679 | r_icache_miss_req = false; |
---|
| 680 | r_icache_unc_req = false; |
---|
| 681 | |
---|
| 682 | // No request from ICACHE_FSM to DCACHE FSM |
---|
| 683 | r_icache_tlb_miss_req = false; |
---|
| 684 | |
---|
| 685 | // No request from ICACHE_FSM to CLEANUP FSMs |
---|
| 686 | r_icache_cleanup_req = false; |
---|
| 687 | |
---|
| 688 | // No pending write in pipeline |
---|
| 689 | r_dcache_p0_valid = false; |
---|
| 690 | r_dcache_p1_valid = false; |
---|
| 691 | |
---|
| 692 | // No request from DCACHE_FSM to CMD_FSM |
---|
| 693 | r_dcache_vci_miss_req = false; |
---|
| 694 | r_dcache_vci_unc_req = false; |
---|
| 695 | r_dcache_vci_sc_req = false; |
---|
| 696 | |
---|
| 697 | // No uncacheable write pending |
---|
| 698 | r_dcache_pending_unc_write = false; |
---|
| 699 | |
---|
| 700 | // No LL reservation |
---|
[198] | 701 | r_dcache_ll_valid = false; |
---|
[183] | 702 | |
---|
| 703 | // No processor XTN request pending |
---|
| 704 | r_dcache_xtn_req = false; |
---|
| 705 | |
---|
| 706 | // No request from DCACHE FSM to CLEANUP FSMs |
---|
| 707 | r_dcache_cleanup_req = false; |
---|
| 708 | |
---|
| 709 | // No request from TGT FSM to ICACHE/DCACHE FSMs |
---|
| 710 | r_tgt_icache_req = false; |
---|
| 711 | r_tgt_dcache_req = false; |
---|
| 712 | |
---|
| 713 | // No signalisation of a coherence request matching a pending miss |
---|
| 714 | r_icache_miss_inval = false; |
---|
| 715 | r_dcache_miss_inval = false; |
---|
| 716 | |
---|
| 717 | // No signalisation of errors |
---|
| 718 | r_vci_rsp_ins_error = false; |
---|
| 719 | r_vci_rsp_data_error = false; |
---|
| 720 | |
---|
| 721 | // Debug variables |
---|
| 722 | m_debug_previous_hit = false; |
---|
| 723 | m_debug_dcache_fsm = false; |
---|
| 724 | m_debug_icache_fsm = false; |
---|
| 725 | m_debug_cleanup_fsm = false; |
---|
| 726 | |
---|
[198] | 727 | /* |
---|
| 728 | // activity counters |
---|
| 729 | m_cpt_dcache_data_read = 0; |
---|
| 730 | m_cpt_dcache_data_write = 0; |
---|
| 731 | m_cpt_dcache_dir_read = 0; |
---|
| 732 | m_cpt_dcache_dir_write = 0; |
---|
| 733 | m_cpt_icache_data_read = 0; |
---|
| 734 | m_cpt_icache_data_write = 0; |
---|
| 735 | m_cpt_icache_dir_read = 0; |
---|
| 736 | m_cpt_icache_dir_write = 0; |
---|
[183] | 737 | |
---|
[198] | 738 | m_cpt_frz_cycles = 0; |
---|
| 739 | m_cpt_dcache_frz_cycles = 0; |
---|
| 740 | m_cpt_total_cycles = 0; |
---|
| 741 | |
---|
| 742 | m_cpt_read = 0; |
---|
| 743 | m_cpt_write = 0; |
---|
| 744 | m_cpt_data_miss = 0; |
---|
| 745 | m_cpt_ins_miss = 0; |
---|
| 746 | m_cpt_unc_read = 0; |
---|
| 747 | m_cpt_write_cached = 0; |
---|
| 748 | m_cpt_ins_read = 0; |
---|
| 749 | |
---|
| 750 | m_cost_write_frz = 0; |
---|
| 751 | m_cost_data_miss_frz = 0; |
---|
| 752 | m_cost_unc_read_frz = 0; |
---|
| 753 | m_cost_ins_miss_frz = 0; |
---|
| 754 | |
---|
| 755 | m_cpt_imiss_transaction = 0; |
---|
| 756 | m_cpt_dmiss_transaction = 0; |
---|
| 757 | m_cpt_unc_transaction = 0; |
---|
| 758 | m_cpt_write_transaction = 0; |
---|
| 759 | m_cpt_icache_unc_transaction = 0; |
---|
| 760 | |
---|
| 761 | m_cost_imiss_transaction = 0; |
---|
| 762 | m_cost_dmiss_transaction = 0; |
---|
| 763 | m_cost_unc_transaction = 0; |
---|
| 764 | m_cost_write_transaction = 0; |
---|
| 765 | m_cost_icache_unc_transaction = 0; |
---|
| 766 | m_length_write_transaction = 0; |
---|
| 767 | |
---|
| 768 | m_cpt_ins_tlb_read = 0; |
---|
| 769 | m_cpt_ins_tlb_miss = 0; |
---|
| 770 | m_cpt_ins_tlb_update_acc = 0; |
---|
| 771 | |
---|
| 772 | m_cpt_data_tlb_read = 0; |
---|
| 773 | m_cpt_data_tlb_miss = 0; |
---|
| 774 | m_cpt_data_tlb_update_acc = 0; |
---|
| 775 | m_cpt_data_tlb_update_dirty = 0; |
---|
| 776 | m_cpt_ins_tlb_hit_dcache = 0; |
---|
| 777 | m_cpt_data_tlb_hit_dcache = 0; |
---|
| 778 | m_cpt_ins_tlb_occup_cache = 0; |
---|
| 779 | m_cpt_data_tlb_occup_cache = 0; |
---|
| 780 | |
---|
| 781 | m_cost_ins_tlb_miss_frz = 0; |
---|
| 782 | m_cost_data_tlb_miss_frz = 0; |
---|
| 783 | m_cost_ins_tlb_update_acc_frz = 0; |
---|
| 784 | m_cost_data_tlb_update_acc_frz = 0; |
---|
| 785 | m_cost_data_tlb_update_dirty_frz = 0; |
---|
| 786 | m_cost_ins_tlb_occup_cache_frz = 0; |
---|
| 787 | m_cost_data_tlb_occup_cache_frz = 0; |
---|
| 788 | |
---|
| 789 | m_cpt_ins_tlb_inval = 0; |
---|
| 790 | m_cpt_data_tlb_inval = 0; |
---|
| 791 | m_cost_ins_tlb_inval_frz = 0; |
---|
| 792 | m_cost_data_tlb_inval_frz = 0; |
---|
| 793 | |
---|
| 794 | m_cpt_cc_update_data = 0; |
---|
| 795 | m_cpt_cc_inval_ins = 0; |
---|
| 796 | m_cpt_cc_inval_data = 0; |
---|
| 797 | m_cpt_cc_broadcast = 0; |
---|
| 798 | |
---|
| 799 | m_cost_updt_data_frz = 0; |
---|
| 800 | m_cost_inval_ins_frz = 0; |
---|
| 801 | m_cost_inval_data_frz = 0; |
---|
| 802 | m_cost_broadcast_frz = 0; |
---|
| 803 | |
---|
| 804 | m_cpt_cc_cleanup_data = 0; |
---|
| 805 | m_cpt_cc_cleanup_ins = 0; |
---|
| 806 | |
---|
| 807 | m_cpt_itlbmiss_transaction = 0; |
---|
| 808 | m_cpt_itlb_ll_transaction = 0; |
---|
| 809 | m_cpt_itlb_sc_transaction = 0; |
---|
| 810 | m_cpt_dtlbmiss_transaction = 0; |
---|
| 811 | m_cpt_dtlb_ll_transaction = 0; |
---|
| 812 | m_cpt_dtlb_sc_transaction = 0; |
---|
| 813 | m_cpt_dtlb_ll_dirty_transaction = 0; |
---|
| 814 | m_cpt_dtlb_sc_dirty_transaction = 0; |
---|
| 815 | |
---|
| 816 | m_cost_itlbmiss_transaction = 0; |
---|
| 817 | m_cost_itlb_ll_transaction = 0; |
---|
| 818 | m_cost_itlb_sc_transaction = 0; |
---|
| 819 | m_cost_dtlbmiss_transaction = 0; |
---|
| 820 | m_cost_dtlb_ll_transaction = 0; |
---|
| 821 | m_cost_dtlb_sc_transaction = 0; |
---|
| 822 | m_cost_dtlb_ll_dirty_transaction = 0; |
---|
| 823 | m_cost_dtlb_sc_dirty_transaction = 0; |
---|
| 824 | |
---|
[183] | 825 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; |
---|
| 826 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; |
---|
| 827 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0; |
---|
| 828 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0; |
---|
| 829 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0; |
---|
| 830 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0; |
---|
| 831 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0; |
---|
| 832 | |
---|
[198] | 833 | */ |
---|
[183] | 834 | return; |
---|
| 835 | } |
---|
| 836 | |
---|
| 837 | // Response FIFOs default values |
---|
| 838 | bool vci_rsp_fifo_icache_get = false; |
---|
| 839 | bool vci_rsp_fifo_icache_put = false; |
---|
| 840 | uint32_t vci_rsp_fifo_icache_data = 0; |
---|
| 841 | |
---|
| 842 | bool vci_rsp_fifo_dcache_get = false; |
---|
| 843 | bool vci_rsp_fifo_dcache_put = false; |
---|
| 844 | uint32_t vci_rsp_fifo_dcache_data = 0; |
---|
| 845 | |
---|
| 846 | #ifdef INSTRUMENTATION |
---|
| 847 | m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; |
---|
| 848 | m_cpt_fsm_icache [r_icache_fsm.read() ] ++; |
---|
| 849 | m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++; |
---|
| 850 | m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++; |
---|
| 851 | m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++; |
---|
| 852 | m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++; |
---|
| 853 | #endif |
---|
| 854 | |
---|
| 855 | m_cpt_total_cycles++; |
---|
| 856 | |
---|
| 857 | m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
| 858 | m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
| 859 | m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
| 860 | |
---|
| 861 | ///////////////////////////////////////////////////////////////////// |
---|
| 862 | // The TGT_FSM controls the following ressources: |
---|
| 863 | // - r_tgt_fsm |
---|
| 864 | // - r_tgt_buf[nwords] |
---|
| 865 | // - r_tgt_be[nwords] |
---|
| 866 | // - r_tgt_update |
---|
| 867 | // - r_tgt_word_min |
---|
| 868 | // - r_tgt_word_max |
---|
| 869 | // - r_tgt_word_count |
---|
| 870 | // - r_tgt_paddr |
---|
| 871 | // - r_tgt_srcid |
---|
| 872 | // - r_tgt_trdid |
---|
| 873 | // - r_tgt_pktid |
---|
| 874 | // - r_tgt_icache_req (set) |
---|
| 875 | // - r_tgt_dcache_req (set) |
---|
| 876 | // |
---|
| 877 | // All VCI commands must be CMD_WRITE. |
---|
| 878 | // - If the 2 LSB bits of the VCI address are 11, it is a broadcast request. |
---|
| 879 | // It is a multicast request otherwise. |
---|
| 880 | // - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS |
---|
| 881 | // (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes |
---|
| 882 | // INVAL/UPDATE (0 for invalidate / 1 for UPDATE). |
---|
| 883 | // |
---|
| 884 | // For all types of coherence request, the line index (i.e. the Z & Y fields) |
---|
| 885 | // is coded on 34 bits, and is contained in the WDATA and BE fields |
---|
| 886 | // of the first VCI flit. |
---|
| 887 | // - for a multicast invalidate or for a broadcast invalidate request |
---|
| 888 | // the VCI packet length is 1 word. |
---|
| 889 | // - for an update request the VCI packet length is (n+2) words. |
---|
| 890 | // The WDATA field of the second VCI word contains the word index. |
---|
| 891 | // The WDATA field of the n following words contains the values. |
---|
| 892 | // - for all transaction types, the VCI response is one single word. |
---|
| 893 | // In case of errors in the VCI command packet, the simulation |
---|
| 894 | // is stopped with an error message. |
---|
| 895 | // |
---|
| 896 | // This FSM is NOT pipelined : It consumes a new coherence request |
---|
| 897 | // on the VCI port only when the previous request is completed. |
---|
| 898 | // |
---|
| 899 | // The VCI_TGT FSM stores the external request arguments in the |
---|
| 900 | // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req |
---|
| 901 | // and/or the r_tgt_dcache_req flip-flops to signal the coherence request |
---|
| 902 | // to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST |
---|
| 903 | // states. It waits the completion of the coherence request by polling the |
---|
| 904 | // r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST |
---|
| 905 | // states. These flip-flops are reset by the ICACHE and DCACHE FSMs. |
---|
| 906 | // These two FSMs signal if a VCI answer must be send by setting |
---|
| 907 | // the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops. |
---|
| 908 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 909 | |
---|
| 910 | switch( r_tgt_fsm.read() ) |
---|
| 911 | { |
---|
| 912 | ////////////// |
---|
| 913 | case TGT_IDLE: |
---|
| 914 | { |
---|
| 915 | if ( p_vci_tgt_c.cmdval.read() ) |
---|
| 916 | { |
---|
| 917 | paddr_t address = p_vci_tgt_c.address.read(); |
---|
| 918 | |
---|
| 919 | // command checking |
---|
| 920 | if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE) |
---|
| 921 | { |
---|
| 922 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 923 | std::cout << "the received VCI coherence command is not a write" << std::endl; |
---|
| 924 | exit(0); |
---|
| 925 | } |
---|
| 926 | |
---|
| 927 | // address checking |
---|
| 928 | if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) ) |
---|
| 929 | { |
---|
| 930 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 931 | std::cout << "out of segment VCI coherence command received" << std::endl; |
---|
| 932 | exit(0); |
---|
| 933 | } |
---|
| 934 | |
---|
| 935 | r_tgt_srcid = p_vci_tgt_c.srcid.read(); |
---|
| 936 | r_tgt_trdid = p_vci_tgt_c.trdid.read(); |
---|
| 937 | r_tgt_pktid = p_vci_tgt_c.pktid.read(); |
---|
| 938 | |
---|
| 939 | r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 | |
---|
| 940 | (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; |
---|
| 941 | |
---|
| 942 | if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type |
---|
| 943 | { |
---|
| 944 | if ( not p_vci_tgt_c.eop.read() ) |
---|
| 945 | { |
---|
| 946 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 947 | std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl; |
---|
| 948 | exit(0); |
---|
| 949 | } |
---|
| 950 | r_tgt_update = false; |
---|
| 951 | r_tgt_fsm = TGT_REQ_BROADCAST; |
---|
| 952 | |
---|
| 953 | #ifdef INSTRUMENTATION |
---|
| 954 | m_cpt_cc_broadcast++; |
---|
| 955 | #endif |
---|
| 956 | } |
---|
| 957 | else // multi-update or multi-invalidate for data type |
---|
| 958 | { |
---|
| 959 | paddr_t cell = address - m_segment.baseAddress(); |
---|
| 960 | |
---|
| 961 | if (cell == 0) // invalidate data |
---|
| 962 | { |
---|
| 963 | if ( not p_vci_tgt_c.eop.read() ) |
---|
| 964 | { |
---|
| 965 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 966 | std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl; |
---|
| 967 | exit(0); |
---|
| 968 | } |
---|
| 969 | r_tgt_update = false; |
---|
| 970 | r_tgt_fsm = TGT_REQ_DCACHE; |
---|
| 971 | |
---|
| 972 | #ifdef INSTRUMENTATION |
---|
| 973 | m_cpt_cc_inval_dcache++; |
---|
| 974 | #endif |
---|
| 975 | } |
---|
| 976 | else if (cell == 4) // invalidate instruction |
---|
| 977 | { |
---|
| 978 | if ( not p_vci_tgt_c.eop.read() ) |
---|
| 979 | { |
---|
| 980 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 981 | std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl; |
---|
| 982 | exit(0); |
---|
| 983 | } |
---|
| 984 | r_tgt_update = false; |
---|
| 985 | r_tgt_fsm = TGT_REQ_ICACHE; |
---|
| 986 | |
---|
| 987 | #ifdef INSTRUMENTATION |
---|
| 988 | m_cpt_cc_inval_icache++; |
---|
| 989 | #endif |
---|
| 990 | } |
---|
| 991 | else if (cell == 8) // update data |
---|
| 992 | { |
---|
| 993 | if ( p_vci_tgt_c.eop.read() ) |
---|
| 994 | { |
---|
| 995 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 996 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
| 997 | exit(0); |
---|
| 998 | } |
---|
| 999 | r_tgt_update = true; |
---|
| 1000 | r_tgt_update_data = true; |
---|
| 1001 | r_tgt_fsm = TGT_UPDT_WORD; |
---|
| 1002 | |
---|
| 1003 | #ifdef INSTRUMENTATION |
---|
| 1004 | m_cpt_cc_update_dcache++; |
---|
| 1005 | #endif |
---|
| 1006 | } |
---|
| 1007 | else // update instruction |
---|
| 1008 | { |
---|
| 1009 | if ( p_vci_tgt_c.eop.read() ) |
---|
| 1010 | { |
---|
| 1011 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1012 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
| 1013 | exit(0); |
---|
| 1014 | } |
---|
| 1015 | r_tgt_update = true; |
---|
| 1016 | r_tgt_update_data = false; |
---|
| 1017 | r_tgt_fsm = TGT_UPDT_WORD; |
---|
| 1018 | |
---|
| 1019 | #ifdef INSTRUMENTATION |
---|
| 1020 | m_cpt_cc_update_icache++; |
---|
| 1021 | #endif |
---|
| 1022 | } |
---|
| 1023 | } // end if multi |
---|
| 1024 | } // end if cmdval |
---|
| 1025 | break; |
---|
| 1026 | } |
---|
| 1027 | /////////////////// |
---|
| 1028 | case TGT_UPDT_WORD: // first word index acquisition |
---|
| 1029 | { |
---|
| 1030 | if (p_vci_tgt_c.cmdval.read()) |
---|
| 1031 | { |
---|
| 1032 | if ( p_vci_tgt_c.eop.read() ) |
---|
| 1033 | { |
---|
| 1034 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1035 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
| 1036 | exit(0); |
---|
| 1037 | } |
---|
| 1038 | for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false; |
---|
| 1039 | |
---|
| 1040 | r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index |
---|
| 1041 | r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index |
---|
| 1042 | r_tgt_fsm = TGT_UPDT_DATA; |
---|
| 1043 | } |
---|
| 1044 | break; |
---|
| 1045 | } |
---|
| 1046 | /////////////////// |
---|
| 1047 | case TGT_UPDT_DATA: |
---|
| 1048 | { |
---|
| 1049 | if (p_vci_tgt_c.cmdval.read()) |
---|
| 1050 | { |
---|
| 1051 | size_t word = r_tgt_word_count.read(); |
---|
| 1052 | if (word >= m_dcache_words) |
---|
| 1053 | { |
---|
| 1054 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1055 | std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl; |
---|
| 1056 | exit(0); |
---|
| 1057 | } |
---|
| 1058 | r_tgt_buf[word] = p_vci_tgt_c.wdata.read(); |
---|
| 1059 | r_tgt_be[word] = p_vci_tgt_c.be.read(); |
---|
| 1060 | r_tgt_word_count = word + 1; |
---|
| 1061 | |
---|
| 1062 | if (p_vci_tgt_c.eop.read()) // last word |
---|
| 1063 | { |
---|
| 1064 | r_tgt_word_max = word; |
---|
| 1065 | if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE; |
---|
| 1066 | else r_tgt_fsm = TGT_REQ_ICACHE; |
---|
| 1067 | } |
---|
| 1068 | } |
---|
| 1069 | break; |
---|
| 1070 | } |
---|
| 1071 | /////////////////////// |
---|
| 1072 | case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs |
---|
| 1073 | { |
---|
| 1074 | if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) |
---|
| 1075 | { |
---|
| 1076 | r_tgt_fsm = TGT_RSP_BROADCAST; |
---|
| 1077 | r_tgt_icache_req = true; |
---|
| 1078 | r_tgt_dcache_req = true; |
---|
| 1079 | } |
---|
| 1080 | break; |
---|
| 1081 | } |
---|
| 1082 | ///////////////////// |
---|
| 1083 | case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending) |
---|
| 1084 | { |
---|
| 1085 | if ( not r_tgt_icache_req.read() ) |
---|
| 1086 | { |
---|
| 1087 | r_tgt_fsm = TGT_RSP_ICACHE; |
---|
| 1088 | r_tgt_icache_req = true; |
---|
| 1089 | } |
---|
| 1090 | break; |
---|
| 1091 | } |
---|
| 1092 | //////////////////// |
---|
| 1093 | case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending) |
---|
| 1094 | { |
---|
| 1095 | if ( not r_tgt_dcache_req.read() ) |
---|
| 1096 | { |
---|
| 1097 | r_tgt_fsm = TGT_RSP_DCACHE; |
---|
| 1098 | r_tgt_dcache_req = true; |
---|
| 1099 | } |
---|
| 1100 | break; |
---|
| 1101 | } |
---|
| 1102 | /////////////////////// |
---|
| 1103 | case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs |
---|
| 1104 | // no response when r_tgt_*cache_rsp is false |
---|
| 1105 | { |
---|
| 1106 | if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed |
---|
| 1107 | { |
---|
| 1108 | if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response |
---|
| 1109 | { |
---|
| 1110 | if ( p_vci_tgt_c.rspack.read() ) |
---|
| 1111 | { |
---|
| 1112 | // reset dcache first if activated |
---|
| 1113 | if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false; |
---|
| 1114 | else r_tgt_icache_rsp = false; |
---|
| 1115 | } |
---|
| 1116 | } |
---|
| 1117 | else |
---|
| 1118 | { |
---|
| 1119 | r_tgt_fsm = TGT_IDLE; |
---|
| 1120 | } |
---|
| 1121 | } |
---|
| 1122 | break; |
---|
| 1123 | } |
---|
| 1124 | //////////////////// |
---|
| 1125 | case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM |
---|
| 1126 | { |
---|
| 1127 | // no response when r_tgt_icache_rsp is false |
---|
| 1128 | if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() ) |
---|
| 1129 | { |
---|
| 1130 | r_tgt_fsm = TGT_IDLE; |
---|
| 1131 | r_tgt_icache_rsp = false; |
---|
| 1132 | } |
---|
| 1133 | break; |
---|
| 1134 | } |
---|
| 1135 | //////////////////// |
---|
| 1136 | case TGT_RSP_DCACHE: |
---|
| 1137 | { |
---|
| 1138 | // no response when r_tgt_dcache_rsp is false |
---|
| 1139 | if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() ) |
---|
| 1140 | { |
---|
| 1141 | r_tgt_fsm = TGT_IDLE; |
---|
| 1142 | r_tgt_dcache_rsp = false; |
---|
| 1143 | } |
---|
| 1144 | break; |
---|
| 1145 | } |
---|
| 1146 | } // end switch TGT_FSM |
---|
| 1147 | |
---|
| 1148 | ///////////////////////////////////////////////////////////////////// |
---|
| 1149 | // Get data and instruction requests from processor |
---|
| 1150 | /////////////////////////////////////////////////////////////////////// |
---|
| 1151 | |
---|
[205] | 1152 | r_iss.getRequests(m_ireq, m_dreq); |
---|
[183] | 1153 | |
---|
| 1154 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 1155 | // ICACHE_FSM |
---|
| 1156 | // |
---|
| 1157 | // There is 9 conditions to exit the IDLE state: |
---|
| 1158 | // One condition is a coherence request from TGT FSM : |
---|
| 1159 | // - Coherence operation => ICACHE_CC_CHEK |
---|
| 1160 | // Five configurations corresponding to XTN processor requests sent by DCACHE FSM : |
---|
[198] | 1161 | // - Flush TLB => ICACHE_XTN_TLB_FLUSH |
---|
| 1162 | // - Flush cache => ICACHE_XTN_CACHE_FLUSH |
---|
[183] | 1163 | // - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL |
---|
| 1164 | // - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@ |
---|
| 1165 | // - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA |
---|
| 1166 | // three configurations corresponding to instruction processor requests : |
---|
[198] | 1167 | // - tlb miss => ICACHE_TLB_WAIT |
---|
[183] | 1168 | // - cacheable read miss => ICACHE_MISS_VICTIM |
---|
| 1169 | // - uncacheable read miss => ICACHE_UNC_REQ |
---|
| 1170 | // |
---|
| 1171 | // In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM |
---|
| 1172 | // using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the |
---|
| 1173 | // transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM |
---|
| 1174 | // state to select a slot and request a VCI transaction to the CLEANUP FSM. |
---|
| 1175 | // It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM. |
---|
| 1176 | // The availability of the missing cache line is signaled by the response fifo, |
---|
| 1177 | // and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state. |
---|
| 1178 | // |
---|
| 1179 | // In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction |
---|
[196] | 1180 | // to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop |
---|
[183] | 1181 | // when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait |
---|
| 1182 | // the response from the RSP FSM, through the response fifo. The missing instruction |
---|
| 1183 | // is directly returned to processor in this state. |
---|
| 1184 | // |
---|
| 1185 | // In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb |
---|
| 1186 | // using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register, |
---|
| 1187 | // and goes to the ICACHE_TLB_WAIT state. |
---|
| 1188 | // The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until |
---|
| 1189 | // the update is completed, and reset r_icache_tlb_miss_req to signal the completion. |
---|
| 1190 | // |
---|
[196] | 1191 | // The DCACHE FSM signals XTN processor requests to ICACHE_FSM |
---|
| 1192 | // using the r_dcache_xtn_req flip-flop. |
---|
[183] | 1193 | // The request opcode and the address to be invalidated are transmitted |
---|
| 1194 | // in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively. |
---|
| 1195 | // The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation |
---|
| 1196 | // is completed. |
---|
| 1197 | // |
---|
| 1198 | // The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error |
---|
| 1199 | // in a cache miss or uncacheable read VCI transaction. Nothing is written |
---|
| 1200 | // in the response fifo. This flip-flop is reset by the ICACHE-FSM. |
---|
| 1201 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
| 1202 | |
---|
[206] | 1203 | // default value for m_irsp |
---|
| 1204 | m_irsp.valid = false; |
---|
| 1205 | m_irsp.error = false; |
---|
| 1206 | m_irsp.instruction = 0; |
---|
[183] | 1207 | |
---|
| 1208 | switch( r_icache_fsm.read() ) |
---|
| 1209 | { |
---|
| 1210 | ///////////////// |
---|
| 1211 | case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent |
---|
| 1212 | // by DCACHE FSM, and coherence requests with a fixed priority: |
---|
| 1213 | // coherence > XTN > instruction |
---|
| 1214 | // We access the itlb and dcache in parallel with the virtual address |
---|
| 1215 | // for itlb, and with a speculative physical address for icache, |
---|
| 1216 | // computed during the previous cycle. |
---|
[198] | 1217 | { |
---|
[183] | 1218 | // coherence request from the target FSM |
---|
| 1219 | if ( r_tgt_icache_req.read() ) |
---|
| 1220 | { |
---|
| 1221 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
| 1222 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1223 | break; |
---|
| 1224 | } |
---|
| 1225 | |
---|
| 1226 | // Decoding processor XTN requests sent by DCACHE FSM |
---|
| 1227 | // These request are not executed in this IDLE state, because |
---|
| 1228 | // they require access to icache or itlb, that are already accessed |
---|
| 1229 | if ( r_dcache_xtn_req.read() ) |
---|
| 1230 | { |
---|
| 1231 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) |
---|
| 1232 | { |
---|
| 1233 | r_icache_fsm = ICACHE_XTN_TLB_FLUSH; |
---|
| 1234 | break; |
---|
| 1235 | } |
---|
| 1236 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH) |
---|
| 1237 | { |
---|
| 1238 | r_icache_flush_count = 0; |
---|
| 1239 | r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; |
---|
| 1240 | break; |
---|
| 1241 | } |
---|
| 1242 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) |
---|
| 1243 | { |
---|
| 1244 | r_icache_fsm = ICACHE_XTN_TLB_INVAL; |
---|
| 1245 | break; |
---|
| 1246 | } |
---|
| 1247 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) |
---|
| 1248 | { |
---|
| 1249 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; |
---|
| 1250 | break; |
---|
| 1251 | } |
---|
| 1252 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) |
---|
| 1253 | { |
---|
| 1254 | r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | |
---|
| 1255 | (paddr_t)r_mmu_word_lo.read(); |
---|
| 1256 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
| 1257 | break; |
---|
| 1258 | } |
---|
| 1259 | } // end if xtn_req |
---|
| 1260 | |
---|
| 1261 | // processor request |
---|
[205] | 1262 | if ( m_ireq.valid ) |
---|
[183] | 1263 | { |
---|
| 1264 | bool cacheable; |
---|
| 1265 | paddr_t paddr; |
---|
| 1266 | |
---|
| 1267 | // We register processor request |
---|
[205] | 1268 | r_icache_vaddr_save = m_ireq.addr; |
---|
[183] | 1269 | |
---|
| 1270 | // speculative icache access (if cache activated) |
---|
| 1271 | // we use the speculative PPN computed during the previous cycle |
---|
| 1272 | |
---|
| 1273 | uint32_t cache_inst = 0; |
---|
| 1274 | bool cache_hit = false; |
---|
| 1275 | |
---|
| 1276 | if ( r_mmu_mode.read() & INS_CACHE_MASK ) |
---|
| 1277 | { |
---|
| 1278 | paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) | |
---|
[205] | 1279 | ((paddr_t)m_ireq.addr & PAGE_K_MASK); |
---|
[183] | 1280 | |
---|
| 1281 | #ifdef INSTRUMENTATION |
---|
| 1282 | m_cpt_icache_data_read++; |
---|
| 1283 | m_cpt_icache_dir_read++; |
---|
| 1284 | #endif |
---|
| 1285 | cache_hit = r_icache.read( spc_paddr, |
---|
| 1286 | &cache_inst ); |
---|
| 1287 | } |
---|
| 1288 | |
---|
| 1289 | // systematic itlb access (if tlb activated) |
---|
| 1290 | // we use the virtual address |
---|
| 1291 | |
---|
| 1292 | paddr_t tlb_paddr; |
---|
| 1293 | pte_info_t tlb_flags; |
---|
| 1294 | size_t tlb_way; |
---|
| 1295 | size_t tlb_set; |
---|
| 1296 | paddr_t tlb_nline; |
---|
| 1297 | bool tlb_hit = false;; |
---|
| 1298 | |
---|
| 1299 | if ( r_mmu_mode.read() & INS_TLB_MASK ) |
---|
| 1300 | { |
---|
| 1301 | |
---|
| 1302 | #ifdef INSTRUMENTATION |
---|
| 1303 | m_cpt_itlb_read++; |
---|
| 1304 | #endif |
---|
[205] | 1305 | tlb_hit = r_itlb.translate( m_ireq.addr, |
---|
[183] | 1306 | &tlb_paddr, |
---|
| 1307 | &tlb_flags, |
---|
| 1308 | &tlb_nline, // unused |
---|
| 1309 | &tlb_way, // unused |
---|
| 1310 | &tlb_set ); // unused |
---|
| 1311 | } |
---|
| 1312 | |
---|
| 1313 | // We compute cacheability, physical address and check access rights: |
---|
| 1314 | // - If MMU activated : cacheability is defined by the C bit in the PTE, |
---|
| 1315 | // the physical address is obtained from the TLB, and the access rights are |
---|
| 1316 | // defined by the U and X bits in the PTE. |
---|
| 1317 | // - If MMU not activated : cacheability is defined by the segment table, |
---|
| 1318 | // the physical address is equal to the virtual address (identity mapping) |
---|
| 1319 | // and there is no access rights checking |
---|
| 1320 | |
---|
| 1321 | if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: |
---|
| 1322 | { |
---|
| 1323 | // cacheability |
---|
| 1324 | if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; |
---|
[205] | 1325 | else cacheable = m_cacheability_table[m_ireq.addr]; |
---|
[183] | 1326 | |
---|
| 1327 | // physical address |
---|
[205] | 1328 | paddr = (paddr_t)m_ireq.addr; |
---|
[183] | 1329 | } |
---|
| 1330 | else // itlb activated |
---|
| 1331 | { |
---|
| 1332 | if ( tlb_hit ) // tlb hit |
---|
| 1333 | { |
---|
| 1334 | // cacheability |
---|
| 1335 | if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; |
---|
| 1336 | else cacheable = tlb_flags.c; |
---|
| 1337 | |
---|
| 1338 | // physical address |
---|
| 1339 | paddr = tlb_paddr; |
---|
| 1340 | |
---|
| 1341 | // access rights checking |
---|
[205] | 1342 | if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) ) |
---|
[183] | 1343 | { |
---|
| 1344 | r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
[205] | 1345 | r_mmu_ibvar = m_ireq.addr; |
---|
| 1346 | m_irsp.valid = true; |
---|
| 1347 | m_irsp.error = true; |
---|
| 1348 | m_irsp.instruction = 0; |
---|
[183] | 1349 | break; |
---|
| 1350 | } |
---|
| 1351 | else if ( not tlb_flags.x ) |
---|
| 1352 | { |
---|
| 1353 | r_mmu_ietr = MMU_READ_EXEC_VIOLATION; |
---|
[205] | 1354 | r_mmu_ibvar = m_ireq.addr; |
---|
| 1355 | m_irsp.valid = true; |
---|
| 1356 | m_irsp.error = true; |
---|
| 1357 | m_irsp.instruction = 0; |
---|
[183] | 1358 | break; |
---|
| 1359 | } |
---|
| 1360 | } |
---|
| 1361 | // in case of TLB miss we send an itlb miss request to DCACHE FSM and break |
---|
| 1362 | else |
---|
| 1363 | { |
---|
| 1364 | |
---|
| 1365 | #ifdef INSTRUMENTATION |
---|
| 1366 | m_cpt_itlb_miss++; |
---|
| 1367 | #endif |
---|
| 1368 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
| 1369 | r_icache_tlb_miss_req = true; |
---|
| 1370 | break; |
---|
| 1371 | } |
---|
| 1372 | } // end if itlb activated |
---|
| 1373 | |
---|
| 1374 | // physical address registration (for next cycle) |
---|
| 1375 | r_icache_vci_paddr = paddr; |
---|
| 1376 | |
---|
[201] | 1377 | // We enter this section only in case of TLB hit: |
---|
| 1378 | // Finally, we get the instruction depending on cacheability, |
---|
| 1379 | // we send the response to processor, and compute next state |
---|
[183] | 1380 | if ( cacheable ) // cacheable read |
---|
| 1381 | { |
---|
[201] | 1382 | if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK) |
---|
| 1383 | != (paddr & ~PAGE_K_MASK) ) // speculative access KO |
---|
| 1384 | { |
---|
| 1385 | |
---|
| 1386 | #ifdef INSTRUMENTATION |
---|
| 1387 | m_cpt_icache_spc_miss++; |
---|
| 1388 | #endif |
---|
| 1389 | // we return an invalid response and stay in IDLE state |
---|
| 1390 | // the cache access will cost one extra cycle. |
---|
| 1391 | break; |
---|
| 1392 | } |
---|
| 1393 | |
---|
[183] | 1394 | if ( not cache_hit ) // cache miss |
---|
| 1395 | { |
---|
| 1396 | // in case of icache miss we send a request to CMD FSM, but we are |
---|
| 1397 | // blocked in IDLE state if the previous cleanup is not completed |
---|
| 1398 | if ( not r_icache_cleanup_req.read() ) |
---|
| 1399 | { |
---|
| 1400 | |
---|
| 1401 | #ifdef INSTRUMENTATION |
---|
| 1402 | m_cpt_icache_miss++; |
---|
| 1403 | #endif |
---|
| 1404 | r_icache_fsm = ICACHE_MISS_VICTIM; |
---|
| 1405 | r_icache_miss_req = true; |
---|
| 1406 | } |
---|
[201] | 1407 | break; |
---|
[183] | 1408 | } |
---|
| 1409 | else // cache hit |
---|
| 1410 | { |
---|
| 1411 | |
---|
| 1412 | #ifdef INSTRUMENTATION |
---|
| 1413 | m_cpt_ins_read++; |
---|
| 1414 | #endif |
---|
[205] | 1415 | m_irsp.valid = true; |
---|
| 1416 | m_irsp.instruction = cache_inst; |
---|
[183] | 1417 | } |
---|
| 1418 | } |
---|
| 1419 | else // non cacheable read |
---|
| 1420 | { |
---|
| 1421 | r_icache_unc_req = true; |
---|
| 1422 | r_icache_fsm = ICACHE_UNC_WAIT; |
---|
| 1423 | } |
---|
[205] | 1424 | } // end if m_ireq.valid |
---|
[183] | 1425 | break; |
---|
| 1426 | } |
---|
| 1427 | ///////////////////// |
---|
| 1428 | case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss |
---|
| 1429 | // the itlb is udated by the DCACHE FSM, as well as the |
---|
| 1430 | // r_mmu_ietr and r_mmu_ibvar registers in case of error. |
---|
| 1431 | // the itlb is not accessed by ICACHE FSM until DCACHE FSM |
---|
| 1432 | // reset the r_icache_tlb_miss_req flip-flop |
---|
| 1433 | // external coherence request are accepted in this state. |
---|
| 1434 | { |
---|
| 1435 | // external coherence request |
---|
| 1436 | if ( r_tgt_icache_req.read() ) |
---|
| 1437 | { |
---|
| 1438 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
| 1439 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1440 | break; |
---|
| 1441 | } |
---|
| 1442 | |
---|
[205] | 1443 | if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++; |
---|
[183] | 1444 | |
---|
| 1445 | // DCACHE FSM signals response by reseting the request flip-flop |
---|
| 1446 | if ( not r_icache_tlb_miss_req.read() ) |
---|
| 1447 | { |
---|
| 1448 | if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated |
---|
| 1449 | { |
---|
| 1450 | r_icache_tlb_rsp_error = false; |
---|
[205] | 1451 | m_irsp.error = true; |
---|
| 1452 | m_irsp.valid = true; |
---|
[183] | 1453 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1454 | } |
---|
| 1455 | else // tlb updated : return to IDLE state |
---|
| 1456 | { |
---|
| 1457 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1458 | } |
---|
| 1459 | } |
---|
| 1460 | break; |
---|
| 1461 | } |
---|
| 1462 | ////////////////////////// |
---|
| 1463 | case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries |
---|
| 1464 | { |
---|
| 1465 | r_itlb.flush(); |
---|
| 1466 | r_dcache_xtn_req = false; |
---|
| 1467 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1468 | break; |
---|
| 1469 | } |
---|
| 1470 | //////////////////////////// |
---|
| 1471 | case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using |
---|
| 1472 | // the r_icache_flush_count register as a slot counter. |
---|
| 1473 | // We loop in this state until all slots have been visited. |
---|
| 1474 | // A cleanup request is generated for each valid line |
---|
| 1475 | // and we are blocked until the previous cleanup is completed |
---|
| 1476 | { |
---|
| 1477 | if ( not r_icache_cleanup_req.read() ) |
---|
| 1478 | { |
---|
| 1479 | size_t way = r_icache_flush_count.read()/m_icache_sets; |
---|
| 1480 | size_t set = r_icache_flush_count.read()%m_icache_sets; |
---|
| 1481 | paddr_t nline; |
---|
| 1482 | bool cleanup_req = r_icache.inval( way, |
---|
| 1483 | set, |
---|
| 1484 | &nline ); |
---|
| 1485 | if ( cleanup_req ) |
---|
| 1486 | { |
---|
| 1487 | r_icache_cleanup_req = true; |
---|
| 1488 | r_icache_cleanup_line = nline; |
---|
| 1489 | } |
---|
| 1490 | r_icache_flush_count = r_icache_flush_count.read() + 1; |
---|
| 1491 | } |
---|
| 1492 | |
---|
| 1493 | if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) ) |
---|
| 1494 | { |
---|
| 1495 | r_dcache_xtn_req = false; |
---|
| 1496 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1497 | } |
---|
| 1498 | break; |
---|
| 1499 | } |
---|
| 1500 | ////////////////////////// |
---|
| 1501 | case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address |
---|
| 1502 | // stored in the r_dcache_p0_wdata register |
---|
| 1503 | { |
---|
| 1504 | r_itlb.inval(r_dcache_p0_wdata.read()); |
---|
| 1505 | r_dcache_xtn_req = false; |
---|
| 1506 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1507 | break; |
---|
| 1508 | } |
---|
| 1509 | /////////////////////////////// |
---|
| 1510 | case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address |
---|
| 1511 | // requires 3 cycles (in case of hit on itlb and icache). |
---|
| 1512 | // In this state, we access TLB to translate virtual address |
---|
| 1513 | // stored in the r_dcache_p0_wdata register. |
---|
| 1514 | { |
---|
| 1515 | paddr_t paddr; |
---|
| 1516 | bool hit; |
---|
| 1517 | |
---|
| 1518 | // read physical address in TLB when MMU activated |
---|
| 1519 | if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated |
---|
| 1520 | { |
---|
| 1521 | |
---|
| 1522 | #ifdef INSTRUMENTATION |
---|
| 1523 | m_cpt_itlb_read++; |
---|
| 1524 | #endif |
---|
| 1525 | hit = r_itlb.translate(r_dcache_p0_wdata.read(), |
---|
| 1526 | &paddr); |
---|
| 1527 | } |
---|
| 1528 | else // itlb not activated |
---|
| 1529 | { |
---|
| 1530 | paddr = (paddr_t)r_dcache_p0_wdata.read(); |
---|
| 1531 | hit = true; |
---|
| 1532 | } |
---|
| 1533 | |
---|
| 1534 | if ( hit ) // continue the selective inval process |
---|
| 1535 | { |
---|
| 1536 | r_icache_vci_paddr = paddr; |
---|
| 1537 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
| 1538 | } |
---|
| 1539 | else // miss : send a request to DCACHE FSM |
---|
| 1540 | { |
---|
| 1541 | |
---|
| 1542 | #ifdef INSTRUMENTATION |
---|
| 1543 | m_cpt_itlb_miss++; |
---|
| 1544 | #endif |
---|
| 1545 | r_icache_tlb_miss_req = true; |
---|
| 1546 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
| 1547 | } |
---|
| 1548 | break; |
---|
| 1549 | } |
---|
| 1550 | /////////////////////////////// |
---|
| 1551 | case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address |
---|
| 1552 | // require 2 cycles. In this state, we read dcache, |
---|
| 1553 | // with address stored in r_icache_vci_paddr register. |
---|
| 1554 | { |
---|
| 1555 | uint32_t data; |
---|
| 1556 | size_t way; |
---|
| 1557 | size_t set; |
---|
| 1558 | size_t word; |
---|
| 1559 | bool hit = r_icache.read(r_icache_vci_paddr.read(), |
---|
| 1560 | &data, |
---|
| 1561 | &way, |
---|
| 1562 | &set, |
---|
| 1563 | &word); |
---|
| 1564 | if ( hit ) // inval to be done |
---|
| 1565 | { |
---|
| 1566 | r_icache_miss_way = way; |
---|
| 1567 | r_icache_miss_set = set; |
---|
| 1568 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; |
---|
| 1569 | } |
---|
| 1570 | else // miss : acknowlege the XTN request and return |
---|
| 1571 | { |
---|
| 1572 | r_dcache_xtn_req = false; |
---|
| 1573 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1574 | } |
---|
| 1575 | break; |
---|
| 1576 | } |
---|
| 1577 | /////////////////////////////// |
---|
| 1578 | case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup. |
---|
| 1579 | // We are blocked if the previous cleanup is not completed |
---|
| 1580 | { |
---|
| 1581 | paddr_t nline; |
---|
| 1582 | |
---|
| 1583 | if ( not r_icache_cleanup_req.read() ) |
---|
| 1584 | { |
---|
| 1585 | r_icache.inval( r_icache_miss_way.read(), |
---|
| 1586 | r_icache_miss_set.read(), |
---|
| 1587 | &nline ); |
---|
| 1588 | |
---|
| 1589 | // request cleanup |
---|
| 1590 | r_icache_cleanup_req = true; |
---|
| 1591 | r_icache_cleanup_line = nline; |
---|
| 1592 | // acknowledge the XTN request and return |
---|
| 1593 | r_dcache_xtn_req = false; |
---|
| 1594 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1595 | } |
---|
| 1596 | break; |
---|
| 1597 | } |
---|
| 1598 | |
---|
| 1599 | //////////////////////// |
---|
| 1600 | case ICACHE_MISS_VICTIM: // Selects a victim line |
---|
| 1601 | // Set the r_icache_cleanup_req flip-flop |
---|
| 1602 | // when the selected slot is not empty |
---|
| 1603 | { |
---|
[205] | 1604 | if ( m_ireq.valid ) m_cost_ins_miss_frz++; |
---|
[183] | 1605 | |
---|
| 1606 | bool valid; |
---|
| 1607 | size_t way; |
---|
| 1608 | size_t set; |
---|
| 1609 | paddr_t victim; |
---|
| 1610 | |
---|
| 1611 | valid = r_icache.victim_select(r_icache_vci_paddr.read(), |
---|
| 1612 | &victim, |
---|
| 1613 | &way, |
---|
| 1614 | &set); |
---|
| 1615 | r_icache_miss_way = way; |
---|
| 1616 | r_icache_miss_set = set; |
---|
| 1617 | |
---|
| 1618 | if ( valid ) |
---|
| 1619 | { |
---|
| 1620 | r_icache_cleanup_req = true; |
---|
| 1621 | r_icache_cleanup_line = victim; |
---|
| 1622 | r_icache_fsm = ICACHE_MISS_INVAL; |
---|
| 1623 | } |
---|
| 1624 | else |
---|
| 1625 | { |
---|
| 1626 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
| 1627 | } |
---|
| 1628 | break; |
---|
| 1629 | } |
---|
| 1630 | /////////////////////// |
---|
| 1631 | case ICACHE_MISS_INVAL: // invalidate the victim line |
---|
| 1632 | { |
---|
| 1633 | paddr_t nline; |
---|
| 1634 | |
---|
| 1635 | r_icache.inval( r_icache_miss_way.read(), |
---|
[194] | 1636 | r_icache_miss_set.read(), |
---|
[183] | 1637 | &nline ); // unused |
---|
| 1638 | |
---|
| 1639 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
| 1640 | break; |
---|
| 1641 | } |
---|
| 1642 | ////////////////////// |
---|
| 1643 | case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM |
---|
| 1644 | { |
---|
[205] | 1645 | if ( m_ireq.valid ) m_cost_ins_miss_frz++; |
---|
[183] | 1646 | |
---|
| 1647 | // external coherence request |
---|
| 1648 | if ( r_tgt_icache_req.read() ) |
---|
| 1649 | { |
---|
| 1650 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
| 1651 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1652 | break; |
---|
| 1653 | } |
---|
| 1654 | |
---|
[198] | 1655 | if ( r_vci_rsp_ins_error.read() ) // bus error |
---|
| 1656 | { |
---|
[183] | 1657 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
| 1658 | r_mmu_ibvar = r_icache_vaddr_save.read(); |
---|
[205] | 1659 | m_irsp.valid = true; |
---|
| 1660 | m_irsp.error = true; |
---|
[183] | 1661 | r_vci_rsp_ins_error = false; |
---|
| 1662 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1663 | } |
---|
| 1664 | else if ( r_vci_rsp_fifo_icache.rok() ) // response available |
---|
| 1665 | { |
---|
| 1666 | r_icache_miss_word = 0; |
---|
| 1667 | r_icache_fsm = ICACHE_MISS_UPDT; |
---|
[198] | 1668 | } |
---|
[183] | 1669 | break; |
---|
| 1670 | } |
---|
| 1671 | ////////////////////// |
---|
| 1672 | case ICACHE_MISS_UPDT: // update the cache (one word per cycle) |
---|
| 1673 | { |
---|
[205] | 1674 | if ( m_ireq.valid ) m_cost_ins_miss_frz++; |
---|
[183] | 1675 | |
---|
| 1676 | if ( r_vci_rsp_fifo_icache.rok() ) // response available |
---|
| 1677 | { |
---|
| 1678 | if ( r_icache_miss_inval ) // Matching coherence request |
---|
| 1679 | // We pop the response FIFO, without updating the cache |
---|
| 1680 | // We send a cleanup for the missing line at the last word |
---|
| 1681 | // Blocked if the previous cleanup is not completed |
---|
| 1682 | { |
---|
| 1683 | if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word |
---|
| 1684 | { |
---|
| 1685 | vci_rsp_fifo_icache_get = true; |
---|
| 1686 | r_icache_miss_word = r_icache_miss_word.read() + 1; |
---|
| 1687 | } |
---|
| 1688 | else // last word |
---|
| 1689 | { |
---|
| 1690 | if ( not r_icache_cleanup_req.read() ) // no pending cleanup |
---|
| 1691 | { |
---|
| 1692 | vci_rsp_fifo_icache_get = true; |
---|
| 1693 | r_icache_cleanup_req = true; |
---|
| 1694 | r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2)); |
---|
| 1695 | r_icache_miss_inval = false; |
---|
| 1696 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1697 | } |
---|
| 1698 | } |
---|
| 1699 | } |
---|
| 1700 | else // No matching coherence request |
---|
| 1701 | // We pop the FIFO and update the cache |
---|
| 1702 | // We update the directory at the last word |
---|
| 1703 | { |
---|
| 1704 | |
---|
| 1705 | #ifdef INSTRUMENTATION |
---|
| 1706 | m_cpt_icache_data_write++; |
---|
| 1707 | #endif |
---|
| 1708 | r_icache.write( r_icache_miss_way.read(), |
---|
| 1709 | r_icache_miss_set.read(), |
---|
| 1710 | r_icache_miss_word.read(), |
---|
| 1711 | r_vci_rsp_fifo_icache.read() ); |
---|
| 1712 | vci_rsp_fifo_icache_get = true; |
---|
| 1713 | r_icache_miss_word = r_icache_miss_word.read() + 1; |
---|
| 1714 | if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word |
---|
| 1715 | { |
---|
| 1716 | |
---|
| 1717 | #ifdef INSTRUMENTATION |
---|
| 1718 | m_cpt_icache_dir_write++; |
---|
| 1719 | #endif |
---|
| 1720 | r_icache.victim_update_tag( r_icache_vci_paddr.read(), |
---|
| 1721 | r_icache_miss_way.read(), |
---|
| 1722 | r_icache_miss_set.read() ); |
---|
| 1723 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1724 | } |
---|
| 1725 | } |
---|
| 1726 | } |
---|
| 1727 | break; |
---|
| 1728 | } |
---|
| 1729 | //////////////////// |
---|
| 1730 | case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM |
---|
| 1731 | // |
---|
| 1732 | { |
---|
| 1733 | // external coherence request |
---|
| 1734 | if ( r_tgt_icache_req.read() ) |
---|
| 1735 | { |
---|
| 1736 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
| 1737 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1738 | break; |
---|
| 1739 | } |
---|
| 1740 | |
---|
| 1741 | if ( r_vci_rsp_ins_error.read() ) // bus error |
---|
| 1742 | { |
---|
| 1743 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
[205] | 1744 | r_mmu_ibvar = m_ireq.addr; |
---|
[183] | 1745 | r_vci_rsp_ins_error = false; |
---|
[205] | 1746 | m_irsp.valid = true; |
---|
| 1747 | m_irsp.error = true; |
---|
[183] | 1748 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1749 | } |
---|
| 1750 | else if (r_vci_rsp_fifo_icache.rok() ) // instruction available |
---|
| 1751 | { |
---|
| 1752 | vci_rsp_fifo_icache_get = true; |
---|
| 1753 | r_icache_fsm = ICACHE_IDLE; |
---|
[205] | 1754 | if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified |
---|
[183] | 1755 | { |
---|
[205] | 1756 | m_irsp.valid = true; |
---|
| 1757 | m_irsp.instruction = r_vci_rsp_fifo_icache.read(); |
---|
[183] | 1758 | } |
---|
| 1759 | } |
---|
| 1760 | break; |
---|
| 1761 | } |
---|
| 1762 | ///////////////////// |
---|
| 1763 | case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm |
---|
| 1764 | // handling coherence requests. |
---|
| 1765 | // the return state is defined in r_icache_fsm_save. |
---|
| 1766 | { |
---|
| 1767 | paddr_t paddr = r_tgt_paddr.read(); |
---|
| 1768 | paddr_t mask = ~((m_icache_words<<2)-1); |
---|
| 1769 | |
---|
| 1770 | if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and |
---|
| 1771 | ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss |
---|
| 1772 | { |
---|
| 1773 | r_icache_miss_inval = true; // signaling the matching |
---|
| 1774 | r_tgt_icache_req = false; // coherence request completed |
---|
| 1775 | r_tgt_icache_rsp = r_tgt_update.read(); // response required if update |
---|
| 1776 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1777 | } |
---|
| 1778 | else // no match |
---|
| 1779 | { |
---|
| 1780 | |
---|
| 1781 | #ifdef INSTRUMENTATION |
---|
| 1782 | m_cpt_icache_dir_read++; |
---|
| 1783 | #endif |
---|
| 1784 | uint32_t inst; |
---|
| 1785 | size_t way; |
---|
| 1786 | size_t set; |
---|
| 1787 | size_t word; |
---|
| 1788 | bool hit = r_icache.read(paddr, |
---|
| 1789 | &inst, |
---|
| 1790 | &way, |
---|
| 1791 | &set, |
---|
| 1792 | &word); |
---|
| 1793 | r_icache_cc_way = way; |
---|
| 1794 | r_icache_cc_set = set; |
---|
| 1795 | |
---|
| 1796 | if ( hit and r_tgt_update.read() ) // hit update |
---|
| 1797 | { |
---|
| 1798 | r_icache_fsm = ICACHE_CC_UPDT; |
---|
| 1799 | r_icache_cc_word = r_tgt_word_min.read(); |
---|
| 1800 | } |
---|
| 1801 | else if ( hit and not r_tgt_update.read() ) // hit inval |
---|
| 1802 | { |
---|
| 1803 | r_icache_fsm = ICACHE_CC_INVAL; |
---|
| 1804 | } |
---|
| 1805 | else // miss can happen |
---|
| 1806 | { |
---|
| 1807 | r_tgt_icache_req = false; |
---|
| 1808 | r_tgt_icache_rsp = r_tgt_update.read(); |
---|
| 1809 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1810 | } |
---|
| 1811 | } |
---|
| 1812 | break; |
---|
| 1813 | } |
---|
| 1814 | |
---|
| 1815 | ///////////////////// |
---|
| 1816 | case ICACHE_CC_INVAL: // invalidate a cache line |
---|
| 1817 | { |
---|
| 1818 | paddr_t nline; |
---|
| 1819 | r_icache.inval( r_icache_cc_way.read(), |
---|
| 1820 | r_icache_cc_set.read(), |
---|
| 1821 | &nline ); |
---|
| 1822 | |
---|
| 1823 | r_tgt_icache_req = false; |
---|
| 1824 | r_tgt_icache_rsp = true; |
---|
| 1825 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1826 | break; |
---|
| 1827 | } |
---|
| 1828 | //////////////////// |
---|
| 1829 | case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max) |
---|
| 1830 | { |
---|
| 1831 | size_t word = r_icache_cc_word.read(); |
---|
| 1832 | size_t way = r_icache_cc_way.read(); |
---|
| 1833 | size_t set = r_icache_cc_set.read(); |
---|
| 1834 | |
---|
| 1835 | r_icache.write( way, |
---|
| 1836 | set, |
---|
| 1837 | word, |
---|
| 1838 | r_tgt_buf[word], |
---|
| 1839 | r_tgt_be[word] ); |
---|
| 1840 | |
---|
| 1841 | r_icache_cc_word = word+1; |
---|
| 1842 | |
---|
| 1843 | if ( word == r_tgt_word_max.read() ) // last word |
---|
| 1844 | { |
---|
| 1845 | r_tgt_icache_req = false; |
---|
| 1846 | r_tgt_icache_rsp = true; |
---|
| 1847 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1848 | } |
---|
| 1849 | break; |
---|
| 1850 | } |
---|
| 1851 | |
---|
| 1852 | } // end switch r_icache_fsm |
---|
| 1853 | |
---|
| 1854 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 1855 | // DCACHE FSM |
---|
| 1856 | // |
---|
| 1857 | // Both the Cacheability Table, and the MMU cacheable bit are used to define |
---|
| 1858 | // the cacheability, depending on the MMU mode. |
---|
| 1859 | // |
---|
| 1860 | // 1/ Coherence requests : |
---|
| 1861 | // There is a coherence request when the tgt_dcache_req flip-flop is set, |
---|
| 1862 | // requesting a line invalidation or a line update. |
---|
| 1863 | // Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states. |
---|
| 1864 | // The actions associated to the pre-empted state are not executed, the DCACHE FSM |
---|
| 1865 | // goes to the CC_CHECK state to execute the requested action, and returns to the |
---|
| 1866 | // pre-empted state. |
---|
| 1867 | // |
---|
[205] | 1868 | // 2/ TLB miss |
---|
| 1869 | // The page tables can be cacheable. |
---|
| 1870 | // In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated |
---|
| 1871 | // sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE, |
---|
| 1872 | // this sub-fsm implement the table-walk... |
---|
| 1873 | // |
---|
| 1874 | // 3/ processor requests : |
---|
[183] | 1875 | // Processor READ, WRITE, LL or SC requests are taken in IDLE state only. |
---|
| 1876 | // The IDLE state implements a three stages pipe-line to handle write bursts: |
---|
| 1877 | // - The physical address is computed by dtlb in stage P0. |
---|
| 1878 | // - The registration in wbuf and the dcache hit are computed in stage P1. |
---|
| 1879 | // - The dcache update is done in stage P2. |
---|
[206] | 1880 | // WRITE or SC requests can require a PTE Dirty bit update (in memory), |
---|
| 1881 | // that is done (before handling the processor request) by a dedicated sub-fsm |
---|
| 1882 | // (DCACHE_DIRTY_TLB_SET state). |
---|
| 1883 | // If a PTE is modified, both the itlb and dtlb are selectively, but sequencially |
---|
[205] | 1884 | // cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state). |
---|
[183] | 1885 | // If there is no write in the pipe, dcache and dtlb are accessed in parallel, |
---|
| 1886 | // (virtual address for itlb, and speculative physical address computed during |
---|
[206] | 1887 | // previous cycle for dcache) in order to return the data in one cycle for a READ |
---|
| 1888 | // request. We just pay an extra cycle when the speculative access is failing. |
---|
[183] | 1889 | // |
---|
[205] | 1890 | // 4/ Atomic instructions LL/SC |
---|
[183] | 1891 | // The LL/SC address can be cacheable or non cacheable. |
---|
| 1892 | // The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and |
---|
| 1893 | // r_dcache_ll_data are stored in the L1 cache controller, and not in the |
---|
| 1894 | // memory controller. |
---|
| 1895 | // - LL requests from the processor are transmitted as standard VCI |
---|
| 1896 | // READ transactions (one word / one line, depending on the cacheability). |
---|
| 1897 | // - SC requests from the processor are systematically transmitted to the |
---|
[205] | 1898 | // memory cache as Compare&swap requests (both the data value stored in the |
---|
[183] | 1899 | // r_dcache_ll_data register and the new value). |
---|
[205] | 1900 | // The cache is not updated, as this is done in case of success by the |
---|
| 1901 | // coherence transaction. |
---|
[183] | 1902 | // |
---|
[205] | 1903 | // 5/ Non cacheable access: |
---|
[183] | 1904 | // This component implement a strong order between non cacheable access |
---|
| 1905 | // (read or write) : A new non cacheable VCI transaction starts only when |
---|
| 1906 | // the previous non cacheable transaction is completed. Both cacheable and |
---|
| 1907 | // non cacheable transactions use the write buffer, but the DCACHE FSM registers |
---|
| 1908 | // a non cacheable write transaction posted in the write buffer by setting the |
---|
| 1909 | // r_dcache_pending_unc_write flip_flop. All other non cacheable requests |
---|
| 1910 | // are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the |
---|
| 1911 | // pending non cacheable write transaction completes). |
---|
| 1912 | // |
---|
[205] | 1913 | // 6/ Error handling: |
---|
[183] | 1914 | // When the MMU is not activated, Read Bus Errors are synchronous events, |
---|
| 1915 | // but Write Bus Errors are asynchronous events (processor is not frozen). |
---|
| 1916 | // - If a Read Bus Error is detected, the VCI_RSP FSM sets the |
---|
| 1917 | // r_vci_rsp_data_error flip-flop, without writing any data in the |
---|
| 1918 | // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled |
---|
| 1919 | // by the DCACHE FSM. |
---|
| 1920 | // - If a Write Bus Error is detected, the VCI_RSP FSM signals |
---|
| 1921 | // the asynchronous error using the setWriteBerr() method. |
---|
| 1922 | // When the MMU is activated bus error are rare events, as the MMU |
---|
| 1923 | // checks the physical address before the VCI transaction starts. |
---|
| 1924 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
| 1925 | |
---|
[206] | 1926 | // default value for m_drsp |
---|
[205] | 1927 | m_drsp.valid = false; |
---|
[206] | 1928 | m_drsp.error = false; |
---|
| 1929 | m_drsp.rdata = 0; |
---|
[183] | 1930 | |
---|
| 1931 | switch ( r_dcache_fsm.read() ) |
---|
| 1932 | { |
---|
| 1933 | case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state : |
---|
[206] | 1934 | // 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE |
---|
[198] | 1935 | // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK |
---|
[183] | 1936 | // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS |
---|
[198] | 1937 | // 4) XTN request (processor) => DCACHE_XTN_* |
---|
| 1938 | // 5) DTLB miss (processor) => DCACHE_TLB_MISS |
---|
[183] | 1939 | // 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM |
---|
[206] | 1940 | // 7) Uncacheable read (processor) => DCACHE_UNC_WAIT |
---|
| 1941 | // 8) SC access (processor) => DCACHE_SC_WAIT |
---|
| 1942 | // |
---|
| 1943 | // The dtlb is unconditionally accessed to translate the |
---|
| 1944 | // virtual adress from processor. |
---|
| 1945 | // |
---|
[183] | 1946 | // There is 4 configurations to access the cache, |
---|
| 1947 | // depending on the pipe-line state, defined |
---|
[201] | 1948 | // by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated |
---|
| 1949 | // and r_dcache_p1_valid (V1) flip-flop : P2 stage activated |
---|
[183] | 1950 | // V0 / V1 / Data / Directory / comment |
---|
| 1951 | // 0 / 0 / read(A0) / read(A0) / read speculative access |
---|
| 1952 | // 0 / 1 / write(A2) / nop / read request delayed |
---|
| 1953 | // 1 / 0 / nop / read(A1) / read request delayed |
---|
| 1954 | // 1 / 1 / write(A2) / read(A1) / read request delayed |
---|
| 1955 | { |
---|
| 1956 | //////////////////////////////////////////////////////////////////////////////// |
---|
| 1957 | // Handling P2 pipe-line stage |
---|
| 1958 | // Inputs are r_dcache_p1_* registers. |
---|
[206] | 1959 | // If r_dcache_p1_valid is true, we update the local copy in dcache. |
---|
| 1960 | // If the modified cache line has copies in TLBs, we launch a TLB invalidate |
---|
| 1961 | // operation, going to DCACHE_INVAL_TLB_SCAN state. |
---|
[183] | 1962 | |
---|
[206] | 1963 | bool tlb_inval_required = false; |
---|
[183] | 1964 | |
---|
| 1965 | if ( r_dcache_p1_valid.read() ) // P2 stage activated |
---|
| 1966 | { |
---|
[204] | 1967 | size_t way = r_dcache_p1_cache_way.read(); |
---|
| 1968 | size_t set = r_dcache_p1_cache_set.read(); |
---|
| 1969 | size_t word = r_dcache_p1_cache_word.read(); |
---|
[183] | 1970 | uint32_t wdata = r_dcache_p1_wdata.read(); |
---|
| 1971 | vci_be_t be = r_dcache_p1_be.read(); |
---|
| 1972 | |
---|
[206] | 1973 | r_dcache.write( way, |
---|
| 1974 | set, |
---|
| 1975 | word, |
---|
| 1976 | wdata, |
---|
| 1977 | be ); |
---|
[183] | 1978 | #ifdef INSTRUMENTATION |
---|
| 1979 | m_cpt_dcache_data_write++; |
---|
| 1980 | #endif |
---|
[206] | 1981 | // cache update after a WRITE hit can require itlb & dtlb inval or flush |
---|
| 1982 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) |
---|
[183] | 1983 | { |
---|
[206] | 1984 | tlb_inval_required = true; |
---|
| 1985 | r_dcache_tlb_inval_count = 0; |
---|
| 1986 | r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2)); |
---|
| 1987 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[183] | 1988 | } |
---|
[206] | 1989 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) |
---|
| 1990 | { |
---|
| 1991 | r_itlb.reset(); |
---|
| 1992 | r_dtlb.reset(); |
---|
| 1993 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
| 1994 | } |
---|
[183] | 1995 | |
---|
| 1996 | #if DEBUG_DCACHE |
---|
[198] | 1997 | if ( m_debug_dcache_fsm ) |
---|
| 1998 | { |
---|
[206] | 1999 | std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec |
---|
| 2000 | << " / WAY = " << way |
---|
| 2001 | << " / SET = " << set |
---|
| 2002 | << " / WORD = " << word << std::hex |
---|
| 2003 | << " / DATA = " << wdata |
---|
| 2004 | << " / BE = " << be << std::endl; |
---|
[198] | 2005 | } |
---|
[183] | 2006 | #endif |
---|
| 2007 | } // end P2 stage |
---|
| 2008 | |
---|
| 2009 | /////////////////////////////////////////////////////////////////////////// |
---|
| 2010 | // Handling P1 pipe-line stage |
---|
| 2011 | // Inputs are r_dcache_p0_* registers. |
---|
[206] | 2012 | // We must write into wbuf and test the hit in dcache. |
---|
| 2013 | // If the write request is non cacheable, and there is a pending |
---|
| 2014 | // non cacheable write, or if the write buffer is full, we break, |
---|
| 2015 | // because the P0 and P1 pipe-line stages are frozen until the write |
---|
| 2016 | // request registration is possible, but he P2 stage is not frozen. |
---|
| 2017 | // The r_dcache_p1_valid bit must be computed at all cycles, and |
---|
| 2018 | // the P2 stage must be activated if there is local copy in dcache. |
---|
[183] | 2019 | |
---|
[206] | 2020 | if ( r_dcache_p0_valid.read() ) // P1 stage activated |
---|
[183] | 2021 | { |
---|
| 2022 | // write not cacheable, and previous non cacheable write registered |
---|
| 2023 | if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() ) |
---|
| 2024 | { |
---|
| 2025 | r_dcache_p1_valid = false; |
---|
| 2026 | break; |
---|
| 2027 | } |
---|
| 2028 | |
---|
| 2029 | // try a registration into write buffer |
---|
| 2030 | bool wok = r_wbuf.write( r_dcache_p0_paddr.read(), |
---|
| 2031 | r_dcache_p0_be.read(), |
---|
| 2032 | r_dcache_p0_wdata.read(), |
---|
| 2033 | r_dcache_p0_cacheable.read() ); |
---|
| 2034 | #ifdef INSTRUMENTATION |
---|
| 2035 | m_cpt_wbuf_write++; |
---|
| 2036 | #endif |
---|
| 2037 | // write buffer full |
---|
| 2038 | if ( not wok ) |
---|
| 2039 | { |
---|
| 2040 | r_dcache_p1_valid = false; |
---|
| 2041 | break; |
---|
| 2042 | } |
---|
| 2043 | // update the write_buffer state extension |
---|
| 2044 | r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read(); |
---|
| 2045 | |
---|
[206] | 2046 | // read directory to check local copy |
---|
[183] | 2047 | size_t cache_way; |
---|
| 2048 | size_t cache_set; |
---|
| 2049 | size_t cache_word; |
---|
| 2050 | bool local_copy; |
---|
| 2051 | if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated |
---|
| 2052 | { |
---|
| 2053 | local_copy = r_dcache.hit( r_dcache_p0_paddr.read(), |
---|
| 2054 | &cache_way, |
---|
| 2055 | &cache_set, |
---|
| 2056 | &cache_word ); |
---|
| 2057 | #ifdef INSTRUMENTATION |
---|
| 2058 | m_cpt_dcache_dir_read++; |
---|
| 2059 | #endif |
---|
| 2060 | } |
---|
| 2061 | else |
---|
| 2062 | { |
---|
| 2063 | local_copy = false; |
---|
| 2064 | } |
---|
| 2065 | |
---|
[206] | 2066 | // store values for P2 pipe stage |
---|
| 2067 | if ( local_copy ) |
---|
[183] | 2068 | { |
---|
| 2069 | r_dcache_p1_valid = true; |
---|
| 2070 | r_dcache_p1_wdata = r_dcache_p0_wdata.read(); |
---|
| 2071 | r_dcache_p1_be = r_dcache_p0_be.read(); |
---|
| 2072 | r_dcache_p1_paddr = r_dcache_p0_paddr.read(); |
---|
| 2073 | r_dcache_p1_cache_way = cache_way; |
---|
| 2074 | r_dcache_p1_cache_set = cache_set; |
---|
| 2075 | r_dcache_p1_cache_word = cache_word; |
---|
| 2076 | } |
---|
| 2077 | else |
---|
| 2078 | { |
---|
| 2079 | r_dcache_p1_valid = false; |
---|
| 2080 | } |
---|
| 2081 | } |
---|
| 2082 | else // P1 stage not activated |
---|
| 2083 | { |
---|
| 2084 | r_dcache_p1_valid = false; |
---|
| 2085 | } // end P1 stage |
---|
| 2086 | |
---|
[206] | 2087 | ///////////////////////////////////////////////////////////////////////////////// |
---|
[204] | 2088 | // handling P0 pipe-line stage |
---|
[205] | 2089 | // This stage is controlling r_dcache_fsm and r_dcache_p0_* registers. |
---|
[206] | 2090 | // The r_dcache_p0_valid flip-flop is only set in case of a WRITE request. |
---|
[204] | 2091 | // - the TLB invalidate requests have the highest priority, |
---|
[183] | 2092 | // - then the external coherence requests, |
---|
| 2093 | // - then the itlb miss requests, |
---|
| 2094 | // - and finally the processor requests. |
---|
[205] | 2095 | // If dtlb is activated, there is an unconditionnal access to dtlb, |
---|
| 2096 | // for address translation. |
---|
[206] | 2097 | // 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if |
---|
| 2098 | // dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully |
---|
| 2099 | // handled by the IDLE state), and the processor request is acknowledged. |
---|
| 2100 | // 2) A processor READ or LL request generate a simultaneouss access to |
---|
[205] | 2101 | // both dcache data and dcache directoty, using speculative PPN, but |
---|
| 2102 | // is delayed if the write pipe-line is not empty. |
---|
| 2103 | // In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or |
---|
| 2104 | // DCACHE_MISS_WAIT states. |
---|
[206] | 2105 | // 3) A processor SC request is delayed until the write pipe-line is empty. |
---|
[205] | 2106 | // A VCI SC transaction is launched, and we wait the VCI response in |
---|
| 2107 | // DCACHE_SC_WAIT state. It can be completed by a "long write" if the |
---|
| 2108 | // PTE dirty bit must be updated in dtlb, dcache, and RAM. |
---|
| 2109 | // The data is not modified in dcache, as it will be done by the |
---|
| 2110 | // coherence transaction. |
---|
[183] | 2111 | |
---|
[204] | 2112 | // TLB inval required |
---|
| 2113 | if ( tlb_inval_required ) |
---|
[183] | 2114 | { |
---|
[204] | 2115 | r_dcache_fsm_save = DCACHE_IDLE; |
---|
| 2116 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
[205] | 2117 | r_dcache_p0_valid = false; |
---|
[183] | 2118 | } |
---|
| 2119 | // external coherence request |
---|
| 2120 | else if ( r_tgt_dcache_req.read() ) |
---|
| 2121 | { |
---|
| 2122 | r_dcache_fsm_save = DCACHE_IDLE; |
---|
[204] | 2123 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
[205] | 2124 | r_dcache_p0_valid = false; |
---|
[183] | 2125 | } |
---|
| 2126 | |
---|
| 2127 | // itlb miss request |
---|
| 2128 | else if ( r_icache_tlb_miss_req.read() ) |
---|
| 2129 | { |
---|
| 2130 | r_dcache_tlb_ins = true; |
---|
| 2131 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
| 2132 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
[205] | 2133 | r_dcache_p0_valid = false; |
---|
[183] | 2134 | } |
---|
| 2135 | |
---|
| 2136 | // processor request |
---|
[205] | 2137 | else if ( m_dreq.valid ) |
---|
[183] | 2138 | { |
---|
| 2139 | // dcache access using speculative PPN only if pipe-line empty |
---|
| 2140 | paddr_t cache_paddr; |
---|
| 2141 | size_t cache_way; |
---|
| 2142 | size_t cache_set; |
---|
| 2143 | size_t cache_word; |
---|
| 2144 | uint32_t cache_rdata; |
---|
| 2145 | bool cache_hit; |
---|
| 2146 | |
---|
| 2147 | if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated |
---|
| 2148 | not r_dcache_p0_valid.read() and |
---|
| 2149 | not r_dcache_p1_valid.read() ) // pipe-line empty |
---|
| 2150 | { |
---|
| 2151 | cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) | |
---|
[205] | 2152 | ((paddr_t)m_dreq.addr & PAGE_K_MASK); |
---|
[183] | 2153 | |
---|
| 2154 | cache_hit = r_dcache.read( cache_paddr, |
---|
| 2155 | &cache_rdata, |
---|
| 2156 | &cache_way, |
---|
| 2157 | &cache_set, |
---|
| 2158 | &cache_word ); |
---|
| 2159 | #ifdef INSTRUMENTATION |
---|
| 2160 | m_cpt_dcache_dir_read++; |
---|
| 2161 | m_cpt_dcache_data_read++; |
---|
| 2162 | #endif |
---|
| 2163 | } |
---|
| 2164 | else |
---|
| 2165 | { |
---|
| 2166 | cache_hit = false; |
---|
| 2167 | } // end dcache access |
---|
| 2168 | |
---|
| 2169 | // systematic dtlb access using virtual address |
---|
| 2170 | paddr_t tlb_paddr; |
---|
| 2171 | pte_info_t tlb_flags; |
---|
| 2172 | size_t tlb_way; |
---|
| 2173 | size_t tlb_set; |
---|
| 2174 | paddr_t tlb_nline; |
---|
| 2175 | bool tlb_hit; |
---|
| 2176 | |
---|
[206] | 2177 | if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated |
---|
[183] | 2178 | { |
---|
[205] | 2179 | tlb_hit = r_dtlb.translate( m_dreq.addr, |
---|
[183] | 2180 | &tlb_paddr, |
---|
| 2181 | &tlb_flags, |
---|
| 2182 | &tlb_nline, |
---|
| 2183 | &tlb_way, |
---|
| 2184 | &tlb_set ); |
---|
| 2185 | #ifdef INSTRUMENTATION |
---|
| 2186 | m_cpt_dtlb_read++; |
---|
| 2187 | #endif |
---|
| 2188 | } |
---|
| 2189 | else |
---|
| 2190 | { |
---|
| 2191 | tlb_hit = false; |
---|
| 2192 | } // end dtlb access |
---|
| 2193 | |
---|
| 2194 | // register the processor request |
---|
[205] | 2195 | r_dcache_p0_vaddr = m_dreq.addr; |
---|
| 2196 | r_dcache_p0_be = m_dreq.be; |
---|
| 2197 | r_dcache_p0_wdata = m_dreq.wdata; |
---|
[183] | 2198 | |
---|
| 2199 | // Handling READ XTN requests from processor |
---|
| 2200 | // They are executed in this DCACHE_IDLE state. |
---|
| 2201 | // The processor must not be in user mode |
---|
[205] | 2202 | if (m_dreq.type == iss_t::XTN_READ) |
---|
[183] | 2203 | { |
---|
[205] | 2204 | int xtn_opcode = (int)m_dreq.addr/4; |
---|
[183] | 2205 | |
---|
| 2206 | // checking processor mode: |
---|
[205] | 2207 | if (m_dreq.mode == iss_t::MODE_USER) |
---|
[183] | 2208 | { |
---|
| 2209 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
[205] | 2210 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2211 | m_drsp.valid = true; |
---|
| 2212 | m_drsp.error = true; |
---|
[183] | 2213 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2214 | } |
---|
| 2215 | else |
---|
| 2216 | { |
---|
| 2217 | switch( xtn_opcode ) |
---|
| 2218 | { |
---|
| 2219 | case iss_t::XTN_INS_ERROR_TYPE: |
---|
[205] | 2220 | m_drsp.rdata = r_mmu_ietr.read(); |
---|
| 2221 | m_drsp.valid = true; |
---|
[183] | 2222 | break; |
---|
| 2223 | |
---|
| 2224 | case iss_t::XTN_DATA_ERROR_TYPE: |
---|
[205] | 2225 | m_drsp.rdata = r_mmu_detr.read(); |
---|
| 2226 | m_drsp.valid = true; |
---|
[183] | 2227 | break; |
---|
| 2228 | |
---|
| 2229 | case iss_t::XTN_INS_BAD_VADDR: |
---|
[205] | 2230 | m_drsp.rdata = r_mmu_ibvar.read(); |
---|
| 2231 | m_drsp.valid = true; |
---|
[183] | 2232 | break; |
---|
| 2233 | |
---|
| 2234 | case iss_t::XTN_DATA_BAD_VADDR: |
---|
[205] | 2235 | m_drsp.rdata = r_mmu_dbvar.read(); |
---|
| 2236 | m_drsp.valid = true; |
---|
[183] | 2237 | break; |
---|
| 2238 | |
---|
| 2239 | case iss_t::XTN_PTPR: |
---|
[205] | 2240 | m_drsp.rdata = r_mmu_ptpr.read(); |
---|
| 2241 | m_drsp.valid = true; |
---|
[183] | 2242 | break; |
---|
| 2243 | |
---|
| 2244 | case iss_t::XTN_TLB_MODE: |
---|
[205] | 2245 | m_drsp.rdata = r_mmu_mode.read(); |
---|
| 2246 | m_drsp.valid = true; |
---|
[183] | 2247 | break; |
---|
| 2248 | |
---|
| 2249 | case iss_t::XTN_MMU_PARAMS: |
---|
[205] | 2250 | m_drsp.rdata = r_mmu_params; |
---|
| 2251 | m_drsp.valid = true; |
---|
[183] | 2252 | break; |
---|
| 2253 | |
---|
| 2254 | case iss_t::XTN_MMU_RELEASE: |
---|
[205] | 2255 | m_drsp.rdata = r_mmu_release; |
---|
| 2256 | m_drsp.valid = true; |
---|
[183] | 2257 | break; |
---|
| 2258 | |
---|
| 2259 | case iss_t::XTN_MMU_WORD_LO: |
---|
[205] | 2260 | m_drsp.rdata = r_mmu_word_lo.read(); |
---|
| 2261 | m_drsp.valid = true; |
---|
[183] | 2262 | break; |
---|
| 2263 | |
---|
| 2264 | case iss_t::XTN_MMU_WORD_HI: |
---|
[205] | 2265 | m_drsp.rdata = r_mmu_word_hi.read(); |
---|
| 2266 | m_drsp.valid = true; |
---|
[183] | 2267 | break; |
---|
| 2268 | |
---|
| 2269 | default: |
---|
| 2270 | r_mmu_detr = MMU_READ_UNDEFINED_XTN; |
---|
[205] | 2271 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2272 | m_drsp.valid = true; |
---|
| 2273 | m_drsp.error = true; |
---|
[183] | 2274 | break; |
---|
| 2275 | } // end switch xtn_opcode |
---|
| 2276 | } // end else |
---|
[205] | 2277 | r_dcache_p0_valid = false; |
---|
[183] | 2278 | } // end if XTN_READ |
---|
| 2279 | |
---|
| 2280 | // Handling WRITE XTN requests from processor. |
---|
| 2281 | // They are not executed in this DCACHE_IDLE state, |
---|
| 2282 | // if they require access to the caches or the TLBs |
---|
| 2283 | // that are already accessed for speculative read. |
---|
| 2284 | // Caches can be invalidated or flushed in user mode, |
---|
| 2285 | // and the sync instruction can be executed in user mode |
---|
[205] | 2286 | else if (m_dreq.type == iss_t::XTN_WRITE) |
---|
[183] | 2287 | { |
---|
[205] | 2288 | int xtn_opcode = (int)m_dreq.addr/4; |
---|
[183] | 2289 | r_dcache_xtn_opcode = xtn_opcode; |
---|
| 2290 | |
---|
| 2291 | // checking processor mode: |
---|
[205] | 2292 | if ( (m_dreq.mode == iss_t::MODE_USER) && |
---|
[183] | 2293 | (xtn_opcode != iss_t:: XTN_SYNC) && |
---|
| 2294 | (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && |
---|
| 2295 | (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && |
---|
| 2296 | (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && |
---|
| 2297 | (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) ) |
---|
| 2298 | { |
---|
| 2299 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
[205] | 2300 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2301 | m_drsp.valid = true; |
---|
| 2302 | m_drsp.error = true; |
---|
[183] | 2303 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2304 | } |
---|
| 2305 | else |
---|
| 2306 | { |
---|
| 2307 | switch( xtn_opcode ) |
---|
| 2308 | { |
---|
| 2309 | case iss_t::XTN_PTPR: // itlb & dtlb must be flushed |
---|
[205] | 2310 | r_mmu_ptpr = m_dreq.wdata; |
---|
[183] | 2311 | r_dcache_xtn_req = true; |
---|
| 2312 | r_dcache_fsm = DCACHE_XTN_SWITCH; |
---|
| 2313 | break; |
---|
| 2314 | |
---|
| 2315 | case iss_t::XTN_TLB_MODE: // no cache or tlb access |
---|
[205] | 2316 | r_mmu_mode = m_dreq.wdata; |
---|
| 2317 | m_drsp.valid = true; |
---|
[183] | 2318 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2319 | break; |
---|
| 2320 | |
---|
| 2321 | case iss_t::XTN_DTLB_INVAL: // dtlb access |
---|
| 2322 | r_dcache_fsm = DCACHE_XTN_DT_INVAL; |
---|
| 2323 | break; |
---|
| 2324 | |
---|
| 2325 | case iss_t::XTN_ITLB_INVAL: // itlb access |
---|
| 2326 | r_dcache_xtn_req = true; |
---|
| 2327 | r_dcache_fsm = DCACHE_XTN_IT_INVAL; |
---|
| 2328 | break; |
---|
| 2329 | |
---|
| 2330 | case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access |
---|
| 2331 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; |
---|
| 2332 | break; |
---|
| 2333 | |
---|
| 2334 | case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access |
---|
| 2335 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
| 2336 | r_dcache_p0_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | |
---|
| 2337 | (paddr_t)r_mmu_word_lo.read(); |
---|
| 2338 | break; |
---|
| 2339 | |
---|
| 2340 | case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset |
---|
| 2341 | r_dcache_flush_count = 0; |
---|
| 2342 | r_dcache_fsm = DCACHE_XTN_DC_FLUSH; |
---|
| 2343 | break; |
---|
| 2344 | |
---|
| 2345 | case iss_t::XTN_ICACHE_INVAL: // icache and itlb access |
---|
| 2346 | r_dcache_xtn_req = true; |
---|
| 2347 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; |
---|
| 2348 | break; |
---|
| 2349 | |
---|
| 2350 | case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access |
---|
| 2351 | r_dcache_xtn_req = true; |
---|
| 2352 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; |
---|
| 2353 | break; |
---|
| 2354 | |
---|
| 2355 | case iss_t::XTN_ICACHE_FLUSH: // icache access |
---|
| 2356 | r_dcache_xtn_req = true; |
---|
| 2357 | r_dcache_fsm = DCACHE_XTN_IC_FLUSH; |
---|
| 2358 | break; |
---|
| 2359 | |
---|
| 2360 | case iss_t::XTN_SYNC: // wait until write buffer empty |
---|
| 2361 | r_dcache_fsm = DCACHE_XTN_SYNC; |
---|
| 2362 | break; |
---|
| 2363 | |
---|
| 2364 | case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access |
---|
[205] | 2365 | r_mmu_word_lo = m_dreq.wdata; |
---|
| 2366 | m_drsp.valid = true; |
---|
[183] | 2367 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2368 | break; |
---|
| 2369 | |
---|
| 2370 | case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access |
---|
[205] | 2371 | r_mmu_word_hi = m_dreq.wdata; |
---|
| 2372 | m_drsp.valid = true; |
---|
[183] | 2373 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2374 | break; |
---|
| 2375 | |
---|
| 2376 | case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action |
---|
| 2377 | case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action |
---|
[205] | 2378 | m_drsp.valid = true; |
---|
[183] | 2379 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2380 | break; |
---|
| 2381 | |
---|
| 2382 | default: |
---|
| 2383 | r_mmu_detr = MMU_WRITE_UNDEFINED_XTN; |
---|
[205] | 2384 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2385 | m_drsp.valid = true; |
---|
| 2386 | m_drsp.error = true; |
---|
[183] | 2387 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2388 | break; |
---|
| 2389 | } // end switch xtn_opcode |
---|
| 2390 | } // end else |
---|
[205] | 2391 | r_dcache_p0_valid = false; |
---|
[183] | 2392 | } // end if XTN_WRITE |
---|
| 2393 | |
---|
[205] | 2394 | // Handling read/write/ll/sc processor requests. |
---|
[183] | 2395 | // The dtlb and dcache can be activated or not. |
---|
| 2396 | // We compute the physical address, the cacheability, and check processor request. |
---|
| 2397 | // - If DTLB not activated : cacheability is defined by the segment table, |
---|
| 2398 | // the physical address is equal to the virtual address (identity mapping) |
---|
| 2399 | // - If DTLB activated : cacheability is defined by the C bit in the PTE, |
---|
| 2400 | // the physical address is obtained from the TLB, and the U & W bits |
---|
| 2401 | // of the PTE are checked. |
---|
| 2402 | // The processor request is decoded only if the TLB is not activated or if |
---|
| 2403 | // the virtual address hits in tLB and access rights are OK. |
---|
| 2404 | // We call the TLB_MISS sub-fsm in case of dtlb miss. |
---|
| 2405 | else |
---|
| 2406 | { |
---|
| 2407 | bool valid_req = false; |
---|
| 2408 | bool cacheable = false; |
---|
| 2409 | paddr_t paddr = 0; |
---|
| 2410 | |
---|
| 2411 | if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated |
---|
| 2412 | { |
---|
| 2413 | valid_req = true; |
---|
| 2414 | |
---|
| 2415 | // cacheability |
---|
| 2416 | if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; |
---|
[205] | 2417 | else cacheable = m_cacheability_table[m_dreq.addr]; |
---|
[183] | 2418 | |
---|
| 2419 | // physical address |
---|
[205] | 2420 | paddr = (paddr_t)m_dreq.addr; |
---|
[183] | 2421 | } |
---|
| 2422 | else // dtlb activated |
---|
| 2423 | { |
---|
| 2424 | if ( tlb_hit ) // tlb hit |
---|
| 2425 | { |
---|
| 2426 | // cacheability |
---|
| 2427 | if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; |
---|
| 2428 | else cacheable = tlb_flags.c; |
---|
| 2429 | |
---|
| 2430 | // access rights checking |
---|
[205] | 2431 | if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) |
---|
[183] | 2432 | { |
---|
[205] | 2433 | if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) ) |
---|
[183] | 2434 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
| 2435 | else |
---|
| 2436 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
| 2437 | |
---|
[205] | 2438 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2439 | m_drsp.valid = true; |
---|
| 2440 | m_drsp.error = true; |
---|
| 2441 | m_drsp.rdata = 0; |
---|
[206] | 2442 | #if DEBUG_DCACHE |
---|
| 2443 | if ( m_debug_dcache_fsm ) |
---|
| 2444 | { |
---|
| 2445 | std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl; |
---|
| 2446 | } |
---|
| 2447 | #endif |
---|
[183] | 2448 | } |
---|
| 2449 | else if ( not tlb_flags.w and |
---|
[205] | 2450 | ((m_dreq.type == iss_t::DATA_WRITE) or |
---|
| 2451 | (m_dreq.type == iss_t::DATA_SC)) ) |
---|
[183] | 2452 | { |
---|
| 2453 | r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; |
---|
[205] | 2454 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2455 | m_drsp.valid = true; |
---|
| 2456 | m_drsp.error = true; |
---|
| 2457 | m_drsp.rdata = 0; |
---|
[206] | 2458 | #if DEBUG_DCACHE |
---|
| 2459 | if ( m_debug_dcache_fsm ) |
---|
| 2460 | { |
---|
| 2461 | std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl; |
---|
| 2462 | } |
---|
| 2463 | #endif |
---|
[183] | 2464 | } |
---|
| 2465 | else |
---|
| 2466 | { |
---|
| 2467 | valid_req = true; |
---|
| 2468 | } |
---|
| 2469 | |
---|
| 2470 | // physical address |
---|
[206] | 2471 | paddr = tlb_paddr; |
---|
[183] | 2472 | } |
---|
| 2473 | else // tlb miss |
---|
| 2474 | { |
---|
[205] | 2475 | r_dcache_tlb_vaddr = m_dreq.addr; |
---|
[183] | 2476 | r_dcache_tlb_ins = false; |
---|
| 2477 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
| 2478 | } |
---|
| 2479 | } // end DTLB activated |
---|
| 2480 | |
---|
[205] | 2481 | if ( valid_req ) // processor request is valid after TLB check |
---|
[183] | 2482 | { |
---|
| 2483 | // physical address and cacheability registration |
---|
| 2484 | r_dcache_p0_paddr = paddr; |
---|
| 2485 | r_dcache_p0_cacheable = cacheable; |
---|
| 2486 | |
---|
| 2487 | // READ or LL request |
---|
| 2488 | // The read requests are taken only if the write pipe-line is empty. |
---|
| 2489 | // If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle. |
---|
| 2490 | // If speculative access is KO we just pay one extra cycle. |
---|
| 2491 | // If dcache miss, we go to DCACHE_MISS_VICTIM state. |
---|
| 2492 | // If uncacheable, we go to DCACHE_UNC_WAIT state. |
---|
[205] | 2493 | if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL)) |
---|
| 2494 | and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() ) |
---|
[183] | 2495 | { |
---|
| 2496 | if ( cacheable ) // cacheable read |
---|
| 2497 | { |
---|
| 2498 | // if the speculative access is illegal, we pay an extra cycle |
---|
| 2499 | if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) |
---|
| 2500 | != (paddr & ~PAGE_K_MASK)) |
---|
| 2501 | { |
---|
| 2502 | #ifdef INSTRUMENTATION |
---|
| 2503 | m_cpt_dcache_spec_miss++; |
---|
| 2504 | #endif |
---|
| 2505 | } |
---|
| 2506 | // if cache miss, try to get the missing line |
---|
| 2507 | else if ( not cache_hit ) |
---|
| 2508 | { |
---|
| 2509 | #ifdef INSTRUMENTATION |
---|
| 2510 | m_cpt_dcache_miss++; |
---|
| 2511 | #endif |
---|
| 2512 | // blocked in IDLE state if previous cleanup not completed |
---|
| 2513 | if ( not r_dcache_cleanup_req.read() ) |
---|
| 2514 | { |
---|
[198] | 2515 | r_dcache_vci_paddr = paddr; |
---|
| 2516 | r_dcache_vci_miss_req = true; |
---|
| 2517 | r_dcache_miss_type = PROC_MISS; |
---|
| 2518 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
[183] | 2519 | } |
---|
| 2520 | } |
---|
| 2521 | // if cache hit return the data |
---|
| 2522 | else |
---|
| 2523 | { |
---|
| 2524 | #ifdef INSTRUMENTATION |
---|
| 2525 | m_cpt_data_read++; |
---|
| 2526 | #endif |
---|
[205] | 2527 | m_drsp.valid = true; |
---|
| 2528 | m_drsp.rdata = cache_rdata; |
---|
[206] | 2529 | #if DEBUG_DCACHE |
---|
| 2530 | if ( m_debug_dcache_fsm ) |
---|
| 2531 | { |
---|
| 2532 | std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl; |
---|
| 2533 | } |
---|
| 2534 | #endif |
---|
[183] | 2535 | } |
---|
| 2536 | } |
---|
| 2537 | else // uncacheable read |
---|
| 2538 | { |
---|
| 2539 | r_dcache_vci_paddr = paddr; |
---|
[205] | 2540 | r_dcache_vci_unc_be = m_dreq.be; |
---|
[183] | 2541 | r_dcache_vci_unc_req = true; |
---|
| 2542 | r_dcache_fsm = DCACHE_UNC_WAIT; |
---|
| 2543 | } |
---|
| 2544 | |
---|
| 2545 | // makes reservation in case of LL |
---|
[205] | 2546 | if ( m_dreq.type == iss_t::DATA_LL ) |
---|
[183] | 2547 | { |
---|
| 2548 | r_dcache_ll_valid = true; |
---|
| 2549 | r_dcache_ll_data = cache_rdata; |
---|
[205] | 2550 | r_dcache_ll_vaddr = m_dreq.addr; |
---|
[183] | 2551 | } |
---|
[205] | 2552 | r_dcache_p0_valid = false; |
---|
[183] | 2553 | } // end READ or LL |
---|
| 2554 | |
---|
| 2555 | // WRITE request: |
---|
[206] | 2556 | // If the TLB is activated and the PTE Dirty bit is not set, we stall |
---|
| 2557 | // the processor and set the Dirty bit before handling the write request. |
---|
| 2558 | // If we don't need to set the Dirty bit, we can acknowledge |
---|
| 2559 | // the processor request, as the write arguments (including the |
---|
| 2560 | // physical address) are registered in r_dcache_p0 registers: |
---|
| 2561 | // We simply activate the P1 pipeline stage. |
---|
[205] | 2562 | else if ( m_dreq.type == iss_t::DATA_WRITE ) |
---|
[183] | 2563 | { |
---|
[206] | 2564 | if ( (r_mmu_mode.read() & DATA_TLB_MASK ) |
---|
| 2565 | and not tlb_flags.d ) // Dirty bit must be set |
---|
| 2566 | { |
---|
| 2567 | // The PTE physical address is obtained from the nline value (dtlb), |
---|
| 2568 | // and the word index (proper bits of the virtual address) |
---|
| 2569 | if ( tlb_flags.b ) // PTE1 |
---|
| 2570 | { |
---|
| 2571 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2572 | (paddr_t)((m_dreq.addr>>19) & 0x3c); |
---|
| 2573 | } |
---|
| 2574 | else // PTE2 |
---|
| 2575 | { |
---|
| 2576 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2577 | (paddr_t)((m_dreq.addr>>9) & 0x38); |
---|
| 2578 | } |
---|
| 2579 | r_dcache_fsm = DCACHE_DIRTY_GET_PTE; |
---|
| 2580 | r_dcache_p0_valid = false; |
---|
| 2581 | } |
---|
| 2582 | else // Write request accepted |
---|
| 2583 | { |
---|
[183] | 2584 | #ifdef INSTRUMENTATION |
---|
| 2585 | m_cpt_data_write++; |
---|
| 2586 | #endif |
---|
[206] | 2587 | m_drsp.valid = true; |
---|
| 2588 | m_drsp.rdata = 0; |
---|
| 2589 | r_dcache_p0_valid = true; |
---|
| 2590 | } |
---|
[183] | 2591 | } // end WRITE |
---|
| 2592 | |
---|
| 2593 | // SC request: |
---|
[205] | 2594 | // The SC requests are taken only if the write pipe-line is empty. |
---|
[206] | 2595 | // - if there is no valid registered LL, we just return rdata = 1 |
---|
| 2596 | // (atomic access failed) and the SC transaction is completed. |
---|
[183] | 2597 | // - if a valid LL reservation (with the same address) is registered, |
---|
[206] | 2598 | // we test if a DIRTY bit update is required. |
---|
| 2599 | // If the TLB is activated and the PTE Dirty bit is not set, we stall |
---|
| 2600 | // the processor and set the Dirty bit before handling the write request. |
---|
| 2601 | // If we don't need to set the Dirty bit, we request a SC transaction |
---|
| 2602 | // to CMD FSM and go to DCACHE_SC_WAIT state, that will return |
---|
| 2603 | // the response to the processor. |
---|
| 2604 | // We don't check a possible write hit in dcache, as the cache update |
---|
| 2605 | // is done by the coherence transaction induced by the SC... |
---|
[205] | 2606 | else if ( ( m_dreq.type == iss_t::DATA_SC ) |
---|
| 2607 | and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() ) |
---|
[183] | 2608 | { |
---|
[206] | 2609 | if ( (r_dcache_ll_vaddr.read() != m_dreq.addr) |
---|
| 2610 | or not r_dcache_ll_valid.read() ) // no valid registered LL |
---|
| 2611 | { |
---|
[183] | 2612 | #ifdef INSTRUMENTATION |
---|
| 2613 | m_cpt_data_sc++; |
---|
| 2614 | #endif |
---|
[205] | 2615 | m_drsp.valid = true; |
---|
| 2616 | m_drsp.rdata = 1; |
---|
| 2617 | r_dcache_ll_valid = false; |
---|
[183] | 2618 | } |
---|
[206] | 2619 | else // valid registered LL |
---|
| 2620 | { |
---|
| 2621 | if ( (r_mmu_mode.read() & DATA_TLB_MASK ) |
---|
| 2622 | and not tlb_flags.d ) // Dirty bit must be set |
---|
| 2623 | { |
---|
| 2624 | // The PTE physical address is obtained from the nline value (dtlb), |
---|
| 2625 | // and the word index (proper bits of the virtual address) |
---|
| 2626 | if ( tlb_flags.b ) // PTE1 |
---|
| 2627 | { |
---|
| 2628 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2629 | (paddr_t)((m_dreq.addr>>19) & 0x3c); |
---|
| 2630 | } |
---|
| 2631 | else // PTE2 |
---|
| 2632 | { |
---|
| 2633 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2634 | (paddr_t)((m_dreq.addr>>9) & 0x38); |
---|
| 2635 | } |
---|
| 2636 | r_dcache_fsm = DCACHE_DIRTY_GET_PTE; |
---|
| 2637 | } |
---|
| 2638 | else // SC request accepted |
---|
| 2639 | { |
---|
| 2640 | #ifdef INSTRUMENTATION |
---|
| 2641 | m_cpt_data_sc++; |
---|
| 2642 | #endif |
---|
| 2643 | |
---|
| 2644 | r_dcache_vci_paddr = paddr; |
---|
| 2645 | r_dcache_vci_sc_req = true; |
---|
| 2646 | r_dcache_vci_sc_old = r_dcache_ll_data.read(); |
---|
| 2647 | r_dcache_vci_sc_new = m_dreq.wdata; |
---|
| 2648 | r_dcache_ll_valid = false; |
---|
| 2649 | r_dcache_fsm = DCACHE_SC_WAIT; |
---|
| 2650 | } |
---|
| 2651 | } |
---|
[205] | 2652 | r_dcache_p0_valid = false; |
---|
[183] | 2653 | } // end SC |
---|
[205] | 2654 | else |
---|
| 2655 | { |
---|
| 2656 | r_dcache_p0_valid = false; |
---|
| 2657 | } |
---|
[183] | 2658 | } // end valid_req |
---|
[205] | 2659 | else |
---|
| 2660 | { |
---|
| 2661 | r_dcache_p0_valid = false; |
---|
| 2662 | } |
---|
| 2663 | } // end if read/write/ll/sc request |
---|
| 2664 | } // end dreq.valid |
---|
| 2665 | else |
---|
| 2666 | { |
---|
| 2667 | r_dcache_p0_valid = false; |
---|
[183] | 2668 | } // end P0 pipe stage |
---|
| 2669 | break; |
---|
| 2670 | } |
---|
| 2671 | ///////////////////// |
---|
[204] | 2672 | case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss. |
---|
[205] | 2673 | // Input arguments are: |
---|
| 2674 | // - r_dcache_tlb_vaddr |
---|
| 2675 | // - r_dcache_tlb_ins (true when itlb miss) |
---|
| 2676 | // The sub-fsm access the dcache to find the missing TLB entry, |
---|
| 2677 | // and activates the cache miss procedure in case of miss. |
---|
| 2678 | // It bypass the first level page table access if possible. |
---|
| 2679 | // It uses atomic access to update the R/L access bits |
---|
| 2680 | // in the page table if required. |
---|
| 2681 | // It directly updates the itlb or dtlb, and writes into the |
---|
| 2682 | // r_mmu_ins_* or r_mmu_data* error reporting registers. |
---|
[183] | 2683 | { |
---|
| 2684 | uint32_t ptba = 0; |
---|
| 2685 | bool bypass; |
---|
[205] | 2686 | paddr_t pte_paddr; |
---|
[183] | 2687 | |
---|
| 2688 | // evaluate bypass in order to skip first level page table access |
---|
| 2689 | if ( r_dcache_tlb_ins.read() ) // itlb miss |
---|
| 2690 | { |
---|
| 2691 | bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
| 2692 | } |
---|
| 2693 | else // dtlb miss |
---|
| 2694 | { |
---|
| 2695 | bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
| 2696 | } |
---|
| 2697 | |
---|
[205] | 2698 | if ( not bypass ) // Try to read PTE1/PTD1 in dcache |
---|
[183] | 2699 | { |
---|
[205] | 2700 | pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) | |
---|
| 2701 | (paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); |
---|
| 2702 | r_dcache_tlb_paddr = pte_paddr; |
---|
[183] | 2703 | r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
| 2704 | } |
---|
[205] | 2705 | else // Try to read PTE2 in dcache |
---|
[183] | 2706 | { |
---|
[205] | 2707 | pte_paddr = (paddr_t)ptba << PAGE_K_NBITS | |
---|
| 2708 | (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); |
---|
| 2709 | r_dcache_tlb_paddr = pte_paddr; |
---|
[183] | 2710 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
| 2711 | } |
---|
| 2712 | |
---|
| 2713 | #if DEBUG_DCACHE |
---|
| 2714 | if ( m_debug_dcache_fsm ) |
---|
| 2715 | { |
---|
| 2716 | if ( r_dcache_tlb_ins.read() ) |
---|
[205] | 2717 | { |
---|
| 2718 | std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss"; |
---|
| 2719 | } |
---|
| 2720 | else |
---|
| 2721 | { |
---|
| 2722 | std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss"; |
---|
| 2723 | } |
---|
| 2724 | std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() |
---|
| 2725 | << " / BYPASS = " << bypass |
---|
| 2726 | << " / PTE_ADR = " << pte_paddr << std::endl; |
---|
[183] | 2727 | } |
---|
| 2728 | #endif |
---|
| 2729 | |
---|
| 2730 | break; |
---|
| 2731 | } |
---|
| 2732 | ///////////////////////// |
---|
| 2733 | case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache |
---|
| 2734 | { |
---|
| 2735 | uint32_t entry; |
---|
| 2736 | size_t way; |
---|
| 2737 | size_t set; |
---|
| 2738 | size_t word; |
---|
| 2739 | |
---|
| 2740 | bool hit = r_dcache.read( r_dcache_tlb_paddr.read(), |
---|
| 2741 | &entry, |
---|
| 2742 | &way, |
---|
| 2743 | &set, |
---|
| 2744 | &word ); |
---|
| 2745 | #ifdef INSTRUMENTATION |
---|
| 2746 | m_cpt_dcache_data_read++; |
---|
| 2747 | m_cpt_dcache_dir_read++; |
---|
| 2748 | #endif |
---|
[204] | 2749 | if ( hit ) // hit in dcache |
---|
[183] | 2750 | { |
---|
| 2751 | if ( not (entry & PTE_V_MASK) ) // unmapped |
---|
| 2752 | { |
---|
| 2753 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2754 | { |
---|
| 2755 | r_mmu_ietr = MMU_READ_PT1_UNMAPPED; |
---|
| 2756 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 2757 | r_icache_tlb_miss_req = false; |
---|
| 2758 | r_icache_tlb_rsp_error = true; |
---|
| 2759 | } |
---|
| 2760 | else |
---|
| 2761 | { |
---|
| 2762 | r_mmu_detr = MMU_READ_PT1_UNMAPPED; |
---|
| 2763 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 2764 | m_drsp.valid = true; |
---|
| 2765 | m_drsp.error = true; |
---|
[183] | 2766 | } |
---|
| 2767 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2768 | |
---|
| 2769 | #if DEBUG_DCACHE |
---|
| 2770 | if ( m_debug_dcache_fsm ) |
---|
| 2771 | { |
---|
[204] | 2772 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped" |
---|
| 2773 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
| 2774 | << std::dec << " / way = " << way |
---|
[183] | 2775 | << std::dec << " / set = " << set |
---|
| 2776 | << std::dec << " / word = " << word |
---|
| 2777 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
| 2778 | } |
---|
| 2779 | #endif |
---|
| 2780 | |
---|
| 2781 | } |
---|
[206] | 2782 | else if( entry & PTE_T_MASK ) // PTD : me must access PT2 |
---|
[183] | 2783 | { |
---|
[206] | 2784 | // mark the cache line ac containing a PTD |
---|
| 2785 | r_dcache_contains_ptd[m_dcache_sets*way+set] = true; |
---|
| 2786 | |
---|
[183] | 2787 | // register bypass |
---|
| 2788 | if ( r_dcache_tlb_ins.read() ) // itlb |
---|
| 2789 | { |
---|
| 2790 | r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
| 2791 | entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), |
---|
| 2792 | r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2))); |
---|
| 2793 | } |
---|
| 2794 | else // dtlb |
---|
| 2795 | { |
---|
| 2796 | r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
| 2797 | entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), |
---|
| 2798 | r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)); |
---|
| 2799 | } |
---|
| 2800 | r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | |
---|
| 2801 | (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); |
---|
| 2802 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
| 2803 | |
---|
| 2804 | #if DEBUG_DCACHE |
---|
| 2805 | if ( m_debug_dcache_fsm ) |
---|
| 2806 | { |
---|
[204] | 2807 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache" |
---|
| 2808 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
| 2809 | << std::dec << " / way = " << way |
---|
[183] | 2810 | << std::dec << " / set = " << set |
---|
| 2811 | << std::dec << " / word = " << word |
---|
| 2812 | << std::hex << " / PTD = " << entry << std::endl; |
---|
| 2813 | } |
---|
| 2814 | #endif |
---|
| 2815 | } |
---|
[206] | 2816 | else // PTE1 : we must update the TLB |
---|
[183] | 2817 | { |
---|
[206] | 2818 | r_dcache_in_tlb[m_icache_sets*way+set] = true; |
---|
[183] | 2819 | r_dcache_tlb_pte_flags = entry; |
---|
| 2820 | r_dcache_tlb_cache_way = way; |
---|
| 2821 | r_dcache_tlb_cache_set = set; |
---|
| 2822 | r_dcache_tlb_cache_word = word; |
---|
| 2823 | r_dcache_fsm = DCACHE_TLB_PTE1_SELECT; |
---|
| 2824 | |
---|
| 2825 | #if DEBUG_DCACHE |
---|
| 2826 | if ( m_debug_dcache_fsm ) |
---|
| 2827 | { |
---|
[204] | 2828 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache" |
---|
| 2829 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
| 2830 | << std::dec << " / way = " << way |
---|
[183] | 2831 | << std::dec << " / set = " << set |
---|
| 2832 | << std::dec << " / word = " << word |
---|
| 2833 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
| 2834 | } |
---|
| 2835 | #endif |
---|
| 2836 | } |
---|
| 2837 | } |
---|
| 2838 | else // we must load the missing cache line in dcache |
---|
| 2839 | { |
---|
[205] | 2840 | r_dcache_vci_miss_req = true; |
---|
[183] | 2841 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
| 2842 | r_dcache_miss_type = PTE1_MISS; |
---|
| 2843 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
| 2844 | |
---|
| 2845 | #if DEBUG_DCACHE |
---|
| 2846 | if ( m_debug_dcache_fsm ) |
---|
| 2847 | { |
---|
| 2848 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:" |
---|
| 2849 | << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
| 2850 | } |
---|
| 2851 | #endif |
---|
| 2852 | } |
---|
| 2853 | break; |
---|
| 2854 | } |
---|
| 2855 | //////////////////////////// |
---|
| 2856 | case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 |
---|
| 2857 | { |
---|
| 2858 | size_t way; |
---|
| 2859 | size_t set; |
---|
| 2860 | |
---|
| 2861 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2862 | { |
---|
| 2863 | r_itlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 2864 | true, // PTE1 |
---|
| 2865 | &way, |
---|
| 2866 | &set ); |
---|
| 2867 | #ifdef INSTRUMENTATION |
---|
| 2868 | m_cpt_itlb_read++; |
---|
| 2869 | #endif |
---|
| 2870 | } |
---|
| 2871 | else |
---|
| 2872 | { |
---|
| 2873 | r_dtlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 2874 | true, // PTE1 |
---|
| 2875 | &way, |
---|
| 2876 | &set ); |
---|
| 2877 | #ifdef INSTRUMENTATION |
---|
| 2878 | m_cpt_dtlb_read++; |
---|
| 2879 | #endif |
---|
| 2880 | } |
---|
| 2881 | r_dcache_tlb_way = way; |
---|
| 2882 | r_dcache_tlb_set = set; |
---|
| 2883 | r_dcache_fsm = DCACHE_TLB_PTE1_UPDT; |
---|
| 2884 | |
---|
| 2885 | #if DEBUG_DCACHE |
---|
| 2886 | if ( m_debug_dcache_fsm ) |
---|
| 2887 | { |
---|
| 2888 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2889 | std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:"; |
---|
| 2890 | else |
---|
| 2891 | std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:"; |
---|
| 2892 | std::cout << " way = " << std::dec << way |
---|
| 2893 | << " / set = " << set << std::endl; |
---|
| 2894 | } |
---|
| 2895 | #endif |
---|
| 2896 | break; |
---|
| 2897 | } |
---|
| 2898 | ////////////////////////// |
---|
| 2899 | case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit |
---|
| 2900 | // if L/R bit already set, exit the sub-fsm |
---|
| 2901 | // if not, the page table must be updated |
---|
| 2902 | { |
---|
| 2903 | paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
| 2904 | uint32_t pte = r_dcache_tlb_pte_flags.read(); |
---|
| 2905 | bool updt = false; |
---|
[205] | 2906 | bool local = true; |
---|
[183] | 2907 | |
---|
[205] | 2908 | // We should compute the access locality: |
---|
| 2909 | // The PPN MSB bits define the destination cluster index. |
---|
| 2910 | // The m_srcid_d MSB bits define the source cluster index. |
---|
| 2911 | // The number of bits to compare depends on the number of clusters, |
---|
| 2912 | // and can be obtained in the mapping table. |
---|
| 2913 | // As long as this computation is not done, all access are local. |
---|
[183] | 2914 | |
---|
[205] | 2915 | if ( local ) // local access |
---|
[183] | 2916 | { |
---|
| 2917 | if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit |
---|
| 2918 | { |
---|
[205] | 2919 | updt = true; |
---|
| 2920 | r_dcache_vci_sc_old = pte; |
---|
| 2921 | r_dcache_vci_sc_new = pte | PTE_L_MASK; |
---|
| 2922 | pte = pte | PTE_L_MASK; |
---|
[183] | 2923 | } |
---|
| 2924 | } |
---|
[205] | 2925 | else // remote access |
---|
[183] | 2926 | { |
---|
| 2927 | if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit |
---|
| 2928 | { |
---|
| 2929 | updt = true; |
---|
[205] | 2930 | r_dcache_vci_sc_old = pte; |
---|
| 2931 | r_dcache_vci_sc_new = pte | PTE_R_MASK; |
---|
| 2932 | pte = pte | PTE_R_MASK; |
---|
[183] | 2933 | } |
---|
| 2934 | } |
---|
| 2935 | |
---|
| 2936 | // update TLB |
---|
| 2937 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2938 | { |
---|
[202] | 2939 | r_itlb.write( true, // 2M page |
---|
| 2940 | pte, |
---|
| 2941 | 0, // argument unused for a PTE1 |
---|
[183] | 2942 | r_dcache_tlb_vaddr.read(), |
---|
| 2943 | r_dcache_tlb_way.read(), |
---|
| 2944 | r_dcache_tlb_set.read(), |
---|
| 2945 | nline ); |
---|
| 2946 | #ifdef INSTRUMENTATION |
---|
| 2947 | m_cpt_itlb_write++; |
---|
| 2948 | #endif |
---|
| 2949 | } |
---|
| 2950 | else |
---|
| 2951 | { |
---|
[202] | 2952 | r_dtlb.write( true, // 2M page |
---|
| 2953 | pte, |
---|
| 2954 | 0, // argument unused for a PTE1 |
---|
[183] | 2955 | r_dcache_tlb_vaddr.read(), |
---|
| 2956 | r_dcache_tlb_way.read(), |
---|
| 2957 | r_dcache_tlb_set.read(), |
---|
| 2958 | nline ); |
---|
| 2959 | #ifdef INSTRUMENTATION |
---|
| 2960 | m_cpt_dtlb_write++; |
---|
| 2961 | #endif |
---|
| 2962 | } |
---|
| 2963 | // next state |
---|
[205] | 2964 | if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update |
---|
[183] | 2965 | else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm |
---|
| 2966 | |
---|
| 2967 | #if DEBUG_DCACHE |
---|
| 2968 | if ( m_debug_dcache_fsm ) |
---|
| 2969 | { |
---|
| 2970 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2971 | { |
---|
[205] | 2972 | std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"; |
---|
| 2973 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 2974 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 2975 | r_itlb.printTrace(); |
---|
[183] | 2976 | } |
---|
| 2977 | else |
---|
| 2978 | { |
---|
[205] | 2979 | std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"; |
---|
| 2980 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 2981 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 2982 | r_dtlb.printTrace(); |
---|
[183] | 2983 | } |
---|
| 2984 | |
---|
| 2985 | } |
---|
| 2986 | #endif |
---|
| 2987 | break; |
---|
| 2988 | } |
---|
| 2989 | ///////////////////////// |
---|
| 2990 | case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache |
---|
| 2991 | { |
---|
| 2992 | uint32_t pte_flags; |
---|
| 2993 | uint32_t pte_ppn; |
---|
| 2994 | size_t way; |
---|
| 2995 | size_t set; |
---|
| 2996 | size_t word; |
---|
| 2997 | |
---|
| 2998 | bool hit = r_dcache.read( r_dcache_tlb_paddr.read(), |
---|
| 2999 | &pte_flags, |
---|
| 3000 | &pte_ppn, |
---|
| 3001 | &way, |
---|
| 3002 | &set, |
---|
| 3003 | &word ); |
---|
| 3004 | #ifdef INSTRUMENTATION |
---|
| 3005 | m_cpt_dcache_data_read++; |
---|
| 3006 | m_cpt_dcache_dir_read++; |
---|
| 3007 | #endif |
---|
| 3008 | if ( hit ) // request hits in dcache |
---|
| 3009 | { |
---|
| 3010 | if ( not (pte_flags & PTE_V_MASK) ) // unmapped |
---|
| 3011 | { |
---|
| 3012 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3013 | { |
---|
| 3014 | r_mmu_ietr = MMU_READ_PT2_UNMAPPED; |
---|
| 3015 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 3016 | r_icache_tlb_miss_req = false; |
---|
| 3017 | r_icache_tlb_rsp_error = true; |
---|
| 3018 | } |
---|
| 3019 | else |
---|
| 3020 | { |
---|
| 3021 | r_mmu_detr = MMU_READ_PT2_UNMAPPED; |
---|
| 3022 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 3023 | m_drsp.valid = true; |
---|
| 3024 | m_drsp.error = true; |
---|
[183] | 3025 | } |
---|
| 3026 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3027 | |
---|
| 3028 | #if DEBUG_DCACHE |
---|
| 3029 | if ( m_debug_dcache_fsm ) |
---|
| 3030 | { |
---|
| 3031 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped" |
---|
| 3032 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
| 3033 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
| 3034 | } |
---|
| 3035 | #endif |
---|
| 3036 | } |
---|
[206] | 3037 | else // mapped : we must update the TLB |
---|
[183] | 3038 | { |
---|
[206] | 3039 | r_dcache_in_tlb[m_dcache_sets*way+set] = true; |
---|
[183] | 3040 | r_dcache_tlb_pte_flags = pte_flags; |
---|
| 3041 | r_dcache_tlb_pte_ppn = pte_ppn; |
---|
| 3042 | r_dcache_tlb_cache_way = way; |
---|
| 3043 | r_dcache_tlb_cache_set = set; |
---|
| 3044 | r_dcache_tlb_cache_word = word; |
---|
| 3045 | r_dcache_fsm = DCACHE_TLB_PTE2_SELECT; |
---|
| 3046 | |
---|
| 3047 | #if DEBUG_DCACHE |
---|
| 3048 | if ( m_debug_dcache_fsm ) |
---|
| 3049 | { |
---|
| 3050 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:" |
---|
| 3051 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
| 3052 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
| 3053 | } |
---|
| 3054 | #endif |
---|
| 3055 | } |
---|
| 3056 | } |
---|
| 3057 | else // we must load the missing cache line in dcache |
---|
| 3058 | { |
---|
[205] | 3059 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
| 3060 | r_dcache_vci_miss_req = true; |
---|
[183] | 3061 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
| 3062 | r_dcache_miss_type = PTE2_MISS; |
---|
| 3063 | |
---|
| 3064 | #if DEBUG_DCACHE |
---|
| 3065 | if ( m_debug_dcache_fsm ) |
---|
| 3066 | { |
---|
| 3067 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:" |
---|
| 3068 | << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
| 3069 | } |
---|
| 3070 | #endif |
---|
| 3071 | } |
---|
| 3072 | break; |
---|
| 3073 | } |
---|
| 3074 | //////////////////////////// |
---|
| 3075 | case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2 |
---|
| 3076 | { |
---|
| 3077 | size_t way; |
---|
| 3078 | size_t set; |
---|
| 3079 | |
---|
| 3080 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3081 | { |
---|
| 3082 | r_itlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 3083 | false, // PTE2 |
---|
| 3084 | &way, |
---|
| 3085 | &set ); |
---|
| 3086 | #ifdef INSTRUMENTATION |
---|
| 3087 | m_cpt_itlb_read++; |
---|
| 3088 | #endif |
---|
| 3089 | } |
---|
| 3090 | else |
---|
| 3091 | { |
---|
| 3092 | r_dtlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 3093 | false, // PTE2 |
---|
| 3094 | &way, |
---|
| 3095 | &set ); |
---|
| 3096 | #ifdef INSTRUMENTATION |
---|
| 3097 | m_cpt_dtlb_read++; |
---|
| 3098 | #endif |
---|
| 3099 | } |
---|
[205] | 3100 | |
---|
| 3101 | #if DEBUG_DCACHE |
---|
| 3102 | if ( m_debug_dcache_fsm ) |
---|
| 3103 | { |
---|
| 3104 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3105 | std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:"; |
---|
| 3106 | else |
---|
| 3107 | std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:"; |
---|
| 3108 | std::cout << " way = " << std::dec << way |
---|
| 3109 | << " / set = " << set << std::endl; |
---|
| 3110 | } |
---|
| 3111 | #endif |
---|
[183] | 3112 | r_dcache_tlb_way = way; |
---|
| 3113 | r_dcache_tlb_set = set; |
---|
| 3114 | r_dcache_fsm = DCACHE_TLB_PTE2_UPDT; |
---|
| 3115 | break; |
---|
| 3116 | } |
---|
| 3117 | ////////////////////////// |
---|
| 3118 | case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit |
---|
[205] | 3119 | // if L/R bit already set, exit the sub-fsm |
---|
[183] | 3120 | // if not, the page table must be updated by an atomic access |
---|
| 3121 | { |
---|
[205] | 3122 | paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
[183] | 3123 | uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); |
---|
| 3124 | uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); |
---|
[205] | 3125 | bool updt = false; |
---|
| 3126 | bool local = true; |
---|
[183] | 3127 | |
---|
[205] | 3128 | // We should compute the access locality: |
---|
| 3129 | // The PPN MSB bits define the destination cluster index. |
---|
| 3130 | // The m_srcid_d MSB bits define the source cluster index. |
---|
| 3131 | // The number of bits to compare depends on the number of clusters, |
---|
| 3132 | // and can be obtained in the mapping table. |
---|
| 3133 | // As long as this computation is not done, all access are local. |
---|
[183] | 3134 | |
---|
[205] | 3135 | if ( local ) // local access |
---|
[183] | 3136 | { |
---|
| 3137 | if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit |
---|
| 3138 | { |
---|
[205] | 3139 | updt = true; |
---|
| 3140 | r_dcache_vci_sc_old = pte_flags; |
---|
| 3141 | r_dcache_vci_sc_new = pte_flags | PTE_L_MASK; |
---|
| 3142 | pte_flags = pte_flags | PTE_L_MASK; |
---|
[183] | 3143 | } |
---|
| 3144 | } |
---|
[205] | 3145 | else // remote access |
---|
[183] | 3146 | { |
---|
| 3147 | if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit |
---|
| 3148 | { |
---|
| 3149 | updt = true; |
---|
[205] | 3150 | r_dcache_vci_sc_old = pte_flags; |
---|
| 3151 | r_dcache_vci_sc_new = pte_flags | PTE_R_MASK; |
---|
| 3152 | pte_flags = pte_flags | PTE_R_MASK; |
---|
[183] | 3153 | } |
---|
| 3154 | } |
---|
| 3155 | |
---|
| 3156 | // update TLB for a PTE2 |
---|
| 3157 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3158 | { |
---|
[205] | 3159 | r_itlb.write( false, // 4K page |
---|
[202] | 3160 | pte_flags, |
---|
[183] | 3161 | pte_ppn, |
---|
| 3162 | r_dcache_tlb_vaddr.read(), |
---|
| 3163 | r_dcache_tlb_way.read(), |
---|
| 3164 | r_dcache_tlb_set.read(), |
---|
| 3165 | nline ); |
---|
| 3166 | #ifdef INSTRUMENTATION |
---|
| 3167 | m_cpt_itlb_write++; |
---|
| 3168 | #endif |
---|
| 3169 | } |
---|
| 3170 | else |
---|
| 3171 | { |
---|
[205] | 3172 | r_dtlb.write( false, // 4K page |
---|
[202] | 3173 | pte_flags, |
---|
[183] | 3174 | pte_ppn, |
---|
| 3175 | r_dcache_tlb_vaddr.read(), |
---|
| 3176 | r_dcache_tlb_way.read(), |
---|
| 3177 | r_dcache_tlb_set.read(), |
---|
| 3178 | nline ); |
---|
| 3179 | #ifdef INSTRUMENTATION |
---|
| 3180 | m_cpt_dtlb_write++; |
---|
| 3181 | #endif |
---|
| 3182 | } |
---|
| 3183 | |
---|
| 3184 | #if DEBUG_DCACHE |
---|
| 3185 | if ( m_debug_dcache_fsm ) |
---|
| 3186 | { |
---|
| 3187 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3188 | { |
---|
[205] | 3189 | std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"; |
---|
| 3190 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 3191 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 3192 | r_itlb.printTrace(); |
---|
[183] | 3193 | } |
---|
| 3194 | else |
---|
| 3195 | { |
---|
[205] | 3196 | std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"; |
---|
| 3197 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 3198 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 3199 | r_dtlb.printTrace(); |
---|
[183] | 3200 | } |
---|
| 3201 | } |
---|
| 3202 | #endif |
---|
| 3203 | // next state |
---|
[205] | 3204 | if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update |
---|
[183] | 3205 | else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm |
---|
| 3206 | break; |
---|
| 3207 | } |
---|
| 3208 | //////////////////////// |
---|
[205] | 3209 | case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit), |
---|
[183] | 3210 | // request a SC transaction to CMD FSM |
---|
| 3211 | { |
---|
[204] | 3212 | #if DEBUG_DCACHE |
---|
| 3213 | if ( m_debug_dcache_fsm ) |
---|
| 3214 | { |
---|
[205] | 3215 | std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl; |
---|
[204] | 3216 | } |
---|
| 3217 | #endif |
---|
[183] | 3218 | r_dcache.write(r_dcache_tlb_cache_way.read(), |
---|
| 3219 | r_dcache_tlb_cache_set.read(), |
---|
| 3220 | r_dcache_tlb_cache_word.read(), |
---|
| 3221 | r_dcache_tlb_pte_flags.read()); |
---|
| 3222 | #ifdef INSTRUMENTATION |
---|
| 3223 | m_cpt_dcache_data_write++; |
---|
| 3224 | #endif |
---|
| 3225 | // r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set |
---|
[205] | 3226 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
[183] | 3227 | r_dcache_vci_sc_req = true; |
---|
[205] | 3228 | r_dcache_fsm = DCACHE_TLB_LR_WAIT; |
---|
[183] | 3229 | break; |
---|
| 3230 | } |
---|
| 3231 | //////////////////////// |
---|
[205] | 3232 | case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction. |
---|
[204] | 3233 | // We consume the response in rsp FIFO, |
---|
| 3234 | // and exit the sub-fsm, but we don't |
---|
| 3235 | // analyse the response, because we don't |
---|
| 3236 | // care if the L/R bit update is not done. |
---|
| 3237 | // We must take the coherence requests because |
---|
[199] | 3238 | // there is a risk of dead-lock |
---|
| 3239 | |
---|
[183] | 3240 | { |
---|
[199] | 3241 | // external coherence request |
---|
| 3242 | if ( r_tgt_dcache_req ) |
---|
| 3243 | { |
---|
| 3244 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3245 | r_dcache_fsm_save = r_dcache_fsm; |
---|
| 3246 | break; |
---|
| 3247 | } |
---|
| 3248 | |
---|
[204] | 3249 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
[183] | 3250 | { |
---|
[205] | 3251 | std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl; |
---|
[204] | 3252 | std::cout << "This should not happen in this state" << std::endl; |
---|
| 3253 | exit(0); |
---|
[183] | 3254 | } |
---|
[204] | 3255 | else if ( r_vci_rsp_fifo_dcache.rok() ) // response available |
---|
| 3256 | { |
---|
| 3257 | #if DEBUG_DCACHE |
---|
| 3258 | if ( m_debug_dcache_fsm ) |
---|
| 3259 | { |
---|
[205] | 3260 | std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl; |
---|
[204] | 3261 | } |
---|
| 3262 | #endif |
---|
| 3263 | vci_rsp_fifo_dcache_get = true; |
---|
| 3264 | r_dcache_fsm = DCACHE_TLB_RETURN; |
---|
| 3265 | } |
---|
[183] | 3266 | break; |
---|
| 3267 | } |
---|
| 3268 | /////////////////////// |
---|
[204] | 3269 | case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type |
---|
[183] | 3270 | { |
---|
[204] | 3271 | #if DEBUG_DCACHE |
---|
| 3272 | if ( m_debug_dcache_fsm ) |
---|
| 3273 | { |
---|
| 3274 | std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl; |
---|
| 3275 | } |
---|
| 3276 | #endif |
---|
[183] | 3277 | if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false; |
---|
| 3278 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3279 | break; |
---|
| 3280 | } |
---|
| 3281 | /////////////////////// |
---|
| 3282 | case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed |
---|
| 3283 | { |
---|
[196] | 3284 | if ( not r_dcache_xtn_req.read() ) |
---|
[183] | 3285 | { |
---|
| 3286 | r_dtlb.flush(); |
---|
| 3287 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3288 | m_drsp.valid = true; |
---|
[183] | 3289 | } |
---|
| 3290 | break; |
---|
| 3291 | } |
---|
| 3292 | ///////////////////// |
---|
| 3293 | case DCACHE_XTN_SYNC: // waiting until write buffer empty |
---|
[196] | 3294 | // The coherence request must be taken |
---|
| 3295 | // as there is a risk of dead-lock |
---|
[183] | 3296 | { |
---|
[196] | 3297 | // external coherence request |
---|
| 3298 | if ( r_tgt_dcache_req.read() ) |
---|
| 3299 | { |
---|
| 3300 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3301 | r_dcache_fsm_save = DCACHE_XTN_SYNC; |
---|
| 3302 | } |
---|
| 3303 | |
---|
[183] | 3304 | if ( r_wbuf.empty() ) |
---|
| 3305 | { |
---|
[205] | 3306 | m_drsp.valid = true; |
---|
[183] | 3307 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3308 | } |
---|
[193] | 3309 | break; |
---|
[183] | 3310 | } |
---|
| 3311 | //////////////////////// |
---|
| 3312 | case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM |
---|
| 3313 | case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken |
---|
| 3314 | case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache |
---|
| 3315 | case DCACHE_XTN_IT_INVAL: // can generate an itlb miss... |
---|
| 3316 | { |
---|
| 3317 | // external coherence request |
---|
| 3318 | if ( r_tgt_dcache_req ) |
---|
| 3319 | { |
---|
| 3320 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3321 | r_dcache_fsm_save = r_dcache_fsm; |
---|
| 3322 | break; |
---|
| 3323 | } |
---|
| 3324 | |
---|
| 3325 | // itlb miss request |
---|
| 3326 | if ( r_icache_tlb_miss_req.read() ) |
---|
| 3327 | { |
---|
| 3328 | r_dcache_tlb_ins = true; |
---|
| 3329 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
| 3330 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
| 3331 | break; |
---|
| 3332 | } |
---|
| 3333 | |
---|
| 3334 | // test if XTN request to icache completed |
---|
| 3335 | if ( not r_dcache_xtn_req.read() ) |
---|
| 3336 | { |
---|
| 3337 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3338 | m_drsp.valid = true; |
---|
[183] | 3339 | } |
---|
| 3340 | break; |
---|
| 3341 | } |
---|
| 3342 | ///////////////////////// |
---|
| 3343 | case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using |
---|
| 3344 | // the r_dcache_flush counter as a slot counter. |
---|
| 3345 | // We loop in this state until all slots have been visited. |
---|
| 3346 | // A cleanup request is generated for each valid line |
---|
| 3347 | // and we are blocked until the previous cleanup is completed |
---|
| 3348 | // Finally, both the itlb and dtlb are reset, because |
---|
| 3349 | // all TLB entries (including global entries) must be invalidated. |
---|
| 3350 | { |
---|
| 3351 | if ( not r_dcache_cleanup_req ) |
---|
| 3352 | { |
---|
| 3353 | paddr_t nline; |
---|
| 3354 | size_t way = r_dcache_flush_count.read()/m_icache_sets; |
---|
| 3355 | size_t set = r_dcache_flush_count.read()%m_icache_sets; |
---|
| 3356 | |
---|
| 3357 | bool cleanup_req = r_dcache.inval( way, |
---|
[198] | 3358 | set, |
---|
| 3359 | &nline ); |
---|
[183] | 3360 | if ( cleanup_req ) |
---|
| 3361 | { |
---|
| 3362 | r_dcache_cleanup_req = true; |
---|
| 3363 | r_dcache_cleanup_line = nline; |
---|
| 3364 | } |
---|
| 3365 | |
---|
| 3366 | r_dcache_flush_count = r_dcache_flush_count.read() + 1; |
---|
| 3367 | |
---|
| 3368 | if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot |
---|
| 3369 | { |
---|
[206] | 3370 | r_dtlb.reset(); |
---|
| 3371 | r_itlb.reset(); |
---|
[183] | 3372 | for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++) |
---|
| 3373 | { |
---|
[206] | 3374 | r_dcache_in_tlb[line] = false; |
---|
| 3375 | r_dcache_contains_ptd[line] = false; |
---|
[183] | 3376 | } |
---|
| 3377 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3378 | m_drsp.valid = true; |
---|
[183] | 3379 | } |
---|
| 3380 | } |
---|
| 3381 | break; |
---|
| 3382 | } |
---|
| 3383 | ///////////////////////// |
---|
| 3384 | case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request |
---|
| 3385 | { |
---|
| 3386 | r_dtlb.inval(r_dcache_p0_wdata.read()); |
---|
| 3387 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3388 | m_drsp.valid = true; |
---|
[183] | 3389 | break; |
---|
| 3390 | } |
---|
| 3391 | //////////////////////////// |
---|
| 3392 | case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address |
---|
| 3393 | // requires 3 cycles: access tlb, read cache, inval cache |
---|
| 3394 | // we compute the physical address in this state |
---|
| 3395 | { |
---|
| 3396 | paddr_t paddr; |
---|
| 3397 | bool hit; |
---|
| 3398 | |
---|
| 3399 | if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated |
---|
| 3400 | { |
---|
| 3401 | #ifdef INSTRUMENTATION |
---|
| 3402 | m_cpt_dtlb_read++; |
---|
| 3403 | #endif |
---|
| 3404 | hit = r_dtlb.translate( r_dcache_p0_wdata.read(), |
---|
| 3405 | &paddr ); |
---|
| 3406 | } |
---|
| 3407 | else // dtlb not activated |
---|
| 3408 | { |
---|
| 3409 | paddr = (paddr_t)r_dcache_p0_wdata.read(); |
---|
| 3410 | hit = true; |
---|
| 3411 | } |
---|
| 3412 | |
---|
| 3413 | if ( hit ) // tlb hit |
---|
| 3414 | { |
---|
| 3415 | r_dcache_p0_paddr = paddr; |
---|
| 3416 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
| 3417 | } |
---|
| 3418 | else // tlb miss |
---|
| 3419 | { |
---|
| 3420 | #ifdef INSTRUMENTATION |
---|
| 3421 | m_cpt_dtlb_miss++; |
---|
| 3422 | #endif |
---|
| 3423 | r_dcache_tlb_ins = false; // dtlb |
---|
| 3424 | r_dcache_tlb_vaddr = r_dcache_p0_wdata.read(); |
---|
| 3425 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
| 3426 | } |
---|
[206] | 3427 | |
---|
| 3428 | #if DEBUG_DCACHE |
---|
| 3429 | if ( m_debug_dcache_fsm ) |
---|
| 3430 | { |
---|
| 3431 | std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex |
---|
| 3432 | << " / VADDR = " << r_dcache_p0_wdata.read() |
---|
| 3433 | << " / PADDR = " << paddr << std::endl; |
---|
| 3434 | } |
---|
| 3435 | #endif |
---|
| 3436 | |
---|
[183] | 3437 | break; |
---|
| 3438 | } |
---|
| 3439 | //////////////////////////// |
---|
| 3440 | case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address |
---|
| 3441 | // requires 2 cycles: read cache / inval cache |
---|
| 3442 | // In this state we read dcache. |
---|
| 3443 | { |
---|
| 3444 | uint32_t data; |
---|
| 3445 | size_t way; |
---|
| 3446 | size_t set; |
---|
| 3447 | size_t word; |
---|
| 3448 | bool hit = r_dcache.read( r_dcache_p0_paddr.read(), |
---|
| 3449 | &data, |
---|
| 3450 | &way, |
---|
| 3451 | &set, |
---|
| 3452 | &word ); |
---|
| 3453 | #ifdef INSTRUMENTATION |
---|
| 3454 | m_cpt_dcache_data_read++; |
---|
| 3455 | m_cpt_dcache_dir_read++; |
---|
| 3456 | #endif |
---|
| 3457 | if ( hit ) // inval to be done |
---|
| 3458 | { |
---|
| 3459 | r_dcache_xtn_way = way; |
---|
| 3460 | r_dcache_xtn_set = set; |
---|
| 3461 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; |
---|
| 3462 | } |
---|
| 3463 | else // miss : nothing to do |
---|
| 3464 | { |
---|
| 3465 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3466 | m_drsp.valid = true; |
---|
[183] | 3467 | } |
---|
[206] | 3468 | |
---|
| 3469 | #if DEBUG_DCACHE |
---|
| 3470 | if ( m_debug_dcache_fsm ) |
---|
| 3471 | { |
---|
| 3472 | std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex |
---|
| 3473 | << " / PADDR = " << r_dcache_p0_paddr.read() << std::dec |
---|
| 3474 | << " / HIT = " << hit |
---|
| 3475 | << " / SET = " << set |
---|
| 3476 | << " / WAY = " << way << std::endl; |
---|
| 3477 | } |
---|
| 3478 | #endif |
---|
[183] | 3479 | break; |
---|
| 3480 | } |
---|
| 3481 | //////////////////////////// |
---|
[206] | 3482 | case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line |
---|
[183] | 3483 | // Blocked if previous cleanup not completed |
---|
[204] | 3484 | // Test if itlb or dtlb inval is required |
---|
[183] | 3485 | { |
---|
| 3486 | if ( not r_dcache_cleanup_req.read() ) |
---|
| 3487 | { |
---|
| 3488 | paddr_t nline; |
---|
[204] | 3489 | size_t way = r_dcache_xtn_way.read(); |
---|
| 3490 | size_t set = r_dcache_xtn_set.read(); |
---|
[183] | 3491 | |
---|
[206] | 3492 | r_dcache.inval( way, |
---|
[183] | 3493 | set, |
---|
| 3494 | &nline ); |
---|
| 3495 | |
---|
| 3496 | // request cleanup |
---|
| 3497 | r_dcache_cleanup_req = true; |
---|
| 3498 | r_dcache_cleanup_line = nline; |
---|
| 3499 | |
---|
[206] | 3500 | // possible itlb & dtlb invalidate |
---|
| 3501 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) |
---|
[183] | 3502 | { |
---|
[204] | 3503 | r_dcache_tlb_inval_line = nline; |
---|
| 3504 | r_dcache_tlb_inval_count = 0; |
---|
| 3505 | r_dcache_fsm_save = DCACHE_XTN_DC_INVAL_END; |
---|
| 3506 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
[206] | 3507 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[183] | 3508 | } |
---|
[206] | 3509 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) |
---|
| 3510 | { |
---|
| 3511 | r_itlb.reset(); |
---|
| 3512 | r_dtlb.reset(); |
---|
| 3513 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
| 3514 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3515 | m_drsp.valid = true; |
---|
| 3516 | } |
---|
[183] | 3517 | else |
---|
| 3518 | { |
---|
| 3519 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3520 | m_drsp.valid = true; |
---|
[183] | 3521 | } |
---|
[206] | 3522 | |
---|
| 3523 | #if DEBUG_DCACHE |
---|
| 3524 | if ( m_debug_dcache_fsm ) |
---|
| 3525 | { |
---|
| 3526 | std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex |
---|
| 3527 | << " / NLINE = " << nline << std::endl; |
---|
| 3528 | } |
---|
| 3529 | #endif |
---|
[183] | 3530 | } |
---|
| 3531 | break; |
---|
| 3532 | } |
---|
| 3533 | ////////////////////////////// |
---|
[206] | 3534 | case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request |
---|
[183] | 3535 | { |
---|
[204] | 3536 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3537 | m_drsp.valid = true; |
---|
[183] | 3538 | break; |
---|
| 3539 | } |
---|
| 3540 | //////////////////////// |
---|
| 3541 | case DCACHE_MISS_VICTIM: // Selects a victim line |
---|
| 3542 | // Set the r_dcache_cleanup_req flip-flop |
---|
| 3543 | // when the selected slot is not empty |
---|
| 3544 | { |
---|
| 3545 | bool valid; |
---|
| 3546 | size_t way; |
---|
| 3547 | size_t set; |
---|
| 3548 | paddr_t victim; |
---|
| 3549 | |
---|
| 3550 | valid = r_dcache.victim_select( r_dcache_vci_paddr.read(), |
---|
| 3551 | &victim, |
---|
| 3552 | &way, |
---|
| 3553 | &set ); |
---|
| 3554 | r_dcache_miss_way = way; |
---|
| 3555 | r_dcache_miss_set = set; |
---|
| 3556 | |
---|
| 3557 | if ( valid ) |
---|
| 3558 | { |
---|
| 3559 | r_dcache_cleanup_req = true; |
---|
| 3560 | r_dcache_cleanup_line = victim; |
---|
| 3561 | r_dcache_fsm = DCACHE_MISS_INVAL; |
---|
| 3562 | } |
---|
| 3563 | else |
---|
| 3564 | { |
---|
| 3565 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
| 3566 | } |
---|
| 3567 | |
---|
| 3568 | #if DEBUG_DCACHE |
---|
| 3569 | if ( m_debug_dcache_fsm ) |
---|
| 3570 | { |
---|
[198] | 3571 | std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" |
---|
[183] | 3572 | << " / way = " << way |
---|
| 3573 | << " / set = " << set |
---|
| 3574 | << " / valid = " << valid |
---|
[196] | 3575 | << " / line = " << std::hex << victim << std::endl; |
---|
[183] | 3576 | } |
---|
| 3577 | #endif |
---|
| 3578 | break; |
---|
| 3579 | } |
---|
| 3580 | /////////////////////// |
---|
| 3581 | case DCACHE_MISS_INVAL: // invalidate the victim line |
---|
[198] | 3582 | // and possibly request itlb or dtlb invalidate |
---|
[183] | 3583 | { |
---|
| 3584 | paddr_t nline; |
---|
[206] | 3585 | size_t way = r_dcache_miss_way.read(); |
---|
| 3586 | size_t set = r_dcache_miss_set.read(); |
---|
[183] | 3587 | |
---|
[198] | 3588 | r_dcache.inval( way, |
---|
| 3589 | set, |
---|
| 3590 | &nline ); |
---|
[183] | 3591 | |
---|
[206] | 3592 | // if selective itlb & dtlb invalidate are required |
---|
[183] | 3593 | // the miss response is not handled before invalidate completed |
---|
[206] | 3594 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) |
---|
[183] | 3595 | { |
---|
[206] | 3596 | r_dcache_tlb_inval_line = nline; |
---|
| 3597 | r_dcache_tlb_inval_count = 0; |
---|
| 3598 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
| 3599 | r_dcache_fsm_save = DCACHE_MISS_WAIT; |
---|
| 3600 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[183] | 3601 | } |
---|
[206] | 3602 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) |
---|
[183] | 3603 | { |
---|
[206] | 3604 | r_itlb.reset(); |
---|
| 3605 | r_dtlb.reset(); |
---|
| 3606 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
[183] | 3607 | } |
---|
[206] | 3608 | else |
---|
| 3609 | { |
---|
| 3610 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
| 3611 | } |
---|
[183] | 3612 | break; |
---|
| 3613 | } |
---|
| 3614 | ////////////////////// |
---|
| 3615 | case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM |
---|
| 3616 | // This state is in charge of error signaling |
---|
| 3617 | // There is 5 types of error depending on the requester |
---|
| 3618 | { |
---|
| 3619 | // external coherence request |
---|
| 3620 | if ( r_tgt_dcache_req ) |
---|
| 3621 | { |
---|
| 3622 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3623 | r_dcache_fsm_save = r_dcache_fsm; |
---|
| 3624 | break; |
---|
| 3625 | } |
---|
| 3626 | |
---|
| 3627 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3628 | { |
---|
| 3629 | switch ( r_dcache_miss_type.read() ) |
---|
| 3630 | { |
---|
| 3631 | case PROC_MISS: |
---|
| 3632 | { |
---|
| 3633 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
| 3634 | r_mmu_dbvar = r_dcache_p0_vaddr.read(); |
---|
[205] | 3635 | m_drsp.valid = true; |
---|
| 3636 | m_drsp.error = true; |
---|
[183] | 3637 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3638 | break; |
---|
| 3639 | } |
---|
| 3640 | case PTE1_MISS: |
---|
| 3641 | { |
---|
| 3642 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3643 | { |
---|
| 3644 | r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
| 3645 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 3646 | r_icache_tlb_miss_req = false; |
---|
| 3647 | r_icache_tlb_rsp_error = true; |
---|
| 3648 | } |
---|
| 3649 | else |
---|
| 3650 | { |
---|
| 3651 | r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
| 3652 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 3653 | m_drsp.valid = true; |
---|
| 3654 | m_drsp.error = true; |
---|
[183] | 3655 | } |
---|
| 3656 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3657 | break; |
---|
| 3658 | } |
---|
| 3659 | case PTE2_MISS: |
---|
| 3660 | { |
---|
| 3661 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3662 | { |
---|
| 3663 | r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
| 3664 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 3665 | r_icache_tlb_miss_req = false; |
---|
| 3666 | r_icache_tlb_rsp_error = true; |
---|
| 3667 | } |
---|
| 3668 | else |
---|
| 3669 | { |
---|
| 3670 | r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
| 3671 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 3672 | m_drsp.valid = true; |
---|
| 3673 | m_drsp.error = true; |
---|
[183] | 3674 | } |
---|
| 3675 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3676 | break; |
---|
| 3677 | } |
---|
| 3678 | } // end switch type |
---|
| 3679 | r_vci_rsp_data_error = false; |
---|
| 3680 | } |
---|
| 3681 | else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available |
---|
| 3682 | { |
---|
| 3683 | r_dcache_miss_word = 0; |
---|
[198] | 3684 | r_dcache_fsm = DCACHE_MISS_UPDT; |
---|
[194] | 3685 | } |
---|
[183] | 3686 | break; |
---|
| 3687 | } |
---|
| 3688 | ////////////////////// |
---|
| 3689 | case DCACHE_MISS_UPDT: // update the dcache (one word per cycle) |
---|
| 3690 | // returns the response depending on the miss type |
---|
| 3691 | { |
---|
| 3692 | if ( r_vci_rsp_fifo_dcache.rok() ) // one word available |
---|
| 3693 | { |
---|
| 3694 | if ( r_dcache_miss_inval.read() ) // Matching coherence request |
---|
| 3695 | // pop the FIFO, without cache update |
---|
| 3696 | // send a cleanup for the missing line |
---|
| 3697 | // if the previous cleanup is completed |
---|
| 3698 | { |
---|
| 3699 | if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last |
---|
| 3700 | { |
---|
| 3701 | vci_rsp_fifo_dcache_get = true; |
---|
| 3702 | r_dcache_miss_word = r_dcache_miss_word.read() + 1; |
---|
| 3703 | } |
---|
| 3704 | else // last word |
---|
| 3705 | { |
---|
| 3706 | if ( not r_dcache_cleanup_req.read() ) // no pending cleanup |
---|
| 3707 | { |
---|
| 3708 | vci_rsp_fifo_dcache_get = true; |
---|
| 3709 | r_dcache_cleanup_req = true; |
---|
| 3710 | r_dcache_cleanup_line = r_dcache_vci_paddr.read() >> |
---|
| 3711 | (uint32_log2(m_dcache_words)+2); |
---|
| 3712 | r_dcache_miss_inval = false; |
---|
| 3713 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3714 | } |
---|
| 3715 | } |
---|
| 3716 | } |
---|
| 3717 | else // No matching coherence request |
---|
| 3718 | // pop the FIFO and update the cache |
---|
| 3719 | // update the directory at the last word |
---|
| 3720 | { |
---|
[206] | 3721 | size_t way = r_dcache_miss_way.read(); |
---|
| 3722 | size_t set = r_dcache_miss_set.read(); |
---|
| 3723 | size_t word = r_dcache_miss_word.read(); |
---|
[183] | 3724 | |
---|
| 3725 | #ifdef INSTRUMENTATION |
---|
| 3726 | m_cpt_dcache_data_write++; |
---|
| 3727 | #endif |
---|
[206] | 3728 | r_dcache.write( way, |
---|
| 3729 | set, |
---|
| 3730 | word, |
---|
[183] | 3731 | r_vci_rsp_fifo_dcache.read()); |
---|
| 3732 | |
---|
| 3733 | vci_rsp_fifo_dcache_get = true; |
---|
| 3734 | r_dcache_miss_word = r_dcache_miss_word.read() + 1; |
---|
| 3735 | |
---|
[206] | 3736 | // if last word, update directory, set in_tlb & contains_ptd bits |
---|
[183] | 3737 | if ( r_dcache_miss_word.read() == (m_dcache_words - 1) ) |
---|
| 3738 | { |
---|
| 3739 | |
---|
| 3740 | #ifdef INSTRUMENTATION |
---|
| 3741 | m_cpt_dcache_dir_write++; |
---|
| 3742 | #endif |
---|
| 3743 | r_dcache.victim_update_tag( r_dcache_vci_paddr.read(), |
---|
| 3744 | r_dcache_miss_way.read(), |
---|
| 3745 | r_dcache_miss_set.read() ); |
---|
[206] | 3746 | |
---|
| 3747 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
| 3748 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
[183] | 3749 | |
---|
| 3750 | if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
| 3751 | else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
| 3752 | else r_dcache_fsm = DCACHE_IDLE; |
---|
| 3753 | } |
---|
| 3754 | } |
---|
| 3755 | |
---|
| 3756 | #if DEBUG_DCACHE |
---|
| 3757 | if ( m_debug_dcache_fsm ) |
---|
| 3758 | { |
---|
| 3759 | if ( r_dcache_miss_inval.read() ) |
---|
| 3760 | { |
---|
| 3761 | if ( r_dcache_miss_word.read() < m_dcache_words-1 ) |
---|
| 3762 | { |
---|
| 3763 | std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:" |
---|
| 3764 | << " pop the FIFO, don't update the cache" << std::endl; |
---|
| 3765 | } |
---|
| 3766 | else |
---|
| 3767 | { |
---|
| 3768 | std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:" |
---|
| 3769 | << " last word : send a cleanup request " << std::endl; |
---|
| 3770 | } |
---|
| 3771 | } |
---|
| 3772 | else |
---|
| 3773 | { |
---|
[198] | 3774 | std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:" |
---|
[183] | 3775 | << " address = " << r_dcache_vci_paddr.read() |
---|
| 3776 | << " / data = " << r_vci_rsp_fifo_dcache.read() |
---|
| 3777 | << " / way = " << r_dcache_miss_way.read() |
---|
| 3778 | << " / set = " << r_dcache_miss_set.read() |
---|
| 3779 | << " / word = " << r_dcache_miss_word.read() << std::endl; |
---|
| 3780 | } |
---|
| 3781 | } |
---|
| 3782 | #endif |
---|
| 3783 | |
---|
| 3784 | } // end if rok |
---|
| 3785 | break; |
---|
| 3786 | } |
---|
| 3787 | ///////////////////// |
---|
| 3788 | case DCACHE_UNC_WAIT: |
---|
| 3789 | { |
---|
| 3790 | // external coherence request |
---|
| 3791 | if ( r_tgt_dcache_req.read() ) |
---|
| 3792 | { |
---|
| 3793 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3794 | r_dcache_fsm_save = r_dcache_fsm; |
---|
| 3795 | break; |
---|
| 3796 | } |
---|
| 3797 | |
---|
| 3798 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3799 | { |
---|
| 3800 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
[205] | 3801 | r_mmu_dbvar = m_dreq.addr; |
---|
[183] | 3802 | r_vci_rsp_data_error = false; |
---|
[205] | 3803 | m_drsp.error = true; |
---|
| 3804 | m_drsp.valid = true; |
---|
[183] | 3805 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3806 | break; |
---|
| 3807 | } |
---|
| 3808 | else if ( r_vci_rsp_fifo_dcache.rok() ) // data available |
---|
| 3809 | { |
---|
| 3810 | vci_rsp_fifo_dcache_get = true; |
---|
| 3811 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3812 | // we acknowledge the processor request if it has not been modified |
---|
[205] | 3813 | if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) ) |
---|
[183] | 3814 | { |
---|
[205] | 3815 | m_drsp.valid = true; |
---|
| 3816 | m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
[183] | 3817 | } |
---|
| 3818 | } |
---|
| 3819 | break; |
---|
| 3820 | } |
---|
[205] | 3821 | //////////////////// |
---|
| 3822 | case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request |
---|
| 3823 | { |
---|
| 3824 | // external coherence request |
---|
| 3825 | if ( r_tgt_dcache_req.read() ) |
---|
| 3826 | { |
---|
| 3827 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3828 | r_dcache_fsm_save = r_dcache_fsm; |
---|
| 3829 | break; |
---|
| 3830 | } |
---|
| 3831 | |
---|
| 3832 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3833 | { |
---|
| 3834 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
| 3835 | r_mmu_dbvar = m_dreq.addr; |
---|
| 3836 | r_vci_rsp_data_error = false; |
---|
| 3837 | m_drsp.error = true; |
---|
| 3838 | m_drsp.valid = true; |
---|
| 3839 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3840 | break; |
---|
| 3841 | } |
---|
| 3842 | else if ( r_vci_rsp_fifo_dcache.rok() ) // response available |
---|
| 3843 | { |
---|
| 3844 | vci_rsp_fifo_dcache_get = true; |
---|
[206] | 3845 | m_drsp.valid = true; |
---|
| 3846 | m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
| 3847 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3848 | } |
---|
| 3849 | break; |
---|
| 3850 | } |
---|
| 3851 | ////////////////////////// |
---|
[206] | 3852 | case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory |
---|
| 3853 | // before handling a processor WRITE or SC request |
---|
| 3854 | // Input argument is r_dcache_dirty_paddr |
---|
| 3855 | // In this first state, we get PTE value in dcache |
---|
| 3856 | // and post a SC request to CMD FSM |
---|
[183] | 3857 | { |
---|
| 3858 | // get PTE in dcache |
---|
[206] | 3859 | uint32_t pte; |
---|
[183] | 3860 | size_t way; |
---|
| 3861 | size_t set; |
---|
[206] | 3862 | size_t word; // unused |
---|
| 3863 | bool hit = r_dcache.read( r_dcache_dirty_paddr.read(), |
---|
[204] | 3864 | &pte, |
---|
[183] | 3865 | &way, |
---|
| 3866 | &set, |
---|
| 3867 | &word ); |
---|
| 3868 | #ifdef INSTRUMENTATION |
---|
| 3869 | m_cpt_dcache_data_read++; |
---|
| 3870 | m_cpt_dcache_dir_read++; |
---|
[198] | 3871 | #endif; |
---|
[205] | 3872 | assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" ); |
---|
[183] | 3873 | |
---|
[205] | 3874 | // request sc transaction to CMD_FSM |
---|
[206] | 3875 | r_dcache_dirty_way = way; |
---|
| 3876 | r_dcache_dirty_set = set; |
---|
[205] | 3877 | r_dcache_vci_sc_req = true; |
---|
[206] | 3878 | r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); |
---|
| 3879 | r_dcache_vci_sc_old = pte; |
---|
| 3880 | r_dcache_vci_sc_new = pte | PTE_D_MASK; |
---|
| 3881 | r_dcache_fsm = DCACHE_DIRTY_SC_WAIT; |
---|
[205] | 3882 | |
---|
[183] | 3883 | #if DEBUG_DCACHE |
---|
| 3884 | if ( m_debug_dcache_fsm ) |
---|
| 3885 | { |
---|
[206] | 3886 | std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex |
---|
| 3887 | << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() |
---|
| 3888 | << " / PTE_VALUE = " << pte << std::dec |
---|
| 3889 | << " / CACHE_SET = " << set |
---|
| 3890 | << " / CACHE_WAY = " << way << std::endl; |
---|
[183] | 3891 | } |
---|
| 3892 | #endif |
---|
| 3893 | break; |
---|
| 3894 | } |
---|
| 3895 | ////////////////////////// |
---|
[205] | 3896 | case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit |
---|
[206] | 3897 | // If the PTE update is a success, return to IDLE state. |
---|
| 3898 | // If the PTE update is a failure, invalidate the cache line |
---|
| 3899 | // in DCACHE and invalidate the matching TLB entries. |
---|
[183] | 3900 | { |
---|
| 3901 | // external coherence request |
---|
| 3902 | if ( r_tgt_dcache_req ) |
---|
| 3903 | { |
---|
| 3904 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3905 | r_dcache_fsm_save = r_dcache_fsm; |
---|
| 3906 | break; |
---|
| 3907 | } |
---|
| 3908 | |
---|
| 3909 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3910 | { |
---|
[205] | 3911 | std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl; |
---|
| 3912 | std::cout << "This should not happen in this state" << std::endl; |
---|
| 3913 | exit(0); |
---|
[183] | 3914 | } |
---|
| 3915 | else if ( r_vci_rsp_fifo_dcache.rok() ) // response available |
---|
| 3916 | { |
---|
[205] | 3917 | vci_rsp_fifo_dcache_get = true; |
---|
| 3918 | if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic |
---|
[183] | 3919 | { |
---|
[206] | 3920 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3921 | |
---|
| 3922 | #if DEBUG_DCACHE |
---|
| 3923 | if ( m_debug_dcache_fsm ) |
---|
| 3924 | { |
---|
| 3925 | std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set" |
---|
| 3926 | << std::endl; |
---|
| 3927 | } |
---|
| 3928 | #endif |
---|
| 3929 | } |
---|
| 3930 | else // invalidate the cache line and TLBs |
---|
| 3931 | { |
---|
| 3932 | paddr_t nline; |
---|
| 3933 | size_t way = r_dcache_dirty_way.read(); |
---|
| 3934 | size_t set = r_dcache_dirty_set.read(); |
---|
| 3935 | |
---|
| 3936 | r_dcache.inval( r_dcache_dirty_way.read(), |
---|
| 3937 | r_dcache_dirty_set.read(), |
---|
| 3938 | &nline ); |
---|
| 3939 | |
---|
| 3940 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE |
---|
[205] | 3941 | { |
---|
[206] | 3942 | r_dcache_tlb_inval_line = nline; |
---|
| 3943 | r_dcache_tlb_inval_count = 0; |
---|
| 3944 | r_dcache_fsm_save = DCACHE_IDLE; |
---|
| 3945 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
| 3946 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
| 3947 | } |
---|
| 3948 | if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD |
---|
[205] | 3949 | { |
---|
[206] | 3950 | r_itlb.reset(); |
---|
| 3951 | r_dtlb.reset(); |
---|
[205] | 3952 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3953 | } |
---|
[206] | 3954 | #if DEBUG_DCACHE |
---|
| 3955 | if ( m_debug_dcache_fsm ) |
---|
| 3956 | { |
---|
| 3957 | std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs" |
---|
| 3958 | << std::endl; |
---|
| 3959 | } |
---|
| 3960 | #endif |
---|
[183] | 3961 | } |
---|
| 3962 | } |
---|
| 3963 | break; |
---|
| 3964 | } |
---|
| 3965 | ///////////////////// |
---|
| 3966 | case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM |
---|
| 3967 | // handling coherence requests. |
---|
| 3968 | // If there is a matching pending miss on the modified cache |
---|
| 3969 | // line this is signaled in the r_dcache_miss inval flip-flop. |
---|
| 3970 | // If the updated (or invalidated) cache line has copies in TLBs |
---|
| 3971 | // these TLB copies are invalidated. |
---|
| 3972 | // The return state is defined in r_dcache_fsm_save |
---|
| 3973 | { |
---|
| 3974 | paddr_t paddr = r_tgt_paddr.read(); |
---|
| 3975 | paddr_t mask = ~((m_dcache_words<<2)-1); |
---|
| 3976 | |
---|
| 3977 | |
---|
| 3978 | if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and |
---|
| 3979 | ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss |
---|
| 3980 | { |
---|
| 3981 | r_dcache_miss_inval = true; // signaling the match |
---|
| 3982 | r_tgt_dcache_req = false; // coherence request completed |
---|
| 3983 | r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update |
---|
| 3984 | r_dcache_fsm = r_dcache_fsm_save; |
---|
| 3985 | |
---|
| 3986 | #if DEBUG_DCACHE |
---|
| 3987 | if ( m_debug_dcache_fsm ) |
---|
| 3988 | { |
---|
| 3989 | std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:" |
---|
| 3990 | << " address = " << std::hex << paddr << std::endl; |
---|
| 3991 | } |
---|
| 3992 | #endif |
---|
| 3993 | |
---|
| 3994 | } |
---|
| 3995 | else // no match |
---|
| 3996 | { |
---|
| 3997 | uint32_t rdata; |
---|
| 3998 | size_t way; |
---|
| 3999 | size_t set; |
---|
| 4000 | size_t word; |
---|
| 4001 | |
---|
| 4002 | bool hit = r_dcache.read(paddr, |
---|
| 4003 | &rdata, // unused |
---|
| 4004 | &way, |
---|
| 4005 | &set, |
---|
| 4006 | &word); // unused |
---|
| 4007 | #ifdef INSTRUMENTATION |
---|
| 4008 | m_cpt_dcache_data_read++; |
---|
| 4009 | m_cpt_dcache_dir_read++; |
---|
| 4010 | #endif |
---|
| 4011 | r_dcache_cc_way = way; |
---|
| 4012 | r_dcache_cc_set = set; |
---|
| 4013 | |
---|
| 4014 | if ( hit and r_tgt_update.read() ) // hit update |
---|
| 4015 | { |
---|
| 4016 | r_dcache_fsm = DCACHE_CC_UPDT; |
---|
| 4017 | r_dcache_cc_word = r_tgt_word_min.read(); |
---|
| 4018 | } |
---|
| 4019 | else if ( hit and not r_tgt_update.read() ) // hit inval |
---|
| 4020 | { |
---|
| 4021 | r_dcache_fsm = DCACHE_CC_INVAL; |
---|
| 4022 | } |
---|
| 4023 | else // miss can happen |
---|
| 4024 | { |
---|
| 4025 | r_tgt_dcache_req = false; |
---|
| 4026 | r_tgt_dcache_rsp = r_tgt_update.read(); |
---|
| 4027 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
| 4028 | } |
---|
| 4029 | |
---|
| 4030 | #if DEBUG_DCACHE |
---|
| 4031 | if ( m_debug_dcache_fsm ) |
---|
| 4032 | { |
---|
| 4033 | |
---|
| 4034 | std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :" |
---|
| 4035 | << " address = " << std::hex << paddr << std::dec; |
---|
| 4036 | if ( hit ) |
---|
| 4037 | { |
---|
| 4038 | std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl; |
---|
| 4039 | } |
---|
| 4040 | else |
---|
| 4041 | { |
---|
| 4042 | std::cout << " / MISS" << std::endl; |
---|
| 4043 | } |
---|
| 4044 | } |
---|
| 4045 | #endif |
---|
| 4046 | |
---|
| 4047 | } |
---|
| 4048 | break; |
---|
| 4049 | } |
---|
| 4050 | ///////////////////// |
---|
| 4051 | case DCACHE_CC_INVAL: // invalidate one cache line |
---|
| 4052 | // and test possible copies in TLBs |
---|
| 4053 | { |
---|
| 4054 | paddr_t nline; |
---|
[204] | 4055 | size_t way = r_dcache_cc_way.read(); |
---|
| 4056 | size_t set = r_dcache_cc_set.read(); |
---|
[183] | 4057 | |
---|
| 4058 | r_dcache.inval( way, |
---|
| 4059 | set, |
---|
| 4060 | &nline ); |
---|
| 4061 | |
---|
[206] | 4062 | // possible itlb & dtlb invalidate |
---|
| 4063 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective inval |
---|
[183] | 4064 | { |
---|
[204] | 4065 | r_dcache_tlb_inval_line = nline; |
---|
| 4066 | r_dcache_tlb_inval_count = 0; |
---|
| 4067 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
[206] | 4068 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[183] | 4069 | } |
---|
[206] | 4070 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // flush |
---|
[183] | 4071 | { |
---|
[206] | 4072 | r_itlb.reset(); |
---|
| 4073 | r_dtlb.reset(); |
---|
[183] | 4074 | r_tgt_dcache_rsp = true; |
---|
| 4075 | r_tgt_dcache_req = false; |
---|
| 4076 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
| 4077 | } |
---|
[206] | 4078 | else // no inval |
---|
| 4079 | { |
---|
| 4080 | r_tgt_dcache_rsp = true; |
---|
| 4081 | r_tgt_dcache_req = false; |
---|
| 4082 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
| 4083 | } |
---|
[183] | 4084 | |
---|
| 4085 | #if DEBUG_DCACHE |
---|
| 4086 | if ( m_debug_dcache_fsm ) |
---|
| 4087 | { |
---|
[206] | 4088 | std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec |
---|
| 4089 | << " / WAY = " << way |
---|
| 4090 | << " / SET = " << set << std::endl; |
---|
[183] | 4091 | } |
---|
| 4092 | #endif |
---|
| 4093 | |
---|
| 4094 | break; |
---|
| 4095 | } |
---|
| 4096 | /////////////////// |
---|
| 4097 | case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max) |
---|
| 4098 | // and test possible copies in TLBs |
---|
| 4099 | { |
---|
[204] | 4100 | size_t word = r_dcache_cc_word.read(); |
---|
| 4101 | size_t way = r_dcache_cc_way.read(); |
---|
| 4102 | size_t set = r_dcache_cc_set.read(); |
---|
| 4103 | paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
[183] | 4104 | |
---|
| 4105 | r_dcache.write( way, |
---|
| 4106 | set, |
---|
| 4107 | word, |
---|
| 4108 | r_tgt_buf[word], |
---|
| 4109 | r_tgt_be[word] ); |
---|
| 4110 | #ifdef INSTRUMENTATION |
---|
| 4111 | m_cpt_dcache_data_write++; |
---|
| 4112 | #endif |
---|
| 4113 | r_dcache_cc_word = word + 1; |
---|
| 4114 | |
---|
| 4115 | if ( word == r_tgt_word_max.read() ) // last word |
---|
| 4116 | { |
---|
[206] | 4117 | // possible itlb & dtlb invalidate |
---|
| 4118 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective inval |
---|
[183] | 4119 | { |
---|
[204] | 4120 | r_dcache_tlb_inval_line = nline; |
---|
| 4121 | r_dcache_tlb_inval_count = 0; |
---|
| 4122 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
[206] | 4123 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[204] | 4124 | } |
---|
[206] | 4125 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // flush |
---|
[183] | 4126 | { |
---|
[206] | 4127 | r_itlb.reset(); |
---|
| 4128 | r_dtlb.reset(); |
---|
[183] | 4129 | r_tgt_dcache_rsp = true; |
---|
| 4130 | r_tgt_dcache_req = false; |
---|
| 4131 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
| 4132 | } |
---|
[206] | 4133 | else // no inval |
---|
| 4134 | { |
---|
| 4135 | r_tgt_dcache_rsp = true; |
---|
| 4136 | r_tgt_dcache_req = false; |
---|
| 4137 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
| 4138 | } |
---|
[183] | 4139 | } |
---|
| 4140 | |
---|
| 4141 | #if DEBUG_DCACHE |
---|
| 4142 | if ( m_debug_dcache_fsm ) |
---|
| 4143 | { |
---|
[206] | 4144 | std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec |
---|
| 4145 | << " / WAY = " << way |
---|
| 4146 | << " / SET = " << set |
---|
| 4147 | << " / WORD = " << word |
---|
| 4148 | << " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl; |
---|
[183] | 4149 | } |
---|
| 4150 | #endif |
---|
| 4151 | |
---|
| 4152 | break; |
---|
| 4153 | } |
---|
[204] | 4154 | /////////////////////////// |
---|
[206] | 4155 | case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB |
---|
[204] | 4156 | // It makes the assumption that (m_itlb_sets == m_dtlb_sets) |
---|
| 4157 | // and (m_itlb_ways == m_dtlb_ways) |
---|
[206] | 4158 | // We enter this state when a DCACHE line is modified, |
---|
[204] | 4159 | // and there is a copy in itlb or dtlb. |
---|
[206] | 4160 | // It can be caused by: |
---|
| 4161 | // - a coherence inval or updt transaction, |
---|
| 4162 | // - a line inval caused by a cache miss |
---|
| 4163 | // - a processor XTN inval request, |
---|
| 4164 | // - a WRITE hit, |
---|
| 4165 | // - a Dirty bit update failure |
---|
| 4166 | // Input arguments are: |
---|
[204] | 4167 | // - r_dcache_tlb_inval_line |
---|
| 4168 | // - r_dcache_tlb_inval_count |
---|
| 4169 | // - r_dcache_fsm_save |
---|
[183] | 4170 | { |
---|
[204] | 4171 | paddr_t line = r_dcache_tlb_inval_line.read(); // nline |
---|
| 4172 | size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way |
---|
| 4173 | size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set |
---|
[206] | 4174 | bool ok; |
---|
[204] | 4175 | |
---|
[206] | 4176 | ok = r_itlb.inval( line, |
---|
| 4177 | way, |
---|
| 4178 | set ); |
---|
[204] | 4179 | #if DEBUG_DCACHE |
---|
| 4180 | if ( m_debug_dcache_fsm and ok ) |
---|
| 4181 | { |
---|
| 4182 | std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex |
---|
| 4183 | << " line = " << line << std::dec |
---|
| 4184 | << " / set = " << set |
---|
| 4185 | << " / way = " << way << std::endl; |
---|
[205] | 4186 | r_itlb.printTrace(); |
---|
[204] | 4187 | } |
---|
| 4188 | #endif |
---|
[206] | 4189 | ok = r_dtlb.inval( line, |
---|
| 4190 | way, |
---|
| 4191 | set ); |
---|
[204] | 4192 | #if DEBUG_DCACHE |
---|
| 4193 | if ( m_debug_dcache_fsm and ok ) |
---|
| 4194 | { |
---|
| 4195 | std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex |
---|
| 4196 | << " line = " << line << std::dec |
---|
| 4197 | << " / set = " << set |
---|
| 4198 | << " / way = " << way << std::endl; |
---|
[205] | 4199 | r_dtlb.printTrace(); |
---|
[204] | 4200 | } |
---|
| 4201 | #endif |
---|
| 4202 | |
---|
| 4203 | // return to the calling state when TLB inval completed |
---|
| 4204 | if ( r_dcache_tlb_inval_count.read() == (m_dtlb_sets*m_dtlb_ways-1) ) |
---|
| 4205 | { |
---|
[206] | 4206 | if ( r_tgt_dcache_req.read() ) // It's a coherence request |
---|
[204] | 4207 | { |
---|
| 4208 | r_tgt_dcache_rsp = true; |
---|
| 4209 | r_tgt_dcache_req = false; |
---|
| 4210 | } |
---|
| 4211 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
| 4212 | } |
---|
| 4213 | r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1; |
---|
[183] | 4214 | } |
---|
| 4215 | } // end switch r_dcache_fsm |
---|
| 4216 | |
---|
| 4217 | ///////////////// wbuf update ////////////////////////////////////////////////////// |
---|
| 4218 | r_wbuf.update(); |
---|
| 4219 | |
---|
[205] | 4220 | //////////////// test processor frozen ///////////////////////////////////////////// |
---|
[183] | 4221 | // The simulation exit if the number of consecutive frozen cycles |
---|
| 4222 | // is larger than the m_max_frozen_cycles (constructor parameter) |
---|
[205] | 4223 | if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) ) |
---|
[183] | 4224 | { |
---|
| 4225 | m_cpt_frz_cycles++; // used for instrumentation |
---|
| 4226 | m_cpt_stop_simulation++; // used for debug |
---|
| 4227 | if ( m_cpt_stop_simulation > m_max_frozen_cycles ) |
---|
| 4228 | { |
---|
| 4229 | std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl |
---|
| 4230 | << " stop at cycle " << m_cpt_total_cycles << std::endl |
---|
| 4231 | << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles |
---|
| 4232 | << std::endl; |
---|
| 4233 | exit(1); |
---|
| 4234 | } |
---|
| 4235 | } |
---|
| 4236 | else |
---|
| 4237 | { |
---|
| 4238 | m_cpt_stop_simulation = 0; |
---|
| 4239 | } |
---|
| 4240 | |
---|
| 4241 | /////////// execute one iss cycle ///////////////////////////////// |
---|
| 4242 | { |
---|
| 4243 | uint32_t it = 0; |
---|
| 4244 | for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i); |
---|
[205] | 4245 | r_iss.executeNCycles(1, m_irsp, m_drsp, it); |
---|
[183] | 4246 | } |
---|
| 4247 | |
---|
| 4248 | //////////////////////////////////////////////////////////////////////////// |
---|
| 4249 | // The VCI_CMD FSM controls the following ressources: |
---|
| 4250 | // - r_vci_cmd_fsm |
---|
| 4251 | // - r_vci_cmd_min |
---|
| 4252 | // - r_vci_cmd_max |
---|
| 4253 | // - r_vci_cmd_cpt |
---|
| 4254 | // - r_vci_cmd_imiss_prio |
---|
| 4255 | // - wbuf (reset) |
---|
| 4256 | // - r_icache_miss_req (reset) |
---|
| 4257 | // - r_icache_unc_req (reset) |
---|
| 4258 | // - r_dcache_vci_miss_req (reset) |
---|
| 4259 | // - r_dcache_vci_unc_req (reset) |
---|
| 4260 | // - r_dcache_vci_sc_req (reset) |
---|
| 4261 | // |
---|
| 4262 | // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM. |
---|
| 4263 | // There is 6 request types, with the following priorities : |
---|
| 4264 | // 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer |
---|
| 4265 | // 2 - Data Read Uncachable : r_dcache_vci_unc_req |
---|
| 4266 | // 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer |
---|
| 4267 | // 4 - Instruction Uncachable : r_icache_unc_req |
---|
| 4268 | // 5 - Data Write : r_wbuf.rok() |
---|
| 4269 | // 6 - Data Store Conditionnal: r_dcache_vci_sc_req |
---|
| 4270 | // |
---|
| 4271 | // As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM |
---|
| 4272 | // and the VCI_RSP_FSM are fully desynchronized. |
---|
| 4273 | // |
---|
| 4274 | // VCI formats: |
---|
| 4275 | // According to the VCI advanced specification, all read requests packets |
---|
| 4276 | // (data Uncached, Miss data, instruction Uncached, Miss instruction) |
---|
| 4277 | // are one word packets. |
---|
| 4278 | // For write burst packets, all words are in the same cache line, |
---|
| 4279 | // and addresses must be contiguous (the BE field is 0 in case of "holes"). |
---|
| 4280 | // The sc command packet implements actually a compare-and-swap mechanism |
---|
| 4281 | // and the packet contains two flits. |
---|
| 4282 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 4283 | |
---|
| 4284 | switch ( r_vci_cmd_fsm.read() ) |
---|
| 4285 | { |
---|
| 4286 | ////////////// |
---|
| 4287 | case CMD_IDLE: |
---|
| 4288 | { |
---|
| 4289 | // r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access |
---|
| 4290 | // to check a possible pending write on the same cache line. |
---|
| 4291 | // As there is only one possible access per cycle to write buffer, we implement |
---|
| 4292 | // a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop. |
---|
| 4293 | |
---|
| 4294 | size_t wbuf_min; |
---|
| 4295 | size_t wbuf_max; |
---|
| 4296 | |
---|
| 4297 | bool dcache_miss_req = r_dcache_vci_miss_req.read() |
---|
| 4298 | and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); |
---|
| 4299 | bool icache_miss_req = r_icache_miss_req.read() |
---|
| 4300 | and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() ); |
---|
| 4301 | |
---|
| 4302 | // 1 - Data Read Miss |
---|
| 4303 | if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) |
---|
| 4304 | { |
---|
| 4305 | r_vci_cmd_fsm = CMD_DATA_MISS; |
---|
| 4306 | r_dcache_vci_miss_req = false; |
---|
| 4307 | r_vci_cmd_imiss_prio = true; |
---|
| 4308 | // m_cpt_dmiss_transaction++; |
---|
| 4309 | } |
---|
| 4310 | // 2 - Data Read Uncachable |
---|
| 4311 | else if ( r_dcache_vci_unc_req.read() ) |
---|
| 4312 | { |
---|
| 4313 | r_vci_cmd_fsm = CMD_DATA_UNC; |
---|
| 4314 | r_dcache_vci_unc_req = false; |
---|
| 4315 | // m_cpt_dunc_transaction++; |
---|
| 4316 | } |
---|
| 4317 | // 3 - Instruction Miss |
---|
| 4318 | else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) ) |
---|
| 4319 | { |
---|
| 4320 | r_vci_cmd_fsm = CMD_INS_MISS; |
---|
| 4321 | r_icache_miss_req = false; |
---|
| 4322 | r_vci_cmd_imiss_prio = false; |
---|
[198] | 4323 | // m_cpt_imiss_transaction++; |
---|
[183] | 4324 | } |
---|
| 4325 | // 4 - Instruction Uncachable |
---|
| 4326 | else if ( r_icache_unc_req.read() ) |
---|
| 4327 | { |
---|
| 4328 | r_vci_cmd_fsm = CMD_INS_UNC; |
---|
| 4329 | r_icache_unc_req = false; |
---|
[198] | 4330 | // m_cpt_iunc_transaction++; |
---|
[183] | 4331 | } |
---|
| 4332 | // 5 - Data Write |
---|
| 4333 | else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) ) |
---|
| 4334 | { |
---|
| 4335 | r_vci_cmd_fsm = CMD_DATA_WRITE; |
---|
| 4336 | r_vci_cmd_cpt = wbuf_min; |
---|
| 4337 | r_vci_cmd_min = wbuf_min; |
---|
| 4338 | r_vci_cmd_max = wbuf_max; |
---|
[198] | 4339 | // m_cpt_write_transaction++; |
---|
| 4340 | // m_length_write_transaction += (wbuf_max-wbuf_min+1); |
---|
[183] | 4341 | } |
---|
| 4342 | // 6 - Data Store Conditionnal |
---|
| 4343 | else if ( r_dcache_vci_sc_req.read() ) |
---|
| 4344 | { |
---|
| 4345 | r_vci_cmd_fsm = CMD_DATA_SC; |
---|
[204] | 4346 | r_dcache_vci_sc_req = false; |
---|
[183] | 4347 | r_vci_cmd_cpt = 0; |
---|
| 4348 | // m_cpt_sc_transaction++; |
---|
| 4349 | } |
---|
| 4350 | break; |
---|
| 4351 | } |
---|
| 4352 | //////////////////// |
---|
| 4353 | case CMD_DATA_WRITE: |
---|
| 4354 | { |
---|
| 4355 | if ( p_vci_ini_d.cmdack.read() ) |
---|
| 4356 | { |
---|
| 4357 | // m_conso_wbuf_read++; |
---|
| 4358 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
| 4359 | if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent |
---|
| 4360 | { |
---|
| 4361 | r_vci_cmd_fsm = CMD_IDLE ; |
---|
| 4362 | r_wbuf.sent() ; |
---|
| 4363 | } |
---|
| 4364 | } |
---|
| 4365 | break; |
---|
| 4366 | } |
---|
| 4367 | ///////////////// |
---|
| 4368 | case CMD_DATA_SC: |
---|
| 4369 | { |
---|
| 4370 | // The SC VCI command contains two flits |
---|
| 4371 | if ( p_vci_ini_d.cmdack.read() ) |
---|
| 4372 | { |
---|
| 4373 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
| 4374 | if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ; |
---|
| 4375 | } |
---|
| 4376 | break; |
---|
| 4377 | } |
---|
| 4378 | ////////////////// |
---|
| 4379 | case CMD_INS_MISS: |
---|
| 4380 | case CMD_INS_UNC: |
---|
| 4381 | case CMD_DATA_MISS: |
---|
| 4382 | case CMD_DATA_UNC: |
---|
| 4383 | { |
---|
| 4384 | // all read VCI commands contain one single flit |
---|
| 4385 | if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE; |
---|
| 4386 | break; |
---|
| 4387 | } |
---|
| 4388 | |
---|
| 4389 | } // end switch r_vci_cmd_fsm |
---|
| 4390 | |
---|
| 4391 | ////////////////////////////////////////////////////////////////////////// |
---|
| 4392 | // The VCI_RSP FSM controls the following ressources: |
---|
| 4393 | // - r_vci_rsp_fsm: |
---|
| 4394 | // - r_vci_rsp_fifo_icache (push) |
---|
| 4395 | // - r_vci_rsp_fifo_dcache (push) |
---|
| 4396 | // - r_vci_rsp_data_error (set) |
---|
| 4397 | // - r_vci_rsp_ins_error (set) |
---|
| 4398 | // - r_vci_rsp_cpt |
---|
| 4399 | // |
---|
| 4400 | // As the VCI_RSP and VCI_CMD are fully desynchronized to support several |
---|
| 4401 | // simultaneous VCI transactions, this FSM uses the VCI TRDID field |
---|
| 4402 | // to identify the transactions. |
---|
| 4403 | // |
---|
| 4404 | // VCI vormat: |
---|
| 4405 | // This component checks the response packet length and accepts only |
---|
| 4406 | // single word packets for write response packets. |
---|
| 4407 | // |
---|
| 4408 | // Error handling: |
---|
| 4409 | // This FSM analyzes the VCI error code and signals directly the Write Bus Error. |
---|
| 4410 | // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error |
---|
| 4411 | // flip_flop and the error is signaled by the DCACHE FSM. |
---|
| 4412 | // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error |
---|
| 4413 | // flip_flop and the error is signaled by the ICACHE FSM. |
---|
| 4414 | // In case of Cleanup Error, the simulation stops with an error message... |
---|
| 4415 | ////////////////////////////////////////////////////////////////////////// |
---|
| 4416 | |
---|
| 4417 | switch ( r_vci_rsp_fsm.read() ) |
---|
| 4418 | { |
---|
| 4419 | ////////////// |
---|
| 4420 | case RSP_IDLE: |
---|
| 4421 | { |
---|
| 4422 | if ( p_vci_ini_d.rspval.read() ) |
---|
| 4423 | { |
---|
| 4424 | r_vci_rsp_cpt = 0; |
---|
| 4425 | |
---|
| 4426 | if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction |
---|
| 4427 | { |
---|
| 4428 | r_vci_rsp_fsm = RSP_DATA_WRITE; |
---|
| 4429 | } |
---|
| 4430 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS ) |
---|
| 4431 | { |
---|
| 4432 | r_vci_rsp_fsm = RSP_INS_MISS; |
---|
| 4433 | } |
---|
| 4434 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC ) |
---|
| 4435 | { |
---|
| 4436 | r_vci_rsp_fsm = RSP_INS_UNC; |
---|
| 4437 | } |
---|
| 4438 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS ) |
---|
| 4439 | { |
---|
| 4440 | r_vci_rsp_fsm = RSP_DATA_MISS; |
---|
| 4441 | } |
---|
| 4442 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC ) |
---|
| 4443 | { |
---|
| 4444 | r_vci_rsp_fsm = RSP_DATA_UNC; |
---|
| 4445 | } |
---|
| 4446 | else |
---|
| 4447 | { |
---|
| 4448 | assert(false and "Unexpected VCI response"); |
---|
| 4449 | } |
---|
| 4450 | } |
---|
| 4451 | break; |
---|
| 4452 | } |
---|
| 4453 | ////////////////// |
---|
| 4454 | case RSP_INS_MISS: |
---|
| 4455 | { |
---|
| 4456 | if ( p_vci_ini_d.rspval.read() ) |
---|
| 4457 | { |
---|
| 4458 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4459 | { |
---|
| 4460 | r_vci_rsp_ins_error = true; |
---|
| 4461 | if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4462 | } |
---|
| 4463 | else // no error reported |
---|
| 4464 | { |
---|
| 4465 | if ( r_vci_rsp_fifo_icache.wok() ) |
---|
| 4466 | { |
---|
| 4467 | assert( (r_vci_rsp_cpt.read() < m_icache_words) and |
---|
| 4468 | "The VCI response packet for instruction miss is too long" ); |
---|
| 4469 | |
---|
| 4470 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
| 4471 | vci_rsp_fifo_icache_put = true, |
---|
| 4472 | vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); |
---|
| 4473 | if ( p_vci_ini_d.reop.read() ) |
---|
| 4474 | { |
---|
| 4475 | assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and |
---|
| 4476 | "The VCI response packet for instruction miss is too short"); |
---|
| 4477 | |
---|
| 4478 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4479 | } |
---|
| 4480 | } |
---|
| 4481 | } |
---|
| 4482 | } |
---|
| 4483 | break; |
---|
| 4484 | } |
---|
| 4485 | ///////////////// |
---|
| 4486 | case RSP_INS_UNC: |
---|
| 4487 | { |
---|
| 4488 | if (p_vci_ini_d.rspval.read() ) |
---|
| 4489 | { |
---|
| 4490 | assert( p_vci_ini_d.reop.read() and |
---|
| 4491 | "illegal VCI response packet for uncachable instruction"); |
---|
| 4492 | |
---|
| 4493 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4494 | { |
---|
| 4495 | r_vci_rsp_ins_error = true; |
---|
| 4496 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4497 | } |
---|
| 4498 | else // no error reported |
---|
| 4499 | { |
---|
| 4500 | if ( r_vci_rsp_fifo_icache.wok()) |
---|
| 4501 | { |
---|
| 4502 | vci_rsp_fifo_icache_put = true; |
---|
| 4503 | vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); |
---|
| 4504 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4505 | } |
---|
| 4506 | } |
---|
| 4507 | } |
---|
| 4508 | break; |
---|
| 4509 | } |
---|
| 4510 | /////////////////// |
---|
| 4511 | case RSP_DATA_MISS: |
---|
| 4512 | { |
---|
| 4513 | if ( p_vci_ini_d.rspval.read() ) |
---|
| 4514 | { |
---|
| 4515 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4516 | { |
---|
| 4517 | r_vci_rsp_data_error = true; |
---|
| 4518 | if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4519 | } |
---|
| 4520 | else // no error reported |
---|
| 4521 | { |
---|
| 4522 | if ( r_vci_rsp_fifo_dcache.wok() ) |
---|
| 4523 | { |
---|
| 4524 | assert( (r_vci_rsp_cpt.read() < m_dcache_words) and |
---|
| 4525 | "The VCI response packet for data miss is too long"); |
---|
| 4526 | |
---|
| 4527 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
| 4528 | vci_rsp_fifo_dcache_put = true, |
---|
| 4529 | vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); |
---|
| 4530 | if ( p_vci_ini_d.reop.read() ) |
---|
| 4531 | { |
---|
| 4532 | assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and |
---|
| 4533 | "The VCI response packet for data miss is too short"); |
---|
| 4534 | |
---|
| 4535 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4536 | } |
---|
| 4537 | } |
---|
| 4538 | } |
---|
| 4539 | } |
---|
| 4540 | break; |
---|
| 4541 | } |
---|
| 4542 | ////////////////// |
---|
| 4543 | case RSP_DATA_UNC: |
---|
| 4544 | { |
---|
| 4545 | if (p_vci_ini_d.rspval.read() ) |
---|
| 4546 | { |
---|
| 4547 | assert( p_vci_ini_d.reop.read() and |
---|
| 4548 | "illegal VCI response packet for uncachable read data"); |
---|
| 4549 | |
---|
| 4550 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4551 | { |
---|
| 4552 | r_vci_rsp_data_error = true; |
---|
| 4553 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4554 | } |
---|
| 4555 | else // no error reported |
---|
| 4556 | { |
---|
| 4557 | if ( r_vci_rsp_fifo_dcache.wok()) |
---|
| 4558 | { |
---|
| 4559 | vci_rsp_fifo_dcache_put = true; |
---|
| 4560 | vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); |
---|
| 4561 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4562 | } |
---|
| 4563 | } |
---|
| 4564 | } |
---|
| 4565 | break; |
---|
| 4566 | } |
---|
| 4567 | //////////////////// |
---|
| 4568 | case RSP_DATA_WRITE: |
---|
| 4569 | { |
---|
| 4570 | if (p_vci_ini_d.rspval.read()) |
---|
| 4571 | { |
---|
| 4572 | assert( p_vci_ini_d.reop.read() and |
---|
| 4573 | "a VCI response packet must contain one flit for a write transaction"); |
---|
| 4574 | |
---|
| 4575 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4576 | uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1)); |
---|
| 4577 | bool cacheable = r_wbuf.completed(wbuf_index); |
---|
| 4578 | if ( not cacheable ) r_dcache_pending_unc_write = false; |
---|
| 4579 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); |
---|
| 4580 | } |
---|
| 4581 | break; |
---|
| 4582 | } |
---|
| 4583 | } // end switch r_vci_rsp_fsm |
---|
| 4584 | |
---|
| 4585 | //////////////////////////////////////////////////////////////////////////////// |
---|
| 4586 | // The CLEANUP FSM send the cleanup commands on the coherence network, |
---|
| 4587 | // and supports simultaneous cleanup transactions, but two simultaneous |
---|
| 4588 | // transactions mut address different cache lines. |
---|
| 4589 | // Therefore, the line number is registered in an associative |
---|
| 4590 | // registration buffer (Content Adressable Memory) by the CLEANUP FSM, |
---|
| 4591 | // and the corresponding slot (identified by the VCI TRDID field) is cleared |
---|
| 4592 | // when the cleanup transaction response is received. |
---|
| 4593 | // It handles cleanup requests from both the DCACHE FSM & ICACHE FSM |
---|
| 4594 | // with a round robin priority, and can support up to 4 simultaneous |
---|
| 4595 | // cleanup transactions (4 slots in the registration buffer). |
---|
| 4596 | // The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset |
---|
| 4597 | // when the command has been sent. |
---|
| 4598 | // The VCI TRDID field is used to distinguish data/instruction cleanups: |
---|
| 4599 | // - if data cleanup : TRDID = 2*index + 0 |
---|
| 4600 | // - if instruction cleanup : TRDID = 2*index + 1 |
---|
| 4601 | //////////////////////////////////////////////////////////////////////////// |
---|
| 4602 | |
---|
| 4603 | switch ( r_cleanup_fsm.read() ) |
---|
| 4604 | { |
---|
| 4605 | /////////////////////// |
---|
| 4606 | case CLEANUP_DATA_IDLE: // dcache has highest priority |
---|
| 4607 | { |
---|
| 4608 | size_t index = 0; |
---|
| 4609 | bool ok; |
---|
| 4610 | if ( r_dcache_cleanup_req.read() ) // dcache request |
---|
| 4611 | { |
---|
| 4612 | ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(), |
---|
| 4613 | &index ); |
---|
| 4614 | if ( ok ) // successful registration |
---|
| 4615 | { |
---|
| 4616 | r_cleanup_fsm = CLEANUP_DATA_GO; |
---|
| 4617 | r_cleanup_trdid = index<<1; |
---|
| 4618 | } |
---|
| 4619 | } |
---|
| 4620 | else if ( r_icache_cleanup_req.read() ) // icache request |
---|
| 4621 | { |
---|
| 4622 | ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(), |
---|
| 4623 | &index ); |
---|
| 4624 | if ( ok ) // successful registration |
---|
| 4625 | { |
---|
| 4626 | r_cleanup_fsm = CLEANUP_INS_GO; |
---|
| 4627 | r_cleanup_trdid = (index<<1) + 1; |
---|
| 4628 | } |
---|
| 4629 | } |
---|
| 4630 | break; |
---|
| 4631 | } |
---|
| 4632 | ////////////////////// |
---|
| 4633 | case CLEANUP_INS_IDLE: // icache has highest priority |
---|
| 4634 | { |
---|
| 4635 | size_t index = 0; |
---|
| 4636 | bool ok; |
---|
| 4637 | if ( r_icache_cleanup_req.read() ) // icache request |
---|
| 4638 | { |
---|
| 4639 | ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(), |
---|
| 4640 | &index ); |
---|
| 4641 | if ( ok ) // successful registration |
---|
| 4642 | { |
---|
| 4643 | r_cleanup_fsm = CLEANUP_INS_GO; |
---|
| 4644 | r_cleanup_trdid = (index<<1) + 1; |
---|
| 4645 | } |
---|
| 4646 | } |
---|
| 4647 | else if ( r_dcache_cleanup_req.read() ) // dcache request |
---|
| 4648 | { |
---|
| 4649 | ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(), |
---|
| 4650 | &index ); |
---|
| 4651 | if ( ok ) // successful registration |
---|
| 4652 | { |
---|
| 4653 | r_cleanup_fsm = CLEANUP_DATA_GO; |
---|
| 4654 | r_cleanup_trdid = index<<1; |
---|
| 4655 | } |
---|
| 4656 | } |
---|
| 4657 | break; |
---|
| 4658 | } |
---|
| 4659 | ///////////////////// |
---|
| 4660 | case CLEANUP_DATA_GO: |
---|
| 4661 | { |
---|
| 4662 | if ( p_vci_ini_c.cmdack.read() ) |
---|
| 4663 | { |
---|
| 4664 | r_dcache_cleanup_req = false; |
---|
| 4665 | r_cleanup_fsm = CLEANUP_INS_IDLE; |
---|
| 4666 | |
---|
| 4667 | #if DEBUG_CLEANUP |
---|
| 4668 | if ( m_debug_cleanup_fsm ) |
---|
| 4669 | { |
---|
| 4670 | std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex |
---|
| 4671 | << " address = " << (r_dcache_cleanup_line.read()*m_dcache_words*4) |
---|
| 4672 | << " / trdid = " << r_cleanup_trdid.read() << std::endl; |
---|
| 4673 | } |
---|
| 4674 | #endif |
---|
| 4675 | } |
---|
| 4676 | } |
---|
| 4677 | //////////////////////// |
---|
| 4678 | case CLEANUP_INS_GO: |
---|
| 4679 | { |
---|
| 4680 | if ( p_vci_ini_c.cmdack.read() ) |
---|
| 4681 | { |
---|
| 4682 | r_icache_cleanup_req = false; |
---|
| 4683 | r_cleanup_fsm = CLEANUP_DATA_IDLE; |
---|
| 4684 | |
---|
| 4685 | #if DEBUG_CLEANUP |
---|
| 4686 | if ( m_debug_cleanup_fsm ) |
---|
| 4687 | { |
---|
| 4688 | std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex |
---|
| 4689 | << " address = " << (r_icache_cleanup_line.read()*m_icache_words*4) |
---|
| 4690 | << " / trdid = " << r_cleanup_trdid.read() << std::endl; |
---|
| 4691 | } |
---|
| 4692 | #endif |
---|
| 4693 | } |
---|
| 4694 | } |
---|
| 4695 | } // end switch CLEANUP FSM |
---|
| 4696 | |
---|
| 4697 | //////////////// Handling cleanup responses ////////////////// |
---|
| 4698 | if ( p_vci_ini_c.rspval.read() ) // valid response |
---|
| 4699 | { |
---|
| 4700 | r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1); |
---|
| 4701 | } |
---|
| 4702 | |
---|
| 4703 | ///////////////// Response FIFOs update ////////////////////// |
---|
| 4704 | r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, |
---|
| 4705 | vci_rsp_fifo_icache_put, |
---|
| 4706 | vci_rsp_fifo_icache_data); |
---|
| 4707 | |
---|
| 4708 | r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get, |
---|
| 4709 | vci_rsp_fifo_dcache_put, |
---|
| 4710 | vci_rsp_fifo_dcache_data); |
---|
| 4711 | } // end transition() |
---|
| 4712 | |
---|
| 4713 | /////////////////////// |
---|
| 4714 | tmpl(void)::genMoore() |
---|
| 4715 | /////////////////////// |
---|
| 4716 | { |
---|
| 4717 | //////////////////////////////////////////////////////////////// |
---|
| 4718 | // VCI initiator command on the coherence network (cleanup) |
---|
| 4719 | // it depends on the CLEANUP FSM state |
---|
| 4720 | |
---|
| 4721 | paddr_t address; |
---|
| 4722 | |
---|
| 4723 | if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO ) |
---|
| 4724 | address = r_dcache_cleanup_line.read()*m_dcache_words*4; |
---|
| 4725 | else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO ) |
---|
| 4726 | address = r_icache_cleanup_line.read()*m_icache_words*4; |
---|
| 4727 | else |
---|
| 4728 | address = 0; |
---|
| 4729 | |
---|
| 4730 | p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or |
---|
| 4731 | (r_cleanup_fsm.read() == CLEANUP_INS_GO) ); |
---|
| 4732 | p_vci_ini_c.address = address; |
---|
| 4733 | p_vci_ini_c.wdata = 0; |
---|
| 4734 | p_vci_ini_c.be = 0xF; |
---|
| 4735 | p_vci_ini_c.plen = 4; |
---|
| 4736 | p_vci_ini_c.cmd = vci_param::CMD_WRITE; |
---|
| 4737 | p_vci_ini_c.trdid = r_cleanup_trdid.read(); |
---|
| 4738 | p_vci_ini_c.pktid = 0; |
---|
| 4739 | p_vci_ini_c.srcid = m_srcid_c; |
---|
| 4740 | p_vci_ini_c.cons = false; |
---|
| 4741 | p_vci_ini_c.wrap = false; |
---|
| 4742 | p_vci_ini_c.contig = false; |
---|
| 4743 | p_vci_ini_c.clen = 0; |
---|
| 4744 | p_vci_ini_c.cfixed = false; |
---|
| 4745 | p_vci_ini_c.eop = true; |
---|
| 4746 | |
---|
| 4747 | ///////////////////////////////////////////////////////////////// |
---|
| 4748 | // VCI initiator response on the coherence network (cleanup) |
---|
| 4749 | // We always consume the response, and we don't use it. |
---|
| 4750 | |
---|
| 4751 | p_vci_ini_c.rspack = true; |
---|
| 4752 | |
---|
| 4753 | ///////////////////////////////////////////////////////////////// |
---|
| 4754 | // VCI initiator command on the direct network |
---|
| 4755 | // it depends on the CMD FSM state |
---|
| 4756 | |
---|
| 4757 | p_vci_ini_d.pktid = 0; |
---|
| 4758 | p_vci_ini_d.srcid = m_srcid_d; |
---|
| 4759 | p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC); |
---|
| 4760 | p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC); |
---|
| 4761 | p_vci_ini_d.wrap = false; |
---|
| 4762 | p_vci_ini_d.clen = 0; |
---|
| 4763 | p_vci_ini_d.cfixed = false; |
---|
| 4764 | |
---|
| 4765 | switch ( r_vci_cmd_fsm.read() ) { |
---|
| 4766 | |
---|
| 4767 | case CMD_IDLE: |
---|
| 4768 | p_vci_ini_d.cmdval = false; |
---|
| 4769 | p_vci_ini_d.address = 0; |
---|
| 4770 | p_vci_ini_d.wdata = 0; |
---|
| 4771 | p_vci_ini_d.be = 0; |
---|
| 4772 | p_vci_ini_d.trdid = 0; |
---|
| 4773 | p_vci_ini_d.plen = 0; |
---|
| 4774 | p_vci_ini_d.cmd = vci_param::CMD_NOP; |
---|
| 4775 | p_vci_ini_d.eop = false; |
---|
| 4776 | break; |
---|
| 4777 | |
---|
| 4778 | case CMD_INS_MISS: |
---|
| 4779 | p_vci_ini_d.cmdval = true; |
---|
| 4780 | p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask; |
---|
| 4781 | p_vci_ini_d.wdata = 0; |
---|
| 4782 | p_vci_ini_d.be = 0xF; |
---|
| 4783 | p_vci_ini_d.trdid = TYPE_INS_MISS; |
---|
| 4784 | p_vci_ini_d.plen = m_icache_words<<2; |
---|
| 4785 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4786 | p_vci_ini_d.eop = true; |
---|
| 4787 | break; |
---|
| 4788 | |
---|
| 4789 | case CMD_INS_UNC: |
---|
| 4790 | p_vci_ini_d.cmdval = true; |
---|
| 4791 | p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3; |
---|
| 4792 | p_vci_ini_d.wdata = 0; |
---|
| 4793 | p_vci_ini_d.be = 0xF; |
---|
| 4794 | p_vci_ini_d.trdid = TYPE_INS_UNC; |
---|
| 4795 | p_vci_ini_d.plen = 4; |
---|
| 4796 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4797 | p_vci_ini_d.eop = true; |
---|
| 4798 | break; |
---|
| 4799 | |
---|
| 4800 | case CMD_DATA_MISS: |
---|
| 4801 | p_vci_ini_d.cmdval = true; |
---|
| 4802 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; |
---|
| 4803 | p_vci_ini_d.wdata = 0; |
---|
| 4804 | p_vci_ini_d.be = 0xF; |
---|
| 4805 | p_vci_ini_d.trdid = TYPE_DATA_MISS; |
---|
| 4806 | p_vci_ini_d.plen = m_dcache_words << 2; |
---|
| 4807 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4808 | p_vci_ini_d.eop = true; |
---|
| 4809 | break; |
---|
| 4810 | |
---|
| 4811 | case CMD_DATA_UNC: |
---|
| 4812 | p_vci_ini_d.cmdval = true; |
---|
| 4813 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
| 4814 | p_vci_ini_d.wdata = 0; |
---|
| 4815 | p_vci_ini_d.be = r_dcache_vci_unc_be.read(); |
---|
| 4816 | p_vci_ini_d.trdid = TYPE_DATA_UNC; |
---|
| 4817 | p_vci_ini_d.plen = 4; |
---|
| 4818 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4819 | p_vci_ini_d.eop = true; |
---|
| 4820 | break; |
---|
| 4821 | |
---|
| 4822 | case CMD_DATA_WRITE: |
---|
| 4823 | p_vci_ini_d.cmdval = true; |
---|
| 4824 | p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; |
---|
| 4825 | p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); |
---|
| 4826 | p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); |
---|
| 4827 | p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1)); |
---|
| 4828 | p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; |
---|
| 4829 | p_vci_ini_d.cmd = vci_param::CMD_WRITE; |
---|
| 4830 | p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); |
---|
| 4831 | break; |
---|
| 4832 | |
---|
| 4833 | case CMD_DATA_SC: |
---|
| 4834 | p_vci_ini_d.cmdval = true; |
---|
| 4835 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
| 4836 | if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read(); |
---|
| 4837 | else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read(); |
---|
| 4838 | p_vci_ini_d.be = 0xF; |
---|
| 4839 | p_vci_ini_d.trdid = TYPE_DATA_UNC; |
---|
| 4840 | p_vci_ini_d.plen = 8; |
---|
| 4841 | p_vci_ini_d.cmd = vci_param::CMD_STORE_COND; |
---|
| 4842 | p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); |
---|
| 4843 | break; |
---|
| 4844 | } // end switch r_vci_cmd_fsm |
---|
| 4845 | |
---|
| 4846 | ////////////////////////////////////////////////////////// |
---|
| 4847 | // VCI initiator response on the direct network |
---|
| 4848 | // it depends on the VCI RSP state |
---|
| 4849 | |
---|
| 4850 | switch (r_vci_rsp_fsm.read() ) |
---|
| 4851 | { |
---|
| 4852 | case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break; |
---|
| 4853 | case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
| 4854 | case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
| 4855 | case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
| 4856 | case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
| 4857 | case RSP_IDLE : p_vci_ini_d.rspack = false; break; |
---|
| 4858 | } // end switch r_vci_rsp_fsm |
---|
| 4859 | |
---|
| 4860 | //////////////////////////////////////////////////////////////// |
---|
| 4861 | // VCI target command and response on the coherence network |
---|
| 4862 | switch ( r_tgt_fsm.read() ) |
---|
| 4863 | { |
---|
| 4864 | case TGT_IDLE: |
---|
| 4865 | case TGT_UPDT_WORD: |
---|
| 4866 | case TGT_UPDT_DATA: |
---|
| 4867 | p_vci_tgt_c.cmdack = true; |
---|
| 4868 | p_vci_tgt_c.rspval = false; |
---|
| 4869 | break; |
---|
| 4870 | |
---|
| 4871 | case TGT_RSP_BROADCAST: |
---|
| 4872 | p_vci_tgt_c.cmdack = false; |
---|
| 4873 | p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() |
---|
| 4874 | and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ); |
---|
| 4875 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
| 4876 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
| 4877 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
| 4878 | p_vci_tgt_c.rdata = 0; |
---|
| 4879 | p_vci_tgt_c.rerror = 0; |
---|
| 4880 | p_vci_tgt_c.reop = true; |
---|
| 4881 | break; |
---|
| 4882 | |
---|
| 4883 | case TGT_RSP_ICACHE: |
---|
| 4884 | p_vci_tgt_c.cmdack = false; |
---|
| 4885 | p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read(); |
---|
| 4886 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
| 4887 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
| 4888 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
| 4889 | p_vci_tgt_c.rdata = 0; |
---|
| 4890 | p_vci_tgt_c.rerror = 0; |
---|
| 4891 | p_vci_tgt_c.reop = true; |
---|
| 4892 | break; |
---|
| 4893 | |
---|
| 4894 | case TGT_RSP_DCACHE: |
---|
| 4895 | p_vci_tgt_c.cmdack = false; |
---|
| 4896 | p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read(); |
---|
| 4897 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
| 4898 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
| 4899 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
| 4900 | p_vci_tgt_c.rdata = 0; |
---|
| 4901 | p_vci_tgt_c.rerror = 0; |
---|
| 4902 | p_vci_tgt_c.reop = true; |
---|
| 4903 | break; |
---|
| 4904 | |
---|
| 4905 | case TGT_REQ_BROADCAST: |
---|
| 4906 | case TGT_REQ_ICACHE: |
---|
| 4907 | case TGT_REQ_DCACHE: |
---|
| 4908 | p_vci_tgt_c.cmdack = false; |
---|
| 4909 | p_vci_tgt_c.rspval = false; |
---|
| 4910 | break; |
---|
| 4911 | |
---|
| 4912 | } // end switch TGT_FSM |
---|
| 4913 | } // end genMoore |
---|
| 4914 | |
---|
| 4915 | }} |
---|
| 4916 | |
---|
| 4917 | // Local Variables: |
---|
| 4918 | // tab-width: 4 |
---|
| 4919 | // c-basic-offset: 4 |
---|
| 4920 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 4921 | // indent-tabs-mode: nil |
---|
| 4922 | // End: |
---|
| 4923 | |
---|
| 4924 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 4925 | |
---|
| 4926 | |
---|
| 4927 | |
---|
| 4928 | |
---|
| 4929 | |
---|
| 4930 | |
---|
| 4931 | |
---|
| 4932 | |
---|
| 4933 | |
---|
| 4934 | |
---|