[183] | 1 | /* -*- c++ -*-C |
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| 2 | * File : vci_cc_vcache_wrapper_v4.cpp |
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| 3 | * Copyright (c) UPMC, Lip6, SoC |
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| 4 | * Authors : Alain GREINER, Yang GAO |
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| 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 7 | * |
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| 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 9 | * |
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| 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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| 13 | * |
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| 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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| 23 | * |
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| 24 | * SOCLIB_LGPL_HEADER_END |
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| 25 | */ |
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| 26 | |
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| 27 | #include <cassert> |
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| 28 | #include "arithmetics.h" |
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| 29 | #include "../include/vci_cc_vcache_wrapper_v4.h" |
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| 30 | |
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| 31 | #define DEBUG_DCACHE 1 |
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| 32 | #define DEBUG_ICACHE 1 |
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| 33 | #define DEBUG_CLEANUP 0 |
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| 34 | |
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| 35 | namespace soclib { |
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| 36 | namespace caba { |
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| 37 | |
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| 38 | namespace { |
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| 39 | const char *icache_fsm_state_str[] = { |
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| 40 | "ICACHE_IDLE", |
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| 41 | |
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| 42 | "ICACHE_XTN_TLB_FLUSH", |
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| 43 | "ICACHE_XTN_CACHE_FLUSH", |
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| 44 | "ICACHE_XTN_TLB_INVAL", |
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| 45 | "ICACHE_XTN_CACHE_INVAL_VA", |
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| 46 | "ICACHE_XTN_CACHE_INVAL_PA", |
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| 47 | "ICACHE_XTN_CACHE_INVAL_GO", |
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| 48 | |
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| 49 | "ICACHE_TLB_WAIT", |
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| 50 | |
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| 51 | "ICACHE_MISS_VICTIM", |
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| 52 | "ICACHE_MISS_INVAL", |
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| 53 | "ICACHE_MISS_WAIT", |
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| 54 | "ICACHE_MISS_UPDT", |
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| 55 | |
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| 56 | "ICACHE_UNC_WAIT", |
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| 57 | |
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| 58 | "ICACHE_CC_CHECK", |
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| 59 | "ICACHE_CC_INVAL", |
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| 60 | "ICACHE_CC_UPDT", |
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| 61 | |
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| 62 | }; |
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| 63 | const char *dcache_fsm_state_str[] = { |
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| 64 | "DCACHE_IDLE", |
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| 65 | |
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| 66 | "DCACHE_TLB_MISS", |
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| 67 | "DCACHE_TLB_PTE1_GET", |
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| 68 | "DCACHE_TLB_PTE1_SELECT", |
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| 69 | "DCACHE_TLB_PTE1_UPDT", |
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| 70 | "DCACHE_TLB_PTE2_GET", |
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| 71 | "DCACHE_TLB_PTE2_SELECT", |
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| 72 | "DCACHE_TLB_PTE2_UPDT", |
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[205] | 73 | "DCACHE_TLB_LR_UPDT", |
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| 74 | "DCACHE_TLB_LR_WAIT", |
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[183] | 75 | "DCACHE_TLB_RETURN", |
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| 76 | |
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| 77 | "DCACHE_XTN_SWITCH", |
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| 78 | "DCACHE_XTN_SYNC", |
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| 79 | "DCACHE_XTN_IC_INVAL_VA", |
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| 80 | "DCACHE_XTN_IC_FLUSH", |
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| 81 | "DCACHE_XTN_IC_INVAL_PA", |
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| 82 | "DCACHE_XTN_IT_INVAL", |
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| 83 | "DCACHE_XTN_DC_FLUSH", |
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| 84 | "DCACHE_XTN_DC_INVAL_VA", |
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| 85 | "DCACHE_XTN_DC_INVAL_PA", |
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[204] | 86 | "DCACHE_XTN_DC_INVAL_END", |
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[183] | 87 | "DCACHE_XTN_DC_INVAL_GO", |
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| 88 | "DCACHE_XTN_DT_INVAL", |
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| 89 | |
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[206] | 90 | "DCACHE_DIRTY_PTE_GET", |
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[205] | 91 | "DCACHE_DIRTY_SC_WAIT", |
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[183] | 92 | |
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| 93 | "DCACHE_MISS_VICTIM", |
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| 94 | "DCACHE_MISS_INVAL", |
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| 95 | "DCACHE_MISS_WAIT", |
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| 96 | "DCACHE_MISS_UPDT", |
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| 97 | |
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| 98 | "DCACHE_UNC_WAIT", |
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[205] | 99 | "DCACHE_SC_WAIT", |
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[183] | 100 | |
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| 101 | "DCACHE_CC_CHECK", |
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| 102 | "DCACHE_CC_INVAL", |
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| 103 | "DCACHE_CC_UPDT", |
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[204] | 104 | |
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| 105 | "DCACHE_INVAL_TLB_SCAN", |
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[183] | 106 | }; |
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| 107 | const char *cmd_fsm_state_str[] = { |
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| 108 | "CMD_IDLE", |
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| 109 | "CMD_INS_MISS", |
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| 110 | "CMD_INS_UNC", |
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| 111 | "CMD_DATA_MISS", |
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| 112 | "CMD_DATA_UNC", |
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| 113 | "CMD_DATA_WRITE", |
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| 114 | "CMD_DATA_SC", |
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| 115 | }; |
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| 116 | const char *rsp_fsm_state_str[] = { |
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| 117 | "RSP_IDLE", |
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| 118 | "RSP_INS_MISS", |
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| 119 | "RSP_INS_UNC", |
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| 120 | "RSP_DATA_MISS", |
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| 121 | "RSP_DATA_UNC", |
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| 122 | "RSP_DATA_WRITE", |
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| 123 | }; |
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| 124 | const char *cleanup_fsm_state_str[] = { |
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| 125 | "CLEANUP_DATA_IDLE", |
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| 126 | "CLEANUP_DATA_GO", |
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| 127 | "CLEANUP_INS_IDLE", |
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| 128 | "CLEANUP_INS_GO", |
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| 129 | }; |
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| 130 | const char *tgt_fsm_state_str[] = { |
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| 131 | "TGT_IDLE", |
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| 132 | "TGT_UPDT_WORD", |
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| 133 | "TGT_UPDT_DATA", |
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| 134 | "TGT_REQ_BROADCAST", |
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| 135 | "TGT_REQ_ICACHE", |
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| 136 | "TGT_REQ_DCACHE", |
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| 137 | "TGT_RSP_BROADCAST", |
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| 138 | "TGT_RSP_ICACHE", |
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| 139 | "TGT_RSP_DCACHE", |
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| 140 | }; |
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| 141 | } |
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| 142 | |
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| 143 | #define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t> |
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| 144 | |
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| 145 | using soclib::common::uint32_log2; |
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| 146 | |
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| 147 | ///////////////////////////////// |
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| 148 | tmpl(/**/)::VciCcVCacheWrapperV4( |
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| 149 | sc_module_name name, |
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| 150 | int proc_id, |
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| 151 | const soclib::common::MappingTable &mtp, |
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| 152 | const soclib::common::MappingTable &mtc, |
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| 153 | const soclib::common::IntTab &initiator_index_d, |
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| 154 | const soclib::common::IntTab &initiator_index_c, |
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| 155 | const soclib::common::IntTab &target_index_d, |
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| 156 | size_t itlb_ways, |
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| 157 | size_t itlb_sets, |
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| 158 | size_t dtlb_ways, |
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| 159 | size_t dtlb_sets, |
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| 160 | size_t icache_ways, |
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| 161 | size_t icache_sets, |
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| 162 | size_t icache_words, |
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| 163 | size_t dcache_ways, |
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| 164 | size_t dcache_sets, |
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| 165 | size_t dcache_words, |
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| 166 | size_t wbuf_nlines, |
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| 167 | size_t wbuf_nwords, |
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| 168 | uint32_t max_frozen_cycles, |
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| 169 | uint32_t debug_start_cycle, |
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| 170 | bool debug_ok) |
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| 171 | : soclib::caba::BaseModule(name), |
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| 172 | |
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| 173 | p_clk("clk"), |
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| 174 | p_resetn("resetn"), |
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| 175 | p_vci_ini_d("vci_ini_d"), |
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| 176 | p_vci_ini_c("vci_ini_c"), |
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| 177 | p_vci_tgt_c("vci_tgt_d"), |
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| 178 | |
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| 179 | m_cacheability_table(mtp.getCacheabilityTable()), |
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| 180 | m_segment(mtc.getSegment(target_index_d)), |
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| 181 | m_srcid_d(mtp.indexForId(initiator_index_d)), |
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| 182 | m_srcid_c(mtp.indexForId(initiator_index_c)), |
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| 183 | |
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| 184 | m_itlb_ways(itlb_ways), |
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| 185 | m_itlb_sets(itlb_sets), |
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| 186 | |
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| 187 | m_dtlb_ways(dtlb_ways), |
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| 188 | m_dtlb_sets(dtlb_sets), |
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| 189 | |
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| 190 | m_icache_ways(icache_ways), |
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| 191 | m_icache_sets(icache_sets), |
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| 192 | m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)), |
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| 193 | m_icache_words(icache_words), |
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| 194 | |
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| 195 | m_dcache_ways(dcache_ways), |
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| 196 | m_dcache_sets(dcache_sets), |
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| 197 | m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)), |
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| 198 | m_dcache_words(dcache_words), |
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| 199 | |
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[201] | 200 | m_proc_id(proc_id), |
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| 201 | |
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[183] | 202 | m_max_frozen_cycles(max_frozen_cycles), |
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| 203 | |
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| 204 | m_paddr_nbits(vci_param::N), |
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| 205 | |
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| 206 | m_debug_start_cycle(debug_start_cycle), |
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| 207 | m_debug_ok(debug_ok), |
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| 208 | |
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| 209 | r_mmu_ptpr("r_mmu_ptpr"), |
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| 210 | r_mmu_mode("r_mmu_mode"), |
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| 211 | r_mmu_word_lo("r_mmu_word_lo"), |
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| 212 | r_mmu_word_hi("r_mmu_word_hi"), |
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| 213 | r_mmu_ibvar("r_mmu_ibvar"), |
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| 214 | r_mmu_dbvar("r_mmu_dbvar"), |
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| 215 | r_mmu_ietr("r_mmu_ietr"), |
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| 216 | r_mmu_detr("r_mmu_detr"), |
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| 217 | |
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| 218 | r_icache_fsm("r_icache_fsm"), |
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| 219 | r_icache_fsm_save("r_icache_fsm_save"), |
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[217] | 220 | |
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[183] | 221 | r_icache_vci_paddr("r_icache_vci_paddr"), |
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| 222 | r_icache_vaddr_save("r_icache_vaddr_save"), |
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| 223 | |
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| 224 | r_icache_miss_way("r_icache_miss_way"), |
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| 225 | r_icache_miss_set("r_icache_miss_set"), |
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| 226 | r_icache_miss_word("r_icache_miss_word"), |
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| 227 | r_icache_miss_inval("r_icache_miss_inval"), |
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| 228 | |
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| 229 | r_icache_cc_way("r_icache_cc_way"), |
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| 230 | r_icache_cc_set("r_icache_cc_set"), |
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| 231 | r_icache_cc_word("r_icache_cc_word"), |
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| 232 | |
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| 233 | r_icache_flush_count("r_icache_flush_count"), |
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| 234 | |
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| 235 | r_icache_miss_req("r_icache_miss_req"), |
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| 236 | r_icache_unc_req("r_icache_unc_req"), |
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| 237 | |
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| 238 | r_icache_tlb_miss_req("r_icache_tlb_read_req"), |
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| 239 | r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), |
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| 240 | |
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| 241 | r_icache_cleanup_req("r_icache_cleanup_req"), |
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| 242 | r_icache_cleanup_line("r_icache_cleanup_line"), |
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| 243 | |
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| 244 | r_dcache_fsm("r_dcache_fsm"), |
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[217] | 245 | r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"), |
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| 246 | r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), |
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[183] | 247 | |
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| 248 | r_dcache_p0_valid("r_dcache_p0_valid"), |
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| 249 | r_dcache_p0_vaddr("r_dcache_p0_vaddr"), |
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| 250 | r_dcache_p0_wdata("r_dcache_p0_wdata"), |
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| 251 | r_dcache_p0_be("r_dcache_p0_be"), |
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| 252 | r_dcache_p0_paddr("r_dcache_p0_paddr"), |
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| 253 | r_dcache_p0_cacheable("r_dcache_p0_cacheable"), |
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| 254 | |
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| 255 | r_dcache_p1_valid("r_dcache_p1_valid"), |
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| 256 | r_dcache_p1_wdata("r_dcache_p1_wdata"), |
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| 257 | r_dcache_p1_be("r_dcache_p1_be"), |
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| 258 | r_dcache_p1_paddr("r_dcache_p1_paddr"), |
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| 259 | r_dcache_p1_cache_way("r_dcache_p1_cache_way"), |
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| 260 | r_dcache_p1_cache_set("r_dcache_p1_cache_set"), |
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| 261 | r_dcache_p1_cache_word("r_dcache_p1_word_save"), |
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| 262 | |
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[206] | 263 | r_dcache_dirty_paddr("r_dcache_dirty_paddr"), |
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| 264 | r_dcache_dirty_way("r_dcache_dirty_way"), |
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| 265 | r_dcache_dirty_set("r_dcache_dirty_set"), |
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[183] | 266 | |
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| 267 | r_dcache_vci_paddr("r_dcache_vci_paddr"), |
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| 268 | r_dcache_vci_miss_req("r_dcache_vci_miss_req"), |
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| 269 | r_dcache_vci_unc_req("r_dcache_vci_unc_req"), |
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| 270 | r_dcache_vci_unc_be("r_dcache_vci_unc_be"), |
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| 271 | r_dcache_vci_sc_req("r_dcache_vci_sc_req"), |
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| 272 | r_dcache_vci_sc_old("r_dcache_vci_sc_old"), |
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| 273 | r_dcache_vci_sc_new("r_dcache_vci_sc_new"), |
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| 274 | |
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| 275 | r_dcache_xtn_way("r_dcache_xtn_way"), |
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| 276 | r_dcache_xtn_set("r_dcache_xtn_set"), |
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| 277 | |
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| 278 | r_dcache_pending_unc_write("r_dcache_pending_unc_write"), |
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| 279 | |
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| 280 | r_dcache_miss_type("r_dcache_miss_type"), |
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| 281 | r_dcache_miss_word("r_dcache_miss_word"), |
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| 282 | r_dcache_miss_way("r_dcache_miss_way"), |
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| 283 | r_dcache_miss_set("r_dcache_miss_set"), |
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| 284 | r_dcache_miss_inval("r_dcache_miss_inval"), |
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| 285 | |
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| 286 | r_dcache_cc_way("r_dcache_cc_way"), |
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| 287 | r_dcache_cc_set("r_dcache_cc_set"), |
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| 288 | r_dcache_cc_word("r_dcache_cc_word"), |
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| 289 | |
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| 290 | r_dcache_flush_count("r_dcache_flush_count"), |
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| 291 | |
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| 292 | r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"), |
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| 293 | r_dcache_tlb_ins("r_dcache_tlb_ins"), |
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| 294 | r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), |
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| 295 | r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), |
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| 296 | r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), |
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| 297 | r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), |
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| 298 | r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), |
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| 299 | r_dcache_tlb_way("r_dcache_tlb_way"), |
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| 300 | r_dcache_tlb_set("r_dcache_tlb_set"), |
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| 301 | |
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| 302 | r_dcache_ll_valid("r_dcache_ll_valid"), |
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| 303 | r_dcache_ll_data("r_dcache_ll_data"), |
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| 304 | r_dcache_ll_vaddr("r_dcache_ll_vaddr"), |
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| 305 | |
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| 306 | r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"), |
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[204] | 307 | r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"), |
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[183] | 308 | |
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| 309 | r_dcache_xtn_req("r_dcache_xtn_req"), |
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| 310 | r_dcache_xtn_opcode("r_dcache_xtn_opcode"), |
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| 311 | |
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| 312 | r_dcache_cleanup_req("r_dcache_cleanup_req"), |
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| 313 | r_dcache_cleanup_line("r_dcache_cleanup_line"), |
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| 314 | |
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| 315 | r_vci_cmd_fsm("r_vci_cmd_fsm"), |
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| 316 | r_vci_cmd_min("r_vci_cmd_min"), |
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| 317 | r_vci_cmd_max("r_vci_cmd_max"), |
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| 318 | r_vci_cmd_cpt("r_vci_cmd_cpt"), |
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| 319 | r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"), |
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| 320 | |
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| 321 | r_vci_rsp_fsm("r_vci_rsp_fsm"), |
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| 322 | r_vci_rsp_cpt("r_vci_rsp_cpt"), |
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| 323 | r_vci_rsp_ins_error("r_vci_rsp_ins_error"), |
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| 324 | r_vci_rsp_data_error("r_vci_rsp_data_error"), |
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| 325 | r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth |
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| 326 | r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth |
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| 327 | |
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| 328 | r_cleanup_fsm("r_cleanup_fsm"), |
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| 329 | r_cleanup_trdid("r_cleanup_trdid"), |
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| 330 | r_cleanup_buffer(4), // up to 4 simultaneous cleanups |
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| 331 | |
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| 332 | r_tgt_fsm("r_tgt_fsm"), |
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| 333 | r_tgt_paddr("r_tgt_paddr"), |
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| 334 | r_tgt_word_count("r_tgt_word_count"), |
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| 335 | r_tgt_word_min("r_tgt_word_min"), |
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| 336 | r_tgt_word_max("r_tgt_word_max"), |
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| 337 | r_tgt_update("r_tgt_update"), |
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| 338 | r_tgt_update_data("r_tgt_update_data"), |
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| 339 | r_tgt_srcid("r_tgt_srcid"), |
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| 340 | r_tgt_pktid("r_tgt_pktid"), |
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| 341 | r_tgt_trdid("r_tgt_trdid"), |
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| 342 | |
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| 343 | r_tgt_icache_req("r_tgt_icache_req"), |
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| 344 | r_tgt_dcache_req("r_tgt_dcache_req"), |
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| 345 | r_tgt_icache_rsp("r_tgt_icache_rsp"), |
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| 346 | r_tgt_dcache_rsp("r_tgt_dcache_rsp"), |
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| 347 | |
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| 348 | r_iss(this->name(), proc_id), |
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| 349 | r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ), |
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| 350 | r_icache("icache", icache_ways, icache_sets, icache_words), |
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| 351 | r_dcache("dcache", dcache_ways, dcache_sets, dcache_words), |
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[202] | 352 | r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N), |
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| 353 | r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N) |
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[183] | 354 | { |
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| 355 | assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and |
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| 356 | "Need more PLEN bits."); |
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| 357 | |
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| 358 | assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and |
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| 359 | "Need more TRDID bits."); |
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| 360 | |
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| 361 | assert( (icache_words == dcache_words) and |
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| 362 | "icache_words and dcache_words parameters must be equal"); |
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| 363 | |
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[204] | 364 | assert( (itlb_sets == dtlb_sets) and |
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| 365 | "itlb_sets and dtlb_sets parameters must be etqual"); |
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| 366 | |
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| 367 | assert( (itlb_ways == dtlb_ways) and |
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| 368 | "itlb_ways and dtlb_ways parameters must be etqual"); |
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| 369 | |
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[198] | 370 | r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | |
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| 371 | (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | |
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| 372 | (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | |
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| 373 | (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | |
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| 374 | (uint32_log2(m_icache_words<<2)); |
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[183] | 375 | |
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[198] | 376 | r_mmu_release = (uint32_t)(1 << 16) | 0x1; |
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[183] | 377 | |
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[206] | 378 | r_tgt_buf = new uint32_t[dcache_words]; |
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| 379 | r_tgt_be = new vci_be_t[dcache_words]; |
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| 380 | r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; |
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| 381 | r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; |
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[183] | 382 | |
---|
| 383 | SC_METHOD(transition); |
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| 384 | dont_initialize(); |
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| 385 | sensitive << p_clk.pos(); |
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| 386 | |
---|
| 387 | SC_METHOD(genMoore); |
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| 388 | dont_initialize(); |
---|
| 389 | sensitive << p_clk.neg(); |
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| 390 | |
---|
| 391 | typename iss_t::CacheInfo cache_info; |
---|
| 392 | cache_info.has_mmu = true; |
---|
| 393 | cache_info.icache_line_size = icache_words*sizeof(uint32_t); |
---|
| 394 | cache_info.icache_assoc = icache_ways; |
---|
| 395 | cache_info.icache_n_lines = icache_sets; |
---|
| 396 | cache_info.dcache_line_size = dcache_words*sizeof(uint32_t); |
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| 397 | cache_info.dcache_assoc = dcache_ways; |
---|
| 398 | cache_info.dcache_n_lines = dcache_sets; |
---|
| 399 | r_iss.setCacheInfo(cache_info); |
---|
| 400 | } |
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| 401 | |
---|
| 402 | ///////////////////////////////////// |
---|
| 403 | tmpl(/**/)::~VciCcVCacheWrapperV4() |
---|
| 404 | ///////////////////////////////////// |
---|
| 405 | { |
---|
| 406 | delete [] r_tgt_be; |
---|
| 407 | delete [] r_tgt_buf; |
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[206] | 408 | delete [] r_dcache_in_tlb; |
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| 409 | delete [] r_dcache_contains_ptd; |
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[183] | 410 | } |
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| 411 | |
---|
| 412 | //////////////////////// |
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| 413 | tmpl(void)::print_cpi() |
---|
| 414 | //////////////////////// |
---|
| 415 | { |
---|
| 416 | std::cout << name() << " CPI = " |
---|
| 417 | << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ; |
---|
| 418 | } |
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| 419 | |
---|
| 420 | //////////////////////////////////// |
---|
| 421 | tmpl(void)::print_trace(size_t mode) |
---|
| 422 | //////////////////////////////////// |
---|
| 423 | { |
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[205] | 424 | // b0 : write buffer trace |
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[183] | 425 | // b1 : write buffer verbose |
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[205] | 426 | // b2 : dcache trace |
---|
| 427 | // b3 : icache trace |
---|
| 428 | // b4 : dtlb trace |
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| 429 | // b5 : itlb trace |
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[183] | 430 | |
---|
| 431 | std::cout << std::dec << "PROC " << name() << std::endl; |
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| 432 | |
---|
[205] | 433 | std::cout << " " << m_ireq << std::endl; |
---|
| 434 | std::cout << " " << m_irsp << std::endl; |
---|
| 435 | std::cout << " " << m_dreq << std::endl; |
---|
| 436 | std::cout << " " << m_drsp << std::endl; |
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[183] | 437 | |
---|
| 438 | std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] |
---|
| 439 | << " | " << dcache_fsm_state_str[r_dcache_fsm.read()] |
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| 440 | << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()] |
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| 441 | << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] |
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[204] | 442 | << " | " << tgt_fsm_state_str[r_tgt_fsm.read()] |
---|
| 443 | << " | " << cleanup_fsm_state_str[r_cleanup_fsm.read()]; |
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[183] | 444 | if (r_dcache_p0_valid.read() ) std::cout << " | P1_WRITE"; |
---|
| 445 | if (r_dcache_p1_valid.read() ) std::cout << " | P2_WRITE"; |
---|
| 446 | std::cout << std::endl; |
---|
| 447 | |
---|
[205] | 448 | if(mode & 0x01) |
---|
[183] | 449 | { |
---|
| 450 | r_wbuf.printTrace((mode>>1)&1); |
---|
| 451 | } |
---|
[205] | 452 | if(mode & 0x04) |
---|
[183] | 453 | { |
---|
[205] | 454 | std::cout << " Data Cache" << std::endl; |
---|
[183] | 455 | r_dcache.printTrace(); |
---|
| 456 | } |
---|
[205] | 457 | if(mode & 0x08) |
---|
[183] | 458 | { |
---|
[205] | 459 | std::cout << " Instruction Cache" << std::endl; |
---|
[183] | 460 | r_icache.printTrace(); |
---|
| 461 | } |
---|
[205] | 462 | if(mode & 0x10) |
---|
| 463 | { |
---|
| 464 | std::cout << " Data TLB" << std::endl; |
---|
| 465 | r_dtlb.printTrace(); |
---|
| 466 | } |
---|
| 467 | if(mode & 0x20) |
---|
| 468 | { |
---|
| 469 | std::cout << " Instruction TLB" << std::endl; |
---|
| 470 | r_itlb.printTrace(); |
---|
| 471 | } |
---|
[183] | 472 | } |
---|
| 473 | |
---|
| 474 | ////////////////////////////////////////// |
---|
| 475 | tmpl(void)::cache_monitor( paddr_t addr ) |
---|
| 476 | ////////////////////////////////////////// |
---|
| 477 | { |
---|
| 478 | size_t cache_way; |
---|
| 479 | size_t cache_set; |
---|
| 480 | size_t cache_word; |
---|
| 481 | uint32_t cache_rdata; |
---|
[210] | 482 | bool cache_hit = r_dcache.read_neutral( addr, |
---|
[183] | 483 | &cache_rdata, |
---|
| 484 | &cache_way, |
---|
| 485 | &cache_set, |
---|
| 486 | &cache_word ); |
---|
[211] | 487 | bool icache_hit = r_icache.read_neutral( addr, |
---|
| 488 | &cache_rdata, |
---|
| 489 | &cache_way, |
---|
| 490 | &cache_set, |
---|
| 491 | &cache_word ); |
---|
[183] | 492 | if ( cache_hit != m_debug_previous_hit ) |
---|
| 493 | { |
---|
| 494 | std::cout << "PROC " << name() |
---|
[211] | 495 | << " dcache change at cycle " << std::dec << m_cpt_total_cycles |
---|
[183] | 496 | << " for adresse " << std::hex << addr |
---|
| 497 | << " / HIT = " << cache_hit << std::endl; |
---|
[211] | 498 | m_debug_previous_hit = cache_hit; |
---|
[183] | 499 | } |
---|
[211] | 500 | if ( icache_hit != m_idebug_previous_hit ) |
---|
| 501 | { |
---|
| 502 | std::cout << "PROC " << name() |
---|
| 503 | << " icache change at cycle " << std::dec << m_cpt_total_cycles |
---|
| 504 | << " for adresse " << std::hex << addr |
---|
| 505 | << " / HIT = " << icache_hit << std::endl; |
---|
| 506 | m_idebug_previous_hit = icache_hit; |
---|
| 507 | } |
---|
[183] | 508 | } |
---|
| 509 | |
---|
[198] | 510 | /* |
---|
[183] | 511 | //////////////////////// |
---|
| 512 | tmpl(void)::print_stats() |
---|
| 513 | //////////////////////// |
---|
| 514 | { |
---|
| 515 | float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); |
---|
[198] | 516 | std::cout << name() << std::endl |
---|
| 517 | << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl |
---|
| 518 | << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl |
---|
| 519 | << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl |
---|
| 520 | << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl |
---|
| 521 | << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl |
---|
| 522 | << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl |
---|
| 523 | << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl |
---|
| 524 | << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl |
---|
| 525 | << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl |
---|
| 526 | << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl |
---|
| 527 | << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl |
---|
| 528 | << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl |
---|
| 529 | << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl |
---|
| 530 | << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl |
---|
| 531 | << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl |
---|
| 532 | << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl |
---|
| 533 | << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl |
---|
| 534 | << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl |
---|
| 535 | << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl |
---|
| 536 | << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl |
---|
| 537 | << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl |
---|
| 538 | << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl |
---|
| 539 | << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl |
---|
| 540 | << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl |
---|
| 541 | << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl |
---|
| 542 | << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl |
---|
| 543 | << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl |
---|
| 544 | << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl |
---|
| 545 | << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl |
---|
| 546 | << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl |
---|
| 547 | << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl |
---|
| 548 | << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl |
---|
| 549 | << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl |
---|
| 550 | << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl |
---|
| 551 | << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl |
---|
| 552 | << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl |
---|
| 553 | << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl |
---|
| 554 | << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl |
---|
| 555 | << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; |
---|
[183] | 556 | } |
---|
| 557 | |
---|
| 558 | //////////////////////// |
---|
| 559 | tmpl(void)::clear_stats() |
---|
| 560 | //////////////////////// |
---|
| 561 | { |
---|
| 562 | m_cpt_dcache_data_read = 0; |
---|
| 563 | m_cpt_dcache_data_write = 0; |
---|
| 564 | m_cpt_dcache_dir_read = 0; |
---|
| 565 | m_cpt_dcache_dir_write = 0; |
---|
| 566 | m_cpt_icache_data_read = 0; |
---|
| 567 | m_cpt_icache_data_write = 0; |
---|
| 568 | m_cpt_icache_dir_read = 0; |
---|
| 569 | m_cpt_icache_dir_write = 0; |
---|
| 570 | |
---|
| 571 | m_cpt_frz_cycles = 0; |
---|
| 572 | m_cpt_dcache_frz_cycles = 0; |
---|
| 573 | m_cpt_total_cycles = 0; |
---|
| 574 | |
---|
[198] | 575 | m_cpt_read = 0; |
---|
| 576 | m_cpt_write = 0; |
---|
[183] | 577 | m_cpt_data_miss = 0; |
---|
| 578 | m_cpt_ins_miss = 0; |
---|
| 579 | m_cpt_unc_read = 0; |
---|
| 580 | m_cpt_write_cached = 0; |
---|
| 581 | m_cpt_ins_read = 0; |
---|
| 582 | |
---|
| 583 | m_cost_write_frz = 0; |
---|
| 584 | m_cost_data_miss_frz = 0; |
---|
| 585 | m_cost_unc_read_frz = 0; |
---|
| 586 | m_cost_ins_miss_frz = 0; |
---|
| 587 | |
---|
| 588 | m_cpt_imiss_transaction = 0; |
---|
| 589 | m_cpt_dmiss_transaction = 0; |
---|
| 590 | m_cpt_unc_transaction = 0; |
---|
| 591 | m_cpt_write_transaction = 0; |
---|
| 592 | m_cpt_icache_unc_transaction = 0; |
---|
| 593 | |
---|
| 594 | m_cost_imiss_transaction = 0; |
---|
| 595 | m_cost_dmiss_transaction = 0; |
---|
| 596 | m_cost_unc_transaction = 0; |
---|
| 597 | m_cost_write_transaction = 0; |
---|
| 598 | m_cost_icache_unc_transaction = 0; |
---|
| 599 | m_length_write_transaction = 0; |
---|
| 600 | |
---|
| 601 | m_cpt_ins_tlb_read = 0; |
---|
| 602 | m_cpt_ins_tlb_miss = 0; |
---|
| 603 | m_cpt_ins_tlb_update_acc = 0; |
---|
[198] | 604 | |
---|
[183] | 605 | m_cpt_data_tlb_read = 0; |
---|
| 606 | m_cpt_data_tlb_miss = 0; |
---|
| 607 | m_cpt_data_tlb_update_acc = 0; |
---|
| 608 | m_cpt_data_tlb_update_dirty = 0; |
---|
[198] | 609 | m_cpt_ins_tlb_hit_dcache = 0; |
---|
[183] | 610 | m_cpt_data_tlb_hit_dcache = 0; |
---|
[198] | 611 | m_cpt_ins_tlb_occup_cache = 0; |
---|
[183] | 612 | m_cpt_data_tlb_occup_cache = 0; |
---|
| 613 | |
---|
| 614 | m_cost_ins_tlb_miss_frz = 0; |
---|
| 615 | m_cost_data_tlb_miss_frz = 0; |
---|
| 616 | m_cost_ins_tlb_update_acc_frz = 0; |
---|
| 617 | m_cost_data_tlb_update_acc_frz = 0; |
---|
| 618 | m_cost_data_tlb_update_dirty_frz = 0; |
---|
| 619 | m_cost_ins_tlb_occup_cache_frz = 0; |
---|
| 620 | m_cost_data_tlb_occup_cache_frz = 0; |
---|
| 621 | |
---|
| 622 | m_cpt_itlbmiss_transaction = 0; |
---|
| 623 | m_cpt_itlb_ll_transaction = 0; |
---|
| 624 | m_cpt_itlb_sc_transaction = 0; |
---|
| 625 | m_cpt_dtlbmiss_transaction = 0; |
---|
| 626 | m_cpt_dtlb_ll_transaction = 0; |
---|
| 627 | m_cpt_dtlb_sc_transaction = 0; |
---|
| 628 | m_cpt_dtlb_ll_dirty_transaction = 0; |
---|
| 629 | m_cpt_dtlb_sc_dirty_transaction = 0; |
---|
| 630 | |
---|
| 631 | m_cost_itlbmiss_transaction = 0; |
---|
| 632 | m_cost_itlb_ll_transaction = 0; |
---|
| 633 | m_cost_itlb_sc_transaction = 0; |
---|
| 634 | m_cost_dtlbmiss_transaction = 0; |
---|
| 635 | m_cost_dtlb_ll_transaction = 0; |
---|
| 636 | m_cost_dtlb_sc_transaction = 0; |
---|
| 637 | m_cost_dtlb_ll_dirty_transaction = 0; |
---|
| 638 | m_cost_dtlb_sc_dirty_transaction = 0; |
---|
| 639 | |
---|
[198] | 640 | m_cpt_cc_update_data = 0; |
---|
| 641 | m_cpt_cc_inval_ins = 0; |
---|
| 642 | m_cpt_cc_inval_data = 0; |
---|
| 643 | m_cpt_cc_broadcast = 0; |
---|
[183] | 644 | |
---|
| 645 | m_cost_updt_data_frz = 0; |
---|
| 646 | m_cost_inval_ins_frz = 0; |
---|
| 647 | m_cost_inval_data_frz = 0; |
---|
| 648 | m_cost_broadcast_frz = 0; |
---|
| 649 | |
---|
| 650 | m_cpt_cc_cleanup_data = 0; |
---|
| 651 | m_cpt_cc_cleanup_ins = 0; |
---|
| 652 | } |
---|
| 653 | |
---|
[198] | 654 | */ |
---|
[183] | 655 | |
---|
| 656 | ///////////////////////// |
---|
| 657 | tmpl(void)::transition() |
---|
| 658 | ///////////////////////// |
---|
| 659 | { |
---|
| 660 | if ( not p_resetn.read() ) |
---|
| 661 | { |
---|
| 662 | r_iss.reset(); |
---|
| 663 | r_wbuf.reset(); |
---|
| 664 | r_icache.reset(); |
---|
| 665 | r_dcache.reset(); |
---|
| 666 | r_itlb.reset(); |
---|
| 667 | r_dtlb.reset(); |
---|
| 668 | |
---|
| 669 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 670 | r_icache_fsm = ICACHE_IDLE; |
---|
| 671 | r_vci_cmd_fsm = CMD_IDLE; |
---|
| 672 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 673 | r_tgt_fsm = TGT_IDLE; |
---|
| 674 | r_cleanup_fsm = CLEANUP_DATA_IDLE; |
---|
| 675 | |
---|
[206] | 676 | // reset dcache directory extension |
---|
| 677 | for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) |
---|
| 678 | { |
---|
| 679 | r_dcache_in_tlb[i] = false; |
---|
| 680 | r_dcache_contains_ptd[i] = false; |
---|
| 681 | } |
---|
[183] | 682 | |
---|
| 683 | // Response FIFOs and cleanup buffer |
---|
| 684 | r_vci_rsp_fifo_icache.init(); |
---|
| 685 | r_vci_rsp_fifo_dcache.init(); |
---|
| 686 | r_cleanup_buffer.reset(); |
---|
| 687 | |
---|
| 688 | // ICACHE & DCACHE activated |
---|
| 689 | r_mmu_mode = 0x3; |
---|
| 690 | |
---|
[198] | 691 | // No request from ICACHE FSM to CMD FSM |
---|
[183] | 692 | r_icache_miss_req = false; |
---|
| 693 | r_icache_unc_req = false; |
---|
| 694 | |
---|
| 695 | // No request from ICACHE_FSM to DCACHE FSM |
---|
| 696 | r_icache_tlb_miss_req = false; |
---|
| 697 | |
---|
| 698 | // No request from ICACHE_FSM to CLEANUP FSMs |
---|
| 699 | r_icache_cleanup_req = false; |
---|
| 700 | |
---|
| 701 | // No pending write in pipeline |
---|
| 702 | r_dcache_p0_valid = false; |
---|
| 703 | r_dcache_p1_valid = false; |
---|
| 704 | |
---|
| 705 | // No request from DCACHE_FSM to CMD_FSM |
---|
| 706 | r_dcache_vci_miss_req = false; |
---|
| 707 | r_dcache_vci_unc_req = false; |
---|
| 708 | r_dcache_vci_sc_req = false; |
---|
| 709 | |
---|
| 710 | // No uncacheable write pending |
---|
| 711 | r_dcache_pending_unc_write = false; |
---|
| 712 | |
---|
| 713 | // No LL reservation |
---|
[198] | 714 | r_dcache_ll_valid = false; |
---|
[183] | 715 | |
---|
| 716 | // No processor XTN request pending |
---|
| 717 | r_dcache_xtn_req = false; |
---|
| 718 | |
---|
| 719 | // No request from DCACHE FSM to CLEANUP FSMs |
---|
| 720 | r_dcache_cleanup_req = false; |
---|
| 721 | |
---|
| 722 | // No request from TGT FSM to ICACHE/DCACHE FSMs |
---|
| 723 | r_tgt_icache_req = false; |
---|
| 724 | r_tgt_dcache_req = false; |
---|
| 725 | |
---|
| 726 | // No signalisation of a coherence request matching a pending miss |
---|
| 727 | r_icache_miss_inval = false; |
---|
| 728 | r_dcache_miss_inval = false; |
---|
| 729 | |
---|
| 730 | // No signalisation of errors |
---|
| 731 | r_vci_rsp_ins_error = false; |
---|
| 732 | r_vci_rsp_data_error = false; |
---|
| 733 | |
---|
| 734 | // Debug variables |
---|
| 735 | m_debug_previous_hit = false; |
---|
[211] | 736 | m_idebug_previous_hit = false; |
---|
[183] | 737 | m_debug_dcache_fsm = false; |
---|
| 738 | m_debug_icache_fsm = false; |
---|
| 739 | m_debug_cleanup_fsm = false; |
---|
| 740 | |
---|
[198] | 741 | // activity counters |
---|
| 742 | m_cpt_dcache_data_read = 0; |
---|
| 743 | m_cpt_dcache_data_write = 0; |
---|
| 744 | m_cpt_dcache_dir_read = 0; |
---|
| 745 | m_cpt_dcache_dir_write = 0; |
---|
| 746 | m_cpt_icache_data_read = 0; |
---|
| 747 | m_cpt_icache_data_write = 0; |
---|
| 748 | m_cpt_icache_dir_read = 0; |
---|
| 749 | m_cpt_icache_dir_write = 0; |
---|
[183] | 750 | |
---|
[198] | 751 | m_cpt_frz_cycles = 0; |
---|
| 752 | m_cpt_total_cycles = 0; |
---|
[209] | 753 | m_cpt_stop_simulation = 0; |
---|
[198] | 754 | |
---|
| 755 | m_cpt_data_miss = 0; |
---|
| 756 | m_cpt_ins_miss = 0; |
---|
| 757 | m_cpt_unc_read = 0; |
---|
| 758 | m_cpt_write_cached = 0; |
---|
| 759 | m_cpt_ins_read = 0; |
---|
| 760 | |
---|
| 761 | m_cost_write_frz = 0; |
---|
| 762 | m_cost_data_miss_frz = 0; |
---|
| 763 | m_cost_unc_read_frz = 0; |
---|
| 764 | m_cost_ins_miss_frz = 0; |
---|
| 765 | |
---|
| 766 | m_cpt_imiss_transaction = 0; |
---|
| 767 | m_cpt_dmiss_transaction = 0; |
---|
| 768 | m_cpt_unc_transaction = 0; |
---|
| 769 | m_cpt_write_transaction = 0; |
---|
| 770 | m_cpt_icache_unc_transaction = 0; |
---|
| 771 | |
---|
| 772 | m_cost_imiss_transaction = 0; |
---|
| 773 | m_cost_dmiss_transaction = 0; |
---|
| 774 | m_cost_unc_transaction = 0; |
---|
| 775 | m_cost_write_transaction = 0; |
---|
| 776 | m_cost_icache_unc_transaction = 0; |
---|
| 777 | m_length_write_transaction = 0; |
---|
| 778 | |
---|
| 779 | m_cpt_ins_tlb_read = 0; |
---|
| 780 | m_cpt_ins_tlb_miss = 0; |
---|
| 781 | m_cpt_ins_tlb_update_acc = 0; |
---|
| 782 | |
---|
| 783 | m_cpt_data_tlb_read = 0; |
---|
| 784 | m_cpt_data_tlb_miss = 0; |
---|
| 785 | m_cpt_data_tlb_update_acc = 0; |
---|
| 786 | m_cpt_data_tlb_update_dirty = 0; |
---|
| 787 | m_cpt_ins_tlb_hit_dcache = 0; |
---|
| 788 | m_cpt_data_tlb_hit_dcache = 0; |
---|
| 789 | m_cpt_ins_tlb_occup_cache = 0; |
---|
| 790 | m_cpt_data_tlb_occup_cache = 0; |
---|
| 791 | |
---|
| 792 | m_cost_ins_tlb_miss_frz = 0; |
---|
| 793 | m_cost_data_tlb_miss_frz = 0; |
---|
| 794 | m_cost_ins_tlb_update_acc_frz = 0; |
---|
| 795 | m_cost_data_tlb_update_acc_frz = 0; |
---|
| 796 | m_cost_data_tlb_update_dirty_frz = 0; |
---|
| 797 | m_cost_ins_tlb_occup_cache_frz = 0; |
---|
| 798 | m_cost_data_tlb_occup_cache_frz = 0; |
---|
| 799 | |
---|
| 800 | m_cpt_ins_tlb_inval = 0; |
---|
| 801 | m_cpt_data_tlb_inval = 0; |
---|
| 802 | m_cost_ins_tlb_inval_frz = 0; |
---|
| 803 | m_cost_data_tlb_inval_frz = 0; |
---|
| 804 | |
---|
| 805 | m_cpt_cc_broadcast = 0; |
---|
| 806 | |
---|
| 807 | m_cost_updt_data_frz = 0; |
---|
| 808 | m_cost_inval_ins_frz = 0; |
---|
| 809 | m_cost_inval_data_frz = 0; |
---|
| 810 | m_cost_broadcast_frz = 0; |
---|
| 811 | |
---|
| 812 | m_cpt_cc_cleanup_data = 0; |
---|
| 813 | m_cpt_cc_cleanup_ins = 0; |
---|
| 814 | |
---|
| 815 | m_cpt_itlbmiss_transaction = 0; |
---|
| 816 | m_cpt_itlb_ll_transaction = 0; |
---|
| 817 | m_cpt_itlb_sc_transaction = 0; |
---|
| 818 | m_cpt_dtlbmiss_transaction = 0; |
---|
| 819 | m_cpt_dtlb_ll_transaction = 0; |
---|
| 820 | m_cpt_dtlb_sc_transaction = 0; |
---|
| 821 | m_cpt_dtlb_ll_dirty_transaction = 0; |
---|
| 822 | m_cpt_dtlb_sc_dirty_transaction = 0; |
---|
| 823 | |
---|
| 824 | m_cost_itlbmiss_transaction = 0; |
---|
| 825 | m_cost_itlb_ll_transaction = 0; |
---|
| 826 | m_cost_itlb_sc_transaction = 0; |
---|
| 827 | m_cost_dtlbmiss_transaction = 0; |
---|
| 828 | m_cost_dtlb_ll_transaction = 0; |
---|
| 829 | m_cost_dtlb_sc_transaction = 0; |
---|
| 830 | m_cost_dtlb_ll_dirty_transaction = 0; |
---|
| 831 | m_cost_dtlb_sc_dirty_transaction = 0; |
---|
[209] | 832 | /* |
---|
| 833 | m_cpt_dcache_frz_cycles = 0; |
---|
| 834 | m_cpt_read = 0; |
---|
| 835 | m_cpt_write = 0; |
---|
| 836 | m_cpt_cc_update_data = 0; |
---|
| 837 | m_cpt_cc_inval_ins = 0; |
---|
| 838 | m_cpt_cc_inval_data = 0; |
---|
| 839 | */ |
---|
[198] | 840 | |
---|
[183] | 841 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; |
---|
| 842 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; |
---|
| 843 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0; |
---|
| 844 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0; |
---|
| 845 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0; |
---|
| 846 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0; |
---|
| 847 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0; |
---|
| 848 | |
---|
| 849 | return; |
---|
| 850 | } |
---|
| 851 | |
---|
| 852 | // Response FIFOs default values |
---|
| 853 | bool vci_rsp_fifo_icache_get = false; |
---|
| 854 | bool vci_rsp_fifo_icache_put = false; |
---|
| 855 | uint32_t vci_rsp_fifo_icache_data = 0; |
---|
| 856 | |
---|
| 857 | bool vci_rsp_fifo_dcache_get = false; |
---|
| 858 | bool vci_rsp_fifo_dcache_put = false; |
---|
| 859 | uint32_t vci_rsp_fifo_dcache_data = 0; |
---|
| 860 | |
---|
| 861 | #ifdef INSTRUMENTATION |
---|
| 862 | m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; |
---|
| 863 | m_cpt_fsm_icache [r_icache_fsm.read() ] ++; |
---|
| 864 | m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++; |
---|
| 865 | m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++; |
---|
| 866 | m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++; |
---|
| 867 | m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++; |
---|
| 868 | #endif |
---|
| 869 | |
---|
| 870 | m_cpt_total_cycles++; |
---|
| 871 | |
---|
| 872 | m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
| 873 | m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
| 874 | m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
| 875 | |
---|
| 876 | ///////////////////////////////////////////////////////////////////// |
---|
| 877 | // The TGT_FSM controls the following ressources: |
---|
| 878 | // - r_tgt_fsm |
---|
| 879 | // - r_tgt_buf[nwords] |
---|
| 880 | // - r_tgt_be[nwords] |
---|
| 881 | // - r_tgt_update |
---|
| 882 | // - r_tgt_word_min |
---|
| 883 | // - r_tgt_word_max |
---|
| 884 | // - r_tgt_word_count |
---|
| 885 | // - r_tgt_paddr |
---|
| 886 | // - r_tgt_srcid |
---|
| 887 | // - r_tgt_trdid |
---|
| 888 | // - r_tgt_pktid |
---|
| 889 | // - r_tgt_icache_req (set) |
---|
| 890 | // - r_tgt_dcache_req (set) |
---|
| 891 | // |
---|
| 892 | // All VCI commands must be CMD_WRITE. |
---|
| 893 | // - If the 2 LSB bits of the VCI address are 11, it is a broadcast request. |
---|
| 894 | // It is a multicast request otherwise. |
---|
| 895 | // - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS |
---|
| 896 | // (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes |
---|
| 897 | // INVAL/UPDATE (0 for invalidate / 1 for UPDATE). |
---|
| 898 | // |
---|
| 899 | // For all types of coherence request, the line index (i.e. the Z & Y fields) |
---|
| 900 | // is coded on 34 bits, and is contained in the WDATA and BE fields |
---|
| 901 | // of the first VCI flit. |
---|
| 902 | // - for a multicast invalidate or for a broadcast invalidate request |
---|
| 903 | // the VCI packet length is 1 word. |
---|
| 904 | // - for an update request the VCI packet length is (n+2) words. |
---|
| 905 | // The WDATA field of the second VCI word contains the word index. |
---|
| 906 | // The WDATA field of the n following words contains the values. |
---|
| 907 | // - for all transaction types, the VCI response is one single word. |
---|
| 908 | // In case of errors in the VCI command packet, the simulation |
---|
| 909 | // is stopped with an error message. |
---|
| 910 | // |
---|
| 911 | // This FSM is NOT pipelined : It consumes a new coherence request |
---|
| 912 | // on the VCI port only when the previous request is completed. |
---|
| 913 | // |
---|
| 914 | // The VCI_TGT FSM stores the external request arguments in the |
---|
| 915 | // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req |
---|
| 916 | // and/or the r_tgt_dcache_req flip-flops to signal the coherence request |
---|
| 917 | // to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST |
---|
| 918 | // states. It waits the completion of the coherence request by polling the |
---|
| 919 | // r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST |
---|
| 920 | // states. These flip-flops are reset by the ICACHE and DCACHE FSMs. |
---|
| 921 | // These two FSMs signal if a VCI answer must be send by setting |
---|
| 922 | // the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops. |
---|
| 923 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 924 | |
---|
| 925 | switch( r_tgt_fsm.read() ) |
---|
| 926 | { |
---|
| 927 | ////////////// |
---|
| 928 | case TGT_IDLE: |
---|
| 929 | { |
---|
| 930 | if ( p_vci_tgt_c.cmdval.read() ) |
---|
| 931 | { |
---|
| 932 | paddr_t address = p_vci_tgt_c.address.read(); |
---|
| 933 | |
---|
| 934 | // command checking |
---|
| 935 | if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE) |
---|
| 936 | { |
---|
| 937 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 938 | std::cout << "the received VCI coherence command is not a write" << std::endl; |
---|
| 939 | exit(0); |
---|
| 940 | } |
---|
| 941 | |
---|
| 942 | // address checking |
---|
| 943 | if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) ) |
---|
| 944 | { |
---|
| 945 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 946 | std::cout << "out of segment VCI coherence command received" << std::endl; |
---|
| 947 | exit(0); |
---|
| 948 | } |
---|
| 949 | |
---|
| 950 | r_tgt_srcid = p_vci_tgt_c.srcid.read(); |
---|
| 951 | r_tgt_trdid = p_vci_tgt_c.trdid.read(); |
---|
| 952 | r_tgt_pktid = p_vci_tgt_c.pktid.read(); |
---|
| 953 | |
---|
[210] | 954 | if (sizeof(paddr_t) <= 32) { |
---|
| 955 | assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr"); |
---|
| 956 | r_tgt_paddr = |
---|
| 957 | (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; |
---|
| 958 | } else { |
---|
| 959 | r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 | |
---|
| 960 | (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; |
---|
| 961 | } |
---|
[183] | 962 | |
---|
| 963 | if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type |
---|
| 964 | { |
---|
| 965 | if ( not p_vci_tgt_c.eop.read() ) |
---|
| 966 | { |
---|
| 967 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 968 | std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl; |
---|
| 969 | exit(0); |
---|
| 970 | } |
---|
| 971 | r_tgt_update = false; |
---|
| 972 | r_tgt_fsm = TGT_REQ_BROADCAST; |
---|
| 973 | |
---|
| 974 | #ifdef INSTRUMENTATION |
---|
| 975 | m_cpt_cc_broadcast++; |
---|
| 976 | #endif |
---|
| 977 | } |
---|
| 978 | else // multi-update or multi-invalidate for data type |
---|
| 979 | { |
---|
| 980 | paddr_t cell = address - m_segment.baseAddress(); |
---|
| 981 | |
---|
| 982 | if (cell == 0) // invalidate data |
---|
| 983 | { |
---|
| 984 | if ( not p_vci_tgt_c.eop.read() ) |
---|
| 985 | { |
---|
| 986 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 987 | std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl; |
---|
| 988 | exit(0); |
---|
| 989 | } |
---|
| 990 | r_tgt_update = false; |
---|
| 991 | r_tgt_fsm = TGT_REQ_DCACHE; |
---|
| 992 | |
---|
| 993 | #ifdef INSTRUMENTATION |
---|
| 994 | m_cpt_cc_inval_dcache++; |
---|
| 995 | #endif |
---|
| 996 | } |
---|
| 997 | else if (cell == 4) // invalidate instruction |
---|
| 998 | { |
---|
| 999 | if ( not p_vci_tgt_c.eop.read() ) |
---|
| 1000 | { |
---|
| 1001 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1002 | std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl; |
---|
| 1003 | exit(0); |
---|
| 1004 | } |
---|
| 1005 | r_tgt_update = false; |
---|
| 1006 | r_tgt_fsm = TGT_REQ_ICACHE; |
---|
| 1007 | |
---|
| 1008 | #ifdef INSTRUMENTATION |
---|
| 1009 | m_cpt_cc_inval_icache++; |
---|
| 1010 | #endif |
---|
| 1011 | } |
---|
| 1012 | else if (cell == 8) // update data |
---|
| 1013 | { |
---|
| 1014 | if ( p_vci_tgt_c.eop.read() ) |
---|
| 1015 | { |
---|
| 1016 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1017 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
| 1018 | exit(0); |
---|
| 1019 | } |
---|
| 1020 | r_tgt_update = true; |
---|
| 1021 | r_tgt_update_data = true; |
---|
| 1022 | r_tgt_fsm = TGT_UPDT_WORD; |
---|
| 1023 | |
---|
| 1024 | #ifdef INSTRUMENTATION |
---|
| 1025 | m_cpt_cc_update_dcache++; |
---|
| 1026 | #endif |
---|
| 1027 | } |
---|
| 1028 | else // update instruction |
---|
| 1029 | { |
---|
| 1030 | if ( p_vci_tgt_c.eop.read() ) |
---|
| 1031 | { |
---|
| 1032 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1033 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
| 1034 | exit(0); |
---|
| 1035 | } |
---|
| 1036 | r_tgt_update = true; |
---|
| 1037 | r_tgt_update_data = false; |
---|
| 1038 | r_tgt_fsm = TGT_UPDT_WORD; |
---|
| 1039 | |
---|
| 1040 | #ifdef INSTRUMENTATION |
---|
| 1041 | m_cpt_cc_update_icache++; |
---|
| 1042 | #endif |
---|
| 1043 | } |
---|
| 1044 | } // end if multi |
---|
| 1045 | } // end if cmdval |
---|
| 1046 | break; |
---|
| 1047 | } |
---|
| 1048 | /////////////////// |
---|
| 1049 | case TGT_UPDT_WORD: // first word index acquisition |
---|
| 1050 | { |
---|
| 1051 | if (p_vci_tgt_c.cmdval.read()) |
---|
| 1052 | { |
---|
| 1053 | if ( p_vci_tgt_c.eop.read() ) |
---|
| 1054 | { |
---|
| 1055 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1056 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
| 1057 | exit(0); |
---|
| 1058 | } |
---|
| 1059 | for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false; |
---|
| 1060 | |
---|
| 1061 | r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index |
---|
| 1062 | r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index |
---|
| 1063 | r_tgt_fsm = TGT_UPDT_DATA; |
---|
| 1064 | } |
---|
| 1065 | break; |
---|
| 1066 | } |
---|
| 1067 | /////////////////// |
---|
| 1068 | case TGT_UPDT_DATA: |
---|
| 1069 | { |
---|
| 1070 | if (p_vci_tgt_c.cmdval.read()) |
---|
| 1071 | { |
---|
| 1072 | size_t word = r_tgt_word_count.read(); |
---|
| 1073 | if (word >= m_dcache_words) |
---|
| 1074 | { |
---|
| 1075 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
| 1076 | std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl; |
---|
| 1077 | exit(0); |
---|
| 1078 | } |
---|
| 1079 | r_tgt_buf[word] = p_vci_tgt_c.wdata.read(); |
---|
| 1080 | r_tgt_be[word] = p_vci_tgt_c.be.read(); |
---|
| 1081 | r_tgt_word_count = word + 1; |
---|
| 1082 | |
---|
| 1083 | if (p_vci_tgt_c.eop.read()) // last word |
---|
| 1084 | { |
---|
| 1085 | r_tgt_word_max = word; |
---|
| 1086 | if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE; |
---|
| 1087 | else r_tgt_fsm = TGT_REQ_ICACHE; |
---|
| 1088 | } |
---|
| 1089 | } |
---|
| 1090 | break; |
---|
| 1091 | } |
---|
| 1092 | /////////////////////// |
---|
| 1093 | case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs |
---|
| 1094 | { |
---|
| 1095 | if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) |
---|
| 1096 | { |
---|
| 1097 | r_tgt_fsm = TGT_RSP_BROADCAST; |
---|
| 1098 | r_tgt_icache_req = true; |
---|
| 1099 | r_tgt_dcache_req = true; |
---|
| 1100 | } |
---|
| 1101 | break; |
---|
| 1102 | } |
---|
| 1103 | ///////////////////// |
---|
| 1104 | case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending) |
---|
| 1105 | { |
---|
| 1106 | if ( not r_tgt_icache_req.read() ) |
---|
| 1107 | { |
---|
| 1108 | r_tgt_fsm = TGT_RSP_ICACHE; |
---|
| 1109 | r_tgt_icache_req = true; |
---|
| 1110 | } |
---|
| 1111 | break; |
---|
| 1112 | } |
---|
| 1113 | //////////////////// |
---|
| 1114 | case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending) |
---|
| 1115 | { |
---|
| 1116 | if ( not r_tgt_dcache_req.read() ) |
---|
| 1117 | { |
---|
| 1118 | r_tgt_fsm = TGT_RSP_DCACHE; |
---|
| 1119 | r_tgt_dcache_req = true; |
---|
| 1120 | } |
---|
| 1121 | break; |
---|
| 1122 | } |
---|
| 1123 | /////////////////////// |
---|
| 1124 | case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs |
---|
| 1125 | // no response when r_tgt_*cache_rsp is false |
---|
| 1126 | { |
---|
| 1127 | if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed |
---|
| 1128 | { |
---|
| 1129 | if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response |
---|
| 1130 | { |
---|
| 1131 | if ( p_vci_tgt_c.rspack.read() ) |
---|
| 1132 | { |
---|
| 1133 | // reset dcache first if activated |
---|
| 1134 | if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false; |
---|
| 1135 | else r_tgt_icache_rsp = false; |
---|
| 1136 | } |
---|
| 1137 | } |
---|
| 1138 | else |
---|
| 1139 | { |
---|
| 1140 | r_tgt_fsm = TGT_IDLE; |
---|
| 1141 | } |
---|
| 1142 | } |
---|
| 1143 | break; |
---|
| 1144 | } |
---|
| 1145 | //////////////////// |
---|
| 1146 | case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM |
---|
| 1147 | { |
---|
| 1148 | // no response when r_tgt_icache_rsp is false |
---|
| 1149 | if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() ) |
---|
| 1150 | { |
---|
| 1151 | r_tgt_fsm = TGT_IDLE; |
---|
| 1152 | r_tgt_icache_rsp = false; |
---|
| 1153 | } |
---|
| 1154 | break; |
---|
| 1155 | } |
---|
| 1156 | //////////////////// |
---|
| 1157 | case TGT_RSP_DCACHE: |
---|
| 1158 | { |
---|
| 1159 | // no response when r_tgt_dcache_rsp is false |
---|
| 1160 | if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() ) |
---|
| 1161 | { |
---|
| 1162 | r_tgt_fsm = TGT_IDLE; |
---|
| 1163 | r_tgt_dcache_rsp = false; |
---|
| 1164 | } |
---|
| 1165 | break; |
---|
| 1166 | } |
---|
| 1167 | } // end switch TGT_FSM |
---|
| 1168 | |
---|
| 1169 | ///////////////////////////////////////////////////////////////////// |
---|
| 1170 | // Get data and instruction requests from processor |
---|
| 1171 | /////////////////////////////////////////////////////////////////////// |
---|
| 1172 | |
---|
[205] | 1173 | r_iss.getRequests(m_ireq, m_dreq); |
---|
[183] | 1174 | |
---|
| 1175 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 1176 | // ICACHE_FSM |
---|
| 1177 | // |
---|
| 1178 | // There is 9 conditions to exit the IDLE state: |
---|
| 1179 | // One condition is a coherence request from TGT FSM : |
---|
| 1180 | // - Coherence operation => ICACHE_CC_CHEK |
---|
| 1181 | // Five configurations corresponding to XTN processor requests sent by DCACHE FSM : |
---|
[198] | 1182 | // - Flush TLB => ICACHE_XTN_TLB_FLUSH |
---|
| 1183 | // - Flush cache => ICACHE_XTN_CACHE_FLUSH |
---|
[183] | 1184 | // - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL |
---|
| 1185 | // - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@ |
---|
| 1186 | // - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA |
---|
| 1187 | // three configurations corresponding to instruction processor requests : |
---|
[198] | 1188 | // - tlb miss => ICACHE_TLB_WAIT |
---|
[183] | 1189 | // - cacheable read miss => ICACHE_MISS_VICTIM |
---|
| 1190 | // - uncacheable read miss => ICACHE_UNC_REQ |
---|
| 1191 | // |
---|
| 1192 | // In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM |
---|
| 1193 | // using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the |
---|
| 1194 | // transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM |
---|
| 1195 | // state to select a slot and request a VCI transaction to the CLEANUP FSM. |
---|
| 1196 | // It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM. |
---|
| 1197 | // The availability of the missing cache line is signaled by the response fifo, |
---|
| 1198 | // and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state. |
---|
| 1199 | // |
---|
| 1200 | // In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction |
---|
[196] | 1201 | // to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop |
---|
[183] | 1202 | // when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait |
---|
| 1203 | // the response from the RSP FSM, through the response fifo. The missing instruction |
---|
| 1204 | // is directly returned to processor in this state. |
---|
| 1205 | // |
---|
| 1206 | // In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb |
---|
| 1207 | // using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register, |
---|
| 1208 | // and goes to the ICACHE_TLB_WAIT state. |
---|
| 1209 | // The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until |
---|
| 1210 | // the update is completed, and reset r_icache_tlb_miss_req to signal the completion. |
---|
| 1211 | // |
---|
[196] | 1212 | // The DCACHE FSM signals XTN processor requests to ICACHE_FSM |
---|
| 1213 | // using the r_dcache_xtn_req flip-flop. |
---|
[183] | 1214 | // The request opcode and the address to be invalidated are transmitted |
---|
| 1215 | // in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively. |
---|
| 1216 | // The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation |
---|
| 1217 | // is completed. |
---|
| 1218 | // |
---|
| 1219 | // The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error |
---|
| 1220 | // in a cache miss or uncacheable read VCI transaction. Nothing is written |
---|
| 1221 | // in the response fifo. This flip-flop is reset by the ICACHE-FSM. |
---|
| 1222 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
| 1223 | |
---|
[206] | 1224 | // default value for m_irsp |
---|
| 1225 | m_irsp.valid = false; |
---|
| 1226 | m_irsp.error = false; |
---|
| 1227 | m_irsp.instruction = 0; |
---|
[183] | 1228 | |
---|
| 1229 | switch( r_icache_fsm.read() ) |
---|
| 1230 | { |
---|
| 1231 | ///////////////// |
---|
| 1232 | case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent |
---|
| 1233 | // by DCACHE FSM, and coherence requests with a fixed priority: |
---|
| 1234 | // coherence > XTN > instruction |
---|
| 1235 | // We access the itlb and dcache in parallel with the virtual address |
---|
| 1236 | // for itlb, and with a speculative physical address for icache, |
---|
| 1237 | // computed during the previous cycle. |
---|
[198] | 1238 | { |
---|
[183] | 1239 | // coherence request from the target FSM |
---|
| 1240 | if ( r_tgt_icache_req.read() ) |
---|
| 1241 | { |
---|
| 1242 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
| 1243 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1244 | break; |
---|
| 1245 | } |
---|
| 1246 | |
---|
| 1247 | // Decoding processor XTN requests sent by DCACHE FSM |
---|
| 1248 | // These request are not executed in this IDLE state, because |
---|
| 1249 | // they require access to icache or itlb, that are already accessed |
---|
| 1250 | if ( r_dcache_xtn_req.read() ) |
---|
| 1251 | { |
---|
| 1252 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) |
---|
| 1253 | { |
---|
| 1254 | r_icache_fsm = ICACHE_XTN_TLB_FLUSH; |
---|
| 1255 | break; |
---|
| 1256 | } |
---|
| 1257 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH) |
---|
| 1258 | { |
---|
| 1259 | r_icache_flush_count = 0; |
---|
| 1260 | r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; |
---|
| 1261 | break; |
---|
| 1262 | } |
---|
| 1263 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) |
---|
| 1264 | { |
---|
| 1265 | r_icache_fsm = ICACHE_XTN_TLB_INVAL; |
---|
| 1266 | break; |
---|
| 1267 | } |
---|
| 1268 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) |
---|
| 1269 | { |
---|
| 1270 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; |
---|
| 1271 | break; |
---|
| 1272 | } |
---|
| 1273 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) |
---|
| 1274 | { |
---|
[210] | 1275 | if (sizeof(paddr_t) <= 32) { |
---|
| 1276 | assert(r_mmu_word_hi.read() == 0 && |
---|
| 1277 | "high bits should be 0 for 32bit paddr"); |
---|
| 1278 | r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); |
---|
| 1279 | } else { |
---|
| 1280 | r_icache_vci_paddr = |
---|
| 1281 | (paddr_t)r_mmu_word_hi.read() << 32 | |
---|
| 1282 | (paddr_t)r_mmu_word_lo.read(); |
---|
| 1283 | } |
---|
[183] | 1284 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
| 1285 | break; |
---|
| 1286 | } |
---|
| 1287 | } // end if xtn_req |
---|
| 1288 | |
---|
| 1289 | // processor request |
---|
[205] | 1290 | if ( m_ireq.valid ) |
---|
[183] | 1291 | { |
---|
| 1292 | bool cacheable; |
---|
| 1293 | paddr_t paddr; |
---|
| 1294 | |
---|
| 1295 | // We register processor request |
---|
[205] | 1296 | r_icache_vaddr_save = m_ireq.addr; |
---|
[183] | 1297 | |
---|
| 1298 | // speculative icache access (if cache activated) |
---|
| 1299 | // we use the speculative PPN computed during the previous cycle |
---|
| 1300 | |
---|
| 1301 | uint32_t cache_inst = 0; |
---|
| 1302 | bool cache_hit = false; |
---|
| 1303 | |
---|
| 1304 | if ( r_mmu_mode.read() & INS_CACHE_MASK ) |
---|
| 1305 | { |
---|
| 1306 | paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) | |
---|
[205] | 1307 | ((paddr_t)m_ireq.addr & PAGE_K_MASK); |
---|
[183] | 1308 | |
---|
| 1309 | #ifdef INSTRUMENTATION |
---|
| 1310 | m_cpt_icache_data_read++; |
---|
| 1311 | m_cpt_icache_dir_read++; |
---|
| 1312 | #endif |
---|
| 1313 | cache_hit = r_icache.read( spc_paddr, |
---|
| 1314 | &cache_inst ); |
---|
| 1315 | } |
---|
| 1316 | |
---|
| 1317 | // systematic itlb access (if tlb activated) |
---|
| 1318 | // we use the virtual address |
---|
| 1319 | |
---|
| 1320 | paddr_t tlb_paddr; |
---|
| 1321 | pte_info_t tlb_flags; |
---|
| 1322 | size_t tlb_way; |
---|
| 1323 | size_t tlb_set; |
---|
| 1324 | paddr_t tlb_nline; |
---|
| 1325 | bool tlb_hit = false;; |
---|
| 1326 | |
---|
| 1327 | if ( r_mmu_mode.read() & INS_TLB_MASK ) |
---|
| 1328 | { |
---|
| 1329 | |
---|
| 1330 | #ifdef INSTRUMENTATION |
---|
| 1331 | m_cpt_itlb_read++; |
---|
| 1332 | #endif |
---|
[205] | 1333 | tlb_hit = r_itlb.translate( m_ireq.addr, |
---|
[183] | 1334 | &tlb_paddr, |
---|
| 1335 | &tlb_flags, |
---|
| 1336 | &tlb_nline, // unused |
---|
| 1337 | &tlb_way, // unused |
---|
| 1338 | &tlb_set ); // unused |
---|
| 1339 | } |
---|
| 1340 | |
---|
| 1341 | // We compute cacheability, physical address and check access rights: |
---|
| 1342 | // - If MMU activated : cacheability is defined by the C bit in the PTE, |
---|
| 1343 | // the physical address is obtained from the TLB, and the access rights are |
---|
| 1344 | // defined by the U and X bits in the PTE. |
---|
| 1345 | // - If MMU not activated : cacheability is defined by the segment table, |
---|
| 1346 | // the physical address is equal to the virtual address (identity mapping) |
---|
| 1347 | // and there is no access rights checking |
---|
| 1348 | |
---|
| 1349 | if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: |
---|
| 1350 | { |
---|
| 1351 | // cacheability |
---|
| 1352 | if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; |
---|
[205] | 1353 | else cacheable = m_cacheability_table[m_ireq.addr]; |
---|
[183] | 1354 | |
---|
| 1355 | // physical address |
---|
[205] | 1356 | paddr = (paddr_t)m_ireq.addr; |
---|
[183] | 1357 | } |
---|
| 1358 | else // itlb activated |
---|
| 1359 | { |
---|
| 1360 | if ( tlb_hit ) // tlb hit |
---|
| 1361 | { |
---|
| 1362 | // cacheability |
---|
| 1363 | if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; |
---|
| 1364 | else cacheable = tlb_flags.c; |
---|
| 1365 | |
---|
| 1366 | // physical address |
---|
| 1367 | paddr = tlb_paddr; |
---|
| 1368 | |
---|
| 1369 | // access rights checking |
---|
[205] | 1370 | if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) ) |
---|
[183] | 1371 | { |
---|
| 1372 | r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
[205] | 1373 | r_mmu_ibvar = m_ireq.addr; |
---|
| 1374 | m_irsp.valid = true; |
---|
| 1375 | m_irsp.error = true; |
---|
| 1376 | m_irsp.instruction = 0; |
---|
[183] | 1377 | break; |
---|
| 1378 | } |
---|
| 1379 | else if ( not tlb_flags.x ) |
---|
| 1380 | { |
---|
| 1381 | r_mmu_ietr = MMU_READ_EXEC_VIOLATION; |
---|
[205] | 1382 | r_mmu_ibvar = m_ireq.addr; |
---|
| 1383 | m_irsp.valid = true; |
---|
| 1384 | m_irsp.error = true; |
---|
| 1385 | m_irsp.instruction = 0; |
---|
[183] | 1386 | break; |
---|
| 1387 | } |
---|
| 1388 | } |
---|
| 1389 | // in case of TLB miss we send an itlb miss request to DCACHE FSM and break |
---|
| 1390 | else |
---|
| 1391 | { |
---|
| 1392 | |
---|
| 1393 | #ifdef INSTRUMENTATION |
---|
| 1394 | m_cpt_itlb_miss++; |
---|
| 1395 | #endif |
---|
| 1396 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
| 1397 | r_icache_tlb_miss_req = true; |
---|
| 1398 | break; |
---|
| 1399 | } |
---|
| 1400 | } // end if itlb activated |
---|
| 1401 | |
---|
| 1402 | // physical address registration (for next cycle) |
---|
| 1403 | r_icache_vci_paddr = paddr; |
---|
| 1404 | |
---|
[201] | 1405 | // We enter this section only in case of TLB hit: |
---|
| 1406 | // Finally, we get the instruction depending on cacheability, |
---|
| 1407 | // we send the response to processor, and compute next state |
---|
[183] | 1408 | if ( cacheable ) // cacheable read |
---|
| 1409 | { |
---|
[201] | 1410 | if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK) |
---|
| 1411 | != (paddr & ~PAGE_K_MASK) ) // speculative access KO |
---|
| 1412 | { |
---|
| 1413 | |
---|
| 1414 | #ifdef INSTRUMENTATION |
---|
| 1415 | m_cpt_icache_spc_miss++; |
---|
| 1416 | #endif |
---|
| 1417 | // we return an invalid response and stay in IDLE state |
---|
| 1418 | // the cache access will cost one extra cycle. |
---|
| 1419 | break; |
---|
| 1420 | } |
---|
| 1421 | |
---|
[183] | 1422 | if ( not cache_hit ) // cache miss |
---|
| 1423 | { |
---|
| 1424 | // in case of icache miss we send a request to CMD FSM, but we are |
---|
| 1425 | // blocked in IDLE state if the previous cleanup is not completed |
---|
| 1426 | if ( not r_icache_cleanup_req.read() ) |
---|
| 1427 | { |
---|
| 1428 | |
---|
| 1429 | #ifdef INSTRUMENTATION |
---|
| 1430 | m_cpt_icache_miss++; |
---|
| 1431 | #endif |
---|
| 1432 | r_icache_fsm = ICACHE_MISS_VICTIM; |
---|
| 1433 | r_icache_miss_req = true; |
---|
| 1434 | } |
---|
[201] | 1435 | break; |
---|
[183] | 1436 | } |
---|
| 1437 | else // cache hit |
---|
| 1438 | { |
---|
| 1439 | |
---|
| 1440 | #ifdef INSTRUMENTATION |
---|
| 1441 | m_cpt_ins_read++; |
---|
| 1442 | #endif |
---|
[205] | 1443 | m_irsp.valid = true; |
---|
| 1444 | m_irsp.instruction = cache_inst; |
---|
[183] | 1445 | } |
---|
| 1446 | } |
---|
| 1447 | else // non cacheable read |
---|
| 1448 | { |
---|
| 1449 | r_icache_unc_req = true; |
---|
| 1450 | r_icache_fsm = ICACHE_UNC_WAIT; |
---|
| 1451 | } |
---|
[205] | 1452 | } // end if m_ireq.valid |
---|
[183] | 1453 | break; |
---|
| 1454 | } |
---|
| 1455 | ///////////////////// |
---|
| 1456 | case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss |
---|
| 1457 | // the itlb is udated by the DCACHE FSM, as well as the |
---|
| 1458 | // r_mmu_ietr and r_mmu_ibvar registers in case of error. |
---|
| 1459 | // the itlb is not accessed by ICACHE FSM until DCACHE FSM |
---|
| 1460 | // reset the r_icache_tlb_miss_req flip-flop |
---|
| 1461 | // external coherence request are accepted in this state. |
---|
| 1462 | { |
---|
| 1463 | // external coherence request |
---|
| 1464 | if ( r_tgt_icache_req.read() ) |
---|
| 1465 | { |
---|
| 1466 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
| 1467 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1468 | break; |
---|
| 1469 | } |
---|
| 1470 | |
---|
[205] | 1471 | if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++; |
---|
[183] | 1472 | |
---|
| 1473 | // DCACHE FSM signals response by reseting the request flip-flop |
---|
| 1474 | if ( not r_icache_tlb_miss_req.read() ) |
---|
| 1475 | { |
---|
| 1476 | if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated |
---|
| 1477 | { |
---|
| 1478 | r_icache_tlb_rsp_error = false; |
---|
[205] | 1479 | m_irsp.error = true; |
---|
| 1480 | m_irsp.valid = true; |
---|
[183] | 1481 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1482 | } |
---|
| 1483 | else // tlb updated : return to IDLE state |
---|
| 1484 | { |
---|
| 1485 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1486 | } |
---|
| 1487 | } |
---|
| 1488 | break; |
---|
| 1489 | } |
---|
| 1490 | ////////////////////////// |
---|
| 1491 | case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries |
---|
| 1492 | { |
---|
| 1493 | r_itlb.flush(); |
---|
| 1494 | r_dcache_xtn_req = false; |
---|
| 1495 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1496 | break; |
---|
| 1497 | } |
---|
| 1498 | //////////////////////////// |
---|
| 1499 | case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using |
---|
| 1500 | // the r_icache_flush_count register as a slot counter. |
---|
| 1501 | // We loop in this state until all slots have been visited. |
---|
| 1502 | // A cleanup request is generated for each valid line |
---|
| 1503 | // and we are blocked until the previous cleanup is completed |
---|
| 1504 | { |
---|
| 1505 | if ( not r_icache_cleanup_req.read() ) |
---|
| 1506 | { |
---|
| 1507 | size_t way = r_icache_flush_count.read()/m_icache_sets; |
---|
| 1508 | size_t set = r_icache_flush_count.read()%m_icache_sets; |
---|
| 1509 | paddr_t nline; |
---|
| 1510 | bool cleanup_req = r_icache.inval( way, |
---|
| 1511 | set, |
---|
| 1512 | &nline ); |
---|
| 1513 | if ( cleanup_req ) |
---|
| 1514 | { |
---|
| 1515 | r_icache_cleanup_req = true; |
---|
| 1516 | r_icache_cleanup_line = nline; |
---|
| 1517 | } |
---|
| 1518 | r_icache_flush_count = r_icache_flush_count.read() + 1; |
---|
| 1519 | } |
---|
| 1520 | |
---|
| 1521 | if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) ) |
---|
| 1522 | { |
---|
| 1523 | r_dcache_xtn_req = false; |
---|
| 1524 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1525 | } |
---|
| 1526 | break; |
---|
| 1527 | } |
---|
| 1528 | ////////////////////////// |
---|
| 1529 | case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address |
---|
| 1530 | // stored in the r_dcache_p0_wdata register |
---|
| 1531 | { |
---|
| 1532 | r_itlb.inval(r_dcache_p0_wdata.read()); |
---|
| 1533 | r_dcache_xtn_req = false; |
---|
| 1534 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1535 | break; |
---|
| 1536 | } |
---|
| 1537 | /////////////////////////////// |
---|
| 1538 | case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address |
---|
| 1539 | // requires 3 cycles (in case of hit on itlb and icache). |
---|
| 1540 | // In this state, we access TLB to translate virtual address |
---|
| 1541 | // stored in the r_dcache_p0_wdata register. |
---|
| 1542 | { |
---|
| 1543 | paddr_t paddr; |
---|
| 1544 | bool hit; |
---|
| 1545 | |
---|
| 1546 | // read physical address in TLB when MMU activated |
---|
| 1547 | if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated |
---|
| 1548 | { |
---|
| 1549 | |
---|
| 1550 | #ifdef INSTRUMENTATION |
---|
| 1551 | m_cpt_itlb_read++; |
---|
| 1552 | #endif |
---|
| 1553 | hit = r_itlb.translate(r_dcache_p0_wdata.read(), |
---|
| 1554 | &paddr); |
---|
| 1555 | } |
---|
| 1556 | else // itlb not activated |
---|
| 1557 | { |
---|
| 1558 | paddr = (paddr_t)r_dcache_p0_wdata.read(); |
---|
| 1559 | hit = true; |
---|
| 1560 | } |
---|
| 1561 | |
---|
| 1562 | if ( hit ) // continue the selective inval process |
---|
| 1563 | { |
---|
| 1564 | r_icache_vci_paddr = paddr; |
---|
| 1565 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
| 1566 | } |
---|
| 1567 | else // miss : send a request to DCACHE FSM |
---|
| 1568 | { |
---|
| 1569 | |
---|
| 1570 | #ifdef INSTRUMENTATION |
---|
| 1571 | m_cpt_itlb_miss++; |
---|
| 1572 | #endif |
---|
| 1573 | r_icache_tlb_miss_req = true; |
---|
| 1574 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
| 1575 | } |
---|
| 1576 | break; |
---|
| 1577 | } |
---|
| 1578 | /////////////////////////////// |
---|
| 1579 | case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address |
---|
| 1580 | // require 2 cycles. In this state, we read dcache, |
---|
| 1581 | // with address stored in r_icache_vci_paddr register. |
---|
| 1582 | { |
---|
| 1583 | uint32_t data; |
---|
| 1584 | size_t way; |
---|
| 1585 | size_t set; |
---|
| 1586 | size_t word; |
---|
| 1587 | bool hit = r_icache.read(r_icache_vci_paddr.read(), |
---|
| 1588 | &data, |
---|
| 1589 | &way, |
---|
| 1590 | &set, |
---|
| 1591 | &word); |
---|
| 1592 | if ( hit ) // inval to be done |
---|
| 1593 | { |
---|
| 1594 | r_icache_miss_way = way; |
---|
| 1595 | r_icache_miss_set = set; |
---|
| 1596 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; |
---|
| 1597 | } |
---|
| 1598 | else // miss : acknowlege the XTN request and return |
---|
| 1599 | { |
---|
| 1600 | r_dcache_xtn_req = false; |
---|
| 1601 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1602 | } |
---|
| 1603 | break; |
---|
| 1604 | } |
---|
| 1605 | /////////////////////////////// |
---|
| 1606 | case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup. |
---|
| 1607 | // We are blocked if the previous cleanup is not completed |
---|
| 1608 | { |
---|
| 1609 | paddr_t nline; |
---|
| 1610 | |
---|
| 1611 | if ( not r_icache_cleanup_req.read() ) |
---|
| 1612 | { |
---|
[213] | 1613 | bool hit; |
---|
| 1614 | hit = r_icache.inval( r_icache_miss_way.read(), |
---|
| 1615 | r_icache_miss_set.read(), |
---|
| 1616 | &nline ); |
---|
| 1617 | assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache"); |
---|
[183] | 1618 | |
---|
| 1619 | // request cleanup |
---|
| 1620 | r_icache_cleanup_req = true; |
---|
| 1621 | r_icache_cleanup_line = nline; |
---|
| 1622 | // acknowledge the XTN request and return |
---|
| 1623 | r_dcache_xtn_req = false; |
---|
| 1624 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1625 | } |
---|
| 1626 | break; |
---|
| 1627 | } |
---|
| 1628 | |
---|
| 1629 | //////////////////////// |
---|
| 1630 | case ICACHE_MISS_VICTIM: // Selects a victim line |
---|
| 1631 | // Set the r_icache_cleanup_req flip-flop |
---|
| 1632 | // when the selected slot is not empty |
---|
| 1633 | { |
---|
[205] | 1634 | if ( m_ireq.valid ) m_cost_ins_miss_frz++; |
---|
[183] | 1635 | |
---|
| 1636 | bool valid; |
---|
| 1637 | size_t way; |
---|
| 1638 | size_t set; |
---|
| 1639 | paddr_t victim; |
---|
| 1640 | |
---|
| 1641 | valid = r_icache.victim_select(r_icache_vci_paddr.read(), |
---|
| 1642 | &victim, |
---|
| 1643 | &way, |
---|
| 1644 | &set); |
---|
| 1645 | r_icache_miss_way = way; |
---|
| 1646 | r_icache_miss_set = set; |
---|
| 1647 | |
---|
| 1648 | if ( valid ) |
---|
| 1649 | { |
---|
| 1650 | r_icache_cleanup_req = true; |
---|
| 1651 | r_icache_cleanup_line = victim; |
---|
| 1652 | r_icache_fsm = ICACHE_MISS_INVAL; |
---|
| 1653 | } |
---|
| 1654 | else |
---|
| 1655 | { |
---|
| 1656 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
| 1657 | } |
---|
| 1658 | break; |
---|
| 1659 | } |
---|
| 1660 | /////////////////////// |
---|
| 1661 | case ICACHE_MISS_INVAL: // invalidate the victim line |
---|
| 1662 | { |
---|
| 1663 | paddr_t nline; |
---|
[210] | 1664 | bool hit; |
---|
[183] | 1665 | |
---|
[210] | 1666 | hit = r_icache.inval( r_icache_miss_way.read(), |
---|
[194] | 1667 | r_icache_miss_set.read(), |
---|
[183] | 1668 | &nline ); // unused |
---|
[210] | 1669 | assert(hit && "selected way/set line should be in icache"); |
---|
[183] | 1670 | |
---|
| 1671 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
| 1672 | break; |
---|
| 1673 | } |
---|
| 1674 | ////////////////////// |
---|
| 1675 | case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM |
---|
| 1676 | { |
---|
[205] | 1677 | if ( m_ireq.valid ) m_cost_ins_miss_frz++; |
---|
[183] | 1678 | |
---|
| 1679 | // external coherence request |
---|
| 1680 | if ( r_tgt_icache_req.read() ) |
---|
| 1681 | { |
---|
| 1682 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
| 1683 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1684 | break; |
---|
| 1685 | } |
---|
| 1686 | |
---|
[198] | 1687 | if ( r_vci_rsp_ins_error.read() ) // bus error |
---|
| 1688 | { |
---|
[183] | 1689 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
| 1690 | r_mmu_ibvar = r_icache_vaddr_save.read(); |
---|
[205] | 1691 | m_irsp.valid = true; |
---|
| 1692 | m_irsp.error = true; |
---|
[183] | 1693 | r_vci_rsp_ins_error = false; |
---|
| 1694 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1695 | } |
---|
| 1696 | else if ( r_vci_rsp_fifo_icache.rok() ) // response available |
---|
| 1697 | { |
---|
| 1698 | r_icache_miss_word = 0; |
---|
| 1699 | r_icache_fsm = ICACHE_MISS_UPDT; |
---|
[198] | 1700 | } |
---|
[183] | 1701 | break; |
---|
| 1702 | } |
---|
| 1703 | ////////////////////// |
---|
| 1704 | case ICACHE_MISS_UPDT: // update the cache (one word per cycle) |
---|
| 1705 | { |
---|
[205] | 1706 | if ( m_ireq.valid ) m_cost_ins_miss_frz++; |
---|
[183] | 1707 | |
---|
| 1708 | if ( r_vci_rsp_fifo_icache.rok() ) // response available |
---|
| 1709 | { |
---|
| 1710 | if ( r_icache_miss_inval ) // Matching coherence request |
---|
| 1711 | // We pop the response FIFO, without updating the cache |
---|
| 1712 | // We send a cleanup for the missing line at the last word |
---|
| 1713 | // Blocked if the previous cleanup is not completed |
---|
| 1714 | { |
---|
| 1715 | if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word |
---|
| 1716 | { |
---|
| 1717 | vci_rsp_fifo_icache_get = true; |
---|
| 1718 | r_icache_miss_word = r_icache_miss_word.read() + 1; |
---|
| 1719 | } |
---|
| 1720 | else // last word |
---|
| 1721 | { |
---|
| 1722 | if ( not r_icache_cleanup_req.read() ) // no pending cleanup |
---|
| 1723 | { |
---|
| 1724 | vci_rsp_fifo_icache_get = true; |
---|
| 1725 | r_icache_cleanup_req = true; |
---|
| 1726 | r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2)); |
---|
| 1727 | r_icache_miss_inval = false; |
---|
| 1728 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1729 | } |
---|
| 1730 | } |
---|
| 1731 | } |
---|
| 1732 | else // No matching coherence request |
---|
| 1733 | // We pop the FIFO and update the cache |
---|
| 1734 | // We update the directory at the last word |
---|
| 1735 | { |
---|
| 1736 | |
---|
| 1737 | #ifdef INSTRUMENTATION |
---|
| 1738 | m_cpt_icache_data_write++; |
---|
| 1739 | #endif |
---|
| 1740 | r_icache.write( r_icache_miss_way.read(), |
---|
| 1741 | r_icache_miss_set.read(), |
---|
| 1742 | r_icache_miss_word.read(), |
---|
| 1743 | r_vci_rsp_fifo_icache.read() ); |
---|
| 1744 | vci_rsp_fifo_icache_get = true; |
---|
| 1745 | r_icache_miss_word = r_icache_miss_word.read() + 1; |
---|
| 1746 | if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word |
---|
| 1747 | { |
---|
| 1748 | |
---|
| 1749 | #ifdef INSTRUMENTATION |
---|
| 1750 | m_cpt_icache_dir_write++; |
---|
| 1751 | #endif |
---|
| 1752 | r_icache.victim_update_tag( r_icache_vci_paddr.read(), |
---|
| 1753 | r_icache_miss_way.read(), |
---|
| 1754 | r_icache_miss_set.read() ); |
---|
| 1755 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1756 | } |
---|
| 1757 | } |
---|
| 1758 | } |
---|
| 1759 | break; |
---|
| 1760 | } |
---|
| 1761 | //////////////////// |
---|
| 1762 | case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM |
---|
| 1763 | // |
---|
| 1764 | { |
---|
| 1765 | // external coherence request |
---|
| 1766 | if ( r_tgt_icache_req.read() ) |
---|
| 1767 | { |
---|
[217] | 1768 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
[183] | 1769 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
| 1770 | break; |
---|
| 1771 | } |
---|
| 1772 | |
---|
| 1773 | if ( r_vci_rsp_ins_error.read() ) // bus error |
---|
| 1774 | { |
---|
| 1775 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
[205] | 1776 | r_mmu_ibvar = m_ireq.addr; |
---|
[183] | 1777 | r_vci_rsp_ins_error = false; |
---|
[218] | 1778 | m_irsp.valid = true; |
---|
| 1779 | m_irsp.error = true; |
---|
[183] | 1780 | r_icache_fsm = ICACHE_IDLE; |
---|
| 1781 | } |
---|
| 1782 | else if (r_vci_rsp_fifo_icache.rok() ) // instruction available |
---|
| 1783 | { |
---|
| 1784 | vci_rsp_fifo_icache_get = true; |
---|
| 1785 | r_icache_fsm = ICACHE_IDLE; |
---|
[205] | 1786 | if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified |
---|
[183] | 1787 | { |
---|
[205] | 1788 | m_irsp.valid = true; |
---|
| 1789 | m_irsp.instruction = r_vci_rsp_fifo_icache.read(); |
---|
[183] | 1790 | } |
---|
| 1791 | } |
---|
| 1792 | break; |
---|
| 1793 | } |
---|
| 1794 | ///////////////////// |
---|
| 1795 | case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm |
---|
| 1796 | // handling coherence requests. |
---|
| 1797 | // the return state is defined in r_icache_fsm_save. |
---|
| 1798 | { |
---|
| 1799 | paddr_t paddr = r_tgt_paddr.read(); |
---|
| 1800 | paddr_t mask = ~((m_icache_words<<2)-1); |
---|
| 1801 | |
---|
| 1802 | if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and |
---|
| 1803 | ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss |
---|
| 1804 | { |
---|
| 1805 | r_icache_miss_inval = true; // signaling the matching |
---|
| 1806 | r_tgt_icache_req = false; // coherence request completed |
---|
| 1807 | r_tgt_icache_rsp = r_tgt_update.read(); // response required if update |
---|
| 1808 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1809 | } |
---|
| 1810 | else // no match |
---|
| 1811 | { |
---|
| 1812 | |
---|
| 1813 | #ifdef INSTRUMENTATION |
---|
| 1814 | m_cpt_icache_dir_read++; |
---|
| 1815 | #endif |
---|
| 1816 | uint32_t inst; |
---|
| 1817 | size_t way; |
---|
| 1818 | size_t set; |
---|
| 1819 | size_t word; |
---|
| 1820 | bool hit = r_icache.read(paddr, |
---|
| 1821 | &inst, |
---|
| 1822 | &way, |
---|
| 1823 | &set, |
---|
| 1824 | &word); |
---|
| 1825 | r_icache_cc_way = way; |
---|
| 1826 | r_icache_cc_set = set; |
---|
| 1827 | |
---|
| 1828 | if ( hit and r_tgt_update.read() ) // hit update |
---|
| 1829 | { |
---|
| 1830 | r_icache_fsm = ICACHE_CC_UPDT; |
---|
| 1831 | r_icache_cc_word = r_tgt_word_min.read(); |
---|
| 1832 | } |
---|
| 1833 | else if ( hit and not r_tgt_update.read() ) // hit inval |
---|
| 1834 | { |
---|
| 1835 | r_icache_fsm = ICACHE_CC_INVAL; |
---|
| 1836 | } |
---|
| 1837 | else // miss can happen |
---|
| 1838 | { |
---|
| 1839 | r_tgt_icache_req = false; |
---|
| 1840 | r_tgt_icache_rsp = r_tgt_update.read(); |
---|
| 1841 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1842 | } |
---|
| 1843 | } |
---|
| 1844 | break; |
---|
| 1845 | } |
---|
| 1846 | |
---|
| 1847 | ///////////////////// |
---|
| 1848 | case ICACHE_CC_INVAL: // invalidate a cache line |
---|
| 1849 | { |
---|
| 1850 | paddr_t nline; |
---|
[213] | 1851 | bool hit; |
---|
| 1852 | hit = r_icache.inval( r_icache_cc_way.read(), |
---|
| 1853 | r_icache_cc_set.read(), |
---|
| 1854 | &nline ); |
---|
| 1855 | assert (hit && "ICACHE_CC_INVAL way/set should still be in icache"); |
---|
[183] | 1856 | r_tgt_icache_req = false; |
---|
| 1857 | r_tgt_icache_rsp = true; |
---|
| 1858 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1859 | break; |
---|
| 1860 | } |
---|
| 1861 | //////////////////// |
---|
| 1862 | case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max) |
---|
| 1863 | { |
---|
| 1864 | size_t word = r_icache_cc_word.read(); |
---|
| 1865 | size_t way = r_icache_cc_way.read(); |
---|
| 1866 | size_t set = r_icache_cc_set.read(); |
---|
| 1867 | |
---|
| 1868 | r_icache.write( way, |
---|
| 1869 | set, |
---|
| 1870 | word, |
---|
| 1871 | r_tgt_buf[word], |
---|
| 1872 | r_tgt_be[word] ); |
---|
| 1873 | |
---|
| 1874 | r_icache_cc_word = word+1; |
---|
| 1875 | |
---|
| 1876 | if ( word == r_tgt_word_max.read() ) // last word |
---|
| 1877 | { |
---|
| 1878 | r_tgt_icache_req = false; |
---|
| 1879 | r_tgt_icache_rsp = true; |
---|
| 1880 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
| 1881 | } |
---|
| 1882 | break; |
---|
| 1883 | } |
---|
| 1884 | |
---|
| 1885 | } // end switch r_icache_fsm |
---|
| 1886 | |
---|
| 1887 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 1888 | // DCACHE FSM |
---|
| 1889 | // |
---|
| 1890 | // Both the Cacheability Table, and the MMU cacheable bit are used to define |
---|
| 1891 | // the cacheability, depending on the MMU mode. |
---|
| 1892 | // |
---|
| 1893 | // 1/ Coherence requests : |
---|
| 1894 | // There is a coherence request when the tgt_dcache_req flip-flop is set, |
---|
| 1895 | // requesting a line invalidation or a line update. |
---|
| 1896 | // Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states. |
---|
| 1897 | // The actions associated to the pre-empted state are not executed, the DCACHE FSM |
---|
| 1898 | // goes to the CC_CHECK state to execute the requested action, and returns to the |
---|
| 1899 | // pre-empted state. |
---|
| 1900 | // |
---|
[205] | 1901 | // 2/ TLB miss |
---|
| 1902 | // The page tables can be cacheable. |
---|
| 1903 | // In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated |
---|
| 1904 | // sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE, |
---|
| 1905 | // this sub-fsm implement the table-walk... |
---|
| 1906 | // |
---|
| 1907 | // 3/ processor requests : |
---|
[183] | 1908 | // Processor READ, WRITE, LL or SC requests are taken in IDLE state only. |
---|
| 1909 | // The IDLE state implements a three stages pipe-line to handle write bursts: |
---|
| 1910 | // - The physical address is computed by dtlb in stage P0. |
---|
| 1911 | // - The registration in wbuf and the dcache hit are computed in stage P1. |
---|
| 1912 | // - The dcache update is done in stage P2. |
---|
[206] | 1913 | // WRITE or SC requests can require a PTE Dirty bit update (in memory), |
---|
| 1914 | // that is done (before handling the processor request) by a dedicated sub-fsm |
---|
| 1915 | // (DCACHE_DIRTY_TLB_SET state). |
---|
| 1916 | // If a PTE is modified, both the itlb and dtlb are selectively, but sequencially |
---|
[205] | 1917 | // cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state). |
---|
[183] | 1918 | // If there is no write in the pipe, dcache and dtlb are accessed in parallel, |
---|
| 1919 | // (virtual address for itlb, and speculative physical address computed during |
---|
[206] | 1920 | // previous cycle for dcache) in order to return the data in one cycle for a READ |
---|
| 1921 | // request. We just pay an extra cycle when the speculative access is failing. |
---|
[183] | 1922 | // |
---|
[205] | 1923 | // 4/ Atomic instructions LL/SC |
---|
[183] | 1924 | // The LL/SC address can be cacheable or non cacheable. |
---|
| 1925 | // The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and |
---|
| 1926 | // r_dcache_ll_data are stored in the L1 cache controller, and not in the |
---|
| 1927 | // memory controller. |
---|
| 1928 | // - LL requests from the processor are transmitted as standard VCI |
---|
| 1929 | // READ transactions (one word / one line, depending on the cacheability). |
---|
| 1930 | // - SC requests from the processor are systematically transmitted to the |
---|
[205] | 1931 | // memory cache as Compare&swap requests (both the data value stored in the |
---|
[183] | 1932 | // r_dcache_ll_data register and the new value). |
---|
[205] | 1933 | // The cache is not updated, as this is done in case of success by the |
---|
| 1934 | // coherence transaction. |
---|
[183] | 1935 | // |
---|
[205] | 1936 | // 5/ Non cacheable access: |
---|
[183] | 1937 | // This component implement a strong order between non cacheable access |
---|
| 1938 | // (read or write) : A new non cacheable VCI transaction starts only when |
---|
| 1939 | // the previous non cacheable transaction is completed. Both cacheable and |
---|
| 1940 | // non cacheable transactions use the write buffer, but the DCACHE FSM registers |
---|
| 1941 | // a non cacheable write transaction posted in the write buffer by setting the |
---|
| 1942 | // r_dcache_pending_unc_write flip_flop. All other non cacheable requests |
---|
| 1943 | // are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the |
---|
| 1944 | // pending non cacheable write transaction completes). |
---|
| 1945 | // |
---|
[205] | 1946 | // 6/ Error handling: |
---|
[183] | 1947 | // When the MMU is not activated, Read Bus Errors are synchronous events, |
---|
| 1948 | // but Write Bus Errors are asynchronous events (processor is not frozen). |
---|
| 1949 | // - If a Read Bus Error is detected, the VCI_RSP FSM sets the |
---|
| 1950 | // r_vci_rsp_data_error flip-flop, without writing any data in the |
---|
| 1951 | // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled |
---|
| 1952 | // by the DCACHE FSM. |
---|
| 1953 | // - If a Write Bus Error is detected, the VCI_RSP FSM signals |
---|
| 1954 | // the asynchronous error using the setWriteBerr() method. |
---|
| 1955 | // When the MMU is activated bus error are rare events, as the MMU |
---|
| 1956 | // checks the physical address before the VCI transaction starts. |
---|
| 1957 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
| 1958 | |
---|
[206] | 1959 | // default value for m_drsp |
---|
[205] | 1960 | m_drsp.valid = false; |
---|
[206] | 1961 | m_drsp.error = false; |
---|
| 1962 | m_drsp.rdata = 0; |
---|
[183] | 1963 | |
---|
| 1964 | switch ( r_dcache_fsm.read() ) |
---|
| 1965 | { |
---|
| 1966 | case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state : |
---|
[206] | 1967 | // 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE |
---|
[198] | 1968 | // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK |
---|
[183] | 1969 | // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS |
---|
[198] | 1970 | // 4) XTN request (processor) => DCACHE_XTN_* |
---|
| 1971 | // 5) DTLB miss (processor) => DCACHE_TLB_MISS |
---|
[183] | 1972 | // 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM |
---|
[206] | 1973 | // 7) Uncacheable read (processor) => DCACHE_UNC_WAIT |
---|
| 1974 | // 8) SC access (processor) => DCACHE_SC_WAIT |
---|
| 1975 | // |
---|
| 1976 | // The dtlb is unconditionally accessed to translate the |
---|
| 1977 | // virtual adress from processor. |
---|
| 1978 | // |
---|
[183] | 1979 | // There is 4 configurations to access the cache, |
---|
| 1980 | // depending on the pipe-line state, defined |
---|
[201] | 1981 | // by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated |
---|
| 1982 | // and r_dcache_p1_valid (V1) flip-flop : P2 stage activated |
---|
[183] | 1983 | // V0 / V1 / Data / Directory / comment |
---|
| 1984 | // 0 / 0 / read(A0) / read(A0) / read speculative access |
---|
| 1985 | // 0 / 1 / write(A2) / nop / read request delayed |
---|
| 1986 | // 1 / 0 / nop / read(A1) / read request delayed |
---|
| 1987 | // 1 / 1 / write(A2) / read(A1) / read request delayed |
---|
| 1988 | { |
---|
| 1989 | //////////////////////////////////////////////////////////////////////////////// |
---|
| 1990 | // Handling P2 pipe-line stage |
---|
| 1991 | // Inputs are r_dcache_p1_* registers. |
---|
[206] | 1992 | // If r_dcache_p1_valid is true, we update the local copy in dcache. |
---|
| 1993 | // If the modified cache line has copies in TLBs, we launch a TLB invalidate |
---|
| 1994 | // operation, going to DCACHE_INVAL_TLB_SCAN state. |
---|
[183] | 1995 | |
---|
[206] | 1996 | bool tlb_inval_required = false; |
---|
[183] | 1997 | |
---|
| 1998 | if ( r_dcache_p1_valid.read() ) // P2 stage activated |
---|
| 1999 | { |
---|
[204] | 2000 | size_t way = r_dcache_p1_cache_way.read(); |
---|
| 2001 | size_t set = r_dcache_p1_cache_set.read(); |
---|
| 2002 | size_t word = r_dcache_p1_cache_word.read(); |
---|
[183] | 2003 | uint32_t wdata = r_dcache_p1_wdata.read(); |
---|
| 2004 | vci_be_t be = r_dcache_p1_be.read(); |
---|
| 2005 | |
---|
[206] | 2006 | r_dcache.write( way, |
---|
| 2007 | set, |
---|
| 2008 | word, |
---|
| 2009 | wdata, |
---|
| 2010 | be ); |
---|
[183] | 2011 | #ifdef INSTRUMENTATION |
---|
| 2012 | m_cpt_dcache_data_write++; |
---|
| 2013 | #endif |
---|
[206] | 2014 | // cache update after a WRITE hit can require itlb & dtlb inval or flush |
---|
| 2015 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) |
---|
[183] | 2016 | { |
---|
[206] | 2017 | tlb_inval_required = true; |
---|
| 2018 | r_dcache_tlb_inval_count = 0; |
---|
| 2019 | r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2)); |
---|
| 2020 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[183] | 2021 | } |
---|
[206] | 2022 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) |
---|
| 2023 | { |
---|
| 2024 | r_itlb.reset(); |
---|
| 2025 | r_dtlb.reset(); |
---|
| 2026 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
| 2027 | } |
---|
[183] | 2028 | |
---|
| 2029 | #if DEBUG_DCACHE |
---|
[198] | 2030 | if ( m_debug_dcache_fsm ) |
---|
| 2031 | { |
---|
[206] | 2032 | std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec |
---|
| 2033 | << " / WAY = " << way |
---|
| 2034 | << " / SET = " << set |
---|
| 2035 | << " / WORD = " << word << std::hex |
---|
| 2036 | << " / DATA = " << wdata |
---|
| 2037 | << " / BE = " << be << std::endl; |
---|
[198] | 2038 | } |
---|
[183] | 2039 | #endif |
---|
| 2040 | } // end P2 stage |
---|
| 2041 | |
---|
| 2042 | /////////////////////////////////////////////////////////////////////////// |
---|
| 2043 | // Handling P1 pipe-line stage |
---|
| 2044 | // Inputs are r_dcache_p0_* registers. |
---|
[206] | 2045 | // We must write into wbuf and test the hit in dcache. |
---|
| 2046 | // If the write request is non cacheable, and there is a pending |
---|
| 2047 | // non cacheable write, or if the write buffer is full, we break, |
---|
| 2048 | // because the P0 and P1 pipe-line stages are frozen until the write |
---|
| 2049 | // request registration is possible, but he P2 stage is not frozen. |
---|
| 2050 | // The r_dcache_p1_valid bit must be computed at all cycles, and |
---|
| 2051 | // the P2 stage must be activated if there is local copy in dcache. |
---|
[183] | 2052 | |
---|
[206] | 2053 | if ( r_dcache_p0_valid.read() ) // P1 stage activated |
---|
[183] | 2054 | { |
---|
| 2055 | // write not cacheable, and previous non cacheable write registered |
---|
| 2056 | if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() ) |
---|
| 2057 | { |
---|
| 2058 | r_dcache_p1_valid = false; |
---|
| 2059 | break; |
---|
| 2060 | } |
---|
| 2061 | |
---|
| 2062 | // try a registration into write buffer |
---|
| 2063 | bool wok = r_wbuf.write( r_dcache_p0_paddr.read(), |
---|
| 2064 | r_dcache_p0_be.read(), |
---|
| 2065 | r_dcache_p0_wdata.read(), |
---|
| 2066 | r_dcache_p0_cacheable.read() ); |
---|
| 2067 | #ifdef INSTRUMENTATION |
---|
| 2068 | m_cpt_wbuf_write++; |
---|
| 2069 | #endif |
---|
| 2070 | // write buffer full |
---|
| 2071 | if ( not wok ) |
---|
| 2072 | { |
---|
| 2073 | r_dcache_p1_valid = false; |
---|
| 2074 | break; |
---|
| 2075 | } |
---|
| 2076 | // update the write_buffer state extension |
---|
| 2077 | r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read(); |
---|
| 2078 | |
---|
[206] | 2079 | // read directory to check local copy |
---|
[183] | 2080 | size_t cache_way; |
---|
| 2081 | size_t cache_set; |
---|
| 2082 | size_t cache_word; |
---|
| 2083 | bool local_copy; |
---|
| 2084 | if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated |
---|
| 2085 | { |
---|
| 2086 | local_copy = r_dcache.hit( r_dcache_p0_paddr.read(), |
---|
| 2087 | &cache_way, |
---|
| 2088 | &cache_set, |
---|
| 2089 | &cache_word ); |
---|
| 2090 | #ifdef INSTRUMENTATION |
---|
| 2091 | m_cpt_dcache_dir_read++; |
---|
| 2092 | #endif |
---|
| 2093 | } |
---|
| 2094 | else |
---|
| 2095 | { |
---|
| 2096 | local_copy = false; |
---|
| 2097 | } |
---|
| 2098 | |
---|
[206] | 2099 | // store values for P2 pipe stage |
---|
| 2100 | if ( local_copy ) |
---|
[183] | 2101 | { |
---|
| 2102 | r_dcache_p1_valid = true; |
---|
| 2103 | r_dcache_p1_wdata = r_dcache_p0_wdata.read(); |
---|
| 2104 | r_dcache_p1_be = r_dcache_p0_be.read(); |
---|
| 2105 | r_dcache_p1_paddr = r_dcache_p0_paddr.read(); |
---|
| 2106 | r_dcache_p1_cache_way = cache_way; |
---|
| 2107 | r_dcache_p1_cache_set = cache_set; |
---|
| 2108 | r_dcache_p1_cache_word = cache_word; |
---|
| 2109 | } |
---|
| 2110 | else |
---|
| 2111 | { |
---|
| 2112 | r_dcache_p1_valid = false; |
---|
| 2113 | } |
---|
| 2114 | } |
---|
| 2115 | else // P1 stage not activated |
---|
| 2116 | { |
---|
| 2117 | r_dcache_p1_valid = false; |
---|
| 2118 | } // end P1 stage |
---|
| 2119 | |
---|
[206] | 2120 | ///////////////////////////////////////////////////////////////////////////////// |
---|
[204] | 2121 | // handling P0 pipe-line stage |
---|
[205] | 2122 | // This stage is controlling r_dcache_fsm and r_dcache_p0_* registers. |
---|
[206] | 2123 | // The r_dcache_p0_valid flip-flop is only set in case of a WRITE request. |
---|
[204] | 2124 | // - the TLB invalidate requests have the highest priority, |
---|
[183] | 2125 | // - then the external coherence requests, |
---|
| 2126 | // - then the itlb miss requests, |
---|
| 2127 | // - and finally the processor requests. |
---|
[205] | 2128 | // If dtlb is activated, there is an unconditionnal access to dtlb, |
---|
| 2129 | // for address translation. |
---|
[206] | 2130 | // 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if |
---|
| 2131 | // dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully |
---|
| 2132 | // handled by the IDLE state), and the processor request is acknowledged. |
---|
| 2133 | // 2) A processor READ or LL request generate a simultaneouss access to |
---|
[205] | 2134 | // both dcache data and dcache directoty, using speculative PPN, but |
---|
| 2135 | // is delayed if the write pipe-line is not empty. |
---|
| 2136 | // In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or |
---|
| 2137 | // DCACHE_MISS_WAIT states. |
---|
[206] | 2138 | // 3) A processor SC request is delayed until the write pipe-line is empty. |
---|
[205] | 2139 | // A VCI SC transaction is launched, and we wait the VCI response in |
---|
| 2140 | // DCACHE_SC_WAIT state. It can be completed by a "long write" if the |
---|
| 2141 | // PTE dirty bit must be updated in dtlb, dcache, and RAM. |
---|
| 2142 | // The data is not modified in dcache, as it will be done by the |
---|
| 2143 | // coherence transaction. |
---|
[183] | 2144 | |
---|
[204] | 2145 | // TLB inval required |
---|
| 2146 | if ( tlb_inval_required ) |
---|
[183] | 2147 | { |
---|
[217] | 2148 | r_dcache_fsm_scan_save = r_dcache_fsm.read(); |
---|
| 2149 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
| 2150 | r_dcache_p0_valid = false; |
---|
[183] | 2151 | } |
---|
| 2152 | // external coherence request |
---|
| 2153 | else if ( r_tgt_dcache_req.read() ) |
---|
| 2154 | { |
---|
[217] | 2155 | r_dcache_fsm_cc_save = r_dcache_fsm.read(); |
---|
| 2156 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 2157 | r_dcache_p0_valid = false; |
---|
[183] | 2158 | } |
---|
| 2159 | |
---|
| 2160 | // itlb miss request |
---|
| 2161 | else if ( r_icache_tlb_miss_req.read() ) |
---|
| 2162 | { |
---|
| 2163 | r_dcache_tlb_ins = true; |
---|
| 2164 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
| 2165 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
[205] | 2166 | r_dcache_p0_valid = false; |
---|
[183] | 2167 | } |
---|
| 2168 | |
---|
| 2169 | // processor request |
---|
[205] | 2170 | else if ( m_dreq.valid ) |
---|
[183] | 2171 | { |
---|
| 2172 | // dcache access using speculative PPN only if pipe-line empty |
---|
| 2173 | paddr_t cache_paddr; |
---|
| 2174 | size_t cache_way; |
---|
| 2175 | size_t cache_set; |
---|
| 2176 | size_t cache_word; |
---|
| 2177 | uint32_t cache_rdata; |
---|
| 2178 | bool cache_hit; |
---|
| 2179 | |
---|
| 2180 | if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated |
---|
| 2181 | not r_dcache_p0_valid.read() and |
---|
| 2182 | not r_dcache_p1_valid.read() ) // pipe-line empty |
---|
| 2183 | { |
---|
| 2184 | cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) | |
---|
[205] | 2185 | ((paddr_t)m_dreq.addr & PAGE_K_MASK); |
---|
[183] | 2186 | |
---|
| 2187 | cache_hit = r_dcache.read( cache_paddr, |
---|
| 2188 | &cache_rdata, |
---|
| 2189 | &cache_way, |
---|
| 2190 | &cache_set, |
---|
| 2191 | &cache_word ); |
---|
| 2192 | #ifdef INSTRUMENTATION |
---|
| 2193 | m_cpt_dcache_dir_read++; |
---|
| 2194 | m_cpt_dcache_data_read++; |
---|
| 2195 | #endif |
---|
| 2196 | } |
---|
| 2197 | else |
---|
| 2198 | { |
---|
| 2199 | cache_hit = false; |
---|
| 2200 | } // end dcache access |
---|
| 2201 | |
---|
| 2202 | // systematic dtlb access using virtual address |
---|
| 2203 | paddr_t tlb_paddr; |
---|
| 2204 | pte_info_t tlb_flags; |
---|
| 2205 | size_t tlb_way; |
---|
| 2206 | size_t tlb_set; |
---|
| 2207 | paddr_t tlb_nline; |
---|
| 2208 | bool tlb_hit; |
---|
| 2209 | |
---|
[206] | 2210 | if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated |
---|
[183] | 2211 | { |
---|
[205] | 2212 | tlb_hit = r_dtlb.translate( m_dreq.addr, |
---|
[183] | 2213 | &tlb_paddr, |
---|
| 2214 | &tlb_flags, |
---|
| 2215 | &tlb_nline, |
---|
| 2216 | &tlb_way, |
---|
| 2217 | &tlb_set ); |
---|
| 2218 | #ifdef INSTRUMENTATION |
---|
| 2219 | m_cpt_dtlb_read++; |
---|
| 2220 | #endif |
---|
| 2221 | } |
---|
| 2222 | else |
---|
| 2223 | { |
---|
| 2224 | tlb_hit = false; |
---|
| 2225 | } // end dtlb access |
---|
| 2226 | |
---|
| 2227 | // register the processor request |
---|
[205] | 2228 | r_dcache_p0_vaddr = m_dreq.addr; |
---|
| 2229 | r_dcache_p0_be = m_dreq.be; |
---|
| 2230 | r_dcache_p0_wdata = m_dreq.wdata; |
---|
[183] | 2231 | |
---|
| 2232 | // Handling READ XTN requests from processor |
---|
| 2233 | // They are executed in this DCACHE_IDLE state. |
---|
| 2234 | // The processor must not be in user mode |
---|
[205] | 2235 | if (m_dreq.type == iss_t::XTN_READ) |
---|
[183] | 2236 | { |
---|
[205] | 2237 | int xtn_opcode = (int)m_dreq.addr/4; |
---|
[183] | 2238 | |
---|
| 2239 | // checking processor mode: |
---|
[205] | 2240 | if (m_dreq.mode == iss_t::MODE_USER) |
---|
[183] | 2241 | { |
---|
| 2242 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
[205] | 2243 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2244 | m_drsp.valid = true; |
---|
| 2245 | m_drsp.error = true; |
---|
[183] | 2246 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2247 | } |
---|
| 2248 | else |
---|
| 2249 | { |
---|
| 2250 | switch( xtn_opcode ) |
---|
| 2251 | { |
---|
| 2252 | case iss_t::XTN_INS_ERROR_TYPE: |
---|
[205] | 2253 | m_drsp.rdata = r_mmu_ietr.read(); |
---|
| 2254 | m_drsp.valid = true; |
---|
[183] | 2255 | break; |
---|
| 2256 | |
---|
| 2257 | case iss_t::XTN_DATA_ERROR_TYPE: |
---|
[205] | 2258 | m_drsp.rdata = r_mmu_detr.read(); |
---|
| 2259 | m_drsp.valid = true; |
---|
[183] | 2260 | break; |
---|
| 2261 | |
---|
| 2262 | case iss_t::XTN_INS_BAD_VADDR: |
---|
[205] | 2263 | m_drsp.rdata = r_mmu_ibvar.read(); |
---|
| 2264 | m_drsp.valid = true; |
---|
[183] | 2265 | break; |
---|
| 2266 | |
---|
| 2267 | case iss_t::XTN_DATA_BAD_VADDR: |
---|
[205] | 2268 | m_drsp.rdata = r_mmu_dbvar.read(); |
---|
| 2269 | m_drsp.valid = true; |
---|
[183] | 2270 | break; |
---|
| 2271 | |
---|
| 2272 | case iss_t::XTN_PTPR: |
---|
[205] | 2273 | m_drsp.rdata = r_mmu_ptpr.read(); |
---|
| 2274 | m_drsp.valid = true; |
---|
[183] | 2275 | break; |
---|
| 2276 | |
---|
| 2277 | case iss_t::XTN_TLB_MODE: |
---|
[205] | 2278 | m_drsp.rdata = r_mmu_mode.read(); |
---|
| 2279 | m_drsp.valid = true; |
---|
[183] | 2280 | break; |
---|
| 2281 | |
---|
| 2282 | case iss_t::XTN_MMU_PARAMS: |
---|
[205] | 2283 | m_drsp.rdata = r_mmu_params; |
---|
| 2284 | m_drsp.valid = true; |
---|
[183] | 2285 | break; |
---|
| 2286 | |
---|
| 2287 | case iss_t::XTN_MMU_RELEASE: |
---|
[205] | 2288 | m_drsp.rdata = r_mmu_release; |
---|
| 2289 | m_drsp.valid = true; |
---|
[183] | 2290 | break; |
---|
| 2291 | |
---|
| 2292 | case iss_t::XTN_MMU_WORD_LO: |
---|
[205] | 2293 | m_drsp.rdata = r_mmu_word_lo.read(); |
---|
| 2294 | m_drsp.valid = true; |
---|
[183] | 2295 | break; |
---|
| 2296 | |
---|
| 2297 | case iss_t::XTN_MMU_WORD_HI: |
---|
[205] | 2298 | m_drsp.rdata = r_mmu_word_hi.read(); |
---|
| 2299 | m_drsp.valid = true; |
---|
[183] | 2300 | break; |
---|
| 2301 | |
---|
| 2302 | default: |
---|
| 2303 | r_mmu_detr = MMU_READ_UNDEFINED_XTN; |
---|
[205] | 2304 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2305 | m_drsp.valid = true; |
---|
| 2306 | m_drsp.error = true; |
---|
[183] | 2307 | break; |
---|
| 2308 | } // end switch xtn_opcode |
---|
| 2309 | } // end else |
---|
[205] | 2310 | r_dcache_p0_valid = false; |
---|
[183] | 2311 | } // end if XTN_READ |
---|
| 2312 | |
---|
| 2313 | // Handling WRITE XTN requests from processor. |
---|
| 2314 | // They are not executed in this DCACHE_IDLE state, |
---|
| 2315 | // if they require access to the caches or the TLBs |
---|
| 2316 | // that are already accessed for speculative read. |
---|
| 2317 | // Caches can be invalidated or flushed in user mode, |
---|
| 2318 | // and the sync instruction can be executed in user mode |
---|
[205] | 2319 | else if (m_dreq.type == iss_t::XTN_WRITE) |
---|
[183] | 2320 | { |
---|
[205] | 2321 | int xtn_opcode = (int)m_dreq.addr/4; |
---|
[183] | 2322 | r_dcache_xtn_opcode = xtn_opcode; |
---|
| 2323 | |
---|
| 2324 | // checking processor mode: |
---|
[205] | 2325 | if ( (m_dreq.mode == iss_t::MODE_USER) && |
---|
[183] | 2326 | (xtn_opcode != iss_t:: XTN_SYNC) && |
---|
| 2327 | (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && |
---|
| 2328 | (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && |
---|
| 2329 | (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && |
---|
| 2330 | (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) ) |
---|
| 2331 | { |
---|
| 2332 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
[205] | 2333 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2334 | m_drsp.valid = true; |
---|
| 2335 | m_drsp.error = true; |
---|
[183] | 2336 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2337 | } |
---|
| 2338 | else |
---|
| 2339 | { |
---|
| 2340 | switch( xtn_opcode ) |
---|
| 2341 | { |
---|
| 2342 | case iss_t::XTN_PTPR: // itlb & dtlb must be flushed |
---|
[205] | 2343 | r_mmu_ptpr = m_dreq.wdata; |
---|
[183] | 2344 | r_dcache_xtn_req = true; |
---|
| 2345 | r_dcache_fsm = DCACHE_XTN_SWITCH; |
---|
| 2346 | break; |
---|
| 2347 | |
---|
| 2348 | case iss_t::XTN_TLB_MODE: // no cache or tlb access |
---|
[205] | 2349 | r_mmu_mode = m_dreq.wdata; |
---|
| 2350 | m_drsp.valid = true; |
---|
[183] | 2351 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2352 | break; |
---|
| 2353 | |
---|
| 2354 | case iss_t::XTN_DTLB_INVAL: // dtlb access |
---|
| 2355 | r_dcache_fsm = DCACHE_XTN_DT_INVAL; |
---|
| 2356 | break; |
---|
| 2357 | |
---|
| 2358 | case iss_t::XTN_ITLB_INVAL: // itlb access |
---|
| 2359 | r_dcache_xtn_req = true; |
---|
| 2360 | r_dcache_fsm = DCACHE_XTN_IT_INVAL; |
---|
| 2361 | break; |
---|
| 2362 | |
---|
| 2363 | case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access |
---|
| 2364 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; |
---|
| 2365 | break; |
---|
| 2366 | |
---|
| 2367 | case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access |
---|
| 2368 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
[210] | 2369 | if (sizeof(paddr_t) <= 32) { |
---|
| 2370 | assert(r_mmu_word_hi.read() == 0 && |
---|
| 2371 | "high bits should be 0 for 32bit paddr"); |
---|
| 2372 | r_dcache_p0_paddr = |
---|
| 2373 | (paddr_t)r_mmu_word_lo.read(); |
---|
| 2374 | } else { |
---|
| 2375 | r_dcache_p0_paddr = |
---|
| 2376 | (paddr_t)r_mmu_word_hi.read() << 32 | |
---|
| 2377 | (paddr_t)r_mmu_word_lo.read(); |
---|
| 2378 | } |
---|
[183] | 2379 | break; |
---|
| 2380 | |
---|
| 2381 | case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset |
---|
| 2382 | r_dcache_flush_count = 0; |
---|
| 2383 | r_dcache_fsm = DCACHE_XTN_DC_FLUSH; |
---|
| 2384 | break; |
---|
| 2385 | |
---|
| 2386 | case iss_t::XTN_ICACHE_INVAL: // icache and itlb access |
---|
| 2387 | r_dcache_xtn_req = true; |
---|
| 2388 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; |
---|
| 2389 | break; |
---|
| 2390 | |
---|
| 2391 | case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access |
---|
| 2392 | r_dcache_xtn_req = true; |
---|
| 2393 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; |
---|
| 2394 | break; |
---|
| 2395 | |
---|
| 2396 | case iss_t::XTN_ICACHE_FLUSH: // icache access |
---|
| 2397 | r_dcache_xtn_req = true; |
---|
| 2398 | r_dcache_fsm = DCACHE_XTN_IC_FLUSH; |
---|
| 2399 | break; |
---|
| 2400 | |
---|
| 2401 | case iss_t::XTN_SYNC: // wait until write buffer empty |
---|
| 2402 | r_dcache_fsm = DCACHE_XTN_SYNC; |
---|
| 2403 | break; |
---|
| 2404 | |
---|
| 2405 | case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access |
---|
[205] | 2406 | r_mmu_word_lo = m_dreq.wdata; |
---|
| 2407 | m_drsp.valid = true; |
---|
[183] | 2408 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2409 | break; |
---|
| 2410 | |
---|
| 2411 | case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access |
---|
[205] | 2412 | r_mmu_word_hi = m_dreq.wdata; |
---|
| 2413 | m_drsp.valid = true; |
---|
[183] | 2414 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2415 | break; |
---|
| 2416 | |
---|
| 2417 | case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action |
---|
| 2418 | case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action |
---|
[205] | 2419 | m_drsp.valid = true; |
---|
[183] | 2420 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2421 | break; |
---|
| 2422 | |
---|
| 2423 | default: |
---|
| 2424 | r_mmu_detr = MMU_WRITE_UNDEFINED_XTN; |
---|
[205] | 2425 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2426 | m_drsp.valid = true; |
---|
| 2427 | m_drsp.error = true; |
---|
[183] | 2428 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2429 | break; |
---|
| 2430 | } // end switch xtn_opcode |
---|
| 2431 | } // end else |
---|
[205] | 2432 | r_dcache_p0_valid = false; |
---|
[183] | 2433 | } // end if XTN_WRITE |
---|
| 2434 | |
---|
[205] | 2435 | // Handling read/write/ll/sc processor requests. |
---|
[183] | 2436 | // The dtlb and dcache can be activated or not. |
---|
| 2437 | // We compute the physical address, the cacheability, and check processor request. |
---|
| 2438 | // - If DTLB not activated : cacheability is defined by the segment table, |
---|
| 2439 | // the physical address is equal to the virtual address (identity mapping) |
---|
| 2440 | // - If DTLB activated : cacheability is defined by the C bit in the PTE, |
---|
| 2441 | // the physical address is obtained from the TLB, and the U & W bits |
---|
| 2442 | // of the PTE are checked. |
---|
| 2443 | // The processor request is decoded only if the TLB is not activated or if |
---|
| 2444 | // the virtual address hits in tLB and access rights are OK. |
---|
| 2445 | // We call the TLB_MISS sub-fsm in case of dtlb miss. |
---|
| 2446 | else |
---|
| 2447 | { |
---|
| 2448 | bool valid_req = false; |
---|
| 2449 | bool cacheable = false; |
---|
| 2450 | paddr_t paddr = 0; |
---|
| 2451 | |
---|
| 2452 | if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated |
---|
| 2453 | { |
---|
| 2454 | valid_req = true; |
---|
| 2455 | |
---|
| 2456 | // cacheability |
---|
| 2457 | if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; |
---|
[205] | 2458 | else cacheable = m_cacheability_table[m_dreq.addr]; |
---|
[183] | 2459 | |
---|
| 2460 | // physical address |
---|
[205] | 2461 | paddr = (paddr_t)m_dreq.addr; |
---|
[183] | 2462 | } |
---|
| 2463 | else // dtlb activated |
---|
| 2464 | { |
---|
| 2465 | if ( tlb_hit ) // tlb hit |
---|
| 2466 | { |
---|
| 2467 | // cacheability |
---|
| 2468 | if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; |
---|
| 2469 | else cacheable = tlb_flags.c; |
---|
| 2470 | |
---|
| 2471 | // access rights checking |
---|
[205] | 2472 | if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) |
---|
[183] | 2473 | { |
---|
[205] | 2474 | if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) ) |
---|
[183] | 2475 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
| 2476 | else |
---|
| 2477 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
| 2478 | |
---|
[205] | 2479 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2480 | m_drsp.valid = true; |
---|
| 2481 | m_drsp.error = true; |
---|
| 2482 | m_drsp.rdata = 0; |
---|
[206] | 2483 | #if DEBUG_DCACHE |
---|
| 2484 | if ( m_debug_dcache_fsm ) |
---|
| 2485 | { |
---|
| 2486 | std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl; |
---|
| 2487 | } |
---|
| 2488 | #endif |
---|
[183] | 2489 | } |
---|
| 2490 | else if ( not tlb_flags.w and |
---|
[205] | 2491 | ((m_dreq.type == iss_t::DATA_WRITE) or |
---|
| 2492 | (m_dreq.type == iss_t::DATA_SC)) ) |
---|
[183] | 2493 | { |
---|
| 2494 | r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; |
---|
[205] | 2495 | r_mmu_dbvar = m_dreq.addr; |
---|
| 2496 | m_drsp.valid = true; |
---|
| 2497 | m_drsp.error = true; |
---|
| 2498 | m_drsp.rdata = 0; |
---|
[206] | 2499 | #if DEBUG_DCACHE |
---|
| 2500 | if ( m_debug_dcache_fsm ) |
---|
| 2501 | { |
---|
| 2502 | std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl; |
---|
| 2503 | } |
---|
| 2504 | #endif |
---|
[183] | 2505 | } |
---|
| 2506 | else |
---|
| 2507 | { |
---|
| 2508 | valid_req = true; |
---|
| 2509 | } |
---|
| 2510 | |
---|
| 2511 | // physical address |
---|
[206] | 2512 | paddr = tlb_paddr; |
---|
[183] | 2513 | } |
---|
| 2514 | else // tlb miss |
---|
| 2515 | { |
---|
[205] | 2516 | r_dcache_tlb_vaddr = m_dreq.addr; |
---|
[183] | 2517 | r_dcache_tlb_ins = false; |
---|
| 2518 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
| 2519 | } |
---|
| 2520 | } // end DTLB activated |
---|
| 2521 | |
---|
[205] | 2522 | if ( valid_req ) // processor request is valid after TLB check |
---|
[183] | 2523 | { |
---|
| 2524 | // physical address and cacheability registration |
---|
| 2525 | r_dcache_p0_paddr = paddr; |
---|
| 2526 | r_dcache_p0_cacheable = cacheable; |
---|
| 2527 | |
---|
| 2528 | // READ or LL request |
---|
| 2529 | // The read requests are taken only if the write pipe-line is empty. |
---|
| 2530 | // If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle. |
---|
| 2531 | // If speculative access is KO we just pay one extra cycle. |
---|
| 2532 | // If dcache miss, we go to DCACHE_MISS_VICTIM state. |
---|
| 2533 | // If uncacheable, we go to DCACHE_UNC_WAIT state. |
---|
[205] | 2534 | if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL)) |
---|
| 2535 | and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() ) |
---|
[183] | 2536 | { |
---|
| 2537 | if ( cacheable ) // cacheable read |
---|
| 2538 | { |
---|
| 2539 | // if the speculative access is illegal, we pay an extra cycle |
---|
| 2540 | if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) |
---|
| 2541 | != (paddr & ~PAGE_K_MASK)) |
---|
| 2542 | { |
---|
| 2543 | #ifdef INSTRUMENTATION |
---|
| 2544 | m_cpt_dcache_spec_miss++; |
---|
| 2545 | #endif |
---|
| 2546 | } |
---|
| 2547 | // if cache miss, try to get the missing line |
---|
| 2548 | else if ( not cache_hit ) |
---|
| 2549 | { |
---|
| 2550 | #ifdef INSTRUMENTATION |
---|
| 2551 | m_cpt_dcache_miss++; |
---|
| 2552 | #endif |
---|
| 2553 | // blocked in IDLE state if previous cleanup not completed |
---|
| 2554 | if ( not r_dcache_cleanup_req.read() ) |
---|
| 2555 | { |
---|
[198] | 2556 | r_dcache_vci_paddr = paddr; |
---|
| 2557 | r_dcache_vci_miss_req = true; |
---|
| 2558 | r_dcache_miss_type = PROC_MISS; |
---|
| 2559 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
[183] | 2560 | } |
---|
| 2561 | } |
---|
| 2562 | // if cache hit return the data |
---|
| 2563 | else |
---|
| 2564 | { |
---|
| 2565 | #ifdef INSTRUMENTATION |
---|
| 2566 | m_cpt_data_read++; |
---|
| 2567 | #endif |
---|
[205] | 2568 | m_drsp.valid = true; |
---|
| 2569 | m_drsp.rdata = cache_rdata; |
---|
[206] | 2570 | #if DEBUG_DCACHE |
---|
| 2571 | if ( m_debug_dcache_fsm ) |
---|
| 2572 | { |
---|
| 2573 | std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl; |
---|
| 2574 | } |
---|
| 2575 | #endif |
---|
[183] | 2576 | } |
---|
| 2577 | } |
---|
| 2578 | else // uncacheable read |
---|
| 2579 | { |
---|
| 2580 | r_dcache_vci_paddr = paddr; |
---|
[205] | 2581 | r_dcache_vci_unc_be = m_dreq.be; |
---|
[183] | 2582 | r_dcache_vci_unc_req = true; |
---|
| 2583 | r_dcache_fsm = DCACHE_UNC_WAIT; |
---|
| 2584 | } |
---|
| 2585 | |
---|
| 2586 | // makes reservation in case of LL |
---|
[205] | 2587 | if ( m_dreq.type == iss_t::DATA_LL ) |
---|
[183] | 2588 | { |
---|
| 2589 | r_dcache_ll_valid = true; |
---|
| 2590 | r_dcache_ll_data = cache_rdata; |
---|
[205] | 2591 | r_dcache_ll_vaddr = m_dreq.addr; |
---|
[183] | 2592 | } |
---|
[205] | 2593 | r_dcache_p0_valid = false; |
---|
[183] | 2594 | } // end READ or LL |
---|
| 2595 | |
---|
| 2596 | // WRITE request: |
---|
[206] | 2597 | // If the TLB is activated and the PTE Dirty bit is not set, we stall |
---|
| 2598 | // the processor and set the Dirty bit before handling the write request. |
---|
| 2599 | // If we don't need to set the Dirty bit, we can acknowledge |
---|
| 2600 | // the processor request, as the write arguments (including the |
---|
| 2601 | // physical address) are registered in r_dcache_p0 registers: |
---|
| 2602 | // We simply activate the P1 pipeline stage. |
---|
[205] | 2603 | else if ( m_dreq.type == iss_t::DATA_WRITE ) |
---|
[183] | 2604 | { |
---|
[206] | 2605 | if ( (r_mmu_mode.read() & DATA_TLB_MASK ) |
---|
| 2606 | and not tlb_flags.d ) // Dirty bit must be set |
---|
| 2607 | { |
---|
| 2608 | // The PTE physical address is obtained from the nline value (dtlb), |
---|
| 2609 | // and the word index (proper bits of the virtual address) |
---|
| 2610 | if ( tlb_flags.b ) // PTE1 |
---|
| 2611 | { |
---|
| 2612 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2613 | (paddr_t)((m_dreq.addr>>19) & 0x3c); |
---|
| 2614 | } |
---|
| 2615 | else // PTE2 |
---|
| 2616 | { |
---|
| 2617 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2618 | (paddr_t)((m_dreq.addr>>9) & 0x38); |
---|
| 2619 | } |
---|
| 2620 | r_dcache_fsm = DCACHE_DIRTY_GET_PTE; |
---|
| 2621 | r_dcache_p0_valid = false; |
---|
| 2622 | } |
---|
| 2623 | else // Write request accepted |
---|
| 2624 | { |
---|
[183] | 2625 | #ifdef INSTRUMENTATION |
---|
| 2626 | m_cpt_data_write++; |
---|
| 2627 | #endif |
---|
[206] | 2628 | m_drsp.valid = true; |
---|
| 2629 | m_drsp.rdata = 0; |
---|
| 2630 | r_dcache_p0_valid = true; |
---|
| 2631 | } |
---|
[183] | 2632 | } // end WRITE |
---|
| 2633 | |
---|
| 2634 | // SC request: |
---|
[205] | 2635 | // The SC requests are taken only if the write pipe-line is empty. |
---|
[206] | 2636 | // - if there is no valid registered LL, we just return rdata = 1 |
---|
| 2637 | // (atomic access failed) and the SC transaction is completed. |
---|
[183] | 2638 | // - if a valid LL reservation (with the same address) is registered, |
---|
[206] | 2639 | // we test if a DIRTY bit update is required. |
---|
| 2640 | // If the TLB is activated and the PTE Dirty bit is not set, we stall |
---|
| 2641 | // the processor and set the Dirty bit before handling the write request. |
---|
| 2642 | // If we don't need to set the Dirty bit, we request a SC transaction |
---|
| 2643 | // to CMD FSM and go to DCACHE_SC_WAIT state, that will return |
---|
| 2644 | // the response to the processor. |
---|
| 2645 | // We don't check a possible write hit in dcache, as the cache update |
---|
| 2646 | // is done by the coherence transaction induced by the SC... |
---|
[205] | 2647 | else if ( ( m_dreq.type == iss_t::DATA_SC ) |
---|
| 2648 | and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() ) |
---|
[183] | 2649 | { |
---|
[206] | 2650 | if ( (r_dcache_ll_vaddr.read() != m_dreq.addr) |
---|
| 2651 | or not r_dcache_ll_valid.read() ) // no valid registered LL |
---|
| 2652 | { |
---|
[183] | 2653 | #ifdef INSTRUMENTATION |
---|
| 2654 | m_cpt_data_sc++; |
---|
| 2655 | #endif |
---|
[205] | 2656 | m_drsp.valid = true; |
---|
| 2657 | m_drsp.rdata = 1; |
---|
| 2658 | r_dcache_ll_valid = false; |
---|
[183] | 2659 | } |
---|
[206] | 2660 | else // valid registered LL |
---|
| 2661 | { |
---|
| 2662 | if ( (r_mmu_mode.read() & DATA_TLB_MASK ) |
---|
| 2663 | and not tlb_flags.d ) // Dirty bit must be set |
---|
| 2664 | { |
---|
| 2665 | // The PTE physical address is obtained from the nline value (dtlb), |
---|
| 2666 | // and the word index (proper bits of the virtual address) |
---|
| 2667 | if ( tlb_flags.b ) // PTE1 |
---|
| 2668 | { |
---|
| 2669 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2670 | (paddr_t)((m_dreq.addr>>19) & 0x3c); |
---|
| 2671 | } |
---|
| 2672 | else // PTE2 |
---|
| 2673 | { |
---|
| 2674 | r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | |
---|
| 2675 | (paddr_t)((m_dreq.addr>>9) & 0x38); |
---|
| 2676 | } |
---|
| 2677 | r_dcache_fsm = DCACHE_DIRTY_GET_PTE; |
---|
| 2678 | } |
---|
| 2679 | else // SC request accepted |
---|
| 2680 | { |
---|
| 2681 | #ifdef INSTRUMENTATION |
---|
| 2682 | m_cpt_data_sc++; |
---|
| 2683 | #endif |
---|
| 2684 | |
---|
| 2685 | r_dcache_vci_paddr = paddr; |
---|
| 2686 | r_dcache_vci_sc_req = true; |
---|
| 2687 | r_dcache_vci_sc_old = r_dcache_ll_data.read(); |
---|
| 2688 | r_dcache_vci_sc_new = m_dreq.wdata; |
---|
| 2689 | r_dcache_ll_valid = false; |
---|
| 2690 | r_dcache_fsm = DCACHE_SC_WAIT; |
---|
| 2691 | } |
---|
| 2692 | } |
---|
[205] | 2693 | r_dcache_p0_valid = false; |
---|
[183] | 2694 | } // end SC |
---|
[205] | 2695 | else |
---|
| 2696 | { |
---|
| 2697 | r_dcache_p0_valid = false; |
---|
| 2698 | } |
---|
[183] | 2699 | } // end valid_req |
---|
[205] | 2700 | else |
---|
| 2701 | { |
---|
| 2702 | r_dcache_p0_valid = false; |
---|
| 2703 | } |
---|
| 2704 | } // end if read/write/ll/sc request |
---|
| 2705 | } // end dreq.valid |
---|
| 2706 | else |
---|
| 2707 | { |
---|
| 2708 | r_dcache_p0_valid = false; |
---|
[183] | 2709 | } // end P0 pipe stage |
---|
| 2710 | break; |
---|
| 2711 | } |
---|
| 2712 | ///////////////////// |
---|
[204] | 2713 | case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss. |
---|
[205] | 2714 | // Input arguments are: |
---|
| 2715 | // - r_dcache_tlb_vaddr |
---|
| 2716 | // - r_dcache_tlb_ins (true when itlb miss) |
---|
| 2717 | // The sub-fsm access the dcache to find the missing TLB entry, |
---|
| 2718 | // and activates the cache miss procedure in case of miss. |
---|
| 2719 | // It bypass the first level page table access if possible. |
---|
| 2720 | // It uses atomic access to update the R/L access bits |
---|
| 2721 | // in the page table if required. |
---|
| 2722 | // It directly updates the itlb or dtlb, and writes into the |
---|
| 2723 | // r_mmu_ins_* or r_mmu_data* error reporting registers. |
---|
[183] | 2724 | { |
---|
| 2725 | uint32_t ptba = 0; |
---|
| 2726 | bool bypass; |
---|
[205] | 2727 | paddr_t pte_paddr; |
---|
[183] | 2728 | |
---|
| 2729 | // evaluate bypass in order to skip first level page table access |
---|
| 2730 | if ( r_dcache_tlb_ins.read() ) // itlb miss |
---|
| 2731 | { |
---|
| 2732 | bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
| 2733 | } |
---|
| 2734 | else // dtlb miss |
---|
| 2735 | { |
---|
| 2736 | bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
| 2737 | } |
---|
| 2738 | |
---|
[205] | 2739 | if ( not bypass ) // Try to read PTE1/PTD1 in dcache |
---|
[183] | 2740 | { |
---|
[205] | 2741 | pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) | |
---|
| 2742 | (paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); |
---|
| 2743 | r_dcache_tlb_paddr = pte_paddr; |
---|
[183] | 2744 | r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
| 2745 | } |
---|
[205] | 2746 | else // Try to read PTE2 in dcache |
---|
[183] | 2747 | { |
---|
[205] | 2748 | pte_paddr = (paddr_t)ptba << PAGE_K_NBITS | |
---|
| 2749 | (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); |
---|
| 2750 | r_dcache_tlb_paddr = pte_paddr; |
---|
[183] | 2751 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
| 2752 | } |
---|
| 2753 | |
---|
| 2754 | #if DEBUG_DCACHE |
---|
| 2755 | if ( m_debug_dcache_fsm ) |
---|
| 2756 | { |
---|
| 2757 | if ( r_dcache_tlb_ins.read() ) |
---|
[205] | 2758 | { |
---|
| 2759 | std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss"; |
---|
| 2760 | } |
---|
| 2761 | else |
---|
| 2762 | { |
---|
| 2763 | std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss"; |
---|
| 2764 | } |
---|
| 2765 | std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() |
---|
| 2766 | << " / BYPASS = " << bypass |
---|
| 2767 | << " / PTE_ADR = " << pte_paddr << std::endl; |
---|
[183] | 2768 | } |
---|
| 2769 | #endif |
---|
| 2770 | |
---|
| 2771 | break; |
---|
| 2772 | } |
---|
| 2773 | ///////////////////////// |
---|
| 2774 | case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache |
---|
| 2775 | { |
---|
| 2776 | uint32_t entry; |
---|
| 2777 | size_t way; |
---|
| 2778 | size_t set; |
---|
| 2779 | size_t word; |
---|
| 2780 | |
---|
| 2781 | bool hit = r_dcache.read( r_dcache_tlb_paddr.read(), |
---|
| 2782 | &entry, |
---|
| 2783 | &way, |
---|
| 2784 | &set, |
---|
| 2785 | &word ); |
---|
| 2786 | #ifdef INSTRUMENTATION |
---|
| 2787 | m_cpt_dcache_data_read++; |
---|
| 2788 | m_cpt_dcache_dir_read++; |
---|
| 2789 | #endif |
---|
[204] | 2790 | if ( hit ) // hit in dcache |
---|
[183] | 2791 | { |
---|
| 2792 | if ( not (entry & PTE_V_MASK) ) // unmapped |
---|
| 2793 | { |
---|
| 2794 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2795 | { |
---|
| 2796 | r_mmu_ietr = MMU_READ_PT1_UNMAPPED; |
---|
| 2797 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 2798 | r_icache_tlb_miss_req = false; |
---|
| 2799 | r_icache_tlb_rsp_error = true; |
---|
| 2800 | } |
---|
| 2801 | else |
---|
| 2802 | { |
---|
| 2803 | r_mmu_detr = MMU_READ_PT1_UNMAPPED; |
---|
| 2804 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 2805 | m_drsp.valid = true; |
---|
| 2806 | m_drsp.error = true; |
---|
[183] | 2807 | } |
---|
| 2808 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 2809 | |
---|
| 2810 | #if DEBUG_DCACHE |
---|
| 2811 | if ( m_debug_dcache_fsm ) |
---|
| 2812 | { |
---|
[204] | 2813 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped" |
---|
| 2814 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
| 2815 | << std::dec << " / way = " << way |
---|
[183] | 2816 | << std::dec << " / set = " << set |
---|
| 2817 | << std::dec << " / word = " << word |
---|
| 2818 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
| 2819 | } |
---|
| 2820 | #endif |
---|
| 2821 | |
---|
| 2822 | } |
---|
[206] | 2823 | else if( entry & PTE_T_MASK ) // PTD : me must access PT2 |
---|
[183] | 2824 | { |
---|
[206] | 2825 | // mark the cache line ac containing a PTD |
---|
| 2826 | r_dcache_contains_ptd[m_dcache_sets*way+set] = true; |
---|
| 2827 | |
---|
[183] | 2828 | // register bypass |
---|
| 2829 | if ( r_dcache_tlb_ins.read() ) // itlb |
---|
| 2830 | { |
---|
| 2831 | r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
| 2832 | entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), |
---|
| 2833 | r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2))); |
---|
| 2834 | } |
---|
| 2835 | else // dtlb |
---|
| 2836 | { |
---|
| 2837 | r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
| 2838 | entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), |
---|
| 2839 | r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)); |
---|
| 2840 | } |
---|
| 2841 | r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | |
---|
| 2842 | (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); |
---|
| 2843 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
| 2844 | |
---|
| 2845 | #if DEBUG_DCACHE |
---|
| 2846 | if ( m_debug_dcache_fsm ) |
---|
| 2847 | { |
---|
[204] | 2848 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache" |
---|
| 2849 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
| 2850 | << std::dec << " / way = " << way |
---|
[183] | 2851 | << std::dec << " / set = " << set |
---|
| 2852 | << std::dec << " / word = " << word |
---|
| 2853 | << std::hex << " / PTD = " << entry << std::endl; |
---|
| 2854 | } |
---|
| 2855 | #endif |
---|
| 2856 | } |
---|
[206] | 2857 | else // PTE1 : we must update the TLB |
---|
[183] | 2858 | { |
---|
[206] | 2859 | r_dcache_in_tlb[m_icache_sets*way+set] = true; |
---|
[183] | 2860 | r_dcache_tlb_pte_flags = entry; |
---|
| 2861 | r_dcache_tlb_cache_way = way; |
---|
| 2862 | r_dcache_tlb_cache_set = set; |
---|
| 2863 | r_dcache_tlb_cache_word = word; |
---|
| 2864 | r_dcache_fsm = DCACHE_TLB_PTE1_SELECT; |
---|
| 2865 | |
---|
| 2866 | #if DEBUG_DCACHE |
---|
| 2867 | if ( m_debug_dcache_fsm ) |
---|
| 2868 | { |
---|
[204] | 2869 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache" |
---|
| 2870 | << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() |
---|
| 2871 | << std::dec << " / way = " << way |
---|
[183] | 2872 | << std::dec << " / set = " << set |
---|
| 2873 | << std::dec << " / word = " << word |
---|
| 2874 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
| 2875 | } |
---|
| 2876 | #endif |
---|
| 2877 | } |
---|
| 2878 | } |
---|
| 2879 | else // we must load the missing cache line in dcache |
---|
| 2880 | { |
---|
[205] | 2881 | r_dcache_vci_miss_req = true; |
---|
[183] | 2882 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
| 2883 | r_dcache_miss_type = PTE1_MISS; |
---|
| 2884 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
| 2885 | |
---|
| 2886 | #if DEBUG_DCACHE |
---|
| 2887 | if ( m_debug_dcache_fsm ) |
---|
| 2888 | { |
---|
| 2889 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:" |
---|
| 2890 | << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
| 2891 | } |
---|
| 2892 | #endif |
---|
| 2893 | } |
---|
| 2894 | break; |
---|
| 2895 | } |
---|
| 2896 | //////////////////////////// |
---|
| 2897 | case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 |
---|
| 2898 | { |
---|
| 2899 | size_t way; |
---|
| 2900 | size_t set; |
---|
| 2901 | |
---|
| 2902 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2903 | { |
---|
| 2904 | r_itlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 2905 | true, // PTE1 |
---|
| 2906 | &way, |
---|
| 2907 | &set ); |
---|
| 2908 | #ifdef INSTRUMENTATION |
---|
| 2909 | m_cpt_itlb_read++; |
---|
| 2910 | #endif |
---|
| 2911 | } |
---|
| 2912 | else |
---|
| 2913 | { |
---|
| 2914 | r_dtlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 2915 | true, // PTE1 |
---|
| 2916 | &way, |
---|
| 2917 | &set ); |
---|
| 2918 | #ifdef INSTRUMENTATION |
---|
| 2919 | m_cpt_dtlb_read++; |
---|
| 2920 | #endif |
---|
| 2921 | } |
---|
| 2922 | r_dcache_tlb_way = way; |
---|
| 2923 | r_dcache_tlb_set = set; |
---|
| 2924 | r_dcache_fsm = DCACHE_TLB_PTE1_UPDT; |
---|
| 2925 | |
---|
| 2926 | #if DEBUG_DCACHE |
---|
| 2927 | if ( m_debug_dcache_fsm ) |
---|
| 2928 | { |
---|
| 2929 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2930 | std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:"; |
---|
| 2931 | else |
---|
| 2932 | std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:"; |
---|
| 2933 | std::cout << " way = " << std::dec << way |
---|
| 2934 | << " / set = " << set << std::endl; |
---|
| 2935 | } |
---|
| 2936 | #endif |
---|
| 2937 | break; |
---|
| 2938 | } |
---|
| 2939 | ////////////////////////// |
---|
| 2940 | case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit |
---|
| 2941 | // if L/R bit already set, exit the sub-fsm |
---|
| 2942 | // if not, the page table must be updated |
---|
| 2943 | { |
---|
| 2944 | paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
| 2945 | uint32_t pte = r_dcache_tlb_pte_flags.read(); |
---|
| 2946 | bool updt = false; |
---|
[205] | 2947 | bool local = true; |
---|
[183] | 2948 | |
---|
[205] | 2949 | // We should compute the access locality: |
---|
| 2950 | // The PPN MSB bits define the destination cluster index. |
---|
| 2951 | // The m_srcid_d MSB bits define the source cluster index. |
---|
| 2952 | // The number of bits to compare depends on the number of clusters, |
---|
| 2953 | // and can be obtained in the mapping table. |
---|
| 2954 | // As long as this computation is not done, all access are local. |
---|
[183] | 2955 | |
---|
[205] | 2956 | if ( local ) // local access |
---|
[183] | 2957 | { |
---|
| 2958 | if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit |
---|
| 2959 | { |
---|
[205] | 2960 | updt = true; |
---|
| 2961 | r_dcache_vci_sc_old = pte; |
---|
| 2962 | r_dcache_vci_sc_new = pte | PTE_L_MASK; |
---|
| 2963 | pte = pte | PTE_L_MASK; |
---|
[183] | 2964 | } |
---|
| 2965 | } |
---|
[205] | 2966 | else // remote access |
---|
[183] | 2967 | { |
---|
| 2968 | if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit |
---|
| 2969 | { |
---|
| 2970 | updt = true; |
---|
[205] | 2971 | r_dcache_vci_sc_old = pte; |
---|
| 2972 | r_dcache_vci_sc_new = pte | PTE_R_MASK; |
---|
| 2973 | pte = pte | PTE_R_MASK; |
---|
[183] | 2974 | } |
---|
| 2975 | } |
---|
| 2976 | |
---|
| 2977 | // update TLB |
---|
| 2978 | if ( r_dcache_tlb_ins.read() ) |
---|
| 2979 | { |
---|
[202] | 2980 | r_itlb.write( true, // 2M page |
---|
| 2981 | pte, |
---|
| 2982 | 0, // argument unused for a PTE1 |
---|
[183] | 2983 | r_dcache_tlb_vaddr.read(), |
---|
| 2984 | r_dcache_tlb_way.read(), |
---|
| 2985 | r_dcache_tlb_set.read(), |
---|
| 2986 | nline ); |
---|
| 2987 | #ifdef INSTRUMENTATION |
---|
| 2988 | m_cpt_itlb_write++; |
---|
| 2989 | #endif |
---|
| 2990 | } |
---|
| 2991 | else |
---|
| 2992 | { |
---|
[202] | 2993 | r_dtlb.write( true, // 2M page |
---|
| 2994 | pte, |
---|
| 2995 | 0, // argument unused for a PTE1 |
---|
[183] | 2996 | r_dcache_tlb_vaddr.read(), |
---|
| 2997 | r_dcache_tlb_way.read(), |
---|
| 2998 | r_dcache_tlb_set.read(), |
---|
| 2999 | nline ); |
---|
| 3000 | #ifdef INSTRUMENTATION |
---|
| 3001 | m_cpt_dtlb_write++; |
---|
| 3002 | #endif |
---|
| 3003 | } |
---|
| 3004 | // next state |
---|
[205] | 3005 | if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update |
---|
[183] | 3006 | else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm |
---|
| 3007 | |
---|
| 3008 | #if DEBUG_DCACHE |
---|
| 3009 | if ( m_debug_dcache_fsm ) |
---|
| 3010 | { |
---|
| 3011 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3012 | { |
---|
[205] | 3013 | std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"; |
---|
| 3014 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 3015 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 3016 | r_itlb.printTrace(); |
---|
[183] | 3017 | } |
---|
| 3018 | else |
---|
| 3019 | { |
---|
[205] | 3020 | std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"; |
---|
| 3021 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 3022 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 3023 | r_dtlb.printTrace(); |
---|
[183] | 3024 | } |
---|
| 3025 | |
---|
| 3026 | } |
---|
| 3027 | #endif |
---|
| 3028 | break; |
---|
| 3029 | } |
---|
| 3030 | ///////////////////////// |
---|
| 3031 | case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache |
---|
| 3032 | { |
---|
| 3033 | uint32_t pte_flags; |
---|
| 3034 | uint32_t pte_ppn; |
---|
| 3035 | size_t way; |
---|
| 3036 | size_t set; |
---|
| 3037 | size_t word; |
---|
| 3038 | |
---|
| 3039 | bool hit = r_dcache.read( r_dcache_tlb_paddr.read(), |
---|
| 3040 | &pte_flags, |
---|
| 3041 | &pte_ppn, |
---|
| 3042 | &way, |
---|
| 3043 | &set, |
---|
| 3044 | &word ); |
---|
| 3045 | #ifdef INSTRUMENTATION |
---|
| 3046 | m_cpt_dcache_data_read++; |
---|
| 3047 | m_cpt_dcache_dir_read++; |
---|
| 3048 | #endif |
---|
| 3049 | if ( hit ) // request hits in dcache |
---|
| 3050 | { |
---|
| 3051 | if ( not (pte_flags & PTE_V_MASK) ) // unmapped |
---|
| 3052 | { |
---|
| 3053 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3054 | { |
---|
| 3055 | r_mmu_ietr = MMU_READ_PT2_UNMAPPED; |
---|
| 3056 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 3057 | r_icache_tlb_miss_req = false; |
---|
| 3058 | r_icache_tlb_rsp_error = true; |
---|
| 3059 | } |
---|
| 3060 | else |
---|
| 3061 | { |
---|
| 3062 | r_mmu_detr = MMU_READ_PT2_UNMAPPED; |
---|
| 3063 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 3064 | m_drsp.valid = true; |
---|
| 3065 | m_drsp.error = true; |
---|
[183] | 3066 | } |
---|
| 3067 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3068 | |
---|
| 3069 | #if DEBUG_DCACHE |
---|
| 3070 | if ( m_debug_dcache_fsm ) |
---|
| 3071 | { |
---|
| 3072 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped" |
---|
| 3073 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
| 3074 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
| 3075 | } |
---|
| 3076 | #endif |
---|
| 3077 | } |
---|
[206] | 3078 | else // mapped : we must update the TLB |
---|
[183] | 3079 | { |
---|
[206] | 3080 | r_dcache_in_tlb[m_dcache_sets*way+set] = true; |
---|
[183] | 3081 | r_dcache_tlb_pte_flags = pte_flags; |
---|
| 3082 | r_dcache_tlb_pte_ppn = pte_ppn; |
---|
| 3083 | r_dcache_tlb_cache_way = way; |
---|
| 3084 | r_dcache_tlb_cache_set = set; |
---|
| 3085 | r_dcache_tlb_cache_word = word; |
---|
| 3086 | r_dcache_fsm = DCACHE_TLB_PTE2_SELECT; |
---|
| 3087 | |
---|
| 3088 | #if DEBUG_DCACHE |
---|
| 3089 | if ( m_debug_dcache_fsm ) |
---|
| 3090 | { |
---|
| 3091 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:" |
---|
| 3092 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
| 3093 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
| 3094 | } |
---|
| 3095 | #endif |
---|
| 3096 | } |
---|
| 3097 | } |
---|
| 3098 | else // we must load the missing cache line in dcache |
---|
| 3099 | { |
---|
[205] | 3100 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
| 3101 | r_dcache_vci_miss_req = true; |
---|
[183] | 3102 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
| 3103 | r_dcache_miss_type = PTE2_MISS; |
---|
| 3104 | |
---|
| 3105 | #if DEBUG_DCACHE |
---|
| 3106 | if ( m_debug_dcache_fsm ) |
---|
| 3107 | { |
---|
| 3108 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:" |
---|
| 3109 | << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
| 3110 | } |
---|
| 3111 | #endif |
---|
| 3112 | } |
---|
| 3113 | break; |
---|
| 3114 | } |
---|
| 3115 | //////////////////////////// |
---|
| 3116 | case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2 |
---|
| 3117 | { |
---|
| 3118 | size_t way; |
---|
| 3119 | size_t set; |
---|
| 3120 | |
---|
| 3121 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3122 | { |
---|
| 3123 | r_itlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 3124 | false, // PTE2 |
---|
| 3125 | &way, |
---|
| 3126 | &set ); |
---|
| 3127 | #ifdef INSTRUMENTATION |
---|
| 3128 | m_cpt_itlb_read++; |
---|
| 3129 | #endif |
---|
| 3130 | } |
---|
| 3131 | else |
---|
| 3132 | { |
---|
| 3133 | r_dtlb.select( r_dcache_tlb_vaddr.read(), |
---|
| 3134 | false, // PTE2 |
---|
| 3135 | &way, |
---|
| 3136 | &set ); |
---|
| 3137 | #ifdef INSTRUMENTATION |
---|
| 3138 | m_cpt_dtlb_read++; |
---|
| 3139 | #endif |
---|
| 3140 | } |
---|
[205] | 3141 | |
---|
| 3142 | #if DEBUG_DCACHE |
---|
| 3143 | if ( m_debug_dcache_fsm ) |
---|
| 3144 | { |
---|
| 3145 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3146 | std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:"; |
---|
| 3147 | else |
---|
| 3148 | std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:"; |
---|
| 3149 | std::cout << " way = " << std::dec << way |
---|
| 3150 | << " / set = " << set << std::endl; |
---|
| 3151 | } |
---|
| 3152 | #endif |
---|
[183] | 3153 | r_dcache_tlb_way = way; |
---|
| 3154 | r_dcache_tlb_set = set; |
---|
| 3155 | r_dcache_fsm = DCACHE_TLB_PTE2_UPDT; |
---|
| 3156 | break; |
---|
| 3157 | } |
---|
| 3158 | ////////////////////////// |
---|
| 3159 | case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit |
---|
[205] | 3160 | // if L/R bit already set, exit the sub-fsm |
---|
[183] | 3161 | // if not, the page table must be updated by an atomic access |
---|
| 3162 | { |
---|
[205] | 3163 | paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
[183] | 3164 | uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); |
---|
| 3165 | uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); |
---|
[205] | 3166 | bool updt = false; |
---|
| 3167 | bool local = true; |
---|
[183] | 3168 | |
---|
[205] | 3169 | // We should compute the access locality: |
---|
| 3170 | // The PPN MSB bits define the destination cluster index. |
---|
| 3171 | // The m_srcid_d MSB bits define the source cluster index. |
---|
| 3172 | // The number of bits to compare depends on the number of clusters, |
---|
| 3173 | // and can be obtained in the mapping table. |
---|
| 3174 | // As long as this computation is not done, all access are local. |
---|
[183] | 3175 | |
---|
[205] | 3176 | if ( local ) // local access |
---|
[183] | 3177 | { |
---|
| 3178 | if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit |
---|
| 3179 | { |
---|
[205] | 3180 | updt = true; |
---|
| 3181 | r_dcache_vci_sc_old = pte_flags; |
---|
| 3182 | r_dcache_vci_sc_new = pte_flags | PTE_L_MASK; |
---|
| 3183 | pte_flags = pte_flags | PTE_L_MASK; |
---|
[183] | 3184 | } |
---|
| 3185 | } |
---|
[205] | 3186 | else // remote access |
---|
[183] | 3187 | { |
---|
| 3188 | if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit |
---|
| 3189 | { |
---|
| 3190 | updt = true; |
---|
[205] | 3191 | r_dcache_vci_sc_old = pte_flags; |
---|
| 3192 | r_dcache_vci_sc_new = pte_flags | PTE_R_MASK; |
---|
| 3193 | pte_flags = pte_flags | PTE_R_MASK; |
---|
[183] | 3194 | } |
---|
| 3195 | } |
---|
| 3196 | |
---|
| 3197 | // update TLB for a PTE2 |
---|
| 3198 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3199 | { |
---|
[205] | 3200 | r_itlb.write( false, // 4K page |
---|
[202] | 3201 | pte_flags, |
---|
[183] | 3202 | pte_ppn, |
---|
| 3203 | r_dcache_tlb_vaddr.read(), |
---|
| 3204 | r_dcache_tlb_way.read(), |
---|
| 3205 | r_dcache_tlb_set.read(), |
---|
| 3206 | nline ); |
---|
| 3207 | #ifdef INSTRUMENTATION |
---|
| 3208 | m_cpt_itlb_write++; |
---|
| 3209 | #endif |
---|
| 3210 | } |
---|
| 3211 | else |
---|
| 3212 | { |
---|
[205] | 3213 | r_dtlb.write( false, // 4K page |
---|
[202] | 3214 | pte_flags, |
---|
[183] | 3215 | pte_ppn, |
---|
| 3216 | r_dcache_tlb_vaddr.read(), |
---|
| 3217 | r_dcache_tlb_way.read(), |
---|
| 3218 | r_dcache_tlb_set.read(), |
---|
| 3219 | nline ); |
---|
| 3220 | #ifdef INSTRUMENTATION |
---|
| 3221 | m_cpt_dtlb_write++; |
---|
| 3222 | #endif |
---|
| 3223 | } |
---|
| 3224 | |
---|
| 3225 | #if DEBUG_DCACHE |
---|
| 3226 | if ( m_debug_dcache_fsm ) |
---|
| 3227 | { |
---|
| 3228 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3229 | { |
---|
[205] | 3230 | std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"; |
---|
| 3231 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 3232 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 3233 | r_itlb.printTrace(); |
---|
[183] | 3234 | } |
---|
| 3235 | else |
---|
| 3236 | { |
---|
[205] | 3237 | std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"; |
---|
| 3238 | std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() |
---|
| 3239 | << " / way = " << r_dcache_tlb_way.read() << std::endl; |
---|
| 3240 | r_dtlb.printTrace(); |
---|
[183] | 3241 | } |
---|
| 3242 | } |
---|
| 3243 | #endif |
---|
| 3244 | // next state |
---|
[205] | 3245 | if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update |
---|
[183] | 3246 | else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm |
---|
| 3247 | break; |
---|
| 3248 | } |
---|
| 3249 | //////////////////////// |
---|
[205] | 3250 | case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit), |
---|
[183] | 3251 | // request a SC transaction to CMD FSM |
---|
| 3252 | { |
---|
[204] | 3253 | #if DEBUG_DCACHE |
---|
| 3254 | if ( m_debug_dcache_fsm ) |
---|
| 3255 | { |
---|
[205] | 3256 | std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl; |
---|
[204] | 3257 | } |
---|
| 3258 | #endif |
---|
[183] | 3259 | r_dcache.write(r_dcache_tlb_cache_way.read(), |
---|
| 3260 | r_dcache_tlb_cache_set.read(), |
---|
| 3261 | r_dcache_tlb_cache_word.read(), |
---|
| 3262 | r_dcache_tlb_pte_flags.read()); |
---|
| 3263 | #ifdef INSTRUMENTATION |
---|
| 3264 | m_cpt_dcache_data_write++; |
---|
| 3265 | #endif |
---|
| 3266 | // r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set |
---|
[205] | 3267 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
[183] | 3268 | r_dcache_vci_sc_req = true; |
---|
[205] | 3269 | r_dcache_fsm = DCACHE_TLB_LR_WAIT; |
---|
[183] | 3270 | break; |
---|
| 3271 | } |
---|
| 3272 | //////////////////////// |
---|
[205] | 3273 | case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction. |
---|
[204] | 3274 | // We consume the response in rsp FIFO, |
---|
| 3275 | // and exit the sub-fsm, but we don't |
---|
| 3276 | // analyse the response, because we don't |
---|
| 3277 | // care if the L/R bit update is not done. |
---|
| 3278 | // We must take the coherence requests because |
---|
[199] | 3279 | // there is a risk of dead-lock |
---|
| 3280 | |
---|
[183] | 3281 | { |
---|
[199] | 3282 | // external coherence request |
---|
| 3283 | if ( r_tgt_dcache_req ) |
---|
| 3284 | { |
---|
[217] | 3285 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
| 3286 | r_dcache_fsm_cc_save = r_dcache_fsm.read(); |
---|
[199] | 3287 | break; |
---|
| 3288 | } |
---|
| 3289 | |
---|
[204] | 3290 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
[183] | 3291 | { |
---|
[205] | 3292 | std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl; |
---|
[204] | 3293 | std::cout << "This should not happen in this state" << std::endl; |
---|
| 3294 | exit(0); |
---|
[183] | 3295 | } |
---|
[204] | 3296 | else if ( r_vci_rsp_fifo_dcache.rok() ) // response available |
---|
| 3297 | { |
---|
| 3298 | #if DEBUG_DCACHE |
---|
| 3299 | if ( m_debug_dcache_fsm ) |
---|
| 3300 | { |
---|
[205] | 3301 | std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl; |
---|
[204] | 3302 | } |
---|
| 3303 | #endif |
---|
| 3304 | vci_rsp_fifo_dcache_get = true; |
---|
| 3305 | r_dcache_fsm = DCACHE_TLB_RETURN; |
---|
| 3306 | } |
---|
[183] | 3307 | break; |
---|
| 3308 | } |
---|
| 3309 | /////////////////////// |
---|
[204] | 3310 | case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type |
---|
[183] | 3311 | { |
---|
[204] | 3312 | #if DEBUG_DCACHE |
---|
| 3313 | if ( m_debug_dcache_fsm ) |
---|
| 3314 | { |
---|
| 3315 | std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl; |
---|
| 3316 | } |
---|
| 3317 | #endif |
---|
[183] | 3318 | if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false; |
---|
| 3319 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3320 | break; |
---|
| 3321 | } |
---|
| 3322 | /////////////////////// |
---|
| 3323 | case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed |
---|
| 3324 | { |
---|
[196] | 3325 | if ( not r_dcache_xtn_req.read() ) |
---|
[183] | 3326 | { |
---|
| 3327 | r_dtlb.flush(); |
---|
| 3328 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3329 | m_drsp.valid = true; |
---|
[183] | 3330 | } |
---|
| 3331 | break; |
---|
| 3332 | } |
---|
| 3333 | ///////////////////// |
---|
| 3334 | case DCACHE_XTN_SYNC: // waiting until write buffer empty |
---|
[196] | 3335 | // The coherence request must be taken |
---|
| 3336 | // as there is a risk of dead-lock |
---|
[183] | 3337 | { |
---|
[196] | 3338 | // external coherence request |
---|
| 3339 | if ( r_tgt_dcache_req.read() ) |
---|
| 3340 | { |
---|
[217] | 3341 | r_dcache_fsm_cc_save = r_dcache_fsm.read(); |
---|
| 3342 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
[196] | 3343 | } |
---|
| 3344 | |
---|
[183] | 3345 | if ( r_wbuf.empty() ) |
---|
| 3346 | { |
---|
[205] | 3347 | m_drsp.valid = true; |
---|
[183] | 3348 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3349 | } |
---|
[193] | 3350 | break; |
---|
[183] | 3351 | } |
---|
| 3352 | //////////////////////// |
---|
| 3353 | case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM |
---|
| 3354 | case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken |
---|
| 3355 | case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache |
---|
| 3356 | case DCACHE_XTN_IT_INVAL: // can generate an itlb miss... |
---|
| 3357 | { |
---|
| 3358 | // external coherence request |
---|
| 3359 | if ( r_tgt_dcache_req ) |
---|
| 3360 | { |
---|
[217] | 3361 | r_dcache_fsm_cc_save = r_dcache_fsm.read(); |
---|
| 3362 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
[183] | 3363 | break; |
---|
| 3364 | } |
---|
| 3365 | |
---|
| 3366 | // itlb miss request |
---|
| 3367 | if ( r_icache_tlb_miss_req.read() ) |
---|
| 3368 | { |
---|
| 3369 | r_dcache_tlb_ins = true; |
---|
| 3370 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
| 3371 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
| 3372 | break; |
---|
| 3373 | } |
---|
| 3374 | |
---|
| 3375 | // test if XTN request to icache completed |
---|
| 3376 | if ( not r_dcache_xtn_req.read() ) |
---|
| 3377 | { |
---|
| 3378 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3379 | m_drsp.valid = true; |
---|
[183] | 3380 | } |
---|
| 3381 | break; |
---|
| 3382 | } |
---|
| 3383 | ///////////////////////// |
---|
| 3384 | case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using |
---|
| 3385 | // the r_dcache_flush counter as a slot counter. |
---|
| 3386 | // We loop in this state until all slots have been visited. |
---|
| 3387 | // A cleanup request is generated for each valid line |
---|
| 3388 | // and we are blocked until the previous cleanup is completed |
---|
| 3389 | // Finally, both the itlb and dtlb are reset, because |
---|
| 3390 | // all TLB entries (including global entries) must be invalidated. |
---|
| 3391 | { |
---|
| 3392 | if ( not r_dcache_cleanup_req ) |
---|
| 3393 | { |
---|
| 3394 | paddr_t nline; |
---|
| 3395 | size_t way = r_dcache_flush_count.read()/m_icache_sets; |
---|
| 3396 | size_t set = r_dcache_flush_count.read()%m_icache_sets; |
---|
| 3397 | |
---|
| 3398 | bool cleanup_req = r_dcache.inval( way, |
---|
[198] | 3399 | set, |
---|
| 3400 | &nline ); |
---|
[183] | 3401 | if ( cleanup_req ) |
---|
| 3402 | { |
---|
| 3403 | r_dcache_cleanup_req = true; |
---|
| 3404 | r_dcache_cleanup_line = nline; |
---|
| 3405 | } |
---|
| 3406 | |
---|
| 3407 | r_dcache_flush_count = r_dcache_flush_count.read() + 1; |
---|
| 3408 | |
---|
| 3409 | if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot |
---|
| 3410 | { |
---|
[206] | 3411 | r_dtlb.reset(); |
---|
| 3412 | r_itlb.reset(); |
---|
[183] | 3413 | for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++) |
---|
| 3414 | { |
---|
[206] | 3415 | r_dcache_in_tlb[line] = false; |
---|
| 3416 | r_dcache_contains_ptd[line] = false; |
---|
[183] | 3417 | } |
---|
| 3418 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3419 | m_drsp.valid = true; |
---|
[183] | 3420 | } |
---|
| 3421 | } |
---|
| 3422 | break; |
---|
| 3423 | } |
---|
| 3424 | ///////////////////////// |
---|
| 3425 | case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request |
---|
| 3426 | { |
---|
| 3427 | r_dtlb.inval(r_dcache_p0_wdata.read()); |
---|
| 3428 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3429 | m_drsp.valid = true; |
---|
[183] | 3430 | break; |
---|
| 3431 | } |
---|
| 3432 | //////////////////////////// |
---|
| 3433 | case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address |
---|
| 3434 | // requires 3 cycles: access tlb, read cache, inval cache |
---|
| 3435 | // we compute the physical address in this state |
---|
| 3436 | { |
---|
| 3437 | paddr_t paddr; |
---|
| 3438 | bool hit; |
---|
| 3439 | |
---|
| 3440 | if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated |
---|
| 3441 | { |
---|
| 3442 | #ifdef INSTRUMENTATION |
---|
| 3443 | m_cpt_dtlb_read++; |
---|
| 3444 | #endif |
---|
| 3445 | hit = r_dtlb.translate( r_dcache_p0_wdata.read(), |
---|
| 3446 | &paddr ); |
---|
| 3447 | } |
---|
| 3448 | else // dtlb not activated |
---|
| 3449 | { |
---|
| 3450 | paddr = (paddr_t)r_dcache_p0_wdata.read(); |
---|
| 3451 | hit = true; |
---|
| 3452 | } |
---|
| 3453 | |
---|
| 3454 | if ( hit ) // tlb hit |
---|
| 3455 | { |
---|
| 3456 | r_dcache_p0_paddr = paddr; |
---|
| 3457 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
| 3458 | } |
---|
| 3459 | else // tlb miss |
---|
| 3460 | { |
---|
| 3461 | #ifdef INSTRUMENTATION |
---|
| 3462 | m_cpt_dtlb_miss++; |
---|
| 3463 | #endif |
---|
| 3464 | r_dcache_tlb_ins = false; // dtlb |
---|
| 3465 | r_dcache_tlb_vaddr = r_dcache_p0_wdata.read(); |
---|
| 3466 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
| 3467 | } |
---|
[206] | 3468 | |
---|
| 3469 | #if DEBUG_DCACHE |
---|
| 3470 | if ( m_debug_dcache_fsm ) |
---|
| 3471 | { |
---|
| 3472 | std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex |
---|
| 3473 | << " / VADDR = " << r_dcache_p0_wdata.read() |
---|
| 3474 | << " / PADDR = " << paddr << std::endl; |
---|
| 3475 | } |
---|
| 3476 | #endif |
---|
| 3477 | |
---|
[183] | 3478 | break; |
---|
| 3479 | } |
---|
| 3480 | //////////////////////////// |
---|
| 3481 | case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address |
---|
| 3482 | // requires 2 cycles: read cache / inval cache |
---|
| 3483 | // In this state we read dcache. |
---|
| 3484 | { |
---|
| 3485 | uint32_t data; |
---|
| 3486 | size_t way; |
---|
| 3487 | size_t set; |
---|
| 3488 | size_t word; |
---|
| 3489 | bool hit = r_dcache.read( r_dcache_p0_paddr.read(), |
---|
| 3490 | &data, |
---|
| 3491 | &way, |
---|
| 3492 | &set, |
---|
| 3493 | &word ); |
---|
| 3494 | #ifdef INSTRUMENTATION |
---|
| 3495 | m_cpt_dcache_data_read++; |
---|
| 3496 | m_cpt_dcache_dir_read++; |
---|
| 3497 | #endif |
---|
| 3498 | if ( hit ) // inval to be done |
---|
| 3499 | { |
---|
| 3500 | r_dcache_xtn_way = way; |
---|
| 3501 | r_dcache_xtn_set = set; |
---|
| 3502 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; |
---|
| 3503 | } |
---|
| 3504 | else // miss : nothing to do |
---|
| 3505 | { |
---|
| 3506 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3507 | m_drsp.valid = true; |
---|
[183] | 3508 | } |
---|
[206] | 3509 | |
---|
| 3510 | #if DEBUG_DCACHE |
---|
| 3511 | if ( m_debug_dcache_fsm ) |
---|
| 3512 | { |
---|
| 3513 | std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex |
---|
| 3514 | << " / PADDR = " << r_dcache_p0_paddr.read() << std::dec |
---|
| 3515 | << " / HIT = " << hit |
---|
| 3516 | << " / SET = " << set |
---|
| 3517 | << " / WAY = " << way << std::endl; |
---|
| 3518 | } |
---|
| 3519 | #endif |
---|
[183] | 3520 | break; |
---|
| 3521 | } |
---|
| 3522 | //////////////////////////// |
---|
[206] | 3523 | case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line |
---|
[183] | 3524 | // Blocked if previous cleanup not completed |
---|
[204] | 3525 | // Test if itlb or dtlb inval is required |
---|
[183] | 3526 | { |
---|
| 3527 | if ( not r_dcache_cleanup_req.read() ) |
---|
| 3528 | { |
---|
| 3529 | paddr_t nline; |
---|
[204] | 3530 | size_t way = r_dcache_xtn_way.read(); |
---|
| 3531 | size_t set = r_dcache_xtn_set.read(); |
---|
[213] | 3532 | bool hit; |
---|
[183] | 3533 | |
---|
[213] | 3534 | hit = r_dcache.inval( way, |
---|
| 3535 | set, |
---|
| 3536 | &nline ); |
---|
| 3537 | assert(hit && "XTN_DC_INVAL way/set should still be in cache"); |
---|
[183] | 3538 | |
---|
| 3539 | // request cleanup |
---|
| 3540 | r_dcache_cleanup_req = true; |
---|
| 3541 | r_dcache_cleanup_line = nline; |
---|
| 3542 | |
---|
[206] | 3543 | // possible itlb & dtlb invalidate |
---|
| 3544 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) |
---|
[183] | 3545 | { |
---|
[204] | 3546 | r_dcache_tlb_inval_line = nline; |
---|
| 3547 | r_dcache_tlb_inval_count = 0; |
---|
[217] | 3548 | r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; |
---|
[204] | 3549 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
[206] | 3550 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[183] | 3551 | } |
---|
[206] | 3552 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) |
---|
| 3553 | { |
---|
| 3554 | r_itlb.reset(); |
---|
| 3555 | r_dtlb.reset(); |
---|
| 3556 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
| 3557 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3558 | m_drsp.valid = true; |
---|
| 3559 | } |
---|
[183] | 3560 | else |
---|
| 3561 | { |
---|
| 3562 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3563 | m_drsp.valid = true; |
---|
[183] | 3564 | } |
---|
[206] | 3565 | |
---|
| 3566 | #if DEBUG_DCACHE |
---|
| 3567 | if ( m_debug_dcache_fsm ) |
---|
| 3568 | { |
---|
| 3569 | std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex |
---|
| 3570 | << " / NLINE = " << nline << std::endl; |
---|
| 3571 | } |
---|
| 3572 | #endif |
---|
[183] | 3573 | } |
---|
| 3574 | break; |
---|
| 3575 | } |
---|
| 3576 | ////////////////////////////// |
---|
[206] | 3577 | case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request |
---|
[183] | 3578 | { |
---|
[204] | 3579 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3580 | m_drsp.valid = true; |
---|
[183] | 3581 | break; |
---|
| 3582 | } |
---|
| 3583 | //////////////////////// |
---|
| 3584 | case DCACHE_MISS_VICTIM: // Selects a victim line |
---|
| 3585 | // Set the r_dcache_cleanup_req flip-flop |
---|
| 3586 | // when the selected slot is not empty |
---|
| 3587 | { |
---|
| 3588 | bool valid; |
---|
| 3589 | size_t way; |
---|
| 3590 | size_t set; |
---|
| 3591 | paddr_t victim; |
---|
| 3592 | |
---|
| 3593 | valid = r_dcache.victim_select( r_dcache_vci_paddr.read(), |
---|
| 3594 | &victim, |
---|
| 3595 | &way, |
---|
| 3596 | &set ); |
---|
| 3597 | r_dcache_miss_way = way; |
---|
| 3598 | r_dcache_miss_set = set; |
---|
| 3599 | |
---|
| 3600 | if ( valid ) |
---|
| 3601 | { |
---|
| 3602 | r_dcache_cleanup_req = true; |
---|
| 3603 | r_dcache_cleanup_line = victim; |
---|
| 3604 | r_dcache_fsm = DCACHE_MISS_INVAL; |
---|
| 3605 | } |
---|
| 3606 | else |
---|
| 3607 | { |
---|
| 3608 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
| 3609 | } |
---|
| 3610 | |
---|
| 3611 | #if DEBUG_DCACHE |
---|
| 3612 | if ( m_debug_dcache_fsm ) |
---|
| 3613 | { |
---|
[198] | 3614 | std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" |
---|
[183] | 3615 | << " / way = " << way |
---|
| 3616 | << " / set = " << set |
---|
| 3617 | << " / valid = " << valid |
---|
[196] | 3618 | << " / line = " << std::hex << victim << std::endl; |
---|
[183] | 3619 | } |
---|
| 3620 | #endif |
---|
| 3621 | break; |
---|
| 3622 | } |
---|
| 3623 | /////////////////////// |
---|
| 3624 | case DCACHE_MISS_INVAL: // invalidate the victim line |
---|
[198] | 3625 | // and possibly request itlb or dtlb invalidate |
---|
[183] | 3626 | { |
---|
| 3627 | paddr_t nline; |
---|
[206] | 3628 | size_t way = r_dcache_miss_way.read(); |
---|
| 3629 | size_t set = r_dcache_miss_set.read(); |
---|
[210] | 3630 | bool hit; |
---|
[183] | 3631 | |
---|
[210] | 3632 | hit = r_dcache.inval( way, |
---|
[198] | 3633 | set, |
---|
| 3634 | &nline ); |
---|
[219] | 3635 | |
---|
[210] | 3636 | assert(hit && "selected way/set line should be in dcache"); |
---|
[183] | 3637 | |
---|
[210] | 3638 | #if DEBUG_DCACHE |
---|
| 3639 | if ( m_debug_dcache_fsm ) |
---|
| 3640 | { |
---|
| 3641 | std::cout << " <PROC.DCACHE_MISS_INVAL> inval line:" |
---|
| 3642 | << " / way = " << way |
---|
| 3643 | << " / set = " << set |
---|
| 3644 | << " / nline = " << std::hex << nline << std::endl; |
---|
| 3645 | } |
---|
| 3646 | #endif |
---|
[206] | 3647 | // if selective itlb & dtlb invalidate are required |
---|
[183] | 3648 | // the miss response is not handled before invalidate completed |
---|
[206] | 3649 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) |
---|
[183] | 3650 | { |
---|
[220] | 3651 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[206] | 3652 | r_dcache_tlb_inval_line = nline; |
---|
| 3653 | r_dcache_tlb_inval_count = 0; |
---|
[217] | 3654 | r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; |
---|
[220] | 3655 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
[183] | 3656 | } |
---|
[206] | 3657 | else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) |
---|
[183] | 3658 | { |
---|
[206] | 3659 | r_itlb.reset(); |
---|
| 3660 | r_dtlb.reset(); |
---|
[219] | 3661 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
| 3662 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
[183] | 3663 | } |
---|
[206] | 3664 | else |
---|
| 3665 | { |
---|
[219] | 3666 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
[206] | 3667 | } |
---|
[183] | 3668 | break; |
---|
| 3669 | } |
---|
| 3670 | ////////////////////// |
---|
| 3671 | case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM |
---|
| 3672 | // This state is in charge of error signaling |
---|
| 3673 | // There is 5 types of error depending on the requester |
---|
| 3674 | { |
---|
| 3675 | // external coherence request |
---|
| 3676 | if ( r_tgt_dcache_req ) |
---|
| 3677 | { |
---|
[217] | 3678 | r_dcache_fsm_cc_save = r_dcache_fsm; |
---|
| 3679 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
[183] | 3680 | break; |
---|
| 3681 | } |
---|
| 3682 | |
---|
| 3683 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3684 | { |
---|
| 3685 | switch ( r_dcache_miss_type.read() ) |
---|
| 3686 | { |
---|
| 3687 | case PROC_MISS: |
---|
| 3688 | { |
---|
| 3689 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
| 3690 | r_mmu_dbvar = r_dcache_p0_vaddr.read(); |
---|
[205] | 3691 | m_drsp.valid = true; |
---|
| 3692 | m_drsp.error = true; |
---|
[183] | 3693 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3694 | break; |
---|
| 3695 | } |
---|
| 3696 | case PTE1_MISS: |
---|
| 3697 | { |
---|
| 3698 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3699 | { |
---|
| 3700 | r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
| 3701 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 3702 | r_icache_tlb_miss_req = false; |
---|
| 3703 | r_icache_tlb_rsp_error = true; |
---|
| 3704 | } |
---|
| 3705 | else |
---|
| 3706 | { |
---|
| 3707 | r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
| 3708 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 3709 | m_drsp.valid = true; |
---|
| 3710 | m_drsp.error = true; |
---|
[183] | 3711 | } |
---|
| 3712 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3713 | break; |
---|
| 3714 | } |
---|
| 3715 | case PTE2_MISS: |
---|
| 3716 | { |
---|
| 3717 | if ( r_dcache_tlb_ins.read() ) |
---|
| 3718 | { |
---|
| 3719 | r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
| 3720 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
| 3721 | r_icache_tlb_miss_req = false; |
---|
| 3722 | r_icache_tlb_rsp_error = true; |
---|
| 3723 | } |
---|
| 3724 | else |
---|
| 3725 | { |
---|
| 3726 | r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
| 3727 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
[205] | 3728 | m_drsp.valid = true; |
---|
| 3729 | m_drsp.error = true; |
---|
[183] | 3730 | } |
---|
| 3731 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3732 | break; |
---|
| 3733 | } |
---|
| 3734 | } // end switch type |
---|
| 3735 | r_vci_rsp_data_error = false; |
---|
| 3736 | } |
---|
| 3737 | else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available |
---|
| 3738 | { |
---|
| 3739 | r_dcache_miss_word = 0; |
---|
[198] | 3740 | r_dcache_fsm = DCACHE_MISS_UPDT; |
---|
[194] | 3741 | } |
---|
[183] | 3742 | break; |
---|
| 3743 | } |
---|
| 3744 | ////////////////////// |
---|
| 3745 | case DCACHE_MISS_UPDT: // update the dcache (one word per cycle) |
---|
| 3746 | // returns the response depending on the miss type |
---|
| 3747 | { |
---|
| 3748 | if ( r_vci_rsp_fifo_dcache.rok() ) // one word available |
---|
| 3749 | { |
---|
| 3750 | if ( r_dcache_miss_inval.read() ) // Matching coherence request |
---|
| 3751 | // pop the FIFO, without cache update |
---|
| 3752 | // send a cleanup for the missing line |
---|
| 3753 | // if the previous cleanup is completed |
---|
| 3754 | { |
---|
| 3755 | if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last |
---|
| 3756 | { |
---|
| 3757 | vci_rsp_fifo_dcache_get = true; |
---|
| 3758 | r_dcache_miss_word = r_dcache_miss_word.read() + 1; |
---|
| 3759 | } |
---|
| 3760 | else // last word |
---|
| 3761 | { |
---|
| 3762 | if ( not r_dcache_cleanup_req.read() ) // no pending cleanup |
---|
| 3763 | { |
---|
| 3764 | vci_rsp_fifo_dcache_get = true; |
---|
| 3765 | r_dcache_cleanup_req = true; |
---|
| 3766 | r_dcache_cleanup_line = r_dcache_vci_paddr.read() >> |
---|
| 3767 | (uint32_log2(m_dcache_words)+2); |
---|
| 3768 | r_dcache_miss_inval = false; |
---|
| 3769 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3770 | } |
---|
| 3771 | } |
---|
| 3772 | } |
---|
| 3773 | else // No matching coherence request |
---|
| 3774 | // pop the FIFO and update the cache |
---|
| 3775 | // update the directory at the last word |
---|
| 3776 | { |
---|
[206] | 3777 | size_t way = r_dcache_miss_way.read(); |
---|
| 3778 | size_t set = r_dcache_miss_set.read(); |
---|
| 3779 | size_t word = r_dcache_miss_word.read(); |
---|
[183] | 3780 | |
---|
| 3781 | #ifdef INSTRUMENTATION |
---|
| 3782 | m_cpt_dcache_data_write++; |
---|
| 3783 | #endif |
---|
[206] | 3784 | r_dcache.write( way, |
---|
| 3785 | set, |
---|
| 3786 | word, |
---|
[183] | 3787 | r_vci_rsp_fifo_dcache.read()); |
---|
| 3788 | |
---|
| 3789 | vci_rsp_fifo_dcache_get = true; |
---|
| 3790 | r_dcache_miss_word = r_dcache_miss_word.read() + 1; |
---|
| 3791 | |
---|
[206] | 3792 | // if last word, update directory, set in_tlb & contains_ptd bits |
---|
[183] | 3793 | if ( r_dcache_miss_word.read() == (m_dcache_words - 1) ) |
---|
| 3794 | { |
---|
| 3795 | |
---|
| 3796 | #ifdef INSTRUMENTATION |
---|
| 3797 | m_cpt_dcache_dir_write++; |
---|
| 3798 | #endif |
---|
| 3799 | r_dcache.victim_update_tag( r_dcache_vci_paddr.read(), |
---|
| 3800 | r_dcache_miss_way.read(), |
---|
| 3801 | r_dcache_miss_set.read() ); |
---|
[206] | 3802 | |
---|
| 3803 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
| 3804 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
[183] | 3805 | |
---|
| 3806 | if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
| 3807 | else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
| 3808 | else r_dcache_fsm = DCACHE_IDLE; |
---|
| 3809 | } |
---|
| 3810 | } |
---|
| 3811 | |
---|
| 3812 | #if DEBUG_DCACHE |
---|
| 3813 | if ( m_debug_dcache_fsm ) |
---|
| 3814 | { |
---|
| 3815 | if ( r_dcache_miss_inval.read() ) |
---|
| 3816 | { |
---|
| 3817 | if ( r_dcache_miss_word.read() < m_dcache_words-1 ) |
---|
| 3818 | { |
---|
| 3819 | std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:" |
---|
| 3820 | << " pop the FIFO, don't update the cache" << std::endl; |
---|
| 3821 | } |
---|
| 3822 | else |
---|
| 3823 | { |
---|
| 3824 | std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:" |
---|
| 3825 | << " last word : send a cleanup request " << std::endl; |
---|
| 3826 | } |
---|
| 3827 | } |
---|
| 3828 | else |
---|
| 3829 | { |
---|
[198] | 3830 | std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:" |
---|
[183] | 3831 | << " address = " << r_dcache_vci_paddr.read() |
---|
| 3832 | << " / data = " << r_vci_rsp_fifo_dcache.read() |
---|
| 3833 | << " / way = " << r_dcache_miss_way.read() |
---|
| 3834 | << " / set = " << r_dcache_miss_set.read() |
---|
| 3835 | << " / word = " << r_dcache_miss_word.read() << std::endl; |
---|
| 3836 | } |
---|
| 3837 | } |
---|
| 3838 | #endif |
---|
| 3839 | |
---|
| 3840 | } // end if rok |
---|
| 3841 | break; |
---|
| 3842 | } |
---|
| 3843 | ///////////////////// |
---|
| 3844 | case DCACHE_UNC_WAIT: |
---|
| 3845 | { |
---|
| 3846 | // external coherence request |
---|
| 3847 | if ( r_tgt_dcache_req.read() ) |
---|
| 3848 | { |
---|
[217] | 3849 | r_dcache_fsm_cc_save = r_dcache_fsm; |
---|
| 3850 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
[183] | 3851 | break; |
---|
| 3852 | } |
---|
| 3853 | |
---|
| 3854 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3855 | { |
---|
| 3856 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
[205] | 3857 | r_mmu_dbvar = m_dreq.addr; |
---|
[183] | 3858 | r_vci_rsp_data_error = false; |
---|
[205] | 3859 | m_drsp.error = true; |
---|
| 3860 | m_drsp.valid = true; |
---|
[183] | 3861 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3862 | break; |
---|
| 3863 | } |
---|
| 3864 | else if ( r_vci_rsp_fifo_dcache.rok() ) // data available |
---|
| 3865 | { |
---|
| 3866 | vci_rsp_fifo_dcache_get = true; |
---|
| 3867 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3868 | // we acknowledge the processor request if it has not been modified |
---|
[205] | 3869 | if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) ) |
---|
[183] | 3870 | { |
---|
[205] | 3871 | m_drsp.valid = true; |
---|
| 3872 | m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
[183] | 3873 | } |
---|
| 3874 | } |
---|
| 3875 | break; |
---|
| 3876 | } |
---|
[205] | 3877 | //////////////////// |
---|
| 3878 | case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request |
---|
| 3879 | { |
---|
| 3880 | // external coherence request |
---|
| 3881 | if ( r_tgt_dcache_req.read() ) |
---|
| 3882 | { |
---|
[217] | 3883 | r_dcache_fsm_cc_save = r_dcache_fsm; |
---|
| 3884 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
[205] | 3885 | break; |
---|
| 3886 | } |
---|
| 3887 | |
---|
| 3888 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3889 | { |
---|
| 3890 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
| 3891 | r_mmu_dbvar = m_dreq.addr; |
---|
| 3892 | r_vci_rsp_data_error = false; |
---|
| 3893 | m_drsp.error = true; |
---|
| 3894 | m_drsp.valid = true; |
---|
| 3895 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3896 | break; |
---|
| 3897 | } |
---|
| 3898 | else if ( r_vci_rsp_fifo_dcache.rok() ) // response available |
---|
| 3899 | { |
---|
| 3900 | vci_rsp_fifo_dcache_get = true; |
---|
[206] | 3901 | m_drsp.valid = true; |
---|
| 3902 | m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
| 3903 | r_dcache_fsm = DCACHE_IDLE; |
---|
[205] | 3904 | } |
---|
| 3905 | break; |
---|
| 3906 | } |
---|
| 3907 | ////////////////////////// |
---|
[206] | 3908 | case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory |
---|
| 3909 | // before handling a processor WRITE or SC request |
---|
| 3910 | // Input argument is r_dcache_dirty_paddr |
---|
| 3911 | // In this first state, we get PTE value in dcache |
---|
| 3912 | // and post a SC request to CMD FSM |
---|
[183] | 3913 | { |
---|
| 3914 | // get PTE in dcache |
---|
[206] | 3915 | uint32_t pte; |
---|
[183] | 3916 | size_t way; |
---|
| 3917 | size_t set; |
---|
[206] | 3918 | size_t word; // unused |
---|
| 3919 | bool hit = r_dcache.read( r_dcache_dirty_paddr.read(), |
---|
[204] | 3920 | &pte, |
---|
[183] | 3921 | &way, |
---|
| 3922 | &set, |
---|
| 3923 | &word ); |
---|
| 3924 | #ifdef INSTRUMENTATION |
---|
| 3925 | m_cpt_dcache_data_read++; |
---|
| 3926 | m_cpt_dcache_dir_read++; |
---|
[209] | 3927 | #endif |
---|
[205] | 3928 | assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" ); |
---|
[183] | 3929 | |
---|
[205] | 3930 | // request sc transaction to CMD_FSM |
---|
[206] | 3931 | r_dcache_dirty_way = way; |
---|
| 3932 | r_dcache_dirty_set = set; |
---|
[205] | 3933 | r_dcache_vci_sc_req = true; |
---|
[206] | 3934 | r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); |
---|
| 3935 | r_dcache_vci_sc_old = pte; |
---|
| 3936 | r_dcache_vci_sc_new = pte | PTE_D_MASK; |
---|
| 3937 | r_dcache_fsm = DCACHE_DIRTY_SC_WAIT; |
---|
[205] | 3938 | |
---|
[183] | 3939 | #if DEBUG_DCACHE |
---|
| 3940 | if ( m_debug_dcache_fsm ) |
---|
| 3941 | { |
---|
[206] | 3942 | std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex |
---|
| 3943 | << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() |
---|
| 3944 | << " / PTE_VALUE = " << pte << std::dec |
---|
| 3945 | << " / CACHE_SET = " << set |
---|
| 3946 | << " / CACHE_WAY = " << way << std::endl; |
---|
[183] | 3947 | } |
---|
| 3948 | #endif |
---|
| 3949 | break; |
---|
| 3950 | } |
---|
| 3951 | ////////////////////////// |
---|
[205] | 3952 | case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit |
---|
[206] | 3953 | // If the PTE update is a success, return to IDLE state. |
---|
| 3954 | // If the PTE update is a failure, invalidate the cache line |
---|
| 3955 | // in DCACHE and invalidate the matching TLB entries. |
---|
[183] | 3956 | { |
---|
| 3957 | // external coherence request |
---|
| 3958 | if ( r_tgt_dcache_req ) |
---|
| 3959 | { |
---|
[217] | 3960 | r_dcache_fsm_cc_save = r_dcache_fsm; |
---|
| 3961 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
[183] | 3962 | break; |
---|
| 3963 | } |
---|
| 3964 | |
---|
| 3965 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
| 3966 | { |
---|
[205] | 3967 | std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl; |
---|
| 3968 | std::cout << "This should not happen in this state" << std::endl; |
---|
| 3969 | exit(0); |
---|
[183] | 3970 | } |
---|
| 3971 | else if ( r_vci_rsp_fifo_dcache.rok() ) // response available |
---|
| 3972 | { |
---|
[205] | 3973 | vci_rsp_fifo_dcache_get = true; |
---|
| 3974 | if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic |
---|
[183] | 3975 | { |
---|
[206] | 3976 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 3977 | |
---|
| 3978 | #if DEBUG_DCACHE |
---|
| 3979 | if ( m_debug_dcache_fsm ) |
---|
| 3980 | { |
---|
| 3981 | std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set" |
---|
| 3982 | << std::endl; |
---|
| 3983 | } |
---|
| 3984 | #endif |
---|
| 3985 | } |
---|
[217] | 3986 | else // invalidate the cache line and TLBs |
---|
[206] | 3987 | { |
---|
| 3988 | paddr_t nline; |
---|
| 3989 | size_t way = r_dcache_dirty_way.read(); |
---|
| 3990 | size_t set = r_dcache_dirty_set.read(); |
---|
[213] | 3991 | bool hit; |
---|
[206] | 3992 | |
---|
[213] | 3993 | hit = r_dcache.inval( r_dcache_dirty_way.read(), |
---|
[206] | 3994 | r_dcache_dirty_set.read(), |
---|
| 3995 | &nline ); |
---|
[213] | 3996 | assert(hit && "PTE should still be in dcache"); |
---|
| 3997 | // request cleanup |
---|
| 3998 | r_dcache_cleanup_req = true; |
---|
| 3999 | r_dcache_cleanup_line = nline; |
---|
[206] | 4000 | |
---|
| 4001 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE |
---|
[205] | 4002 | { |
---|
[206] | 4003 | r_dcache_tlb_inval_line = nline; |
---|
| 4004 | r_dcache_tlb_inval_count = 0; |
---|
[217] | 4005 | r_dcache_fsm_scan_save = DCACHE_IDLE; |
---|
[206] | 4006 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
| 4007 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
| 4008 | } |
---|
| 4009 | if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD |
---|
[205] | 4010 | { |
---|
[206] | 4011 | r_itlb.reset(); |
---|
| 4012 | r_dtlb.reset(); |
---|
[219] | 4013 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
[205] | 4014 | r_dcache_fsm = DCACHE_IDLE; |
---|
| 4015 | } |
---|
[206] | 4016 | #if DEBUG_DCACHE |
---|
| 4017 | if ( m_debug_dcache_fsm ) |
---|
| 4018 | { |
---|
| 4019 | std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs" |
---|
| 4020 | << std::endl; |
---|
| 4021 | } |
---|
| 4022 | #endif |
---|
[183] | 4023 | } |
---|
| 4024 | } |
---|
| 4025 | break; |
---|
| 4026 | } |
---|
| 4027 | ///////////////////// |
---|
| 4028 | case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM |
---|
| 4029 | // handling coherence requests. |
---|
| 4030 | // If there is a matching pending miss on the modified cache |
---|
| 4031 | // line this is signaled in the r_dcache_miss inval flip-flop. |
---|
| 4032 | // If the updated (or invalidated) cache line has copies in TLBs |
---|
| 4033 | // these TLB copies are invalidated. |
---|
[217] | 4034 | // The return state is defined in r_dcache_fsm_cc_save |
---|
[183] | 4035 | { |
---|
| 4036 | paddr_t paddr = r_tgt_paddr.read(); |
---|
| 4037 | paddr_t mask = ~((m_dcache_words<<2)-1); |
---|
| 4038 | |
---|
| 4039 | |
---|
[217] | 4040 | if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and |
---|
[183] | 4041 | ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss |
---|
| 4042 | { |
---|
| 4043 | r_dcache_miss_inval = true; // signaling the match |
---|
| 4044 | r_tgt_dcache_req = false; // coherence request completed |
---|
| 4045 | r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update |
---|
[217] | 4046 | r_dcache_fsm = r_dcache_fsm_cc_save.read(); |
---|
[183] | 4047 | |
---|
| 4048 | #if DEBUG_DCACHE |
---|
| 4049 | if ( m_debug_dcache_fsm ) |
---|
| 4050 | { |
---|
| 4051 | std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:" |
---|
| 4052 | << " address = " << std::hex << paddr << std::endl; |
---|
| 4053 | } |
---|
| 4054 | #endif |
---|
| 4055 | |
---|
| 4056 | } |
---|
| 4057 | else // no match |
---|
| 4058 | { |
---|
| 4059 | uint32_t rdata; |
---|
| 4060 | size_t way; |
---|
| 4061 | size_t set; |
---|
| 4062 | size_t word; |
---|
| 4063 | |
---|
| 4064 | bool hit = r_dcache.read(paddr, |
---|
| 4065 | &rdata, // unused |
---|
| 4066 | &way, |
---|
| 4067 | &set, |
---|
| 4068 | &word); // unused |
---|
| 4069 | #ifdef INSTRUMENTATION |
---|
| 4070 | m_cpt_dcache_data_read++; |
---|
| 4071 | m_cpt_dcache_dir_read++; |
---|
| 4072 | #endif |
---|
| 4073 | r_dcache_cc_way = way; |
---|
| 4074 | r_dcache_cc_set = set; |
---|
| 4075 | |
---|
| 4076 | if ( hit and r_tgt_update.read() ) // hit update |
---|
| 4077 | { |
---|
| 4078 | r_dcache_fsm = DCACHE_CC_UPDT; |
---|
| 4079 | r_dcache_cc_word = r_tgt_word_min.read(); |
---|
| 4080 | } |
---|
| 4081 | else if ( hit and not r_tgt_update.read() ) // hit inval |
---|
| 4082 | { |
---|
| 4083 | r_dcache_fsm = DCACHE_CC_INVAL; |
---|
| 4084 | } |
---|
| 4085 | else // miss can happen |
---|
| 4086 | { |
---|
| 4087 | r_tgt_dcache_req = false; |
---|
| 4088 | r_tgt_dcache_rsp = r_tgt_update.read(); |
---|
[217] | 4089 | r_dcache_fsm = r_dcache_fsm_cc_save.read(); |
---|
[183] | 4090 | } |
---|
| 4091 | |
---|
| 4092 | #if DEBUG_DCACHE |
---|
| 4093 | if ( m_debug_dcache_fsm ) |
---|
| 4094 | { |
---|
| 4095 | |
---|
| 4096 | std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :" |
---|
| 4097 | << " address = " << std::hex << paddr << std::dec; |
---|
| 4098 | if ( hit ) |
---|
| 4099 | { |
---|
| 4100 | std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl; |
---|
| 4101 | } |
---|
| 4102 | else |
---|
| 4103 | { |
---|
| 4104 | std::cout << " / MISS" << std::endl; |
---|
| 4105 | } |
---|
| 4106 | } |
---|
| 4107 | #endif |
---|
| 4108 | |
---|
| 4109 | } |
---|
| 4110 | break; |
---|
| 4111 | } |
---|
| 4112 | ///////////////////// |
---|
| 4113 | case DCACHE_CC_INVAL: // invalidate one cache line |
---|
| 4114 | // and test possible copies in TLBs |
---|
| 4115 | { |
---|
| 4116 | paddr_t nline; |
---|
[204] | 4117 | size_t way = r_dcache_cc_way.read(); |
---|
| 4118 | size_t set = r_dcache_cc_set.read(); |
---|
[213] | 4119 | bool hit; |
---|
[183] | 4120 | |
---|
[221] | 4121 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval |
---|
[183] | 4122 | { |
---|
[219] | 4123 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[204] | 4124 | r_dcache_tlb_inval_line = nline; |
---|
| 4125 | r_dcache_tlb_inval_count = 0; |
---|
[217] | 4126 | r_dcache_fsm_scan_save = r_dcache_fsm.read(); |
---|
[204] | 4127 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
[183] | 4128 | } |
---|
[221] | 4129 | else // actual cache line inval |
---|
[183] | 4130 | { |
---|
[221] | 4131 | if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush |
---|
| 4132 | { |
---|
| 4133 | r_itlb.reset(); |
---|
| 4134 | r_dtlb.reset(); |
---|
| 4135 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
| 4136 | } |
---|
[183] | 4137 | r_tgt_dcache_rsp = true; |
---|
| 4138 | r_tgt_dcache_req = false; |
---|
[217] | 4139 | r_dcache_fsm = r_dcache_fsm_cc_save.read(); |
---|
[221] | 4140 | |
---|
| 4141 | hit = r_dcache.inval( way, |
---|
| 4142 | set, |
---|
| 4143 | &nline ); |
---|
[183] | 4144 | #if DEBUG_DCACHE |
---|
| 4145 | if ( m_debug_dcache_fsm ) |
---|
| 4146 | { |
---|
[206] | 4147 | std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec |
---|
| 4148 | << " / WAY = " << way |
---|
| 4149 | << " / SET = " << set << std::endl; |
---|
[183] | 4150 | } |
---|
| 4151 | #endif |
---|
| 4152 | |
---|
[221] | 4153 | assert(hit && "CC_INVAL way/set should still be in dcache"); |
---|
| 4154 | } |
---|
[183] | 4155 | break; |
---|
| 4156 | } |
---|
| 4157 | /////////////////// |
---|
| 4158 | case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max) |
---|
| 4159 | // and test possible copies in TLBs |
---|
| 4160 | { |
---|
[204] | 4161 | size_t word = r_dcache_cc_word.read(); |
---|
| 4162 | size_t way = r_dcache_cc_way.read(); |
---|
| 4163 | size_t set = r_dcache_cc_set.read(); |
---|
| 4164 | paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
[183] | 4165 | |
---|
[221] | 4166 | if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval |
---|
[218] | 4167 | { |
---|
[219] | 4168 | r_dcache_in_tlb[way*m_dcache_sets+set] = false; |
---|
[218] | 4169 | r_dcache_tlb_inval_line = nline; |
---|
| 4170 | r_dcache_tlb_inval_count = 0; |
---|
| 4171 | r_dcache_fsm_scan_save = r_dcache_fsm.read(); |
---|
| 4172 | r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; |
---|
| 4173 | } |
---|
[221] | 4174 | else // cache update |
---|
[218] | 4175 | { |
---|
[221] | 4176 | if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush |
---|
| 4177 | { |
---|
| 4178 | r_itlb.reset(); |
---|
| 4179 | r_dtlb.reset(); |
---|
| 4180 | r_dcache_contains_ptd[way*m_dcache_sets+set] = false; |
---|
| 4181 | } |
---|
| 4182 | |
---|
[218] | 4183 | r_dcache.write( way, |
---|
| 4184 | set, |
---|
| 4185 | word, |
---|
| 4186 | r_tgt_buf[word], |
---|
| 4187 | r_tgt_be[word] ); |
---|
[183] | 4188 | #ifdef INSTRUMENTATION |
---|
| 4189 | m_cpt_dcache_data_write++; |
---|
| 4190 | #endif |
---|
[218] | 4191 | r_dcache_cc_word = word + 1; |
---|
[183] | 4192 | |
---|
| 4193 | #if DEBUG_DCACHE |
---|
| 4194 | if ( m_debug_dcache_fsm ) |
---|
| 4195 | { |
---|
[206] | 4196 | std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec |
---|
| 4197 | << " / WAY = " << way |
---|
| 4198 | << " / SET = " << set |
---|
| 4199 | << " / WORD = " << word |
---|
| 4200 | << " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl; |
---|
[183] | 4201 | } |
---|
| 4202 | #endif |
---|
[221] | 4203 | if ( word == r_tgt_word_max.read() ) // last word |
---|
| 4204 | { |
---|
| 4205 | r_tgt_dcache_rsp = true; |
---|
| 4206 | r_tgt_dcache_req = false; |
---|
| 4207 | r_dcache_fsm = r_dcache_fsm_cc_save.read(); |
---|
| 4208 | } |
---|
| 4209 | } |
---|
| 4210 | |
---|
[183] | 4211 | break; |
---|
| 4212 | } |
---|
[204] | 4213 | /////////////////////////// |
---|
[206] | 4214 | case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB |
---|
[204] | 4215 | // It makes the assumption that (m_itlb_sets == m_dtlb_sets) |
---|
| 4216 | // and (m_itlb_ways == m_dtlb_ways) |
---|
[206] | 4217 | // We enter this state when a DCACHE line is modified, |
---|
[204] | 4218 | // and there is a copy in itlb or dtlb. |
---|
[206] | 4219 | // It can be caused by: |
---|
| 4220 | // - a coherence inval or updt transaction, |
---|
| 4221 | // - a line inval caused by a cache miss |
---|
| 4222 | // - a processor XTN inval request, |
---|
| 4223 | // - a WRITE hit, |
---|
| 4224 | // - a Dirty bit update failure |
---|
| 4225 | // Input arguments are: |
---|
[204] | 4226 | // - r_dcache_tlb_inval_line |
---|
| 4227 | // - r_dcache_tlb_inval_count |
---|
[217] | 4228 | // - r_dcache_fsm_cc_save |
---|
[183] | 4229 | { |
---|
[204] | 4230 | paddr_t line = r_dcache_tlb_inval_line.read(); // nline |
---|
| 4231 | size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way |
---|
| 4232 | size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set |
---|
[206] | 4233 | bool ok; |
---|
[204] | 4234 | |
---|
[206] | 4235 | ok = r_itlb.inval( line, |
---|
| 4236 | way, |
---|
| 4237 | set ); |
---|
[204] | 4238 | #if DEBUG_DCACHE |
---|
| 4239 | if ( m_debug_dcache_fsm and ok ) |
---|
| 4240 | { |
---|
| 4241 | std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex |
---|
| 4242 | << " line = " << line << std::dec |
---|
| 4243 | << " / set = " << set |
---|
| 4244 | << " / way = " << way << std::endl; |
---|
[205] | 4245 | r_itlb.printTrace(); |
---|
[204] | 4246 | } |
---|
| 4247 | #endif |
---|
[206] | 4248 | ok = r_dtlb.inval( line, |
---|
| 4249 | way, |
---|
| 4250 | set ); |
---|
[204] | 4251 | #if DEBUG_DCACHE |
---|
| 4252 | if ( m_debug_dcache_fsm and ok ) |
---|
| 4253 | { |
---|
| 4254 | std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex |
---|
| 4255 | << " line = " << line << std::dec |
---|
| 4256 | << " / set = " << set |
---|
| 4257 | << " / way = " << way << std::endl; |
---|
[205] | 4258 | r_dtlb.printTrace(); |
---|
[204] | 4259 | } |
---|
| 4260 | #endif |
---|
| 4261 | |
---|
| 4262 | // return to the calling state when TLB inval completed |
---|
| 4263 | if ( r_dcache_tlb_inval_count.read() == (m_dtlb_sets*m_dtlb_ways-1) ) |
---|
| 4264 | { |
---|
[217] | 4265 | r_dcache_fsm = r_dcache_fsm_scan_save.read(); |
---|
[204] | 4266 | } |
---|
| 4267 | r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1; |
---|
[183] | 4268 | } |
---|
| 4269 | } // end switch r_dcache_fsm |
---|
| 4270 | |
---|
| 4271 | ///////////////// wbuf update ////////////////////////////////////////////////////// |
---|
| 4272 | r_wbuf.update(); |
---|
| 4273 | |
---|
[205] | 4274 | //////////////// test processor frozen ///////////////////////////////////////////// |
---|
[183] | 4275 | // The simulation exit if the number of consecutive frozen cycles |
---|
| 4276 | // is larger than the m_max_frozen_cycles (constructor parameter) |
---|
[205] | 4277 | if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) ) |
---|
[183] | 4278 | { |
---|
| 4279 | m_cpt_frz_cycles++; // used for instrumentation |
---|
| 4280 | m_cpt_stop_simulation++; // used for debug |
---|
| 4281 | if ( m_cpt_stop_simulation > m_max_frozen_cycles ) |
---|
| 4282 | { |
---|
| 4283 | std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl |
---|
| 4284 | << " stop at cycle " << m_cpt_total_cycles << std::endl |
---|
| 4285 | << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles |
---|
| 4286 | << std::endl; |
---|
| 4287 | exit(1); |
---|
| 4288 | } |
---|
| 4289 | } |
---|
| 4290 | else |
---|
| 4291 | { |
---|
| 4292 | m_cpt_stop_simulation = 0; |
---|
| 4293 | } |
---|
| 4294 | |
---|
| 4295 | /////////// execute one iss cycle ///////////////////////////////// |
---|
| 4296 | { |
---|
| 4297 | uint32_t it = 0; |
---|
| 4298 | for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i); |
---|
[205] | 4299 | r_iss.executeNCycles(1, m_irsp, m_drsp, it); |
---|
[183] | 4300 | } |
---|
| 4301 | |
---|
| 4302 | //////////////////////////////////////////////////////////////////////////// |
---|
| 4303 | // The VCI_CMD FSM controls the following ressources: |
---|
| 4304 | // - r_vci_cmd_fsm |
---|
| 4305 | // - r_vci_cmd_min |
---|
| 4306 | // - r_vci_cmd_max |
---|
| 4307 | // - r_vci_cmd_cpt |
---|
| 4308 | // - r_vci_cmd_imiss_prio |
---|
| 4309 | // - wbuf (reset) |
---|
| 4310 | // - r_icache_miss_req (reset) |
---|
| 4311 | // - r_icache_unc_req (reset) |
---|
| 4312 | // - r_dcache_vci_miss_req (reset) |
---|
| 4313 | // - r_dcache_vci_unc_req (reset) |
---|
| 4314 | // - r_dcache_vci_sc_req (reset) |
---|
| 4315 | // |
---|
| 4316 | // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM. |
---|
| 4317 | // There is 6 request types, with the following priorities : |
---|
| 4318 | // 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer |
---|
| 4319 | // 2 - Data Read Uncachable : r_dcache_vci_unc_req |
---|
| 4320 | // 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer |
---|
| 4321 | // 4 - Instruction Uncachable : r_icache_unc_req |
---|
| 4322 | // 5 - Data Write : r_wbuf.rok() |
---|
| 4323 | // 6 - Data Store Conditionnal: r_dcache_vci_sc_req |
---|
| 4324 | // |
---|
| 4325 | // As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM |
---|
| 4326 | // and the VCI_RSP_FSM are fully desynchronized. |
---|
| 4327 | // |
---|
| 4328 | // VCI formats: |
---|
| 4329 | // According to the VCI advanced specification, all read requests packets |
---|
| 4330 | // (data Uncached, Miss data, instruction Uncached, Miss instruction) |
---|
| 4331 | // are one word packets. |
---|
| 4332 | // For write burst packets, all words are in the same cache line, |
---|
| 4333 | // and addresses must be contiguous (the BE field is 0 in case of "holes"). |
---|
| 4334 | // The sc command packet implements actually a compare-and-swap mechanism |
---|
| 4335 | // and the packet contains two flits. |
---|
| 4336 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 4337 | |
---|
| 4338 | switch ( r_vci_cmd_fsm.read() ) |
---|
| 4339 | { |
---|
| 4340 | ////////////// |
---|
| 4341 | case CMD_IDLE: |
---|
| 4342 | { |
---|
| 4343 | // r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access |
---|
| 4344 | // to check a possible pending write on the same cache line. |
---|
| 4345 | // As there is only one possible access per cycle to write buffer, we implement |
---|
| 4346 | // a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop. |
---|
| 4347 | |
---|
| 4348 | size_t wbuf_min; |
---|
| 4349 | size_t wbuf_max; |
---|
| 4350 | |
---|
| 4351 | bool dcache_miss_req = r_dcache_vci_miss_req.read() |
---|
| 4352 | and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); |
---|
[217] | 4353 | |
---|
[183] | 4354 | bool icache_miss_req = r_icache_miss_req.read() |
---|
| 4355 | and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() ); |
---|
| 4356 | |
---|
| 4357 | // 1 - Data Read Miss |
---|
| 4358 | if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) |
---|
| 4359 | { |
---|
| 4360 | r_vci_cmd_fsm = CMD_DATA_MISS; |
---|
| 4361 | r_dcache_vci_miss_req = false; |
---|
| 4362 | r_vci_cmd_imiss_prio = true; |
---|
| 4363 | // m_cpt_dmiss_transaction++; |
---|
| 4364 | } |
---|
| 4365 | // 2 - Data Read Uncachable |
---|
| 4366 | else if ( r_dcache_vci_unc_req.read() ) |
---|
| 4367 | { |
---|
| 4368 | r_vci_cmd_fsm = CMD_DATA_UNC; |
---|
| 4369 | r_dcache_vci_unc_req = false; |
---|
| 4370 | // m_cpt_dunc_transaction++; |
---|
| 4371 | } |
---|
| 4372 | // 3 - Instruction Miss |
---|
| 4373 | else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) ) |
---|
| 4374 | { |
---|
| 4375 | r_vci_cmd_fsm = CMD_INS_MISS; |
---|
| 4376 | r_icache_miss_req = false; |
---|
| 4377 | r_vci_cmd_imiss_prio = false; |
---|
[198] | 4378 | // m_cpt_imiss_transaction++; |
---|
[183] | 4379 | } |
---|
| 4380 | // 4 - Instruction Uncachable |
---|
| 4381 | else if ( r_icache_unc_req.read() ) |
---|
| 4382 | { |
---|
| 4383 | r_vci_cmd_fsm = CMD_INS_UNC; |
---|
| 4384 | r_icache_unc_req = false; |
---|
[198] | 4385 | // m_cpt_iunc_transaction++; |
---|
[183] | 4386 | } |
---|
| 4387 | // 5 - Data Write |
---|
| 4388 | else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) ) |
---|
| 4389 | { |
---|
| 4390 | r_vci_cmd_fsm = CMD_DATA_WRITE; |
---|
| 4391 | r_vci_cmd_cpt = wbuf_min; |
---|
| 4392 | r_vci_cmd_min = wbuf_min; |
---|
| 4393 | r_vci_cmd_max = wbuf_max; |
---|
[198] | 4394 | // m_cpt_write_transaction++; |
---|
| 4395 | // m_length_write_transaction += (wbuf_max-wbuf_min+1); |
---|
[183] | 4396 | } |
---|
| 4397 | // 6 - Data Store Conditionnal |
---|
| 4398 | else if ( r_dcache_vci_sc_req.read() ) |
---|
| 4399 | { |
---|
| 4400 | r_vci_cmd_fsm = CMD_DATA_SC; |
---|
[204] | 4401 | r_dcache_vci_sc_req = false; |
---|
[183] | 4402 | r_vci_cmd_cpt = 0; |
---|
| 4403 | // m_cpt_sc_transaction++; |
---|
| 4404 | } |
---|
| 4405 | break; |
---|
| 4406 | } |
---|
| 4407 | //////////////////// |
---|
| 4408 | case CMD_DATA_WRITE: |
---|
| 4409 | { |
---|
| 4410 | if ( p_vci_ini_d.cmdack.read() ) |
---|
| 4411 | { |
---|
| 4412 | // m_conso_wbuf_read++; |
---|
| 4413 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
| 4414 | if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent |
---|
| 4415 | { |
---|
| 4416 | r_vci_cmd_fsm = CMD_IDLE ; |
---|
| 4417 | r_wbuf.sent() ; |
---|
| 4418 | } |
---|
| 4419 | } |
---|
| 4420 | break; |
---|
| 4421 | } |
---|
| 4422 | ///////////////// |
---|
| 4423 | case CMD_DATA_SC: |
---|
| 4424 | { |
---|
| 4425 | // The SC VCI command contains two flits |
---|
| 4426 | if ( p_vci_ini_d.cmdack.read() ) |
---|
| 4427 | { |
---|
| 4428 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
| 4429 | if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ; |
---|
| 4430 | } |
---|
| 4431 | break; |
---|
| 4432 | } |
---|
| 4433 | ////////////////// |
---|
| 4434 | case CMD_INS_MISS: |
---|
| 4435 | case CMD_INS_UNC: |
---|
| 4436 | case CMD_DATA_MISS: |
---|
| 4437 | case CMD_DATA_UNC: |
---|
| 4438 | { |
---|
| 4439 | // all read VCI commands contain one single flit |
---|
| 4440 | if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE; |
---|
| 4441 | break; |
---|
| 4442 | } |
---|
| 4443 | |
---|
| 4444 | } // end switch r_vci_cmd_fsm |
---|
| 4445 | |
---|
| 4446 | ////////////////////////////////////////////////////////////////////////// |
---|
| 4447 | // The VCI_RSP FSM controls the following ressources: |
---|
| 4448 | // - r_vci_rsp_fsm: |
---|
| 4449 | // - r_vci_rsp_fifo_icache (push) |
---|
| 4450 | // - r_vci_rsp_fifo_dcache (push) |
---|
| 4451 | // - r_vci_rsp_data_error (set) |
---|
| 4452 | // - r_vci_rsp_ins_error (set) |
---|
| 4453 | // - r_vci_rsp_cpt |
---|
| 4454 | // |
---|
| 4455 | // As the VCI_RSP and VCI_CMD are fully desynchronized to support several |
---|
| 4456 | // simultaneous VCI transactions, this FSM uses the VCI TRDID field |
---|
| 4457 | // to identify the transactions. |
---|
| 4458 | // |
---|
| 4459 | // VCI vormat: |
---|
| 4460 | // This component checks the response packet length and accepts only |
---|
| 4461 | // single word packets for write response packets. |
---|
| 4462 | // |
---|
| 4463 | // Error handling: |
---|
| 4464 | // This FSM analyzes the VCI error code and signals directly the Write Bus Error. |
---|
| 4465 | // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error |
---|
| 4466 | // flip_flop and the error is signaled by the DCACHE FSM. |
---|
| 4467 | // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error |
---|
| 4468 | // flip_flop and the error is signaled by the ICACHE FSM. |
---|
| 4469 | // In case of Cleanup Error, the simulation stops with an error message... |
---|
| 4470 | ////////////////////////////////////////////////////////////////////////// |
---|
| 4471 | |
---|
| 4472 | switch ( r_vci_rsp_fsm.read() ) |
---|
| 4473 | { |
---|
| 4474 | ////////////// |
---|
| 4475 | case RSP_IDLE: |
---|
| 4476 | { |
---|
| 4477 | if ( p_vci_ini_d.rspval.read() ) |
---|
| 4478 | { |
---|
| 4479 | r_vci_rsp_cpt = 0; |
---|
| 4480 | |
---|
| 4481 | if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction |
---|
| 4482 | { |
---|
| 4483 | r_vci_rsp_fsm = RSP_DATA_WRITE; |
---|
| 4484 | } |
---|
| 4485 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS ) |
---|
| 4486 | { |
---|
| 4487 | r_vci_rsp_fsm = RSP_INS_MISS; |
---|
| 4488 | } |
---|
| 4489 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC ) |
---|
| 4490 | { |
---|
| 4491 | r_vci_rsp_fsm = RSP_INS_UNC; |
---|
| 4492 | } |
---|
| 4493 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS ) |
---|
| 4494 | { |
---|
| 4495 | r_vci_rsp_fsm = RSP_DATA_MISS; |
---|
| 4496 | } |
---|
| 4497 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC ) |
---|
| 4498 | { |
---|
| 4499 | r_vci_rsp_fsm = RSP_DATA_UNC; |
---|
| 4500 | } |
---|
| 4501 | else |
---|
| 4502 | { |
---|
| 4503 | assert(false and "Unexpected VCI response"); |
---|
| 4504 | } |
---|
| 4505 | } |
---|
| 4506 | break; |
---|
| 4507 | } |
---|
| 4508 | ////////////////// |
---|
| 4509 | case RSP_INS_MISS: |
---|
| 4510 | { |
---|
| 4511 | if ( p_vci_ini_d.rspval.read() ) |
---|
| 4512 | { |
---|
| 4513 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4514 | { |
---|
| 4515 | r_vci_rsp_ins_error = true; |
---|
| 4516 | if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4517 | } |
---|
| 4518 | else // no error reported |
---|
| 4519 | { |
---|
| 4520 | if ( r_vci_rsp_fifo_icache.wok() ) |
---|
| 4521 | { |
---|
| 4522 | assert( (r_vci_rsp_cpt.read() < m_icache_words) and |
---|
| 4523 | "The VCI response packet for instruction miss is too long" ); |
---|
| 4524 | |
---|
| 4525 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
| 4526 | vci_rsp_fifo_icache_put = true, |
---|
| 4527 | vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); |
---|
| 4528 | if ( p_vci_ini_d.reop.read() ) |
---|
| 4529 | { |
---|
| 4530 | assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and |
---|
| 4531 | "The VCI response packet for instruction miss is too short"); |
---|
| 4532 | |
---|
| 4533 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4534 | } |
---|
| 4535 | } |
---|
| 4536 | } |
---|
| 4537 | } |
---|
| 4538 | break; |
---|
| 4539 | } |
---|
| 4540 | ///////////////// |
---|
| 4541 | case RSP_INS_UNC: |
---|
| 4542 | { |
---|
| 4543 | if (p_vci_ini_d.rspval.read() ) |
---|
| 4544 | { |
---|
| 4545 | assert( p_vci_ini_d.reop.read() and |
---|
| 4546 | "illegal VCI response packet for uncachable instruction"); |
---|
| 4547 | |
---|
| 4548 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4549 | { |
---|
| 4550 | r_vci_rsp_ins_error = true; |
---|
| 4551 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4552 | } |
---|
| 4553 | else // no error reported |
---|
| 4554 | { |
---|
| 4555 | if ( r_vci_rsp_fifo_icache.wok()) |
---|
| 4556 | { |
---|
| 4557 | vci_rsp_fifo_icache_put = true; |
---|
| 4558 | vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); |
---|
| 4559 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4560 | } |
---|
| 4561 | } |
---|
| 4562 | } |
---|
| 4563 | break; |
---|
| 4564 | } |
---|
| 4565 | /////////////////// |
---|
| 4566 | case RSP_DATA_MISS: |
---|
| 4567 | { |
---|
| 4568 | if ( p_vci_ini_d.rspval.read() ) |
---|
| 4569 | { |
---|
| 4570 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4571 | { |
---|
| 4572 | r_vci_rsp_data_error = true; |
---|
| 4573 | if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4574 | } |
---|
| 4575 | else // no error reported |
---|
| 4576 | { |
---|
| 4577 | if ( r_vci_rsp_fifo_dcache.wok() ) |
---|
| 4578 | { |
---|
| 4579 | assert( (r_vci_rsp_cpt.read() < m_dcache_words) and |
---|
| 4580 | "The VCI response packet for data miss is too long"); |
---|
| 4581 | |
---|
| 4582 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
| 4583 | vci_rsp_fifo_dcache_put = true, |
---|
| 4584 | vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); |
---|
| 4585 | if ( p_vci_ini_d.reop.read() ) |
---|
| 4586 | { |
---|
| 4587 | assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and |
---|
| 4588 | "The VCI response packet for data miss is too short"); |
---|
| 4589 | |
---|
| 4590 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4591 | } |
---|
| 4592 | } |
---|
| 4593 | } |
---|
| 4594 | } |
---|
| 4595 | break; |
---|
| 4596 | } |
---|
| 4597 | ////////////////// |
---|
| 4598 | case RSP_DATA_UNC: |
---|
| 4599 | { |
---|
| 4600 | if (p_vci_ini_d.rspval.read() ) |
---|
| 4601 | { |
---|
| 4602 | assert( p_vci_ini_d.reop.read() and |
---|
| 4603 | "illegal VCI response packet for uncachable read data"); |
---|
| 4604 | |
---|
| 4605 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
| 4606 | { |
---|
| 4607 | r_vci_rsp_data_error = true; |
---|
| 4608 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4609 | } |
---|
| 4610 | else // no error reported |
---|
| 4611 | { |
---|
| 4612 | if ( r_vci_rsp_fifo_dcache.wok()) |
---|
| 4613 | { |
---|
| 4614 | vci_rsp_fifo_dcache_put = true; |
---|
| 4615 | vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); |
---|
| 4616 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4617 | } |
---|
| 4618 | } |
---|
| 4619 | } |
---|
| 4620 | break; |
---|
| 4621 | } |
---|
| 4622 | //////////////////// |
---|
| 4623 | case RSP_DATA_WRITE: |
---|
| 4624 | { |
---|
| 4625 | if (p_vci_ini_d.rspval.read()) |
---|
| 4626 | { |
---|
| 4627 | assert( p_vci_ini_d.reop.read() and |
---|
| 4628 | "a VCI response packet must contain one flit for a write transaction"); |
---|
| 4629 | |
---|
| 4630 | r_vci_rsp_fsm = RSP_IDLE; |
---|
| 4631 | uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1)); |
---|
| 4632 | bool cacheable = r_wbuf.completed(wbuf_index); |
---|
| 4633 | if ( not cacheable ) r_dcache_pending_unc_write = false; |
---|
| 4634 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); |
---|
| 4635 | } |
---|
| 4636 | break; |
---|
| 4637 | } |
---|
| 4638 | } // end switch r_vci_rsp_fsm |
---|
| 4639 | |
---|
| 4640 | //////////////////////////////////////////////////////////////////////////////// |
---|
| 4641 | // The CLEANUP FSM send the cleanup commands on the coherence network, |
---|
| 4642 | // and supports simultaneous cleanup transactions, but two simultaneous |
---|
| 4643 | // transactions mut address different cache lines. |
---|
| 4644 | // Therefore, the line number is registered in an associative |
---|
| 4645 | // registration buffer (Content Adressable Memory) by the CLEANUP FSM, |
---|
| 4646 | // and the corresponding slot (identified by the VCI TRDID field) is cleared |
---|
| 4647 | // when the cleanup transaction response is received. |
---|
| 4648 | // It handles cleanup requests from both the DCACHE FSM & ICACHE FSM |
---|
| 4649 | // with a round robin priority, and can support up to 4 simultaneous |
---|
| 4650 | // cleanup transactions (4 slots in the registration buffer). |
---|
| 4651 | // The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset |
---|
| 4652 | // when the command has been sent. |
---|
| 4653 | // The VCI TRDID field is used to distinguish data/instruction cleanups: |
---|
| 4654 | // - if data cleanup : TRDID = 2*index + 0 |
---|
| 4655 | // - if instruction cleanup : TRDID = 2*index + 1 |
---|
| 4656 | //////////////////////////////////////////////////////////////////////////// |
---|
| 4657 | |
---|
| 4658 | switch ( r_cleanup_fsm.read() ) |
---|
| 4659 | { |
---|
| 4660 | /////////////////////// |
---|
| 4661 | case CLEANUP_DATA_IDLE: // dcache has highest priority |
---|
| 4662 | { |
---|
| 4663 | size_t index = 0; |
---|
| 4664 | bool ok; |
---|
| 4665 | if ( r_dcache_cleanup_req.read() ) // dcache request |
---|
| 4666 | { |
---|
| 4667 | ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(), |
---|
| 4668 | &index ); |
---|
| 4669 | if ( ok ) // successful registration |
---|
| 4670 | { |
---|
| 4671 | r_cleanup_fsm = CLEANUP_DATA_GO; |
---|
| 4672 | r_cleanup_trdid = index<<1; |
---|
| 4673 | } |
---|
| 4674 | } |
---|
| 4675 | else if ( r_icache_cleanup_req.read() ) // icache request |
---|
| 4676 | { |
---|
| 4677 | ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(), |
---|
| 4678 | &index ); |
---|
| 4679 | if ( ok ) // successful registration |
---|
| 4680 | { |
---|
| 4681 | r_cleanup_fsm = CLEANUP_INS_GO; |
---|
| 4682 | r_cleanup_trdid = (index<<1) + 1; |
---|
| 4683 | } |
---|
| 4684 | } |
---|
| 4685 | break; |
---|
| 4686 | } |
---|
| 4687 | ////////////////////// |
---|
| 4688 | case CLEANUP_INS_IDLE: // icache has highest priority |
---|
| 4689 | { |
---|
| 4690 | size_t index = 0; |
---|
| 4691 | bool ok; |
---|
| 4692 | if ( r_icache_cleanup_req.read() ) // icache request |
---|
| 4693 | { |
---|
| 4694 | ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(), |
---|
| 4695 | &index ); |
---|
| 4696 | if ( ok ) // successful registration |
---|
| 4697 | { |
---|
| 4698 | r_cleanup_fsm = CLEANUP_INS_GO; |
---|
| 4699 | r_cleanup_trdid = (index<<1) + 1; |
---|
| 4700 | } |
---|
| 4701 | } |
---|
| 4702 | else if ( r_dcache_cleanup_req.read() ) // dcache request |
---|
| 4703 | { |
---|
| 4704 | ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(), |
---|
| 4705 | &index ); |
---|
| 4706 | if ( ok ) // successful registration |
---|
| 4707 | { |
---|
| 4708 | r_cleanup_fsm = CLEANUP_DATA_GO; |
---|
| 4709 | r_cleanup_trdid = index<<1; |
---|
| 4710 | } |
---|
| 4711 | } |
---|
| 4712 | break; |
---|
| 4713 | } |
---|
| 4714 | ///////////////////// |
---|
| 4715 | case CLEANUP_DATA_GO: |
---|
| 4716 | { |
---|
| 4717 | if ( p_vci_ini_c.cmdack.read() ) |
---|
| 4718 | { |
---|
| 4719 | r_dcache_cleanup_req = false; |
---|
| 4720 | r_cleanup_fsm = CLEANUP_INS_IDLE; |
---|
| 4721 | |
---|
| 4722 | #if DEBUG_CLEANUP |
---|
| 4723 | if ( m_debug_cleanup_fsm ) |
---|
| 4724 | { |
---|
| 4725 | std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex |
---|
| 4726 | << " address = " << (r_dcache_cleanup_line.read()*m_dcache_words*4) |
---|
| 4727 | << " / trdid = " << r_cleanup_trdid.read() << std::endl; |
---|
| 4728 | } |
---|
| 4729 | #endif |
---|
| 4730 | } |
---|
[211] | 4731 | break; |
---|
[183] | 4732 | } |
---|
| 4733 | //////////////////////// |
---|
| 4734 | case CLEANUP_INS_GO: |
---|
| 4735 | { |
---|
| 4736 | if ( p_vci_ini_c.cmdack.read() ) |
---|
| 4737 | { |
---|
| 4738 | r_icache_cleanup_req = false; |
---|
| 4739 | r_cleanup_fsm = CLEANUP_DATA_IDLE; |
---|
| 4740 | |
---|
| 4741 | #if DEBUG_CLEANUP |
---|
| 4742 | if ( m_debug_cleanup_fsm ) |
---|
| 4743 | { |
---|
| 4744 | std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex |
---|
| 4745 | << " address = " << (r_icache_cleanup_line.read()*m_icache_words*4) |
---|
| 4746 | << " / trdid = " << r_cleanup_trdid.read() << std::endl; |
---|
| 4747 | } |
---|
| 4748 | #endif |
---|
| 4749 | } |
---|
[211] | 4750 | break; |
---|
[183] | 4751 | } |
---|
| 4752 | } // end switch CLEANUP FSM |
---|
| 4753 | |
---|
| 4754 | //////////////// Handling cleanup responses ////////////////// |
---|
| 4755 | if ( p_vci_ini_c.rspval.read() ) // valid response |
---|
| 4756 | { |
---|
| 4757 | r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1); |
---|
| 4758 | } |
---|
| 4759 | |
---|
| 4760 | ///////////////// Response FIFOs update ////////////////////// |
---|
| 4761 | r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, |
---|
| 4762 | vci_rsp_fifo_icache_put, |
---|
| 4763 | vci_rsp_fifo_icache_data); |
---|
| 4764 | |
---|
| 4765 | r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get, |
---|
| 4766 | vci_rsp_fifo_dcache_put, |
---|
| 4767 | vci_rsp_fifo_dcache_data); |
---|
| 4768 | } // end transition() |
---|
| 4769 | |
---|
| 4770 | /////////////////////// |
---|
| 4771 | tmpl(void)::genMoore() |
---|
| 4772 | /////////////////////// |
---|
| 4773 | { |
---|
| 4774 | //////////////////////////////////////////////////////////////// |
---|
| 4775 | // VCI initiator command on the coherence network (cleanup) |
---|
| 4776 | // it depends on the CLEANUP FSM state |
---|
| 4777 | |
---|
| 4778 | paddr_t address; |
---|
| 4779 | |
---|
| 4780 | if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO ) |
---|
| 4781 | address = r_dcache_cleanup_line.read()*m_dcache_words*4; |
---|
| 4782 | else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO ) |
---|
| 4783 | address = r_icache_cleanup_line.read()*m_icache_words*4; |
---|
| 4784 | else |
---|
| 4785 | address = 0; |
---|
| 4786 | |
---|
| 4787 | p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or |
---|
| 4788 | (r_cleanup_fsm.read() == CLEANUP_INS_GO) ); |
---|
| 4789 | p_vci_ini_c.address = address; |
---|
| 4790 | p_vci_ini_c.wdata = 0; |
---|
| 4791 | p_vci_ini_c.be = 0xF; |
---|
| 4792 | p_vci_ini_c.plen = 4; |
---|
| 4793 | p_vci_ini_c.cmd = vci_param::CMD_WRITE; |
---|
| 4794 | p_vci_ini_c.trdid = r_cleanup_trdid.read(); |
---|
| 4795 | p_vci_ini_c.pktid = 0; |
---|
| 4796 | p_vci_ini_c.srcid = m_srcid_c; |
---|
| 4797 | p_vci_ini_c.cons = false; |
---|
| 4798 | p_vci_ini_c.wrap = false; |
---|
| 4799 | p_vci_ini_c.contig = false; |
---|
| 4800 | p_vci_ini_c.clen = 0; |
---|
| 4801 | p_vci_ini_c.cfixed = false; |
---|
| 4802 | p_vci_ini_c.eop = true; |
---|
| 4803 | |
---|
| 4804 | ///////////////////////////////////////////////////////////////// |
---|
| 4805 | // VCI initiator response on the coherence network (cleanup) |
---|
| 4806 | // We always consume the response, and we don't use it. |
---|
| 4807 | |
---|
| 4808 | p_vci_ini_c.rspack = true; |
---|
| 4809 | |
---|
| 4810 | ///////////////////////////////////////////////////////////////// |
---|
| 4811 | // VCI initiator command on the direct network |
---|
| 4812 | // it depends on the CMD FSM state |
---|
| 4813 | |
---|
| 4814 | p_vci_ini_d.pktid = 0; |
---|
| 4815 | p_vci_ini_d.srcid = m_srcid_d; |
---|
| 4816 | p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC); |
---|
| 4817 | p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC); |
---|
| 4818 | p_vci_ini_d.wrap = false; |
---|
| 4819 | p_vci_ini_d.clen = 0; |
---|
| 4820 | p_vci_ini_d.cfixed = false; |
---|
| 4821 | |
---|
| 4822 | switch ( r_vci_cmd_fsm.read() ) { |
---|
| 4823 | |
---|
| 4824 | case CMD_IDLE: |
---|
| 4825 | p_vci_ini_d.cmdval = false; |
---|
| 4826 | p_vci_ini_d.address = 0; |
---|
| 4827 | p_vci_ini_d.wdata = 0; |
---|
| 4828 | p_vci_ini_d.be = 0; |
---|
| 4829 | p_vci_ini_d.trdid = 0; |
---|
| 4830 | p_vci_ini_d.plen = 0; |
---|
| 4831 | p_vci_ini_d.cmd = vci_param::CMD_NOP; |
---|
| 4832 | p_vci_ini_d.eop = false; |
---|
| 4833 | break; |
---|
| 4834 | |
---|
| 4835 | case CMD_INS_MISS: |
---|
| 4836 | p_vci_ini_d.cmdval = true; |
---|
| 4837 | p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask; |
---|
| 4838 | p_vci_ini_d.wdata = 0; |
---|
| 4839 | p_vci_ini_d.be = 0xF; |
---|
| 4840 | p_vci_ini_d.trdid = TYPE_INS_MISS; |
---|
| 4841 | p_vci_ini_d.plen = m_icache_words<<2; |
---|
| 4842 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4843 | p_vci_ini_d.eop = true; |
---|
| 4844 | break; |
---|
| 4845 | |
---|
| 4846 | case CMD_INS_UNC: |
---|
| 4847 | p_vci_ini_d.cmdval = true; |
---|
| 4848 | p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3; |
---|
| 4849 | p_vci_ini_d.wdata = 0; |
---|
| 4850 | p_vci_ini_d.be = 0xF; |
---|
| 4851 | p_vci_ini_d.trdid = TYPE_INS_UNC; |
---|
| 4852 | p_vci_ini_d.plen = 4; |
---|
| 4853 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4854 | p_vci_ini_d.eop = true; |
---|
| 4855 | break; |
---|
| 4856 | |
---|
| 4857 | case CMD_DATA_MISS: |
---|
| 4858 | p_vci_ini_d.cmdval = true; |
---|
| 4859 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; |
---|
| 4860 | p_vci_ini_d.wdata = 0; |
---|
| 4861 | p_vci_ini_d.be = 0xF; |
---|
| 4862 | p_vci_ini_d.trdid = TYPE_DATA_MISS; |
---|
| 4863 | p_vci_ini_d.plen = m_dcache_words << 2; |
---|
| 4864 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4865 | p_vci_ini_d.eop = true; |
---|
| 4866 | break; |
---|
| 4867 | |
---|
| 4868 | case CMD_DATA_UNC: |
---|
| 4869 | p_vci_ini_d.cmdval = true; |
---|
| 4870 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
| 4871 | p_vci_ini_d.wdata = 0; |
---|
| 4872 | p_vci_ini_d.be = r_dcache_vci_unc_be.read(); |
---|
| 4873 | p_vci_ini_d.trdid = TYPE_DATA_UNC; |
---|
| 4874 | p_vci_ini_d.plen = 4; |
---|
| 4875 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
| 4876 | p_vci_ini_d.eop = true; |
---|
| 4877 | break; |
---|
| 4878 | |
---|
| 4879 | case CMD_DATA_WRITE: |
---|
| 4880 | p_vci_ini_d.cmdval = true; |
---|
| 4881 | p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; |
---|
| 4882 | p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); |
---|
| 4883 | p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); |
---|
| 4884 | p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1)); |
---|
| 4885 | p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; |
---|
| 4886 | p_vci_ini_d.cmd = vci_param::CMD_WRITE; |
---|
| 4887 | p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); |
---|
| 4888 | break; |
---|
| 4889 | |
---|
| 4890 | case CMD_DATA_SC: |
---|
| 4891 | p_vci_ini_d.cmdval = true; |
---|
| 4892 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
| 4893 | if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read(); |
---|
| 4894 | else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read(); |
---|
| 4895 | p_vci_ini_d.be = 0xF; |
---|
| 4896 | p_vci_ini_d.trdid = TYPE_DATA_UNC; |
---|
| 4897 | p_vci_ini_d.plen = 8; |
---|
| 4898 | p_vci_ini_d.cmd = vci_param::CMD_STORE_COND; |
---|
| 4899 | p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); |
---|
| 4900 | break; |
---|
| 4901 | } // end switch r_vci_cmd_fsm |
---|
| 4902 | |
---|
| 4903 | ////////////////////////////////////////////////////////// |
---|
| 4904 | // VCI initiator response on the direct network |
---|
| 4905 | // it depends on the VCI RSP state |
---|
| 4906 | |
---|
| 4907 | switch (r_vci_rsp_fsm.read() ) |
---|
| 4908 | { |
---|
| 4909 | case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break; |
---|
| 4910 | case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
| 4911 | case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
| 4912 | case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
| 4913 | case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
| 4914 | case RSP_IDLE : p_vci_ini_d.rspack = false; break; |
---|
| 4915 | } // end switch r_vci_rsp_fsm |
---|
| 4916 | |
---|
| 4917 | //////////////////////////////////////////////////////////////// |
---|
| 4918 | // VCI target command and response on the coherence network |
---|
| 4919 | switch ( r_tgt_fsm.read() ) |
---|
| 4920 | { |
---|
| 4921 | case TGT_IDLE: |
---|
| 4922 | case TGT_UPDT_WORD: |
---|
| 4923 | case TGT_UPDT_DATA: |
---|
| 4924 | p_vci_tgt_c.cmdack = true; |
---|
| 4925 | p_vci_tgt_c.rspval = false; |
---|
| 4926 | break; |
---|
| 4927 | |
---|
| 4928 | case TGT_RSP_BROADCAST: |
---|
| 4929 | p_vci_tgt_c.cmdack = false; |
---|
| 4930 | p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() |
---|
| 4931 | and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ); |
---|
| 4932 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
| 4933 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
| 4934 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
| 4935 | p_vci_tgt_c.rdata = 0; |
---|
| 4936 | p_vci_tgt_c.rerror = 0; |
---|
| 4937 | p_vci_tgt_c.reop = true; |
---|
| 4938 | break; |
---|
| 4939 | |
---|
| 4940 | case TGT_RSP_ICACHE: |
---|
| 4941 | p_vci_tgt_c.cmdack = false; |
---|
| 4942 | p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read(); |
---|
| 4943 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
| 4944 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
| 4945 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
| 4946 | p_vci_tgt_c.rdata = 0; |
---|
| 4947 | p_vci_tgt_c.rerror = 0; |
---|
| 4948 | p_vci_tgt_c.reop = true; |
---|
| 4949 | break; |
---|
| 4950 | |
---|
| 4951 | case TGT_RSP_DCACHE: |
---|
| 4952 | p_vci_tgt_c.cmdack = false; |
---|
| 4953 | p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read(); |
---|
| 4954 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
| 4955 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
| 4956 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
| 4957 | p_vci_tgt_c.rdata = 0; |
---|
| 4958 | p_vci_tgt_c.rerror = 0; |
---|
| 4959 | p_vci_tgt_c.reop = true; |
---|
| 4960 | break; |
---|
| 4961 | |
---|
| 4962 | case TGT_REQ_BROADCAST: |
---|
| 4963 | case TGT_REQ_ICACHE: |
---|
| 4964 | case TGT_REQ_DCACHE: |
---|
| 4965 | p_vci_tgt_c.cmdack = false; |
---|
| 4966 | p_vci_tgt_c.rspval = false; |
---|
| 4967 | break; |
---|
| 4968 | |
---|
| 4969 | } // end switch TGT_FSM |
---|
| 4970 | } // end genMoore |
---|
| 4971 | |
---|
| 4972 | }} |
---|
| 4973 | |
---|
| 4974 | // Local Variables: |
---|
| 4975 | // tab-width: 4 |
---|
| 4976 | // c-basic-offset: 4 |
---|
| 4977 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 4978 | // indent-tabs-mode: nil |
---|
| 4979 | // End: |
---|
| 4980 | |
---|
| 4981 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 4982 | |
---|
| 4983 | |
---|
| 4984 | |
---|
| 4985 | |
---|
| 4986 | |
---|
| 4987 | |
---|
| 4988 | |
---|
| 4989 | |
---|
| 4990 | |
---|
| 4991 | |
---|