1 | /* -*- c++ -*-C |
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2 | * File : vci_cc_vcache_wrapper_v4.cpp |
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3 | * Copyright (c) UPMC, Lip6, SoC |
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4 | * Authors : Alain GREINER, Yang GAO |
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5 | * |
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6 | * SOCLIB_LGPL_HEADER_BEGIN |
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7 | * |
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8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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9 | * |
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10 | * SoCLib is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU Lesser General Public License as published |
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12 | * by the Free Software Foundation; version 2.1 of the License. |
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13 | * |
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14 | * SoCLib is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * Lesser General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU Lesser General Public |
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20 | * License along with SoCLib; if not, write to the Free Software |
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21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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22 | * 02110-1301 USA |
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23 | * |
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24 | * SOCLIB_LGPL_HEADER_END |
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25 | */ |
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26 | |
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27 | #include <cassert> |
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28 | #include "arithmetics.h" |
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29 | #include "../include/vci_cc_vcache_wrapper_v4.h" |
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30 | |
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31 | #define DEBUG_DCACHE 1 |
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32 | #define DEBUG_ICACHE 1 |
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33 | #define DEBUG_CLEANUP 0 |
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34 | #define DEBUG_INVAL_ITLB 1 |
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35 | #define DEBUG_INVAL_DTLB 1 |
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36 | |
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37 | namespace soclib { |
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38 | namespace caba { |
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39 | |
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40 | namespace { |
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41 | const char *icache_fsm_state_str[] = { |
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42 | "ICACHE_IDLE", |
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43 | |
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44 | "ICACHE_XTN_TLB_FLUSH", |
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45 | "ICACHE_XTN_CACHE_FLUSH", |
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46 | "ICACHE_XTN_TLB_INVAL", |
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47 | "ICACHE_XTN_CACHE_INVAL_VA", |
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48 | "ICACHE_XTN_CACHE_INVAL_PA", |
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49 | "ICACHE_XTN_CACHE_INVAL_GO", |
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50 | |
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51 | "ICACHE_TLB_WAIT", |
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52 | |
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53 | "ICACHE_MISS_VICTIM", |
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54 | "ICACHE_MISS_INVAL", |
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55 | "ICACHE_MISS_WAIT", |
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56 | "ICACHE_MISS_UPDT", |
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57 | |
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58 | "ICACHE_UNC_WAIT", |
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59 | |
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60 | "ICACHE_CC_CHECK", |
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61 | "ICACHE_CC_INVAL", |
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62 | "ICACHE_CC_UPDT", |
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63 | |
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64 | }; |
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65 | const char *dcache_fsm_state_str[] = { |
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66 | "DCACHE_IDLE", |
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67 | |
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68 | "DCACHE_TLB_MISS", |
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69 | "DCACHE_TLB_PTE1_GET", |
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70 | "DCACHE_TLB_PTE1_SELECT", |
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71 | "DCACHE_TLB_PTE1_UPDT", |
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72 | "DCACHE_TLB_PTE2_GET", |
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73 | "DCACHE_TLB_PTE2_SELECT", |
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74 | "DCACHE_TLB_PTE2_UPDT", |
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75 | "DCACHE_TLB_SC_UPDT", |
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76 | "DCACHE_TLB_SC_WAIT", |
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77 | "DCACHE_TLB_RETURN", |
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78 | |
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79 | "DCACHE_XTN_SWITCH", |
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80 | "DCACHE_XTN_SYNC", |
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81 | "DCACHE_XTN_IC_INVAL_VA", |
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82 | "DCACHE_XTN_IC_FLUSH", |
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83 | "DCACHE_XTN_IC_INVAL_PA", |
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84 | "DCACHE_XTN_IT_INVAL", |
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85 | "DCACHE_XTN_DC_FLUSH", |
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86 | "DCACHE_XTN_DC_INVAL_VA", |
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87 | "DCACHE_XTN_DC_INVAL_PA", |
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88 | "DCACHE_XTN_DC_INVAL_WAIT", |
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89 | "DCACHE_XTN_DC_INVAL_GO", |
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90 | "DCACHE_XTN_DT_INVAL", |
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91 | |
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92 | "DCACHE_WRITE_TLB_DIRTY", |
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93 | "DCACHE_WRITE_CACHE_DIRTY", |
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94 | "DCACHE_WRITE_SC_WAIT", |
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95 | "DCACHE_WRITE_UNC_WAIT", |
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96 | |
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97 | "DCACHE_MISS_VICTIM", |
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98 | "DCACHE_MISS_INVAL", |
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99 | "DCACHE_MISS_INVAL_WAIT", |
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100 | "DCACHE_MISS_WAIT", |
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101 | "DCACHE_MISS_UPDT", |
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102 | |
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103 | "DCACHE_UNC_WAIT", |
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104 | |
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105 | "DCACHE_CC_CHECK", |
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106 | "DCACHE_CC_INVAL", |
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107 | "DCACHE_CC_UPDT", |
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108 | "DCACHE_CC_WAIT", |
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109 | }; |
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110 | const char *cmd_fsm_state_str[] = { |
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111 | "CMD_IDLE", |
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112 | "CMD_INS_MISS", |
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113 | "CMD_INS_UNC", |
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114 | "CMD_DATA_MISS", |
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115 | "CMD_DATA_UNC", |
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116 | "CMD_DATA_WRITE", |
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117 | "CMD_DATA_SC", |
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118 | }; |
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119 | const char *rsp_fsm_state_str[] = { |
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120 | "RSP_IDLE", |
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121 | "RSP_INS_MISS", |
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122 | "RSP_INS_UNC", |
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123 | "RSP_DATA_MISS", |
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124 | "RSP_DATA_UNC", |
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125 | "RSP_DATA_WRITE", |
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126 | }; |
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127 | const char *cleanup_fsm_state_str[] = { |
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128 | "CLEANUP_DATA_IDLE", |
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129 | "CLEANUP_DATA_GO", |
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130 | "CLEANUP_INS_IDLE", |
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131 | "CLEANUP_INS_GO", |
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132 | }; |
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133 | const char *tgt_fsm_state_str[] = { |
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134 | "TGT_IDLE", |
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135 | "TGT_UPDT_WORD", |
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136 | "TGT_UPDT_DATA", |
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137 | "TGT_REQ_BROADCAST", |
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138 | "TGT_REQ_ICACHE", |
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139 | "TGT_REQ_DCACHE", |
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140 | "TGT_RSP_BROADCAST", |
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141 | "TGT_RSP_ICACHE", |
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142 | "TGT_RSP_DCACHE", |
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143 | }; |
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144 | const char *inval_itlb_fsm_state_str[] = { |
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145 | "INVAL_ITLB_IDLE", |
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146 | "INVAL_ITLB_SCAN", |
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147 | }; |
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148 | const char *inval_dtlb_fsm_state_str[] = { |
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149 | "INVAL_DTLB_IDLE", |
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150 | "INVAL_DTLB_SCAN", |
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151 | }; |
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152 | } |
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153 | |
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154 | #define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t> |
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155 | |
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156 | using soclib::common::uint32_log2; |
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157 | |
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158 | ///////////////////////////////// |
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159 | tmpl(/**/)::VciCcVCacheWrapperV4( |
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160 | sc_module_name name, |
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161 | int proc_id, |
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162 | const soclib::common::MappingTable &mtp, |
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163 | const soclib::common::MappingTable &mtc, |
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164 | const soclib::common::IntTab &initiator_index_d, |
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165 | const soclib::common::IntTab &initiator_index_c, |
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166 | const soclib::common::IntTab &target_index_d, |
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167 | size_t itlb_ways, |
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168 | size_t itlb_sets, |
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169 | size_t dtlb_ways, |
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170 | size_t dtlb_sets, |
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171 | size_t icache_ways, |
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172 | size_t icache_sets, |
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173 | size_t icache_words, |
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174 | size_t dcache_ways, |
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175 | size_t dcache_sets, |
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176 | size_t dcache_words, |
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177 | size_t wbuf_nlines, |
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178 | size_t wbuf_nwords, |
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179 | uint32_t max_frozen_cycles, |
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180 | uint32_t debug_start_cycle, |
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181 | bool debug_ok) |
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182 | : soclib::caba::BaseModule(name), |
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183 | |
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184 | p_clk("clk"), |
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185 | p_resetn("resetn"), |
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186 | p_vci_ini_d("vci_ini_d"), |
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187 | p_vci_ini_c("vci_ini_c"), |
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188 | p_vci_tgt_c("vci_tgt_d"), |
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189 | |
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190 | m_cacheability_table(mtp.getCacheabilityTable()), |
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191 | m_segment(mtc.getSegment(target_index_d)), |
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192 | m_srcid_d(mtp.indexForId(initiator_index_d)), |
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193 | m_srcid_c(mtp.indexForId(initiator_index_c)), |
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194 | |
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195 | m_itlb_ways(itlb_ways), |
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196 | m_itlb_sets(itlb_sets), |
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197 | |
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198 | m_dtlb_ways(dtlb_ways), |
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199 | m_dtlb_sets(dtlb_sets), |
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200 | |
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201 | m_icache_ways(icache_ways), |
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202 | m_icache_sets(icache_sets), |
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203 | m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)), |
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204 | m_icache_words(icache_words), |
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205 | |
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206 | m_dcache_ways(dcache_ways), |
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207 | m_dcache_sets(dcache_sets), |
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208 | m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)), |
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209 | m_dcache_words(dcache_words), |
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210 | |
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211 | m_proc_id(proc_id), |
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212 | |
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213 | m_max_frozen_cycles(max_frozen_cycles), |
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214 | |
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215 | m_paddr_nbits(vci_param::N), |
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216 | |
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217 | m_debug_start_cycle(debug_start_cycle), |
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218 | m_debug_ok(debug_ok), |
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219 | |
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220 | r_mmu_ptpr("r_mmu_ptpr"), |
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221 | r_mmu_mode("r_mmu_mode"), |
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222 | r_mmu_word_lo("r_mmu_word_lo"), |
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223 | r_mmu_word_hi("r_mmu_word_hi"), |
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224 | r_mmu_ibvar("r_mmu_ibvar"), |
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225 | r_mmu_dbvar("r_mmu_dbvar"), |
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226 | r_mmu_ietr("r_mmu_ietr"), |
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227 | r_mmu_detr("r_mmu_detr"), |
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228 | |
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229 | r_icache_fsm("r_icache_fsm"), |
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230 | r_icache_fsm_save("r_icache_fsm_save"), |
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231 | r_icache_vci_paddr("r_icache_vci_paddr"), |
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232 | r_icache_vaddr_save("r_icache_vaddr_save"), |
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233 | |
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234 | r_icache_miss_way("r_icache_miss_way"), |
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235 | r_icache_miss_set("r_icache_miss_set"), |
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236 | r_icache_miss_word("r_icache_miss_word"), |
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237 | r_icache_miss_inval("r_icache_miss_inval"), |
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238 | |
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239 | r_icache_cc_way("r_icache_cc_way"), |
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240 | r_icache_cc_set("r_icache_cc_set"), |
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241 | r_icache_cc_word("r_icache_cc_word"), |
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242 | |
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243 | r_icache_flush_count("r_icache_flush_count"), |
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244 | |
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245 | r_icache_miss_req("r_icache_miss_req"), |
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246 | r_icache_unc_req("r_icache_unc_req"), |
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247 | |
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248 | r_icache_tlb_miss_req("r_icache_tlb_read_req"), |
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249 | r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), |
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250 | |
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251 | r_icache_cleanup_req("r_icache_cleanup_req"), |
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252 | r_icache_cleanup_line("r_icache_cleanup_line"), |
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253 | |
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254 | r_dcache_fsm("r_dcache_fsm"), |
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255 | r_dcache_fsm_save("r_dcache_fsm_save"), |
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256 | |
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257 | r_dcache_p0_valid("r_dcache_p0_valid"), |
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258 | r_dcache_p0_vaddr("r_dcache_p0_vaddr"), |
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259 | r_dcache_p0_wdata("r_dcache_p0_wdata"), |
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260 | r_dcache_p0_be("r_dcache_p0_be"), |
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261 | r_dcache_p0_paddr("r_dcache_p0_paddr"), |
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262 | r_dcache_p0_cacheable("r_dcache_p0_cacheable"), |
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263 | r_dcache_p0_tlb_way("r_dcache_p0_tlb_way"), |
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264 | r_dcache_p0_tlb_set("r_dcache_p0_tlb_set"), |
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265 | r_dcache_p0_tlb_nline("r_dcache_p0_tlb_nline"), |
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266 | r_dcache_p0_tlb_dirty("r_dcache_p0_tlb_dirty"), |
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267 | r_dcache_p0_tlb_big("r_dcache_p0_tlb_big"), |
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268 | |
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269 | r_dcache_p1_valid("r_dcache_p1_valid"), |
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270 | r_dcache_p1_updt_cache("r_dcache_p1_updt_cache"), |
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271 | r_dcache_p1_set_dirty("r_dcache_p1_set_dirty"), |
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272 | r_dcache_p1_vaddr("r_dcache_p1_vaddr"), |
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273 | r_dcache_p1_wdata("r_dcache_p1_wdata"), |
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274 | r_dcache_p1_be("r_dcache_p1_be"), |
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275 | r_dcache_p1_paddr("r_dcache_p1_paddr"), |
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276 | r_dcache_p1_cache_way("r_dcache_p1_cache_way"), |
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277 | r_dcache_p1_cache_set("r_dcache_p1_cache_set"), |
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278 | r_dcache_p1_cache_word("r_dcache_p1_word_save"), |
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279 | r_dcache_p1_tlb_way("r_dcache_p1_tlb_way"), |
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280 | r_dcache_p1_tlb_set("r_dcache_p1_tlb_set"), |
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281 | r_dcache_p1_tlb_nline("r_dcache_p1_tlb_nline"), |
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282 | |
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283 | r_dcache_p2_vaddr("r_dcache_p2_vaddr"), |
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284 | r_dcache_p2_tlb_way("r_dcache_p2_tlb_way"), |
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285 | r_dcache_p2_tlb_set("r_dcache_p2_tlb_set"), |
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286 | r_dcache_p2_set_dirty("r_dcache_p2_set_dirty"), |
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287 | r_dcache_p2_pte_paddr("r_dcache_p2_pte_paddr"), |
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288 | r_dcache_p2_pte_way("r_dcache_p2_pte_way"), |
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289 | r_dcache_p2_pte_set("r_dcache_p2_pte_set"), |
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290 | r_dcache_p2_pte_word("r_dcache_p2_pte_word"), |
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291 | r_dcache_p2_pte_flags("r_dcache_p2_pte_flags"), |
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292 | |
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293 | r_dcache_vci_paddr("r_dcache_vci_paddr"), |
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294 | r_dcache_vci_miss_req("r_dcache_vci_miss_req"), |
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295 | r_dcache_vci_unc_req("r_dcache_vci_unc_req"), |
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296 | r_dcache_vci_unc_be("r_dcache_vci_unc_be"), |
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297 | r_dcache_vci_sc_req("r_dcache_vci_sc_req"), |
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298 | r_dcache_vci_sc_old("r_dcache_vci_sc_old"), |
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299 | r_dcache_vci_sc_new("r_dcache_vci_sc_new"), |
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300 | |
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301 | r_dcache_xtn_way("r_dcache_xtn_way"), |
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302 | r_dcache_xtn_set("r_dcache_xtn_set"), |
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303 | |
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304 | r_dcache_pending_unc_write("r_dcache_pending_unc_write"), |
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305 | |
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306 | r_dcache_miss_type("r_dcache_miss_type"), |
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307 | r_dcache_miss_word("r_dcache_miss_word"), |
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308 | r_dcache_miss_way("r_dcache_miss_way"), |
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309 | r_dcache_miss_set("r_dcache_miss_set"), |
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310 | r_dcache_miss_inval("r_dcache_miss_inval"), |
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311 | |
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312 | r_dcache_cc_way("r_dcache_cc_way"), |
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313 | r_dcache_cc_set("r_dcache_cc_set"), |
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314 | r_dcache_cc_word("r_dcache_cc_word"), |
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315 | |
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316 | r_dcache_flush_count("r_dcache_flush_count"), |
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317 | |
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318 | r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"), |
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319 | r_dcache_tlb_ins("r_dcache_tlb_ins"), |
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320 | r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), |
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321 | r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), |
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322 | r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), |
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323 | r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), |
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324 | r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), |
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325 | r_dcache_tlb_way("r_dcache_tlb_way"), |
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326 | r_dcache_tlb_set("r_dcache_tlb_set"), |
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327 | |
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328 | r_dcache_ll_valid("r_dcache_ll_valid"), |
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329 | r_dcache_ll_data("r_dcache_ll_data"), |
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330 | r_dcache_ll_vaddr("r_dcache_ll_vaddr"), |
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331 | |
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332 | r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"), |
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333 | r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"), |
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334 | r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"), |
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335 | |
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336 | r_dcache_xtn_req("r_dcache_xtn_req"), |
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337 | r_dcache_xtn_opcode("r_dcache_xtn_opcode"), |
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338 | |
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339 | r_dcache_cleanup_req("r_dcache_cleanup_req"), |
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340 | r_dcache_cleanup_line("r_dcache_cleanup_line"), |
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341 | |
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342 | r_vci_cmd_fsm("r_vci_cmd_fsm"), |
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343 | r_vci_cmd_min("r_vci_cmd_min"), |
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344 | r_vci_cmd_max("r_vci_cmd_max"), |
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345 | r_vci_cmd_cpt("r_vci_cmd_cpt"), |
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346 | r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"), |
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347 | |
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348 | r_vci_rsp_fsm("r_vci_rsp_fsm"), |
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349 | r_vci_rsp_cpt("r_vci_rsp_cpt"), |
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350 | r_vci_rsp_ins_error("r_vci_rsp_ins_error"), |
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351 | r_vci_rsp_data_error("r_vci_rsp_data_error"), |
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352 | r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth |
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353 | r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth |
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354 | |
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355 | r_cleanup_fsm("r_cleanup_fsm"), |
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356 | r_cleanup_trdid("r_cleanup_trdid"), |
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357 | r_cleanup_buffer(4), // up to 4 simultaneous cleanups |
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358 | |
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359 | r_tgt_fsm("r_tgt_fsm"), |
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360 | r_tgt_paddr("r_tgt_paddr"), |
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361 | r_tgt_word_count("r_tgt_word_count"), |
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362 | r_tgt_word_min("r_tgt_word_min"), |
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363 | r_tgt_word_max("r_tgt_word_max"), |
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364 | r_tgt_update("r_tgt_update"), |
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365 | r_tgt_update_data("r_tgt_update_data"), |
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366 | r_tgt_srcid("r_tgt_srcid"), |
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367 | r_tgt_pktid("r_tgt_pktid"), |
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368 | r_tgt_trdid("r_tgt_trdid"), |
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369 | |
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370 | r_tgt_icache_req("r_tgt_icache_req"), |
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371 | r_tgt_dcache_req("r_tgt_dcache_req"), |
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372 | r_tgt_icache_rsp("r_tgt_icache_rsp"), |
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373 | r_tgt_dcache_rsp("r_tgt_dcache_rsp"), |
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374 | |
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375 | r_inval_itlb_fsm("r_inval_itlb_fsm"), |
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376 | r_inval_itlb_count("r_inval_itlb_count"), |
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377 | |
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378 | r_inval_dtlb_fsm("r_inval_dtlb_fsm"), |
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379 | r_inval_dtlb_count("r_inval_dtlb_count"), |
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380 | |
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381 | r_iss(this->name(), proc_id), |
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382 | r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ), |
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383 | r_icache("icache", icache_ways, icache_sets, icache_words), |
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384 | r_dcache("dcache", dcache_ways, dcache_sets, dcache_words), |
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385 | r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N), |
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386 | r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N) |
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387 | { |
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388 | assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and |
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389 | "Need more PLEN bits."); |
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390 | |
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391 | assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and |
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392 | "Need more TRDID bits."); |
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393 | |
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394 | assert( (icache_words == dcache_words) and |
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395 | "icache_words and dcache_words parameters must be equal"); |
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396 | |
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397 | r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | |
---|
398 | (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | |
---|
399 | (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | |
---|
400 | (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | |
---|
401 | (uint32_log2(m_icache_words<<2)); |
---|
402 | |
---|
403 | r_mmu_release = (uint32_t)(1 << 16) | 0x1; |
---|
404 | |
---|
405 | r_tgt_buf = new uint32_t[dcache_words]; |
---|
406 | r_tgt_be = new vci_be_t[dcache_words]; |
---|
407 | r_dcache_in_itlb = new bool[dcache_ways*dcache_sets]; |
---|
408 | r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets]; |
---|
409 | |
---|
410 | SC_METHOD(transition); |
---|
411 | dont_initialize(); |
---|
412 | sensitive << p_clk.pos(); |
---|
413 | |
---|
414 | SC_METHOD(genMoore); |
---|
415 | dont_initialize(); |
---|
416 | sensitive << p_clk.neg(); |
---|
417 | |
---|
418 | typename iss_t::CacheInfo cache_info; |
---|
419 | cache_info.has_mmu = true; |
---|
420 | cache_info.icache_line_size = icache_words*sizeof(uint32_t); |
---|
421 | cache_info.icache_assoc = icache_ways; |
---|
422 | cache_info.icache_n_lines = icache_sets; |
---|
423 | cache_info.dcache_line_size = dcache_words*sizeof(uint32_t); |
---|
424 | cache_info.dcache_assoc = dcache_ways; |
---|
425 | cache_info.dcache_n_lines = dcache_sets; |
---|
426 | r_iss.setCacheInfo(cache_info); |
---|
427 | } |
---|
428 | |
---|
429 | ///////////////////////////////////// |
---|
430 | tmpl(/**/)::~VciCcVCacheWrapperV4() |
---|
431 | ///////////////////////////////////// |
---|
432 | { |
---|
433 | delete [] r_tgt_be; |
---|
434 | delete [] r_tgt_buf; |
---|
435 | delete [] r_dcache_in_itlb; |
---|
436 | delete [] r_dcache_in_dtlb; |
---|
437 | } |
---|
438 | |
---|
439 | //////////////////////// |
---|
440 | tmpl(void)::print_cpi() |
---|
441 | //////////////////////// |
---|
442 | { |
---|
443 | std::cout << name() << " CPI = " |
---|
444 | << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ; |
---|
445 | } |
---|
446 | |
---|
447 | //////////////////////////////////// |
---|
448 | tmpl(void)::print_trace(size_t mode) |
---|
449 | //////////////////////////////////// |
---|
450 | { |
---|
451 | // b0 : write buffer print trace |
---|
452 | // b1 : write buffer verbose |
---|
453 | // b2 : dcache print trace |
---|
454 | // b3 : icache print trace |
---|
455 | |
---|
456 | typename iss_t::InstructionRequest ireq; |
---|
457 | typename iss_t::InstructionResponse irsp; |
---|
458 | typename iss_t::DataRequest dreq; |
---|
459 | typename iss_t::DataResponse drsp; |
---|
460 | |
---|
461 | ireq.valid = m_ireq_valid; |
---|
462 | ireq.addr = m_ireq_addr; |
---|
463 | ireq.mode = m_ireq_mode; |
---|
464 | |
---|
465 | irsp.valid = m_irsp_valid; |
---|
466 | irsp.instruction = m_irsp_instruction; |
---|
467 | irsp.error = m_irsp_error; |
---|
468 | |
---|
469 | dreq.valid = m_dreq_valid; |
---|
470 | dreq.addr = m_dreq_addr; |
---|
471 | dreq.mode = m_dreq_mode; |
---|
472 | dreq.type = m_dreq_type; |
---|
473 | dreq.wdata = m_dreq_wdata; |
---|
474 | dreq.be = m_dreq_be; |
---|
475 | |
---|
476 | drsp.valid = m_drsp_valid; |
---|
477 | drsp.rdata = m_drsp_rdata; |
---|
478 | drsp.error = m_drsp_error; |
---|
479 | |
---|
480 | std::cout << std::dec << "PROC " << name() << std::endl; |
---|
481 | |
---|
482 | std::cout << " " << ireq << std::endl; |
---|
483 | std::cout << " " << irsp << std::endl; |
---|
484 | std::cout << " " << dreq << std::endl; |
---|
485 | std::cout << " " << drsp << std::endl; |
---|
486 | |
---|
487 | std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] |
---|
488 | << " | " << dcache_fsm_state_str[r_dcache_fsm.read()] |
---|
489 | << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()] |
---|
490 | << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] |
---|
491 | << " | " << tgt_fsm_state_str[r_tgt_fsm.read()] << std::endl; |
---|
492 | std::cout << " " << cleanup_fsm_state_str[r_cleanup_fsm.read()] |
---|
493 | << " | " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] |
---|
494 | << " | " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm]; |
---|
495 | if (r_dcache_p0_valid.read() ) std::cout << " | P1_WRITE"; |
---|
496 | if (r_dcache_p1_valid.read() ) std::cout << " | P2_WRITE"; |
---|
497 | std::cout << std::endl; |
---|
498 | |
---|
499 | if(mode & 0x1) |
---|
500 | { |
---|
501 | r_wbuf.printTrace((mode>>1)&1); |
---|
502 | } |
---|
503 | if(mode & 0x4) |
---|
504 | { |
---|
505 | std::cout << " Data cache" << std::endl; |
---|
506 | r_dcache.printTrace(); |
---|
507 | } |
---|
508 | if(mode & 0x8) |
---|
509 | { |
---|
510 | std::cout << " Instruction cache" << std::endl; |
---|
511 | r_icache.printTrace(); |
---|
512 | } |
---|
513 | } |
---|
514 | |
---|
515 | ////////////////////////////////////////// |
---|
516 | tmpl(void)::cache_monitor( paddr_t addr ) |
---|
517 | ////////////////////////////////////////// |
---|
518 | { |
---|
519 | size_t cache_way; |
---|
520 | size_t cache_set; |
---|
521 | size_t cache_word; |
---|
522 | uint32_t cache_rdata; |
---|
523 | bool cache_hit = r_dcache.read( addr, |
---|
524 | &cache_rdata, |
---|
525 | &cache_way, |
---|
526 | &cache_set, |
---|
527 | &cache_word ); |
---|
528 | if ( cache_hit != m_debug_previous_hit ) |
---|
529 | { |
---|
530 | std::cout << "PROC " << name() |
---|
531 | << " cache change at cycle " << std::dec << m_cpt_total_cycles |
---|
532 | << " for adresse " << std::hex << addr |
---|
533 | << " / HIT = " << cache_hit << std::endl; |
---|
534 | } |
---|
535 | m_debug_previous_hit = cache_hit; |
---|
536 | } |
---|
537 | |
---|
538 | |
---|
539 | |
---|
540 | /* |
---|
541 | //////////////////////// |
---|
542 | tmpl(void)::print_stats() |
---|
543 | //////////////////////// |
---|
544 | { |
---|
545 | float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); |
---|
546 | std::cout << name() << std::endl |
---|
547 | << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl |
---|
548 | << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl |
---|
549 | << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl |
---|
550 | << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl |
---|
551 | << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl |
---|
552 | << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl |
---|
553 | << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl |
---|
554 | << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl |
---|
555 | << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl |
---|
556 | << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl |
---|
557 | << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl |
---|
558 | << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl |
---|
559 | << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl |
---|
560 | << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl |
---|
561 | << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl |
---|
562 | << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl |
---|
563 | << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl |
---|
564 | << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl |
---|
565 | << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl |
---|
566 | << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl |
---|
567 | << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl |
---|
568 | << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl |
---|
569 | << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl |
---|
570 | << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl |
---|
571 | << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl |
---|
572 | << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl |
---|
573 | << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl |
---|
574 | << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl |
---|
575 | << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl |
---|
576 | << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl |
---|
577 | << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl |
---|
578 | << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl |
---|
579 | << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl |
---|
580 | << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl |
---|
581 | << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl |
---|
582 | << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl |
---|
583 | << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl |
---|
584 | << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl |
---|
585 | << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; |
---|
586 | } |
---|
587 | |
---|
588 | //////////////////////// |
---|
589 | tmpl(void)::clear_stats() |
---|
590 | //////////////////////// |
---|
591 | { |
---|
592 | m_cpt_dcache_data_read = 0; |
---|
593 | m_cpt_dcache_data_write = 0; |
---|
594 | m_cpt_dcache_dir_read = 0; |
---|
595 | m_cpt_dcache_dir_write = 0; |
---|
596 | m_cpt_icache_data_read = 0; |
---|
597 | m_cpt_icache_data_write = 0; |
---|
598 | m_cpt_icache_dir_read = 0; |
---|
599 | m_cpt_icache_dir_write = 0; |
---|
600 | |
---|
601 | m_cpt_frz_cycles = 0; |
---|
602 | m_cpt_dcache_frz_cycles = 0; |
---|
603 | m_cpt_total_cycles = 0; |
---|
604 | |
---|
605 | m_cpt_read = 0; |
---|
606 | m_cpt_write = 0; |
---|
607 | m_cpt_data_miss = 0; |
---|
608 | m_cpt_ins_miss = 0; |
---|
609 | m_cpt_unc_read = 0; |
---|
610 | m_cpt_write_cached = 0; |
---|
611 | m_cpt_ins_read = 0; |
---|
612 | |
---|
613 | m_cost_write_frz = 0; |
---|
614 | m_cost_data_miss_frz = 0; |
---|
615 | m_cost_unc_read_frz = 0; |
---|
616 | m_cost_ins_miss_frz = 0; |
---|
617 | |
---|
618 | m_cpt_imiss_transaction = 0; |
---|
619 | m_cpt_dmiss_transaction = 0; |
---|
620 | m_cpt_unc_transaction = 0; |
---|
621 | m_cpt_write_transaction = 0; |
---|
622 | m_cpt_icache_unc_transaction = 0; |
---|
623 | |
---|
624 | m_cost_imiss_transaction = 0; |
---|
625 | m_cost_dmiss_transaction = 0; |
---|
626 | m_cost_unc_transaction = 0; |
---|
627 | m_cost_write_transaction = 0; |
---|
628 | m_cost_icache_unc_transaction = 0; |
---|
629 | m_length_write_transaction = 0; |
---|
630 | |
---|
631 | m_cpt_ins_tlb_read = 0; |
---|
632 | m_cpt_ins_tlb_miss = 0; |
---|
633 | m_cpt_ins_tlb_update_acc = 0; |
---|
634 | |
---|
635 | m_cpt_data_tlb_read = 0; |
---|
636 | m_cpt_data_tlb_miss = 0; |
---|
637 | m_cpt_data_tlb_update_acc = 0; |
---|
638 | m_cpt_data_tlb_update_dirty = 0; |
---|
639 | m_cpt_ins_tlb_hit_dcache = 0; |
---|
640 | m_cpt_data_tlb_hit_dcache = 0; |
---|
641 | m_cpt_ins_tlb_occup_cache = 0; |
---|
642 | m_cpt_data_tlb_occup_cache = 0; |
---|
643 | |
---|
644 | m_cost_ins_tlb_miss_frz = 0; |
---|
645 | m_cost_data_tlb_miss_frz = 0; |
---|
646 | m_cost_ins_tlb_update_acc_frz = 0; |
---|
647 | m_cost_data_tlb_update_acc_frz = 0; |
---|
648 | m_cost_data_tlb_update_dirty_frz = 0; |
---|
649 | m_cost_ins_tlb_occup_cache_frz = 0; |
---|
650 | m_cost_data_tlb_occup_cache_frz = 0; |
---|
651 | |
---|
652 | m_cpt_itlbmiss_transaction = 0; |
---|
653 | m_cpt_itlb_ll_transaction = 0; |
---|
654 | m_cpt_itlb_sc_transaction = 0; |
---|
655 | m_cpt_dtlbmiss_transaction = 0; |
---|
656 | m_cpt_dtlb_ll_transaction = 0; |
---|
657 | m_cpt_dtlb_sc_transaction = 0; |
---|
658 | m_cpt_dtlb_ll_dirty_transaction = 0; |
---|
659 | m_cpt_dtlb_sc_dirty_transaction = 0; |
---|
660 | |
---|
661 | m_cost_itlbmiss_transaction = 0; |
---|
662 | m_cost_itlb_ll_transaction = 0; |
---|
663 | m_cost_itlb_sc_transaction = 0; |
---|
664 | m_cost_dtlbmiss_transaction = 0; |
---|
665 | m_cost_dtlb_ll_transaction = 0; |
---|
666 | m_cost_dtlb_sc_transaction = 0; |
---|
667 | m_cost_dtlb_ll_dirty_transaction = 0; |
---|
668 | m_cost_dtlb_sc_dirty_transaction = 0; |
---|
669 | |
---|
670 | m_cpt_cc_update_data = 0; |
---|
671 | m_cpt_cc_inval_ins = 0; |
---|
672 | m_cpt_cc_inval_data = 0; |
---|
673 | m_cpt_cc_broadcast = 0; |
---|
674 | |
---|
675 | m_cost_updt_data_frz = 0; |
---|
676 | m_cost_inval_ins_frz = 0; |
---|
677 | m_cost_inval_data_frz = 0; |
---|
678 | m_cost_broadcast_frz = 0; |
---|
679 | |
---|
680 | m_cpt_cc_cleanup_data = 0; |
---|
681 | m_cpt_cc_cleanup_ins = 0; |
---|
682 | } |
---|
683 | |
---|
684 | */ |
---|
685 | |
---|
686 | ///////////////////////// |
---|
687 | tmpl(void)::transition() |
---|
688 | ///////////////////////// |
---|
689 | { |
---|
690 | if ( not p_resetn.read() ) |
---|
691 | { |
---|
692 | r_iss.reset(); |
---|
693 | r_wbuf.reset(); |
---|
694 | r_icache.reset(); |
---|
695 | r_dcache.reset(); |
---|
696 | r_itlb.reset(); |
---|
697 | r_dtlb.reset(); |
---|
698 | |
---|
699 | r_dcache_fsm = DCACHE_IDLE; |
---|
700 | r_icache_fsm = ICACHE_IDLE; |
---|
701 | r_vci_cmd_fsm = CMD_IDLE; |
---|
702 | r_vci_rsp_fsm = RSP_IDLE; |
---|
703 | r_tgt_fsm = TGT_IDLE; |
---|
704 | r_inval_itlb_fsm = INVAL_ITLB_IDLE; |
---|
705 | r_inval_dtlb_fsm = INVAL_DTLB_IDLE; |
---|
706 | r_cleanup_fsm = CLEANUP_DATA_IDLE; |
---|
707 | |
---|
708 | std::memset(r_dcache_in_itlb, 0, sizeof(*r_dcache_in_itlb)*m_icache_ways*m_icache_sets); |
---|
709 | std::memset(r_dcache_in_dtlb, 0, sizeof(*r_dcache_in_dtlb)*m_dcache_ways*m_dcache_sets); |
---|
710 | |
---|
711 | |
---|
712 | // Response FIFOs and cleanup buffer |
---|
713 | r_vci_rsp_fifo_icache.init(); |
---|
714 | r_vci_rsp_fifo_dcache.init(); |
---|
715 | r_cleanup_buffer.reset(); |
---|
716 | |
---|
717 | // ICACHE & DCACHE activated |
---|
718 | r_mmu_mode = 0x3; |
---|
719 | |
---|
720 | // No request from ICACHE FSM to CMD FSM |
---|
721 | r_icache_miss_req = false; |
---|
722 | r_icache_unc_req = false; |
---|
723 | |
---|
724 | // No request from ICACHE_FSM to DCACHE FSM |
---|
725 | r_icache_tlb_miss_req = false; |
---|
726 | |
---|
727 | // No request from ICACHE_FSM to CLEANUP FSMs |
---|
728 | r_icache_cleanup_req = false; |
---|
729 | |
---|
730 | // No pending write in pipeline |
---|
731 | r_dcache_p0_valid = false; |
---|
732 | r_dcache_p1_valid = false; |
---|
733 | |
---|
734 | // No request from DCACHE_FSM to CMD_FSM |
---|
735 | r_dcache_vci_miss_req = false; |
---|
736 | r_dcache_vci_unc_req = false; |
---|
737 | r_dcache_vci_sc_req = false; |
---|
738 | |
---|
739 | // No uncacheable write pending |
---|
740 | r_dcache_pending_unc_write = false; |
---|
741 | |
---|
742 | // No LL reservation |
---|
743 | r_dcache_ll_valid = false; |
---|
744 | |
---|
745 | // No request from DCACHE FSM to INVAL TLB FSMs |
---|
746 | r_dcache_itlb_inval_req = false; |
---|
747 | r_dcache_dtlb_inval_req = false; |
---|
748 | |
---|
749 | // No processor XTN request pending |
---|
750 | r_dcache_xtn_req = false; |
---|
751 | |
---|
752 | // No request from DCACHE FSM to CLEANUP FSMs |
---|
753 | r_dcache_cleanup_req = false; |
---|
754 | |
---|
755 | // No request from TGT FSM to ICACHE/DCACHE FSMs |
---|
756 | r_tgt_icache_req = false; |
---|
757 | r_tgt_dcache_req = false; |
---|
758 | |
---|
759 | // No signalisation of a coherence request matching a pending miss |
---|
760 | r_icache_miss_inval = false; |
---|
761 | r_dcache_miss_inval = false; |
---|
762 | |
---|
763 | // No signalisation of errors |
---|
764 | r_vci_rsp_ins_error = false; |
---|
765 | r_vci_rsp_data_error = false; |
---|
766 | |
---|
767 | // Debug variables |
---|
768 | m_debug_previous_hit = false; |
---|
769 | m_debug_dcache_fsm = false; |
---|
770 | m_debug_icache_fsm = false; |
---|
771 | m_debug_cleanup_fsm = false; |
---|
772 | m_debug_inval_itlb_fsm = false; |
---|
773 | m_debug_inval_dtlb_fsm = false; |
---|
774 | |
---|
775 | /* |
---|
776 | // activity counters |
---|
777 | m_cpt_dcache_data_read = 0; |
---|
778 | m_cpt_dcache_data_write = 0; |
---|
779 | m_cpt_dcache_dir_read = 0; |
---|
780 | m_cpt_dcache_dir_write = 0; |
---|
781 | m_cpt_icache_data_read = 0; |
---|
782 | m_cpt_icache_data_write = 0; |
---|
783 | m_cpt_icache_dir_read = 0; |
---|
784 | m_cpt_icache_dir_write = 0; |
---|
785 | |
---|
786 | m_cpt_frz_cycles = 0; |
---|
787 | m_cpt_dcache_frz_cycles = 0; |
---|
788 | m_cpt_total_cycles = 0; |
---|
789 | |
---|
790 | m_cpt_read = 0; |
---|
791 | m_cpt_write = 0; |
---|
792 | m_cpt_data_miss = 0; |
---|
793 | m_cpt_ins_miss = 0; |
---|
794 | m_cpt_unc_read = 0; |
---|
795 | m_cpt_write_cached = 0; |
---|
796 | m_cpt_ins_read = 0; |
---|
797 | |
---|
798 | m_cost_write_frz = 0; |
---|
799 | m_cost_data_miss_frz = 0; |
---|
800 | m_cost_unc_read_frz = 0; |
---|
801 | m_cost_ins_miss_frz = 0; |
---|
802 | |
---|
803 | m_cpt_imiss_transaction = 0; |
---|
804 | m_cpt_dmiss_transaction = 0; |
---|
805 | m_cpt_unc_transaction = 0; |
---|
806 | m_cpt_write_transaction = 0; |
---|
807 | m_cpt_icache_unc_transaction = 0; |
---|
808 | |
---|
809 | m_cost_imiss_transaction = 0; |
---|
810 | m_cost_dmiss_transaction = 0; |
---|
811 | m_cost_unc_transaction = 0; |
---|
812 | m_cost_write_transaction = 0; |
---|
813 | m_cost_icache_unc_transaction = 0; |
---|
814 | m_length_write_transaction = 0; |
---|
815 | |
---|
816 | m_cpt_ins_tlb_read = 0; |
---|
817 | m_cpt_ins_tlb_miss = 0; |
---|
818 | m_cpt_ins_tlb_update_acc = 0; |
---|
819 | |
---|
820 | m_cpt_data_tlb_read = 0; |
---|
821 | m_cpt_data_tlb_miss = 0; |
---|
822 | m_cpt_data_tlb_update_acc = 0; |
---|
823 | m_cpt_data_tlb_update_dirty = 0; |
---|
824 | m_cpt_ins_tlb_hit_dcache = 0; |
---|
825 | m_cpt_data_tlb_hit_dcache = 0; |
---|
826 | m_cpt_ins_tlb_occup_cache = 0; |
---|
827 | m_cpt_data_tlb_occup_cache = 0; |
---|
828 | |
---|
829 | m_cost_ins_tlb_miss_frz = 0; |
---|
830 | m_cost_data_tlb_miss_frz = 0; |
---|
831 | m_cost_ins_tlb_update_acc_frz = 0; |
---|
832 | m_cost_data_tlb_update_acc_frz = 0; |
---|
833 | m_cost_data_tlb_update_dirty_frz = 0; |
---|
834 | m_cost_ins_tlb_occup_cache_frz = 0; |
---|
835 | m_cost_data_tlb_occup_cache_frz = 0; |
---|
836 | |
---|
837 | m_cpt_ins_tlb_inval = 0; |
---|
838 | m_cpt_data_tlb_inval = 0; |
---|
839 | m_cost_ins_tlb_inval_frz = 0; |
---|
840 | m_cost_data_tlb_inval_frz = 0; |
---|
841 | |
---|
842 | m_cpt_cc_update_data = 0; |
---|
843 | m_cpt_cc_inval_ins = 0; |
---|
844 | m_cpt_cc_inval_data = 0; |
---|
845 | m_cpt_cc_broadcast = 0; |
---|
846 | |
---|
847 | m_cost_updt_data_frz = 0; |
---|
848 | m_cost_inval_ins_frz = 0; |
---|
849 | m_cost_inval_data_frz = 0; |
---|
850 | m_cost_broadcast_frz = 0; |
---|
851 | |
---|
852 | m_cpt_cc_cleanup_data = 0; |
---|
853 | m_cpt_cc_cleanup_ins = 0; |
---|
854 | |
---|
855 | m_cpt_itlbmiss_transaction = 0; |
---|
856 | m_cpt_itlb_ll_transaction = 0; |
---|
857 | m_cpt_itlb_sc_transaction = 0; |
---|
858 | m_cpt_dtlbmiss_transaction = 0; |
---|
859 | m_cpt_dtlb_ll_transaction = 0; |
---|
860 | m_cpt_dtlb_sc_transaction = 0; |
---|
861 | m_cpt_dtlb_ll_dirty_transaction = 0; |
---|
862 | m_cpt_dtlb_sc_dirty_transaction = 0; |
---|
863 | |
---|
864 | m_cost_itlbmiss_transaction = 0; |
---|
865 | m_cost_itlb_ll_transaction = 0; |
---|
866 | m_cost_itlb_sc_transaction = 0; |
---|
867 | m_cost_dtlbmiss_transaction = 0; |
---|
868 | m_cost_dtlb_ll_transaction = 0; |
---|
869 | m_cost_dtlb_sc_transaction = 0; |
---|
870 | m_cost_dtlb_ll_dirty_transaction = 0; |
---|
871 | m_cost_dtlb_sc_dirty_transaction = 0; |
---|
872 | |
---|
873 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; |
---|
874 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; |
---|
875 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0; |
---|
876 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0; |
---|
877 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0; |
---|
878 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0; |
---|
879 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0; |
---|
880 | |
---|
881 | */ |
---|
882 | return; |
---|
883 | } |
---|
884 | |
---|
885 | // Response FIFOs default values |
---|
886 | bool vci_rsp_fifo_icache_get = false; |
---|
887 | bool vci_rsp_fifo_icache_put = false; |
---|
888 | uint32_t vci_rsp_fifo_icache_data = 0; |
---|
889 | |
---|
890 | bool vci_rsp_fifo_dcache_get = false; |
---|
891 | bool vci_rsp_fifo_dcache_put = false; |
---|
892 | uint32_t vci_rsp_fifo_dcache_data = 0; |
---|
893 | |
---|
894 | #ifdef INSTRUMENTATION |
---|
895 | m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; |
---|
896 | m_cpt_fsm_icache [r_icache_fsm.read() ] ++; |
---|
897 | m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++; |
---|
898 | m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++; |
---|
899 | m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++; |
---|
900 | m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++; |
---|
901 | #endif |
---|
902 | |
---|
903 | m_cpt_total_cycles++; |
---|
904 | |
---|
905 | m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
906 | m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
907 | m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
908 | m_debug_inval_itlb_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
909 | m_debug_inval_dtlb_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
910 | |
---|
911 | ///////////////////////////////////////////////////////////////////// |
---|
912 | // The TGT_FSM controls the following ressources: |
---|
913 | // - r_tgt_fsm |
---|
914 | // - r_tgt_buf[nwords] |
---|
915 | // - r_tgt_be[nwords] |
---|
916 | // - r_tgt_update |
---|
917 | // - r_tgt_word_min |
---|
918 | // - r_tgt_word_max |
---|
919 | // - r_tgt_word_count |
---|
920 | // - r_tgt_paddr |
---|
921 | // - r_tgt_srcid |
---|
922 | // - r_tgt_trdid |
---|
923 | // - r_tgt_pktid |
---|
924 | // - r_tgt_icache_req (set) |
---|
925 | // - r_tgt_dcache_req (set) |
---|
926 | // |
---|
927 | // All VCI commands must be CMD_WRITE. |
---|
928 | // - If the 2 LSB bits of the VCI address are 11, it is a broadcast request. |
---|
929 | // It is a multicast request otherwise. |
---|
930 | // - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS |
---|
931 | // (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes |
---|
932 | // INVAL/UPDATE (0 for invalidate / 1 for UPDATE). |
---|
933 | // |
---|
934 | // For all types of coherence request, the line index (i.e. the Z & Y fields) |
---|
935 | // is coded on 34 bits, and is contained in the WDATA and BE fields |
---|
936 | // of the first VCI flit. |
---|
937 | // - for a multicast invalidate or for a broadcast invalidate request |
---|
938 | // the VCI packet length is 1 word. |
---|
939 | // - for an update request the VCI packet length is (n+2) words. |
---|
940 | // The WDATA field of the second VCI word contains the word index. |
---|
941 | // The WDATA field of the n following words contains the values. |
---|
942 | // - for all transaction types, the VCI response is one single word. |
---|
943 | // In case of errors in the VCI command packet, the simulation |
---|
944 | // is stopped with an error message. |
---|
945 | // |
---|
946 | // This FSM is NOT pipelined : It consumes a new coherence request |
---|
947 | // on the VCI port only when the previous request is completed. |
---|
948 | // |
---|
949 | // The VCI_TGT FSM stores the external request arguments in the |
---|
950 | // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req |
---|
951 | // and/or the r_tgt_dcache_req flip-flops to signal the coherence request |
---|
952 | // to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST |
---|
953 | // states. It waits the completion of the coherence request by polling the |
---|
954 | // r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST |
---|
955 | // states. These flip-flops are reset by the ICACHE and DCACHE FSMs. |
---|
956 | // These two FSMs signal if a VCI answer must be send by setting |
---|
957 | // the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops. |
---|
958 | /////////////////////////////////////////////////////////////////////////////// |
---|
959 | |
---|
960 | switch( r_tgt_fsm.read() ) |
---|
961 | { |
---|
962 | ////////////// |
---|
963 | case TGT_IDLE: |
---|
964 | { |
---|
965 | if ( p_vci_tgt_c.cmdval.read() ) |
---|
966 | { |
---|
967 | paddr_t address = p_vci_tgt_c.address.read(); |
---|
968 | |
---|
969 | // command checking |
---|
970 | if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE) |
---|
971 | { |
---|
972 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
973 | std::cout << "the received VCI coherence command is not a write" << std::endl; |
---|
974 | exit(0); |
---|
975 | } |
---|
976 | |
---|
977 | // address checking |
---|
978 | if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) ) |
---|
979 | { |
---|
980 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
981 | std::cout << "out of segment VCI coherence command received" << std::endl; |
---|
982 | exit(0); |
---|
983 | } |
---|
984 | |
---|
985 | r_tgt_srcid = p_vci_tgt_c.srcid.read(); |
---|
986 | r_tgt_trdid = p_vci_tgt_c.trdid.read(); |
---|
987 | r_tgt_pktid = p_vci_tgt_c.pktid.read(); |
---|
988 | |
---|
989 | r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 | |
---|
990 | (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; |
---|
991 | |
---|
992 | if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type |
---|
993 | { |
---|
994 | if ( not p_vci_tgt_c.eop.read() ) |
---|
995 | { |
---|
996 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
997 | std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl; |
---|
998 | exit(0); |
---|
999 | } |
---|
1000 | r_tgt_update = false; |
---|
1001 | r_tgt_fsm = TGT_REQ_BROADCAST; |
---|
1002 | |
---|
1003 | #ifdef INSTRUMENTATION |
---|
1004 | m_cpt_cc_broadcast++; |
---|
1005 | #endif |
---|
1006 | } |
---|
1007 | else // multi-update or multi-invalidate for data type |
---|
1008 | { |
---|
1009 | paddr_t cell = address - m_segment.baseAddress(); |
---|
1010 | |
---|
1011 | if (cell == 0) // invalidate data |
---|
1012 | { |
---|
1013 | if ( not p_vci_tgt_c.eop.read() ) |
---|
1014 | { |
---|
1015 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
1016 | std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl; |
---|
1017 | exit(0); |
---|
1018 | } |
---|
1019 | r_tgt_update = false; |
---|
1020 | r_tgt_fsm = TGT_REQ_DCACHE; |
---|
1021 | |
---|
1022 | #ifdef INSTRUMENTATION |
---|
1023 | m_cpt_cc_inval_dcache++; |
---|
1024 | #endif |
---|
1025 | } |
---|
1026 | else if (cell == 4) // invalidate instruction |
---|
1027 | { |
---|
1028 | if ( not p_vci_tgt_c.eop.read() ) |
---|
1029 | { |
---|
1030 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
1031 | std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl; |
---|
1032 | exit(0); |
---|
1033 | } |
---|
1034 | r_tgt_update = false; |
---|
1035 | r_tgt_fsm = TGT_REQ_ICACHE; |
---|
1036 | |
---|
1037 | #ifdef INSTRUMENTATION |
---|
1038 | m_cpt_cc_inval_icache++; |
---|
1039 | #endif |
---|
1040 | } |
---|
1041 | else if (cell == 8) // update data |
---|
1042 | { |
---|
1043 | if ( p_vci_tgt_c.eop.read() ) |
---|
1044 | { |
---|
1045 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
1046 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
1047 | exit(0); |
---|
1048 | } |
---|
1049 | r_tgt_update = true; |
---|
1050 | r_tgt_update_data = true; |
---|
1051 | r_tgt_fsm = TGT_UPDT_WORD; |
---|
1052 | |
---|
1053 | #ifdef INSTRUMENTATION |
---|
1054 | m_cpt_cc_update_dcache++; |
---|
1055 | #endif |
---|
1056 | } |
---|
1057 | else // update instruction |
---|
1058 | { |
---|
1059 | if ( p_vci_tgt_c.eop.read() ) |
---|
1060 | { |
---|
1061 | std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
1062 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
1063 | exit(0); |
---|
1064 | } |
---|
1065 | r_tgt_update = true; |
---|
1066 | r_tgt_update_data = false; |
---|
1067 | r_tgt_fsm = TGT_UPDT_WORD; |
---|
1068 | |
---|
1069 | #ifdef INSTRUMENTATION |
---|
1070 | m_cpt_cc_update_icache++; |
---|
1071 | #endif |
---|
1072 | } |
---|
1073 | } // end if multi |
---|
1074 | } // end if cmdval |
---|
1075 | break; |
---|
1076 | } |
---|
1077 | /////////////////// |
---|
1078 | case TGT_UPDT_WORD: // first word index acquisition |
---|
1079 | { |
---|
1080 | if (p_vci_tgt_c.cmdval.read()) |
---|
1081 | { |
---|
1082 | if ( p_vci_tgt_c.eop.read() ) |
---|
1083 | { |
---|
1084 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
1085 | std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl; |
---|
1086 | exit(0); |
---|
1087 | } |
---|
1088 | for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false; |
---|
1089 | |
---|
1090 | r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index |
---|
1091 | r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index |
---|
1092 | r_tgt_fsm = TGT_UPDT_DATA; |
---|
1093 | } |
---|
1094 | break; |
---|
1095 | } |
---|
1096 | /////////////////// |
---|
1097 | case TGT_UPDT_DATA: |
---|
1098 | { |
---|
1099 | if (p_vci_tgt_c.cmdval.read()) |
---|
1100 | { |
---|
1101 | size_t word = r_tgt_word_count.read(); |
---|
1102 | if (word >= m_dcache_words) |
---|
1103 | { |
---|
1104 | std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; |
---|
1105 | std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl; |
---|
1106 | exit(0); |
---|
1107 | } |
---|
1108 | r_tgt_buf[word] = p_vci_tgt_c.wdata.read(); |
---|
1109 | r_tgt_be[word] = p_vci_tgt_c.be.read(); |
---|
1110 | r_tgt_word_count = word + 1; |
---|
1111 | |
---|
1112 | if (p_vci_tgt_c.eop.read()) // last word |
---|
1113 | { |
---|
1114 | r_tgt_word_max = word; |
---|
1115 | if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE; |
---|
1116 | else r_tgt_fsm = TGT_REQ_ICACHE; |
---|
1117 | } |
---|
1118 | } |
---|
1119 | break; |
---|
1120 | } |
---|
1121 | /////////////////////// |
---|
1122 | case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs |
---|
1123 | { |
---|
1124 | if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) |
---|
1125 | { |
---|
1126 | r_tgt_fsm = TGT_RSP_BROADCAST; |
---|
1127 | r_tgt_icache_req = true; |
---|
1128 | r_tgt_dcache_req = true; |
---|
1129 | } |
---|
1130 | break; |
---|
1131 | } |
---|
1132 | ///////////////////// |
---|
1133 | case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending) |
---|
1134 | { |
---|
1135 | if ( not r_tgt_icache_req.read() ) |
---|
1136 | { |
---|
1137 | r_tgt_fsm = TGT_RSP_ICACHE; |
---|
1138 | r_tgt_icache_req = true; |
---|
1139 | } |
---|
1140 | break; |
---|
1141 | } |
---|
1142 | //////////////////// |
---|
1143 | case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending) |
---|
1144 | { |
---|
1145 | if ( not r_tgt_dcache_req.read() ) |
---|
1146 | { |
---|
1147 | r_tgt_fsm = TGT_RSP_DCACHE; |
---|
1148 | r_tgt_dcache_req = true; |
---|
1149 | } |
---|
1150 | break; |
---|
1151 | } |
---|
1152 | /////////////////////// |
---|
1153 | case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs |
---|
1154 | // no response when r_tgt_*cache_rsp is false |
---|
1155 | { |
---|
1156 | if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed |
---|
1157 | { |
---|
1158 | if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response |
---|
1159 | { |
---|
1160 | if ( p_vci_tgt_c.rspack.read() ) |
---|
1161 | { |
---|
1162 | // reset dcache first if activated |
---|
1163 | if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false; |
---|
1164 | else r_tgt_icache_rsp = false; |
---|
1165 | } |
---|
1166 | } |
---|
1167 | else |
---|
1168 | { |
---|
1169 | r_tgt_fsm = TGT_IDLE; |
---|
1170 | } |
---|
1171 | } |
---|
1172 | break; |
---|
1173 | } |
---|
1174 | //////////////////// |
---|
1175 | case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM |
---|
1176 | { |
---|
1177 | // no response when r_tgt_icache_rsp is false |
---|
1178 | if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() ) |
---|
1179 | { |
---|
1180 | r_tgt_fsm = TGT_IDLE; |
---|
1181 | r_tgt_icache_rsp = false; |
---|
1182 | } |
---|
1183 | break; |
---|
1184 | } |
---|
1185 | //////////////////// |
---|
1186 | case TGT_RSP_DCACHE: |
---|
1187 | { |
---|
1188 | // no response when r_tgt_dcache_rsp is false |
---|
1189 | if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() ) |
---|
1190 | { |
---|
1191 | r_tgt_fsm = TGT_IDLE; |
---|
1192 | r_tgt_dcache_rsp = false; |
---|
1193 | } |
---|
1194 | break; |
---|
1195 | } |
---|
1196 | } // end switch TGT_FSM |
---|
1197 | |
---|
1198 | ///////////////////////////////////////////////////////////////////// |
---|
1199 | // Get data and instruction requests from processor |
---|
1200 | /////////////////////////////////////////////////////////////////////// |
---|
1201 | |
---|
1202 | typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER; |
---|
1203 | typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER; |
---|
1204 | |
---|
1205 | r_iss.getRequests(ireq, dreq); |
---|
1206 | |
---|
1207 | //////////////////////////////////////////////////////////////////////////////////// |
---|
1208 | // ICACHE_FSM |
---|
1209 | // |
---|
1210 | // There is 9 conditions to exit the IDLE state: |
---|
1211 | // One condition is a coherence request from TGT FSM : |
---|
1212 | // - Coherence operation => ICACHE_CC_CHEK |
---|
1213 | // Five configurations corresponding to XTN processor requests sent by DCACHE FSM : |
---|
1214 | // - Flush TLB => ICACHE_XTN_TLB_FLUSH |
---|
1215 | // - Flush cache => ICACHE_XTN_CACHE_FLUSH |
---|
1216 | // - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL |
---|
1217 | // - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@ |
---|
1218 | // - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA |
---|
1219 | // three configurations corresponding to instruction processor requests : |
---|
1220 | // - tlb miss => ICACHE_TLB_WAIT |
---|
1221 | // - cacheable read miss => ICACHE_MISS_VICTIM |
---|
1222 | // - uncacheable read miss => ICACHE_UNC_REQ |
---|
1223 | // |
---|
1224 | // In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM |
---|
1225 | // using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the |
---|
1226 | // transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM |
---|
1227 | // state to select a slot and request a VCI transaction to the CLEANUP FSM. |
---|
1228 | // It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM. |
---|
1229 | // The availability of the missing cache line is signaled by the response fifo, |
---|
1230 | // and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state. |
---|
1231 | // |
---|
1232 | // In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction |
---|
1233 | // to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop |
---|
1234 | // when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait |
---|
1235 | // the response from the RSP FSM, through the response fifo. The missing instruction |
---|
1236 | // is directly returned to processor in this state. |
---|
1237 | // |
---|
1238 | // In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb |
---|
1239 | // using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register, |
---|
1240 | // and goes to the ICACHE_TLB_WAIT state. |
---|
1241 | // The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until |
---|
1242 | // the update is completed, and reset r_icache_tlb_miss_req to signal the completion. |
---|
1243 | // |
---|
1244 | // The DCACHE FSM signals XTN processor requests to ICACHE_FSM |
---|
1245 | // using the r_dcache_xtn_req flip-flop. |
---|
1246 | // The request opcode and the address to be invalidated are transmitted |
---|
1247 | // in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively. |
---|
1248 | // The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation |
---|
1249 | // is completed. |
---|
1250 | // |
---|
1251 | // The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error |
---|
1252 | // in a cache miss or uncacheable read VCI transaction. Nothing is written |
---|
1253 | // in the response fifo. This flip-flop is reset by the ICACHE-FSM. |
---|
1254 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
1255 | |
---|
1256 | // The default value for irsp.valid is false |
---|
1257 | typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER; |
---|
1258 | |
---|
1259 | switch( r_icache_fsm.read() ) |
---|
1260 | { |
---|
1261 | ///////////////// |
---|
1262 | case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent |
---|
1263 | // by DCACHE FSM, and coherence requests with a fixed priority: |
---|
1264 | // coherence > XTN > instruction |
---|
1265 | // We access the itlb and dcache in parallel with the virtual address |
---|
1266 | // for itlb, and with a speculative physical address for icache, |
---|
1267 | // computed during the previous cycle. |
---|
1268 | { |
---|
1269 | // coherence request from the target FSM |
---|
1270 | if ( r_tgt_icache_req.read() ) |
---|
1271 | { |
---|
1272 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
1273 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
1274 | break; |
---|
1275 | } |
---|
1276 | |
---|
1277 | // Decoding processor XTN requests sent by DCACHE FSM |
---|
1278 | // These request are not executed in this IDLE state, because |
---|
1279 | // they require access to icache or itlb, that are already accessed |
---|
1280 | if ( r_dcache_xtn_req.read() ) |
---|
1281 | { |
---|
1282 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) |
---|
1283 | { |
---|
1284 | r_icache_fsm = ICACHE_XTN_TLB_FLUSH; |
---|
1285 | break; |
---|
1286 | } |
---|
1287 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH) |
---|
1288 | { |
---|
1289 | r_icache_flush_count = 0; |
---|
1290 | r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; |
---|
1291 | break; |
---|
1292 | } |
---|
1293 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) |
---|
1294 | { |
---|
1295 | r_icache_fsm = ICACHE_XTN_TLB_INVAL; |
---|
1296 | break; |
---|
1297 | } |
---|
1298 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) |
---|
1299 | { |
---|
1300 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; |
---|
1301 | break; |
---|
1302 | } |
---|
1303 | if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) |
---|
1304 | { |
---|
1305 | r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | |
---|
1306 | (paddr_t)r_mmu_word_lo.read(); |
---|
1307 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
1308 | break; |
---|
1309 | } |
---|
1310 | } // end if xtn_req |
---|
1311 | |
---|
1312 | // processor request |
---|
1313 | if ( ireq.valid ) |
---|
1314 | { |
---|
1315 | bool cacheable; |
---|
1316 | paddr_t paddr; |
---|
1317 | |
---|
1318 | // We register processor request |
---|
1319 | r_icache_vaddr_save = ireq.addr; |
---|
1320 | |
---|
1321 | // speculative icache access (if cache activated) |
---|
1322 | // we use the speculative PPN computed during the previous cycle |
---|
1323 | |
---|
1324 | uint32_t cache_inst = 0; |
---|
1325 | bool cache_hit = false; |
---|
1326 | |
---|
1327 | if ( r_mmu_mode.read() & INS_CACHE_MASK ) |
---|
1328 | { |
---|
1329 | paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) | |
---|
1330 | ((paddr_t)ireq.addr & PAGE_K_MASK); |
---|
1331 | |
---|
1332 | #ifdef INSTRUMENTATION |
---|
1333 | m_cpt_icache_data_read++; |
---|
1334 | m_cpt_icache_dir_read++; |
---|
1335 | #endif |
---|
1336 | cache_hit = r_icache.read( spc_paddr, |
---|
1337 | &cache_inst ); |
---|
1338 | } |
---|
1339 | |
---|
1340 | // systematic itlb access (if tlb activated) |
---|
1341 | // we use the virtual address |
---|
1342 | |
---|
1343 | paddr_t tlb_paddr; |
---|
1344 | pte_info_t tlb_flags; |
---|
1345 | size_t tlb_way; |
---|
1346 | size_t tlb_set; |
---|
1347 | paddr_t tlb_nline; |
---|
1348 | bool tlb_hit = false;; |
---|
1349 | |
---|
1350 | if ( r_mmu_mode.read() & INS_TLB_MASK ) |
---|
1351 | { |
---|
1352 | |
---|
1353 | #ifdef INSTRUMENTATION |
---|
1354 | m_cpt_itlb_read++; |
---|
1355 | #endif |
---|
1356 | tlb_hit = r_itlb.translate( ireq.addr, |
---|
1357 | &tlb_paddr, |
---|
1358 | &tlb_flags, |
---|
1359 | &tlb_nline, // unused |
---|
1360 | &tlb_way, // unused |
---|
1361 | &tlb_set ); // unused |
---|
1362 | } |
---|
1363 | |
---|
1364 | // We compute cacheability, physical address and check access rights: |
---|
1365 | // - If MMU activated : cacheability is defined by the C bit in the PTE, |
---|
1366 | // the physical address is obtained from the TLB, and the access rights are |
---|
1367 | // defined by the U and X bits in the PTE. |
---|
1368 | // - If MMU not activated : cacheability is defined by the segment table, |
---|
1369 | // the physical address is equal to the virtual address (identity mapping) |
---|
1370 | // and there is no access rights checking |
---|
1371 | |
---|
1372 | if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: |
---|
1373 | { |
---|
1374 | // cacheability |
---|
1375 | if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; |
---|
1376 | else cacheable = m_cacheability_table[ireq.addr]; |
---|
1377 | |
---|
1378 | // physical address |
---|
1379 | paddr = (paddr_t)ireq.addr; |
---|
1380 | } |
---|
1381 | else // itlb activated |
---|
1382 | { |
---|
1383 | if ( tlb_hit ) // tlb hit |
---|
1384 | { |
---|
1385 | // cacheability |
---|
1386 | if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; |
---|
1387 | else cacheable = tlb_flags.c; |
---|
1388 | |
---|
1389 | // physical address |
---|
1390 | paddr = tlb_paddr; |
---|
1391 | |
---|
1392 | // access rights checking |
---|
1393 | if ( not tlb_flags.u && (ireq.mode == iss_t::MODE_USER) ) |
---|
1394 | { |
---|
1395 | r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
1396 | r_mmu_ibvar = ireq.addr; |
---|
1397 | irsp.valid = true; |
---|
1398 | irsp.error = true; |
---|
1399 | irsp.instruction = 0; |
---|
1400 | break; |
---|
1401 | } |
---|
1402 | else if ( not tlb_flags.x ) |
---|
1403 | { |
---|
1404 | r_mmu_ietr = MMU_READ_EXEC_VIOLATION; |
---|
1405 | r_mmu_ibvar = ireq.addr; |
---|
1406 | irsp.valid = true; |
---|
1407 | irsp.error = true; |
---|
1408 | irsp.instruction = 0; |
---|
1409 | break; |
---|
1410 | } |
---|
1411 | } |
---|
1412 | // in case of TLB miss we send an itlb miss request to DCACHE FSM and break |
---|
1413 | else |
---|
1414 | { |
---|
1415 | |
---|
1416 | #ifdef INSTRUMENTATION |
---|
1417 | m_cpt_itlb_miss++; |
---|
1418 | #endif |
---|
1419 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
1420 | r_icache_tlb_miss_req = true; |
---|
1421 | break; |
---|
1422 | } |
---|
1423 | } // end if itlb activated |
---|
1424 | |
---|
1425 | // physical address registration (for next cycle) |
---|
1426 | r_icache_vci_paddr = paddr; |
---|
1427 | |
---|
1428 | // We enter this section only in case of TLB hit: |
---|
1429 | // Finally, we get the instruction depending on cacheability, |
---|
1430 | // we send the response to processor, and compute next state |
---|
1431 | if ( cacheable ) // cacheable read |
---|
1432 | { |
---|
1433 | if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK) |
---|
1434 | != (paddr & ~PAGE_K_MASK) ) // speculative access KO |
---|
1435 | { |
---|
1436 | |
---|
1437 | #ifdef INSTRUMENTATION |
---|
1438 | m_cpt_icache_spc_miss++; |
---|
1439 | #endif |
---|
1440 | // we return an invalid response and stay in IDLE state |
---|
1441 | // the cache access will cost one extra cycle. |
---|
1442 | break; |
---|
1443 | } |
---|
1444 | |
---|
1445 | if ( not cache_hit ) // cache miss |
---|
1446 | { |
---|
1447 | // in case of icache miss we send a request to CMD FSM, but we are |
---|
1448 | // blocked in IDLE state if the previous cleanup is not completed |
---|
1449 | if ( not r_icache_cleanup_req.read() ) |
---|
1450 | { |
---|
1451 | |
---|
1452 | #ifdef INSTRUMENTATION |
---|
1453 | m_cpt_icache_miss++; |
---|
1454 | #endif |
---|
1455 | r_icache_fsm = ICACHE_MISS_VICTIM; |
---|
1456 | r_icache_miss_req = true; |
---|
1457 | } |
---|
1458 | break; |
---|
1459 | } |
---|
1460 | else // cache hit |
---|
1461 | { |
---|
1462 | |
---|
1463 | #ifdef INSTRUMENTATION |
---|
1464 | m_cpt_ins_read++; |
---|
1465 | #endif |
---|
1466 | irsp.valid = true; |
---|
1467 | irsp.instruction = cache_inst; |
---|
1468 | } |
---|
1469 | } |
---|
1470 | else // non cacheable read |
---|
1471 | { |
---|
1472 | r_icache_unc_req = true; |
---|
1473 | r_icache_fsm = ICACHE_UNC_WAIT; |
---|
1474 | } |
---|
1475 | } // end if ireq.valid |
---|
1476 | break; |
---|
1477 | } |
---|
1478 | ///////////////////// |
---|
1479 | case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss |
---|
1480 | // the itlb is udated by the DCACHE FSM, as well as the |
---|
1481 | // r_mmu_ietr and r_mmu_ibvar registers in case of error. |
---|
1482 | // the itlb is not accessed by ICACHE FSM until DCACHE FSM |
---|
1483 | // reset the r_icache_tlb_miss_req flip-flop |
---|
1484 | // external coherence request are accepted in this state. |
---|
1485 | { |
---|
1486 | // external coherence request |
---|
1487 | if ( r_tgt_icache_req.read() ) |
---|
1488 | { |
---|
1489 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
1490 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
1491 | break; |
---|
1492 | } |
---|
1493 | |
---|
1494 | if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; |
---|
1495 | |
---|
1496 | // DCACHE FSM signals response by reseting the request flip-flop |
---|
1497 | if ( not r_icache_tlb_miss_req.read() ) |
---|
1498 | { |
---|
1499 | if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated |
---|
1500 | { |
---|
1501 | r_icache_tlb_rsp_error = false; |
---|
1502 | irsp.error = true; |
---|
1503 | irsp.valid = true; |
---|
1504 | r_icache_fsm = ICACHE_IDLE; |
---|
1505 | } |
---|
1506 | else // tlb updated : return to IDLE state |
---|
1507 | { |
---|
1508 | r_icache_fsm = ICACHE_IDLE; |
---|
1509 | } |
---|
1510 | } |
---|
1511 | break; |
---|
1512 | } |
---|
1513 | ////////////////////////// |
---|
1514 | case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries |
---|
1515 | { |
---|
1516 | r_itlb.flush(); |
---|
1517 | r_dcache_xtn_req = false; |
---|
1518 | r_icache_fsm = ICACHE_IDLE; |
---|
1519 | break; |
---|
1520 | } |
---|
1521 | //////////////////////////// |
---|
1522 | case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using |
---|
1523 | // the r_icache_flush_count register as a slot counter. |
---|
1524 | // We loop in this state until all slots have been visited. |
---|
1525 | // A cleanup request is generated for each valid line |
---|
1526 | // and we are blocked until the previous cleanup is completed |
---|
1527 | { |
---|
1528 | if ( not r_icache_cleanup_req.read() ) |
---|
1529 | { |
---|
1530 | size_t way = r_icache_flush_count.read()/m_icache_sets; |
---|
1531 | size_t set = r_icache_flush_count.read()%m_icache_sets; |
---|
1532 | paddr_t nline; |
---|
1533 | bool cleanup_req = r_icache.inval( way, |
---|
1534 | set, |
---|
1535 | &nline ); |
---|
1536 | if ( cleanup_req ) |
---|
1537 | { |
---|
1538 | r_icache_cleanup_req = true; |
---|
1539 | r_icache_cleanup_line = nline; |
---|
1540 | } |
---|
1541 | r_icache_flush_count = r_icache_flush_count.read() + 1; |
---|
1542 | } |
---|
1543 | |
---|
1544 | if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) ) |
---|
1545 | { |
---|
1546 | r_dcache_xtn_req = false; |
---|
1547 | r_icache_fsm = ICACHE_IDLE; |
---|
1548 | } |
---|
1549 | break; |
---|
1550 | } |
---|
1551 | ////////////////////////// |
---|
1552 | case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address |
---|
1553 | // stored in the r_dcache_p0_wdata register |
---|
1554 | { |
---|
1555 | r_itlb.inval(r_dcache_p0_wdata.read()); |
---|
1556 | r_dcache_xtn_req = false; |
---|
1557 | r_icache_fsm = ICACHE_IDLE; |
---|
1558 | break; |
---|
1559 | } |
---|
1560 | /////////////////////////////// |
---|
1561 | case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address |
---|
1562 | // requires 3 cycles (in case of hit on itlb and icache). |
---|
1563 | // In this state, we access TLB to translate virtual address |
---|
1564 | // stored in the r_dcache_p0_wdata register. |
---|
1565 | { |
---|
1566 | paddr_t paddr; |
---|
1567 | bool hit; |
---|
1568 | |
---|
1569 | // read physical address in TLB when MMU activated |
---|
1570 | if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated |
---|
1571 | { |
---|
1572 | |
---|
1573 | #ifdef INSTRUMENTATION |
---|
1574 | m_cpt_itlb_read++; |
---|
1575 | #endif |
---|
1576 | hit = r_itlb.translate(r_dcache_p0_wdata.read(), |
---|
1577 | &paddr); |
---|
1578 | } |
---|
1579 | else // itlb not activated |
---|
1580 | { |
---|
1581 | paddr = (paddr_t)r_dcache_p0_wdata.read(); |
---|
1582 | hit = true; |
---|
1583 | } |
---|
1584 | |
---|
1585 | if ( hit ) // continue the selective inval process |
---|
1586 | { |
---|
1587 | r_icache_vci_paddr = paddr; |
---|
1588 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; |
---|
1589 | } |
---|
1590 | else // miss : send a request to DCACHE FSM |
---|
1591 | { |
---|
1592 | |
---|
1593 | #ifdef INSTRUMENTATION |
---|
1594 | m_cpt_itlb_miss++; |
---|
1595 | #endif |
---|
1596 | r_icache_tlb_miss_req = true; |
---|
1597 | r_icache_fsm = ICACHE_TLB_WAIT; |
---|
1598 | } |
---|
1599 | break; |
---|
1600 | } |
---|
1601 | /////////////////////////////// |
---|
1602 | case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address |
---|
1603 | // require 2 cycles. In this state, we read dcache, |
---|
1604 | // with address stored in r_icache_vci_paddr register. |
---|
1605 | { |
---|
1606 | uint32_t data; |
---|
1607 | size_t way; |
---|
1608 | size_t set; |
---|
1609 | size_t word; |
---|
1610 | bool hit = r_icache.read(r_icache_vci_paddr.read(), |
---|
1611 | &data, |
---|
1612 | &way, |
---|
1613 | &set, |
---|
1614 | &word); |
---|
1615 | if ( hit ) // inval to be done |
---|
1616 | { |
---|
1617 | r_icache_miss_way = way; |
---|
1618 | r_icache_miss_set = set; |
---|
1619 | r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; |
---|
1620 | } |
---|
1621 | else // miss : acknowlege the XTN request and return |
---|
1622 | { |
---|
1623 | r_dcache_xtn_req = false; |
---|
1624 | r_icache_fsm = ICACHE_IDLE; |
---|
1625 | } |
---|
1626 | break; |
---|
1627 | } |
---|
1628 | /////////////////////////////// |
---|
1629 | case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup. |
---|
1630 | // We are blocked if the previous cleanup is not completed |
---|
1631 | { |
---|
1632 | paddr_t nline; |
---|
1633 | |
---|
1634 | if ( not r_icache_cleanup_req.read() ) |
---|
1635 | { |
---|
1636 | r_icache.inval( r_icache_miss_way.read(), |
---|
1637 | r_icache_miss_set.read(), |
---|
1638 | &nline ); |
---|
1639 | |
---|
1640 | // request cleanup |
---|
1641 | r_icache_cleanup_req = true; |
---|
1642 | r_icache_cleanup_line = nline; |
---|
1643 | // acknowledge the XTN request and return |
---|
1644 | r_dcache_xtn_req = false; |
---|
1645 | r_icache_fsm = ICACHE_IDLE; |
---|
1646 | } |
---|
1647 | break; |
---|
1648 | } |
---|
1649 | |
---|
1650 | //////////////////////// |
---|
1651 | case ICACHE_MISS_VICTIM: // Selects a victim line |
---|
1652 | // Set the r_icache_cleanup_req flip-flop |
---|
1653 | // when the selected slot is not empty |
---|
1654 | { |
---|
1655 | if ( ireq.valid ) m_cost_ins_miss_frz++; |
---|
1656 | |
---|
1657 | bool valid; |
---|
1658 | size_t way; |
---|
1659 | size_t set; |
---|
1660 | paddr_t victim; |
---|
1661 | |
---|
1662 | valid = r_icache.victim_select(r_icache_vci_paddr.read(), |
---|
1663 | &victim, |
---|
1664 | &way, |
---|
1665 | &set); |
---|
1666 | r_icache_miss_way = way; |
---|
1667 | r_icache_miss_set = set; |
---|
1668 | |
---|
1669 | if ( valid ) |
---|
1670 | { |
---|
1671 | r_icache_cleanup_req = true; |
---|
1672 | r_icache_cleanup_line = victim; |
---|
1673 | r_icache_fsm = ICACHE_MISS_INVAL; |
---|
1674 | } |
---|
1675 | else |
---|
1676 | { |
---|
1677 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
1678 | } |
---|
1679 | break; |
---|
1680 | } |
---|
1681 | /////////////////////// |
---|
1682 | case ICACHE_MISS_INVAL: // invalidate the victim line |
---|
1683 | { |
---|
1684 | paddr_t nline; |
---|
1685 | |
---|
1686 | r_icache.inval( r_icache_miss_way.read(), |
---|
1687 | r_icache_miss_set.read(), |
---|
1688 | &nline ); // unused |
---|
1689 | |
---|
1690 | r_icache_fsm = ICACHE_MISS_WAIT; |
---|
1691 | break; |
---|
1692 | } |
---|
1693 | ////////////////////// |
---|
1694 | case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM |
---|
1695 | { |
---|
1696 | if ( ireq.valid ) m_cost_ins_miss_frz++; |
---|
1697 | |
---|
1698 | // external coherence request |
---|
1699 | if ( r_tgt_icache_req.read() ) |
---|
1700 | { |
---|
1701 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
1702 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
1703 | break; |
---|
1704 | } |
---|
1705 | |
---|
1706 | if ( r_vci_rsp_ins_error.read() ) // bus error |
---|
1707 | { |
---|
1708 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
1709 | r_mmu_ibvar = r_icache_vaddr_save.read(); |
---|
1710 | irsp.valid = true; |
---|
1711 | irsp.error = true; |
---|
1712 | r_vci_rsp_ins_error = false; |
---|
1713 | r_icache_fsm = ICACHE_IDLE; |
---|
1714 | } |
---|
1715 | else if ( r_vci_rsp_fifo_icache.rok() ) // response available |
---|
1716 | { |
---|
1717 | r_icache_miss_word = 0; |
---|
1718 | r_icache_fsm = ICACHE_MISS_UPDT; |
---|
1719 | } |
---|
1720 | break; |
---|
1721 | } |
---|
1722 | ////////////////////// |
---|
1723 | case ICACHE_MISS_UPDT: // update the cache (one word per cycle) |
---|
1724 | { |
---|
1725 | if ( ireq.valid ) m_cost_ins_miss_frz++; |
---|
1726 | |
---|
1727 | if ( r_vci_rsp_fifo_icache.rok() ) // response available |
---|
1728 | { |
---|
1729 | if ( r_icache_miss_inval ) // Matching coherence request |
---|
1730 | // We pop the response FIFO, without updating the cache |
---|
1731 | // We send a cleanup for the missing line at the last word |
---|
1732 | // Blocked if the previous cleanup is not completed |
---|
1733 | { |
---|
1734 | if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word |
---|
1735 | { |
---|
1736 | vci_rsp_fifo_icache_get = true; |
---|
1737 | r_icache_miss_word = r_icache_miss_word.read() + 1; |
---|
1738 | } |
---|
1739 | else // last word |
---|
1740 | { |
---|
1741 | if ( not r_icache_cleanup_req.read() ) // no pending cleanup |
---|
1742 | { |
---|
1743 | vci_rsp_fifo_icache_get = true; |
---|
1744 | r_icache_cleanup_req = true; |
---|
1745 | r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2)); |
---|
1746 | r_icache_miss_inval = false; |
---|
1747 | r_icache_fsm = ICACHE_IDLE; |
---|
1748 | } |
---|
1749 | } |
---|
1750 | } |
---|
1751 | else // No matching coherence request |
---|
1752 | // We pop the FIFO and update the cache |
---|
1753 | // We update the directory at the last word |
---|
1754 | { |
---|
1755 | |
---|
1756 | #ifdef INSTRUMENTATION |
---|
1757 | m_cpt_icache_data_write++; |
---|
1758 | #endif |
---|
1759 | r_icache.write( r_icache_miss_way.read(), |
---|
1760 | r_icache_miss_set.read(), |
---|
1761 | r_icache_miss_word.read(), |
---|
1762 | r_vci_rsp_fifo_icache.read() ); |
---|
1763 | vci_rsp_fifo_icache_get = true; |
---|
1764 | r_icache_miss_word = r_icache_miss_word.read() + 1; |
---|
1765 | if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word |
---|
1766 | { |
---|
1767 | |
---|
1768 | #ifdef INSTRUMENTATION |
---|
1769 | m_cpt_icache_dir_write++; |
---|
1770 | #endif |
---|
1771 | r_icache.victim_update_tag( r_icache_vci_paddr.read(), |
---|
1772 | r_icache_miss_way.read(), |
---|
1773 | r_icache_miss_set.read() ); |
---|
1774 | r_icache_fsm = ICACHE_IDLE; |
---|
1775 | } |
---|
1776 | } |
---|
1777 | } |
---|
1778 | break; |
---|
1779 | } |
---|
1780 | //////////////////// |
---|
1781 | case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM |
---|
1782 | // |
---|
1783 | { |
---|
1784 | // external coherence request |
---|
1785 | if ( r_tgt_icache_req.read() ) |
---|
1786 | { |
---|
1787 | r_icache_fsm = ICACHE_CC_CHECK; |
---|
1788 | r_icache_fsm_save = r_icache_fsm.read(); |
---|
1789 | break; |
---|
1790 | } |
---|
1791 | |
---|
1792 | if ( r_vci_rsp_ins_error.read() ) // bus error |
---|
1793 | { |
---|
1794 | r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
1795 | r_mmu_ibvar = ireq.addr; |
---|
1796 | r_vci_rsp_ins_error = false; |
---|
1797 | irsp.valid = true; |
---|
1798 | irsp.error = true; |
---|
1799 | r_icache_fsm = ICACHE_IDLE; |
---|
1800 | } |
---|
1801 | else if (r_vci_rsp_fifo_icache.rok() ) // instruction available |
---|
1802 | { |
---|
1803 | vci_rsp_fifo_icache_get = true; |
---|
1804 | r_icache_fsm = ICACHE_IDLE; |
---|
1805 | if ( ireq.valid and (ireq.addr == r_icache_vaddr_save.read()) ) // request not modified |
---|
1806 | { |
---|
1807 | irsp.valid = true; |
---|
1808 | irsp.instruction = r_vci_rsp_fifo_icache.read(); |
---|
1809 | } |
---|
1810 | } |
---|
1811 | break; |
---|
1812 | } |
---|
1813 | ///////////////////// |
---|
1814 | case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm |
---|
1815 | // handling coherence requests. |
---|
1816 | // the return state is defined in r_icache_fsm_save. |
---|
1817 | { |
---|
1818 | paddr_t paddr = r_tgt_paddr.read(); |
---|
1819 | paddr_t mask = ~((m_icache_words<<2)-1); |
---|
1820 | |
---|
1821 | if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and |
---|
1822 | ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss |
---|
1823 | { |
---|
1824 | r_icache_miss_inval = true; // signaling the matching |
---|
1825 | r_tgt_icache_req = false; // coherence request completed |
---|
1826 | r_tgt_icache_rsp = r_tgt_update.read(); // response required if update |
---|
1827 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
1828 | } |
---|
1829 | else // no match |
---|
1830 | { |
---|
1831 | |
---|
1832 | #ifdef INSTRUMENTATION |
---|
1833 | m_cpt_icache_dir_read++; |
---|
1834 | #endif |
---|
1835 | uint32_t inst; |
---|
1836 | size_t way; |
---|
1837 | size_t set; |
---|
1838 | size_t word; |
---|
1839 | bool hit = r_icache.read(paddr, |
---|
1840 | &inst, |
---|
1841 | &way, |
---|
1842 | &set, |
---|
1843 | &word); |
---|
1844 | r_icache_cc_way = way; |
---|
1845 | r_icache_cc_set = set; |
---|
1846 | |
---|
1847 | if ( hit and r_tgt_update.read() ) // hit update |
---|
1848 | { |
---|
1849 | r_icache_fsm = ICACHE_CC_UPDT; |
---|
1850 | r_icache_cc_word = r_tgt_word_min.read(); |
---|
1851 | } |
---|
1852 | else if ( hit and not r_tgt_update.read() ) // hit inval |
---|
1853 | { |
---|
1854 | r_icache_fsm = ICACHE_CC_INVAL; |
---|
1855 | } |
---|
1856 | else // miss can happen |
---|
1857 | { |
---|
1858 | r_tgt_icache_req = false; |
---|
1859 | r_tgt_icache_rsp = r_tgt_update.read(); |
---|
1860 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
1861 | } |
---|
1862 | } |
---|
1863 | break; |
---|
1864 | } |
---|
1865 | |
---|
1866 | ///////////////////// |
---|
1867 | case ICACHE_CC_INVAL: // invalidate a cache line |
---|
1868 | { |
---|
1869 | paddr_t nline; |
---|
1870 | r_icache.inval( r_icache_cc_way.read(), |
---|
1871 | r_icache_cc_set.read(), |
---|
1872 | &nline ); |
---|
1873 | |
---|
1874 | r_tgt_icache_req = false; |
---|
1875 | r_tgt_icache_rsp = true; |
---|
1876 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
1877 | break; |
---|
1878 | } |
---|
1879 | //////////////////// |
---|
1880 | case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max) |
---|
1881 | { |
---|
1882 | size_t word = r_icache_cc_word.read(); |
---|
1883 | size_t way = r_icache_cc_way.read(); |
---|
1884 | size_t set = r_icache_cc_set.read(); |
---|
1885 | |
---|
1886 | r_icache.write( way, |
---|
1887 | set, |
---|
1888 | word, |
---|
1889 | r_tgt_buf[word], |
---|
1890 | r_tgt_be[word] ); |
---|
1891 | |
---|
1892 | r_icache_cc_word = word+1; |
---|
1893 | |
---|
1894 | if ( word == r_tgt_word_max.read() ) // last word |
---|
1895 | { |
---|
1896 | r_tgt_icache_req = false; |
---|
1897 | r_tgt_icache_rsp = true; |
---|
1898 | r_icache_fsm = r_icache_fsm_save.read(); |
---|
1899 | } |
---|
1900 | break; |
---|
1901 | } |
---|
1902 | |
---|
1903 | } // end switch r_icache_fsm |
---|
1904 | |
---|
1905 | // save the IREQ and IRSP fields for the print_trace() function |
---|
1906 | m_ireq_valid = ireq.valid; |
---|
1907 | m_ireq_addr = ireq.addr; |
---|
1908 | m_ireq_mode = ireq.mode; |
---|
1909 | |
---|
1910 | m_irsp_valid = irsp.valid; |
---|
1911 | m_irsp_instruction = irsp.instruction; |
---|
1912 | m_irsp_error = irsp.error; |
---|
1913 | |
---|
1914 | //////////////////////////////////////////////////////////////////////////////////// |
---|
1915 | // INVAL ITLB FSM |
---|
1916 | // This FSM works in parallel with the ICACHE FSM. |
---|
1917 | // When the r_dcache_itlb_inval_req flip-flop is activated by the DCACHE FSM |
---|
1918 | // it scans sequencially all entries in the ITLB, and invalidates the |
---|
1919 | // entries matching the evicted line. |
---|
1920 | // It signals the completion of invalidation by reseting r_dcache_itlb_inval_req. |
---|
1921 | //////////////////////////////////////////////////////////////////////////////////// |
---|
1922 | |
---|
1923 | switch(r_inval_itlb_fsm) |
---|
1924 | { |
---|
1925 | ///////////////////// |
---|
1926 | case INVAL_ITLB_IDLE: |
---|
1927 | { |
---|
1928 | if ( r_dcache_itlb_inval_req.read() ) |
---|
1929 | { |
---|
1930 | r_itlb.reset_bypass(r_dcache_tlb_inval_line.read()); |
---|
1931 | r_inval_itlb_count = 0; |
---|
1932 | r_inval_itlb_fsm = INVAL_ITLB_SCAN; |
---|
1933 | |
---|
1934 | #if DEBUG_INVAL_ITLB |
---|
1935 | if ( m_debug_inval_itlb_fsm ) |
---|
1936 | { |
---|
1937 | std::cout << " <PROC.INVAL_ITLB_IDLE> Invalidate request for line " |
---|
1938 | << std::hex << r_dcache_tlb_inval_line.read() << std::endl; |
---|
1939 | r_itlb.print(); |
---|
1940 | } |
---|
1941 | #endif |
---|
1942 | } |
---|
1943 | break; |
---|
1944 | } |
---|
1945 | ///////////////////// |
---|
1946 | case INVAL_ITLB_SCAN: |
---|
1947 | { |
---|
1948 | paddr_t line = r_dcache_tlb_inval_line.read(); // nline |
---|
1949 | size_t way = r_inval_itlb_count.read()/m_itlb_sets; // way |
---|
1950 | size_t set = r_inval_itlb_count.read()%m_itlb_sets; // set |
---|
1951 | |
---|
1952 | bool ok = r_itlb.inval( line, |
---|
1953 | way, |
---|
1954 | set ); |
---|
1955 | |
---|
1956 | #if DEBUG_INVAL_ITLB |
---|
1957 | if ( m_debug_inval_itlb_fsm ) |
---|
1958 | { |
---|
1959 | std::cout << " <PROC.INVAL_ITLB_SCAN>" << std::hex |
---|
1960 | << " line = " << line << std::dec |
---|
1961 | << " / set = " << set |
---|
1962 | << " / way = " << way; |
---|
1963 | if ( ok ) std::cout << " / HIT" << std::endl; |
---|
1964 | else std::cout << " / MISS" << std::endl; |
---|
1965 | } |
---|
1966 | #endif |
---|
1967 | |
---|
1968 | r_inval_itlb_count = r_inval_itlb_count.read() + 1; |
---|
1969 | if ( r_inval_itlb_count.read() == (m_itlb_sets*m_itlb_ways - 1) ) |
---|
1970 | { |
---|
1971 | r_inval_itlb_fsm = INVAL_ITLB_IDLE; |
---|
1972 | r_dcache_itlb_inval_req = false; |
---|
1973 | } |
---|
1974 | break; |
---|
1975 | } |
---|
1976 | } // end switch r_inval_itlb_fsm |
---|
1977 | |
---|
1978 | //////////////////////////////////////////////////////////////////////////////////// |
---|
1979 | // DCACHE FSM |
---|
1980 | // |
---|
1981 | // Both the Cacheability Table, and the MMU cacheable bit are used to define |
---|
1982 | // the cacheability, depending on the MMU mode. |
---|
1983 | // |
---|
1984 | // 1/ Coherence requests : |
---|
1985 | // There is a coherence request when the tgt_dcache_req flip-flop is set, |
---|
1986 | // requesting a line invalidation or a line update. |
---|
1987 | // Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states. |
---|
1988 | // The actions associated to the pre-empted state are not executed, the DCACHE FSM |
---|
1989 | // goes to the CC_CHECK state to execute the requested action, and returns to the |
---|
1990 | // pre-empted state. |
---|
1991 | // |
---|
1992 | // 2/ processor requests : |
---|
1993 | // Processor READ, WRITE, LL or SC requests are taken in IDLE state only. |
---|
1994 | // The IDLE state implements a three stages pipe-line to handle write bursts: |
---|
1995 | // - The physical address is computed by dtlb in stage P0. |
---|
1996 | // - The registration in wbuf and the dcache hit are computed in stage P1. |
---|
1997 | // - The dcache update is done in stage P2. |
---|
1998 | // A write operation can require a fourth stage if the dirty bit must be updated, |
---|
1999 | // or if the TLBs must be cleared, but these "long write" operation requires |
---|
2000 | // to exit the IDLE stage |
---|
2001 | // If there is no write in the pipe, dcache and dtlb are accessed in parallel, |
---|
2002 | // (virtual address for itlb, and speculative physical address computed during |
---|
2003 | // previous cycle for dcache) in order to return the data in one cycle for a read. |
---|
2004 | // We just pay an extra cycle when the speculative access is illegal. |
---|
2005 | // |
---|
2006 | // 3/ Atomic instructions LL/SC |
---|
2007 | // The LL/SC address can be cacheable or non cacheable. |
---|
2008 | // The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and |
---|
2009 | // r_dcache_ll_data are stored in the L1 cache controller, and not in the |
---|
2010 | // memory controller. |
---|
2011 | // - LL requests from the processor are transmitted as standard VCI |
---|
2012 | // READ transactions (one word / one line, depending on the cacheability). |
---|
2013 | // - SC requests from the processor are systematically transmitted to the |
---|
2014 | // memory cache as COMPARE&swap requests (both the data value stored in the |
---|
2015 | // r_dcache_ll_data register and the new value). |
---|
2016 | // |
---|
2017 | // 4/ Non cacheable access: |
---|
2018 | // This component implement a strong order between non cacheable access |
---|
2019 | // (read or write) : A new non cacheable VCI transaction starts only when |
---|
2020 | // the previous non cacheable transaction is completed. Both cacheable and |
---|
2021 | // non cacheable transactions use the write buffer, but the DCACHE FSM registers |
---|
2022 | // a non cacheable write transaction posted in the write buffer by setting the |
---|
2023 | // r_dcache_pending_unc_write flip_flop. All other non cacheable requests |
---|
2024 | // are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the |
---|
2025 | // pending non cacheable write transaction completes). |
---|
2026 | // |
---|
2027 | // 5/ Error handling: |
---|
2028 | // When the MMU is not activated, Read Bus Errors are synchronous events, |
---|
2029 | // but Write Bus Errors are asynchronous events (processor is not frozen). |
---|
2030 | // - If a Read Bus Error is detected, the VCI_RSP FSM sets the |
---|
2031 | // r_vci_rsp_data_error flip-flop, without writing any data in the |
---|
2032 | // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled |
---|
2033 | // by the DCACHE FSM. |
---|
2034 | // - If a Write Bus Error is detected, the VCI_RSP FSM signals |
---|
2035 | // the asynchronous error using the setWriteBerr() method. |
---|
2036 | // When the MMU is activated bus error are rare events, as the MMU |
---|
2037 | // checks the physical address before the VCI transaction starts. |
---|
2038 | //////////////////////////////////////////////////////////////////////////////////////// |
---|
2039 | |
---|
2040 | // The default value for drsp.valid is false |
---|
2041 | typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER; |
---|
2042 | |
---|
2043 | switch ( r_dcache_fsm.read() ) |
---|
2044 | { |
---|
2045 | case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state : |
---|
2046 | // 1) Long write request (DCACHE FSM) => DCACHE_WRITE_*** |
---|
2047 | // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK |
---|
2048 | // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS |
---|
2049 | // 4) XTN request (processor) => DCACHE_XTN_* |
---|
2050 | // 5) DTLB miss (processor) => DCACHE_TLB_MISS |
---|
2051 | // 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM |
---|
2052 | // 7) Uncacheable read (processor) => DCACHE_UNC_REQ |
---|
2053 | // 8) SC access (processor) => DCACHE_SC |
---|
2054 | // There is 4 configurations to access the cache, |
---|
2055 | // depending on the pipe-line state, defined |
---|
2056 | // by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated |
---|
2057 | // and r_dcache_p1_valid (V1) flip-flop : P2 stage activated |
---|
2058 | // V0 / V1 / Data / Directory / comment |
---|
2059 | // 0 / 0 / read(A0) / read(A0) / read speculative access |
---|
2060 | // 0 / 1 / write(A2) / nop / read request delayed |
---|
2061 | // 1 / 0 / nop / read(A1) / read request delayed |
---|
2062 | // 1 / 1 / write(A2) / read(A1) / read request delayed |
---|
2063 | { |
---|
2064 | //////////////////////////////////////////////////////////////////////////////// |
---|
2065 | // Handling P2 pipe-line stage |
---|
2066 | // Inputs are r_dcache_p1_* registers. |
---|
2067 | // Three actions are executed in this P2 stage: |
---|
2068 | // - If r_dcache_p1_updt_cache is true, we update the local copy in dcache. |
---|
2069 | // - If the modified cache line has copies in itlb (resp. dtlb), and if the |
---|
2070 | // INVAL_ITLB (resp. INVAL_DTLB) FSM is idle, we launch the TLB invalidate |
---|
2071 | // operation. This operation is NOT blocking for the processor: the DCACHE FSM |
---|
2072 | // doesn't wait the TLB invalidate completion to handle processor requests. |
---|
2073 | // If the INVAL_ITLB (resp INVAL_DTLB) FSM is already processintg a previous |
---|
2074 | // invalidation request, the DCACHE FSM is frosen until completion of the |
---|
2075 | // previous TLB invalidate operation. |
---|
2076 | // - If the PTE dirty bit must be updated, we start a "long write", that is |
---|
2077 | // blocking for the processor, because we switch to the DCACHE_WRITE_SET_DIRTY |
---|
2078 | // state, and the number of cycles can be large... |
---|
2079 | |
---|
2080 | bool long_write_set_dirty = false; |
---|
2081 | bool tlb_inval_frozen = false; |
---|
2082 | |
---|
2083 | if ( r_dcache_p1_valid.read() ) // P2 stage activated |
---|
2084 | { |
---|
2085 | bool cache_updt = r_dcache_p1_updt_cache.read(); |
---|
2086 | size_t cache_way = r_dcache_p1_cache_way.read(); |
---|
2087 | size_t cache_set = r_dcache_p1_cache_set.read(); |
---|
2088 | size_t cache_word = r_dcache_p1_cache_word.read(); |
---|
2089 | uint32_t wdata = r_dcache_p1_wdata.read(); |
---|
2090 | vci_be_t be = r_dcache_p1_be.read(); |
---|
2091 | |
---|
2092 | // The PTE address is used when the PTE dirty bit must be set. |
---|
2093 | // It is the concatenation of the nline value (from dtlb) |
---|
2094 | // and the word index (from virtual address) |
---|
2095 | paddr_t pte_paddr = (paddr_t)(r_dcache_p1_tlb_nline.read()*(m_dcache_words<<2)) |
---|
2096 | | (paddr_t)(r_dcache_p1_vaddr.read()%(m_dcache_words<<2)); |
---|
2097 | |
---|
2098 | // The line index is used when a TLB inval is required |
---|
2099 | paddr_t inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2)); |
---|
2100 | |
---|
2101 | // checking dcache update |
---|
2102 | if ( cache_updt ) |
---|
2103 | { |
---|
2104 | r_dcache.write( cache_way, |
---|
2105 | cache_set, |
---|
2106 | cache_word, |
---|
2107 | wdata, |
---|
2108 | be ); |
---|
2109 | #ifdef INSTRUMENTATION |
---|
2110 | m_cpt_dcache_data_write++; |
---|
2111 | #endif |
---|
2112 | |
---|
2113 | // Checking copies in TLBs |
---|
2114 | bool itlb_inval = ( (r_mmu_mode.read() & INS_TLB_MASK) and |
---|
2115 | r_dcache_in_itlb[cache_way*m_dcache_sets+cache_set] ); |
---|
2116 | bool dtlb_inval = ( (r_mmu_mode.read() & DATA_TLB_MASK) and |
---|
2117 | r_dcache_in_dtlb[cache_way*m_dcache_sets+cache_set] ); |
---|
2118 | |
---|
2119 | if ( (dtlb_inval and r_dcache_dtlb_inval_req.read() ) or |
---|
2120 | (itlb_inval and r_dcache_itlb_inval_req.read() ) ) // at least one FSM not idle |
---|
2121 | { |
---|
2122 | tlb_inval_frozen = true; |
---|
2123 | } |
---|
2124 | else // requested FSM idle |
---|
2125 | { |
---|
2126 | r_dcache_tlb_inval_line = inval_line; |
---|
2127 | r_dcache_itlb_inval_req = itlb_inval; |
---|
2128 | r_dcache_dtlb_inval_req = dtlb_inval; |
---|
2129 | r_dcache_in_itlb[cache_way*m_dcache_sets+cache_set] = false; |
---|
2130 | r_dcache_in_dtlb[cache_way*m_dcache_sets+cache_set] = false; |
---|
2131 | } |
---|
2132 | } // end dcache update |
---|
2133 | |
---|
2134 | // checking dirty bit update |
---|
2135 | if ( r_dcache_p1_set_dirty.read() ) |
---|
2136 | { |
---|
2137 | long_write_set_dirty = true; |
---|
2138 | r_dcache_p2_vaddr = r_dcache_p1_vaddr.read(); |
---|
2139 | r_dcache_p2_set_dirty = r_dcache_p1_set_dirty.read(); |
---|
2140 | r_dcache_p2_tlb_way = r_dcache_p1_tlb_way.read(); |
---|
2141 | r_dcache_p2_tlb_set = r_dcache_p1_tlb_set.read(); |
---|
2142 | r_dcache_p2_pte_paddr = pte_paddr; |
---|
2143 | } |
---|
2144 | |
---|
2145 | #if DEBUG_DCACHE |
---|
2146 | if ( m_debug_dcache_fsm ) |
---|
2147 | { |
---|
2148 | if ( cache_updt ) |
---|
2149 | std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec |
---|
2150 | << " / way = " << cache_way |
---|
2151 | << " / set = " << cache_set |
---|
2152 | << " / word = " << cache_word << std::hex |
---|
2153 | << " / wdata = " << wdata |
---|
2154 | << " / be = " << be << std::endl; |
---|
2155 | if ( long_write_set_dirty ) |
---|
2156 | std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required" |
---|
2157 | << " / pte_paddr = " << std::hex << pte_paddr << std::endl; |
---|
2158 | } |
---|
2159 | #endif |
---|
2160 | } // end P2 stage |
---|
2161 | |
---|
2162 | /////////////////////////////////////////////////////////////////////////// |
---|
2163 | // Handling P1 pipe-line stage |
---|
2164 | // Inputs are r_dcache_p0_* registers. |
---|
2165 | // - We must write into wbuf and test the hit in dcache. |
---|
2166 | // If the write request is not cacheable, and there is a pending |
---|
2167 | // non cacheable write, or if the write buffer is full, we break: |
---|
2168 | // The P0 and P1 pipe-line stages are frozen until the write |
---|
2169 | // request registration is possible, but the P2 stage is not frozen. |
---|
2170 | // - The r_dcache_p1_valid bit activating the P2 pipe-line stage |
---|
2171 | // must be computed at all cycles. The P2 stage must be activated |
---|
2172 | // if there is local copy in dcache, or if the PTE dirty bit must be set. |
---|
2173 | |
---|
2174 | if ( r_dcache_p0_valid.read() and not tlb_inval_frozen ) // P1 stage activated |
---|
2175 | { |
---|
2176 | // write not cacheable, and previous non cacheable write registered |
---|
2177 | if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() ) |
---|
2178 | { |
---|
2179 | r_dcache_p1_valid = false; |
---|
2180 | break; |
---|
2181 | } |
---|
2182 | |
---|
2183 | // try a registration into write buffer |
---|
2184 | bool wok = r_wbuf.write( r_dcache_p0_paddr.read(), |
---|
2185 | r_dcache_p0_be.read(), |
---|
2186 | r_dcache_p0_wdata.read(), |
---|
2187 | r_dcache_p0_cacheable.read() ); |
---|
2188 | #ifdef INSTRUMENTATION |
---|
2189 | m_cpt_wbuf_write++; |
---|
2190 | #endif |
---|
2191 | // write buffer full |
---|
2192 | if ( not wok ) |
---|
2193 | { |
---|
2194 | r_dcache_p1_valid = false; |
---|
2195 | break; |
---|
2196 | } |
---|
2197 | // update the write_buffer state extension |
---|
2198 | r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read(); |
---|
2199 | |
---|
2200 | // read directory to detect local copy |
---|
2201 | size_t cache_way; |
---|
2202 | size_t cache_set; |
---|
2203 | size_t cache_word; |
---|
2204 | bool local_copy; |
---|
2205 | if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated |
---|
2206 | { |
---|
2207 | local_copy = r_dcache.hit( r_dcache_p0_paddr.read(), |
---|
2208 | &cache_way, |
---|
2209 | &cache_set, |
---|
2210 | &cache_word ); |
---|
2211 | #ifdef INSTRUMENTATION |
---|
2212 | m_cpt_dcache_dir_read++; |
---|
2213 | #endif |
---|
2214 | } |
---|
2215 | else |
---|
2216 | { |
---|
2217 | local_copy = false; |
---|
2218 | } |
---|
2219 | |
---|
2220 | // dirty bit update requested |
---|
2221 | bool dirty_req = (r_mmu_mode.read() & DATA_TLB_MASK) and not r_dcache_p0_tlb_dirty.read(); |
---|
2222 | |
---|
2223 | // if there is a local copy or a dirty bit update requested |
---|
2224 | if ( local_copy or dirty_req ) |
---|
2225 | { |
---|
2226 | r_dcache_p1_valid = true; |
---|
2227 | r_dcache_p1_set_dirty = dirty_req; |
---|
2228 | r_dcache_p1_updt_cache = local_copy; |
---|
2229 | r_dcache_p1_vaddr = r_dcache_p0_vaddr.read(); |
---|
2230 | r_dcache_p1_wdata = r_dcache_p0_wdata.read(); |
---|
2231 | r_dcache_p1_be = r_dcache_p0_be.read(); |
---|
2232 | r_dcache_p1_paddr = r_dcache_p0_paddr.read(); |
---|
2233 | r_dcache_p1_tlb_way = r_dcache_p0_tlb_way; |
---|
2234 | r_dcache_p1_tlb_set = r_dcache_p0_tlb_set; |
---|
2235 | r_dcache_p1_tlb_nline = r_dcache_p0_tlb_nline; |
---|
2236 | r_dcache_p1_cache_way = cache_way; |
---|
2237 | r_dcache_p1_cache_set = cache_set; |
---|
2238 | r_dcache_p1_cache_word = cache_word; |
---|
2239 | } |
---|
2240 | else |
---|
2241 | { |
---|
2242 | r_dcache_p1_valid = false; |
---|
2243 | } |
---|
2244 | } |
---|
2245 | else // P1 stage not activated |
---|
2246 | { |
---|
2247 | r_dcache_p1_valid = false; |
---|
2248 | } // end P1 stage |
---|
2249 | |
---|
2250 | ///////////////////////////////////////////////////////////////////////////// |
---|
2251 | // handling P0 write pipe-line stage |
---|
2252 | // This stage is controlling the DCACHE FSM state register: |
---|
2253 | // - the FSM is frozen if a TLB invalidate operation must be delayed, |
---|
2254 | // - the long write requests have the highest priority, |
---|
2255 | // - then the external coherence requests, |
---|
2256 | // - then the itlb miss requests, |
---|
2257 | // - and finally the processor requests. |
---|
2258 | // A processor read request generate a dcache access using speculative PPN |
---|
2259 | // only if the write pipe-line is empty. There is an unconditionnal access |
---|
2260 | // to the dtlb, using virtual address from processor. |
---|
2261 | // The r_dcache_p0_valid value must be computed at all cycles. |
---|
2262 | |
---|
2263 | bool p0_valid = false; // default value |
---|
2264 | |
---|
2265 | // TLB inval delayed |
---|
2266 | if ( tlb_inval_frozen ) |
---|
2267 | { |
---|
2268 | break; |
---|
2269 | } |
---|
2270 | |
---|
2271 | // long write request |
---|
2272 | else if ( long_write_set_dirty ) |
---|
2273 | { |
---|
2274 | r_dcache_fsm = DCACHE_WRITE_TLB_DIRTY; |
---|
2275 | } |
---|
2276 | |
---|
2277 | // external coherence request |
---|
2278 | else if ( r_tgt_dcache_req.read() ) |
---|
2279 | { |
---|
2280 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
2281 | r_dcache_fsm_save = DCACHE_IDLE; |
---|
2282 | } |
---|
2283 | |
---|
2284 | // itlb miss request |
---|
2285 | else if ( r_icache_tlb_miss_req.read() ) |
---|
2286 | { |
---|
2287 | r_dcache_tlb_ins = true; |
---|
2288 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
2289 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
2290 | } |
---|
2291 | |
---|
2292 | // processor request |
---|
2293 | else if (dreq.valid ) |
---|
2294 | { |
---|
2295 | // dcache access using speculative PPN only if pipe-line empty |
---|
2296 | paddr_t cache_paddr; |
---|
2297 | size_t cache_way; |
---|
2298 | size_t cache_set; |
---|
2299 | size_t cache_word; |
---|
2300 | uint32_t cache_rdata; |
---|
2301 | bool cache_hit; |
---|
2302 | |
---|
2303 | if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated |
---|
2304 | not r_dcache_p0_valid.read() and |
---|
2305 | not r_dcache_p1_valid.read() ) // pipe-line empty |
---|
2306 | { |
---|
2307 | cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) | |
---|
2308 | ((paddr_t)dreq.addr & PAGE_K_MASK); |
---|
2309 | |
---|
2310 | cache_hit = r_dcache.read( cache_paddr, |
---|
2311 | &cache_rdata, |
---|
2312 | &cache_way, |
---|
2313 | &cache_set, |
---|
2314 | &cache_word ); |
---|
2315 | #ifdef INSTRUMENTATION |
---|
2316 | m_cpt_dcache_dir_read++; |
---|
2317 | m_cpt_dcache_data_read++; |
---|
2318 | #endif |
---|
2319 | } |
---|
2320 | else |
---|
2321 | { |
---|
2322 | cache_hit = false; |
---|
2323 | } // end dcache access |
---|
2324 | |
---|
2325 | // systematic dtlb access using virtual address |
---|
2326 | |
---|
2327 | paddr_t tlb_paddr; |
---|
2328 | pte_info_t tlb_flags; |
---|
2329 | size_t tlb_way; |
---|
2330 | size_t tlb_set; |
---|
2331 | paddr_t tlb_nline; |
---|
2332 | bool tlb_hit; |
---|
2333 | |
---|
2334 | if ( r_mmu_mode.read() & DATA_TLB_MASK ) // TLB activated |
---|
2335 | { |
---|
2336 | tlb_hit = r_dtlb.translate( dreq.addr, |
---|
2337 | &tlb_paddr, |
---|
2338 | &tlb_flags, |
---|
2339 | &tlb_nline, |
---|
2340 | &tlb_way, |
---|
2341 | &tlb_set ); |
---|
2342 | #ifdef INSTRUMENTATION |
---|
2343 | m_cpt_dtlb_read++; |
---|
2344 | #endif |
---|
2345 | // register dtlb outputs |
---|
2346 | r_dcache_p0_tlb_nline = tlb_nline; |
---|
2347 | r_dcache_p0_tlb_way = tlb_way; |
---|
2348 | r_dcache_p0_tlb_set = tlb_set; |
---|
2349 | r_dcache_p0_tlb_dirty = tlb_flags.d; |
---|
2350 | r_dcache_p0_tlb_big = tlb_flags.b; |
---|
2351 | } |
---|
2352 | else |
---|
2353 | { |
---|
2354 | tlb_hit = false; |
---|
2355 | } // end dtlb access |
---|
2356 | |
---|
2357 | // register the processor request |
---|
2358 | r_dcache_p0_vaddr = dreq.addr; |
---|
2359 | r_dcache_p0_be = dreq.be; |
---|
2360 | r_dcache_p0_wdata = dreq.wdata; |
---|
2361 | |
---|
2362 | // Handling READ XTN requests from processor |
---|
2363 | // They are executed in this DCACHE_IDLE state. |
---|
2364 | // The processor must not be in user mode |
---|
2365 | if (dreq.type == iss_t::XTN_READ) |
---|
2366 | { |
---|
2367 | int xtn_opcode = (int)dreq.addr/4; |
---|
2368 | |
---|
2369 | // checking processor mode: |
---|
2370 | if (dreq.mode == iss_t::MODE_USER) |
---|
2371 | { |
---|
2372 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
2373 | r_mmu_dbvar = dreq.addr; |
---|
2374 | drsp.valid = true; |
---|
2375 | drsp.error = true; |
---|
2376 | r_dcache_fsm = DCACHE_IDLE; |
---|
2377 | } |
---|
2378 | else |
---|
2379 | { |
---|
2380 | switch( xtn_opcode ) |
---|
2381 | { |
---|
2382 | case iss_t::XTN_INS_ERROR_TYPE: |
---|
2383 | drsp.rdata = r_mmu_ietr.read(); |
---|
2384 | drsp.valid = true; |
---|
2385 | break; |
---|
2386 | |
---|
2387 | case iss_t::XTN_DATA_ERROR_TYPE: |
---|
2388 | drsp.rdata = r_mmu_detr.read(); |
---|
2389 | drsp.valid = true; |
---|
2390 | break; |
---|
2391 | |
---|
2392 | case iss_t::XTN_INS_BAD_VADDR: |
---|
2393 | drsp.rdata = r_mmu_ibvar.read(); |
---|
2394 | drsp.valid = true; |
---|
2395 | break; |
---|
2396 | |
---|
2397 | case iss_t::XTN_DATA_BAD_VADDR: |
---|
2398 | drsp.rdata = r_mmu_dbvar.read(); |
---|
2399 | drsp.valid = true; |
---|
2400 | break; |
---|
2401 | |
---|
2402 | case iss_t::XTN_PTPR: |
---|
2403 | drsp.rdata = r_mmu_ptpr.read(); |
---|
2404 | drsp.valid = true; |
---|
2405 | break; |
---|
2406 | |
---|
2407 | case iss_t::XTN_TLB_MODE: |
---|
2408 | drsp.rdata = r_mmu_mode.read(); |
---|
2409 | drsp.valid = true; |
---|
2410 | break; |
---|
2411 | |
---|
2412 | case iss_t::XTN_MMU_PARAMS: |
---|
2413 | drsp.rdata = r_mmu_params; |
---|
2414 | drsp.valid = true; |
---|
2415 | break; |
---|
2416 | |
---|
2417 | case iss_t::XTN_MMU_RELEASE: |
---|
2418 | drsp.rdata = r_mmu_release; |
---|
2419 | drsp.valid = true; |
---|
2420 | break; |
---|
2421 | |
---|
2422 | case iss_t::XTN_MMU_WORD_LO: |
---|
2423 | drsp.rdata = r_mmu_word_lo.read(); |
---|
2424 | drsp.valid = true; |
---|
2425 | break; |
---|
2426 | |
---|
2427 | case iss_t::XTN_MMU_WORD_HI: |
---|
2428 | drsp.rdata = r_mmu_word_hi.read(); |
---|
2429 | drsp.valid = true; |
---|
2430 | break; |
---|
2431 | |
---|
2432 | default: |
---|
2433 | r_mmu_detr = MMU_READ_UNDEFINED_XTN; |
---|
2434 | r_mmu_dbvar = dreq.addr; |
---|
2435 | drsp.valid = true; |
---|
2436 | drsp.error = true; |
---|
2437 | break; |
---|
2438 | } // end switch xtn_opcode |
---|
2439 | } // end else |
---|
2440 | } // end if XTN_READ |
---|
2441 | |
---|
2442 | // Handling WRITE XTN requests from processor. |
---|
2443 | // They are not executed in this DCACHE_IDLE state, |
---|
2444 | // if they require access to the caches or the TLBs |
---|
2445 | // that are already accessed for speculative read. |
---|
2446 | // Caches can be invalidated or flushed in user mode, |
---|
2447 | // and the sync instruction can be executed in user mode |
---|
2448 | else if (dreq.type == iss_t::XTN_WRITE) |
---|
2449 | { |
---|
2450 | int xtn_opcode = (int)dreq.addr/4; |
---|
2451 | r_dcache_xtn_opcode = xtn_opcode; |
---|
2452 | |
---|
2453 | // checking processor mode: |
---|
2454 | if ( (dreq.mode == iss_t::MODE_USER) && |
---|
2455 | (xtn_opcode != iss_t:: XTN_SYNC) && |
---|
2456 | (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && |
---|
2457 | (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && |
---|
2458 | (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && |
---|
2459 | (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) ) |
---|
2460 | { |
---|
2461 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
2462 | r_mmu_dbvar = dreq.addr; |
---|
2463 | drsp.valid = true; |
---|
2464 | drsp.error = true; |
---|
2465 | r_dcache_fsm = DCACHE_IDLE; |
---|
2466 | } |
---|
2467 | else |
---|
2468 | { |
---|
2469 | switch( xtn_opcode ) |
---|
2470 | { |
---|
2471 | case iss_t::XTN_PTPR: // itlb & dtlb must be flushed |
---|
2472 | r_mmu_ptpr = dreq.wdata; |
---|
2473 | r_dcache_xtn_req = true; |
---|
2474 | r_dcache_fsm = DCACHE_XTN_SWITCH; |
---|
2475 | break; |
---|
2476 | |
---|
2477 | case iss_t::XTN_TLB_MODE: // no cache or tlb access |
---|
2478 | r_mmu_mode = dreq.wdata; |
---|
2479 | drsp.valid = true; |
---|
2480 | r_dcache_fsm = DCACHE_IDLE; |
---|
2481 | break; |
---|
2482 | |
---|
2483 | case iss_t::XTN_DTLB_INVAL: // dtlb access |
---|
2484 | r_dcache_fsm = DCACHE_XTN_DT_INVAL; |
---|
2485 | break; |
---|
2486 | |
---|
2487 | case iss_t::XTN_ITLB_INVAL: // itlb access |
---|
2488 | r_dcache_xtn_req = true; |
---|
2489 | r_dcache_fsm = DCACHE_XTN_IT_INVAL; |
---|
2490 | break; |
---|
2491 | |
---|
2492 | case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access |
---|
2493 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; |
---|
2494 | break; |
---|
2495 | |
---|
2496 | case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access |
---|
2497 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
2498 | r_dcache_p0_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | |
---|
2499 | (paddr_t)r_mmu_word_lo.read(); |
---|
2500 | break; |
---|
2501 | |
---|
2502 | case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset |
---|
2503 | r_dcache_flush_count = 0; |
---|
2504 | r_dcache_fsm = DCACHE_XTN_DC_FLUSH; |
---|
2505 | break; |
---|
2506 | |
---|
2507 | case iss_t::XTN_ICACHE_INVAL: // icache and itlb access |
---|
2508 | r_dcache_xtn_req = true; |
---|
2509 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; |
---|
2510 | break; |
---|
2511 | |
---|
2512 | case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access |
---|
2513 | r_dcache_xtn_req = true; |
---|
2514 | r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; |
---|
2515 | break; |
---|
2516 | |
---|
2517 | case iss_t::XTN_ICACHE_FLUSH: // icache access |
---|
2518 | r_dcache_xtn_req = true; |
---|
2519 | r_dcache_fsm = DCACHE_XTN_IC_FLUSH; |
---|
2520 | break; |
---|
2521 | |
---|
2522 | case iss_t::XTN_SYNC: // wait until write buffer empty |
---|
2523 | r_dcache_fsm = DCACHE_XTN_SYNC; |
---|
2524 | break; |
---|
2525 | |
---|
2526 | case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access |
---|
2527 | r_mmu_word_lo = dreq.wdata; |
---|
2528 | drsp.valid = true; |
---|
2529 | r_dcache_fsm = DCACHE_IDLE; |
---|
2530 | break; |
---|
2531 | |
---|
2532 | case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access |
---|
2533 | r_mmu_word_hi = dreq.wdata; |
---|
2534 | drsp.valid = true; |
---|
2535 | r_dcache_fsm = DCACHE_IDLE; |
---|
2536 | break; |
---|
2537 | |
---|
2538 | case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action |
---|
2539 | case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action |
---|
2540 | drsp.valid = true; |
---|
2541 | r_dcache_fsm = DCACHE_IDLE; |
---|
2542 | break; |
---|
2543 | |
---|
2544 | default: |
---|
2545 | r_mmu_detr = MMU_WRITE_UNDEFINED_XTN; |
---|
2546 | r_mmu_dbvar = dreq.addr; |
---|
2547 | drsp.valid = true; |
---|
2548 | drsp.error = true; |
---|
2549 | r_dcache_fsm = DCACHE_IDLE; |
---|
2550 | break; |
---|
2551 | } // end switch xtn_opcode |
---|
2552 | } // end else |
---|
2553 | } // end if XTN_WRITE |
---|
2554 | |
---|
2555 | // Handling read/write processor requests. |
---|
2556 | // The dtlb and dcache can be activated or not. |
---|
2557 | // We compute the physical address, the cacheability, and check processor request. |
---|
2558 | // - If DTLB not activated : cacheability is defined by the segment table, |
---|
2559 | // the physical address is equal to the virtual address (identity mapping) |
---|
2560 | // - If DTLB activated : cacheability is defined by the C bit in the PTE, |
---|
2561 | // the physical address is obtained from the TLB, and the U & W bits |
---|
2562 | // of the PTE are checked. |
---|
2563 | // The processor request is decoded only if the TLB is not activated or if |
---|
2564 | // the virtual address hits in tLB and access rights are OK. |
---|
2565 | // We call the TLB_MISS sub-fsm in case of dtlb miss. |
---|
2566 | else |
---|
2567 | { |
---|
2568 | bool valid_req = false; |
---|
2569 | bool cacheable = false; |
---|
2570 | paddr_t paddr = 0; |
---|
2571 | |
---|
2572 | if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated |
---|
2573 | { |
---|
2574 | valid_req = true; |
---|
2575 | |
---|
2576 | // cacheability |
---|
2577 | if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; |
---|
2578 | else cacheable = m_cacheability_table[dreq.addr]; |
---|
2579 | |
---|
2580 | // physical address |
---|
2581 | paddr = (paddr_t)dreq.addr; |
---|
2582 | } |
---|
2583 | else // dtlb activated |
---|
2584 | { |
---|
2585 | if ( tlb_hit ) // tlb hit |
---|
2586 | { |
---|
2587 | // cacheability |
---|
2588 | if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; |
---|
2589 | else cacheable = tlb_flags.c; |
---|
2590 | |
---|
2591 | // access rights checking |
---|
2592 | if ( not tlb_flags.u and (dreq.mode == iss_t::MODE_USER)) |
---|
2593 | { |
---|
2594 | if ( (dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL) ) |
---|
2595 | r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; |
---|
2596 | else |
---|
2597 | r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; |
---|
2598 | |
---|
2599 | r_mmu_dbvar = dreq.addr; |
---|
2600 | drsp.valid = true; |
---|
2601 | drsp.error = true; |
---|
2602 | drsp.rdata = 0; |
---|
2603 | } |
---|
2604 | else if ( not tlb_flags.w and |
---|
2605 | ((dreq.type == iss_t::DATA_WRITE) or |
---|
2606 | (dreq.type == iss_t::DATA_SC)) ) |
---|
2607 | { |
---|
2608 | r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; |
---|
2609 | r_mmu_dbvar = dreq.addr; |
---|
2610 | drsp.valid = true; |
---|
2611 | drsp.error = true; |
---|
2612 | drsp.rdata = 0; |
---|
2613 | } |
---|
2614 | else |
---|
2615 | { |
---|
2616 | valid_req = true; |
---|
2617 | } |
---|
2618 | |
---|
2619 | // physical address |
---|
2620 | paddr = tlb_paddr; |
---|
2621 | } |
---|
2622 | else // tlb miss |
---|
2623 | { |
---|
2624 | r_dcache_tlb_vaddr = dreq.addr; |
---|
2625 | r_dcache_tlb_ins = false; |
---|
2626 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
2627 | } |
---|
2628 | } // end DTLB activated |
---|
2629 | |
---|
2630 | if ( valid_req ) // processor request is valid |
---|
2631 | { |
---|
2632 | // physical address and cacheability registration |
---|
2633 | r_dcache_p0_paddr = paddr; |
---|
2634 | r_dcache_p0_cacheable = cacheable; |
---|
2635 | |
---|
2636 | // READ or LL request |
---|
2637 | // The read requests are taken only if the write pipe-line is empty. |
---|
2638 | // If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle. |
---|
2639 | // If speculative access is KO we just pay one extra cycle. |
---|
2640 | // If dcache miss, we go to DCACHE_MISS_VICTIM state. |
---|
2641 | // If uncacheable, we go to DCACHE_UNC_WAIT state. |
---|
2642 | if ( ((dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL)) and |
---|
2643 | not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() ) |
---|
2644 | { |
---|
2645 | if ( cacheable ) // cacheable read |
---|
2646 | { |
---|
2647 | // if the speculative access is illegal, we pay an extra cycle |
---|
2648 | if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) |
---|
2649 | != (paddr & ~PAGE_K_MASK)) |
---|
2650 | { |
---|
2651 | #ifdef INSTRUMENTATION |
---|
2652 | m_cpt_dcache_spec_miss++; |
---|
2653 | #endif |
---|
2654 | } |
---|
2655 | // if cache miss, try to get the missing line |
---|
2656 | else if ( not cache_hit ) |
---|
2657 | { |
---|
2658 | #ifdef INSTRUMENTATION |
---|
2659 | m_cpt_dcache_miss++; |
---|
2660 | #endif |
---|
2661 | // blocked in IDLE state if previous cleanup not completed |
---|
2662 | if ( not r_dcache_cleanup_req.read() ) |
---|
2663 | { |
---|
2664 | r_dcache_vci_paddr = paddr; |
---|
2665 | r_dcache_vci_miss_req = true; |
---|
2666 | r_dcache_miss_type = PROC_MISS; |
---|
2667 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
2668 | } |
---|
2669 | } |
---|
2670 | // if cache hit return the data |
---|
2671 | else |
---|
2672 | { |
---|
2673 | #ifdef INSTRUMENTATION |
---|
2674 | m_cpt_data_read++; |
---|
2675 | #endif |
---|
2676 | drsp.valid = true; |
---|
2677 | drsp.rdata = cache_rdata; |
---|
2678 | } |
---|
2679 | } |
---|
2680 | else // uncacheable read |
---|
2681 | { |
---|
2682 | r_dcache_vci_paddr = paddr; |
---|
2683 | r_dcache_vci_unc_be = dreq.be; |
---|
2684 | r_dcache_vci_unc_req = true; |
---|
2685 | r_dcache_fsm = DCACHE_UNC_WAIT; |
---|
2686 | } |
---|
2687 | |
---|
2688 | // makes reservation in case of LL |
---|
2689 | if ( dreq.type == iss_t::DATA_LL ) |
---|
2690 | { |
---|
2691 | r_dcache_ll_valid = true; |
---|
2692 | r_dcache_ll_data = cache_rdata; |
---|
2693 | r_dcache_ll_vaddr = dreq.addr; |
---|
2694 | } |
---|
2695 | } // end READ or LL |
---|
2696 | |
---|
2697 | // WRITE request: |
---|
2698 | // The write request arguments have been registered. |
---|
2699 | // The physical address has been computed and registered. |
---|
2700 | // We acknowledge the processor request and activate the P1 pipeline stage. |
---|
2701 | else if ( dreq.type == iss_t::DATA_WRITE ) |
---|
2702 | { |
---|
2703 | |
---|
2704 | #ifdef INSTRUMENTATION |
---|
2705 | m_cpt_data_write++; |
---|
2706 | #endif |
---|
2707 | p0_valid = true; |
---|
2708 | drsp.valid = true; |
---|
2709 | drsp.rdata = 0; |
---|
2710 | } // end WRITE |
---|
2711 | |
---|
2712 | // SC request: |
---|
2713 | // - if a valid LL reservation (with the same address) is registered, |
---|
2714 | // we request a SC transaction to CMD FSM and go to the DCACHE_UNC_WAIT state |
---|
2715 | // that will directly return the response to the processor, and invalidate |
---|
2716 | // the LL reservation. We don't check a possible write hit in dcache, |
---|
2717 | // as the cache update is done by the coherence transaction... |
---|
2718 | // - if there is no registerd LL, we just stay in IDLE state, invalidate |
---|
2719 | // the LL reservation, and return 1 (atomic access failed) |
---|
2720 | else if ( dreq.type == iss_t::DATA_SC ) |
---|
2721 | { |
---|
2722 | #ifdef INSTRUMENTATION |
---|
2723 | m_cpt_data_sc++; |
---|
2724 | #endif |
---|
2725 | // test if valid registered LL |
---|
2726 | if ( r_dcache_ll_valid.read() and (r_dcache_ll_vaddr.read() == dreq.addr)) |
---|
2727 | { |
---|
2728 | r_dcache_vci_paddr = paddr; |
---|
2729 | r_dcache_vci_sc_req = true; |
---|
2730 | r_dcache_vci_sc_old = r_dcache_ll_data.read(); |
---|
2731 | r_dcache_vci_sc_new = dreq.wdata; |
---|
2732 | r_dcache_fsm = DCACHE_UNC_WAIT; |
---|
2733 | } |
---|
2734 | else // no registered LL |
---|
2735 | { |
---|
2736 | drsp.valid = true; |
---|
2737 | drsp.rdata = 1; |
---|
2738 | r_dcache_ll_valid = false; |
---|
2739 | } |
---|
2740 | } // end SC |
---|
2741 | } // end valid_req |
---|
2742 | } // end if read/write request |
---|
2743 | } // end P0 pipe stage |
---|
2744 | |
---|
2745 | r_dcache_p0_valid = p0_valid; |
---|
2746 | break; |
---|
2747 | } |
---|
2748 | ///////////////////// |
---|
2749 | case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling tlb miss. |
---|
2750 | // - Input arguments are r_dcache_tlb_vaddr & r_dcache_tlb_ins |
---|
2751 | // - It try to find the missing TLB entry in dcache, |
---|
2752 | // and activates the cache miss procedure in case of miss. |
---|
2753 | // - It bypass the first level page table access if possible. |
---|
2754 | // - It uses atomic access to update the R/L access bits |
---|
2755 | // in the page table if required. |
---|
2756 | // - It directly updates the itlb or dtlb, and writes into the |
---|
2757 | // r_mmu_ins_* or r_mmu_data* error reporting registers. |
---|
2758 | { |
---|
2759 | uint32_t ptba = 0; |
---|
2760 | bool bypass; |
---|
2761 | paddr_t paddr; |
---|
2762 | |
---|
2763 | // evaluate bypass in order to skip first level page table access |
---|
2764 | if ( r_dcache_tlb_ins.read() ) // itlb miss |
---|
2765 | { |
---|
2766 | bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
2767 | } |
---|
2768 | else // dtlb miss |
---|
2769 | { |
---|
2770 | bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); |
---|
2771 | } |
---|
2772 | |
---|
2773 | if ( not bypass ) // Try to read the PTE1/PTD1 in dcache |
---|
2774 | { |
---|
2775 | paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) | |
---|
2776 | (paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); |
---|
2777 | r_dcache_tlb_paddr = paddr; |
---|
2778 | r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
2779 | } |
---|
2780 | else // Try to read directly the PTE2 in dcache |
---|
2781 | { |
---|
2782 | paddr = (paddr_t)ptba << PAGE_K_NBITS | |
---|
2783 | (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); |
---|
2784 | r_dcache_tlb_paddr = paddr; |
---|
2785 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
2786 | } |
---|
2787 | |
---|
2788 | #if DEBUG_DCACHE |
---|
2789 | if ( m_debug_dcache_fsm ) |
---|
2790 | { |
---|
2791 | if ( r_dcache_tlb_ins.read() ) |
---|
2792 | std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss request:"; |
---|
2793 | else |
---|
2794 | std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss request:"; |
---|
2795 | std::cout << " vaddr = " << std::hex << r_dcache_tlb_vaddr.read() |
---|
2796 | << " / bypass = " << bypass |
---|
2797 | << " / PTE address = " << paddr << std::endl; |
---|
2798 | } |
---|
2799 | #endif |
---|
2800 | |
---|
2801 | break; |
---|
2802 | } |
---|
2803 | ///////////////////////// |
---|
2804 | case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache |
---|
2805 | { |
---|
2806 | uint32_t entry; |
---|
2807 | size_t way; |
---|
2808 | size_t set; |
---|
2809 | size_t word; |
---|
2810 | |
---|
2811 | bool hit = r_dcache.read( r_dcache_tlb_paddr.read(), |
---|
2812 | &entry, |
---|
2813 | &way, |
---|
2814 | &set, |
---|
2815 | &word ); |
---|
2816 | #ifdef INSTRUMENTATION |
---|
2817 | m_cpt_dcache_data_read++; |
---|
2818 | m_cpt_dcache_dir_read++; |
---|
2819 | #endif |
---|
2820 | if ( hit ) // request hit in dcache |
---|
2821 | { |
---|
2822 | if ( not (entry & PTE_V_MASK) ) // unmapped |
---|
2823 | { |
---|
2824 | if ( r_dcache_tlb_ins.read() ) |
---|
2825 | { |
---|
2826 | r_mmu_ietr = MMU_READ_PT1_UNMAPPED; |
---|
2827 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
2828 | r_icache_tlb_miss_req = false; |
---|
2829 | r_icache_tlb_rsp_error = true; |
---|
2830 | } |
---|
2831 | else |
---|
2832 | { |
---|
2833 | r_mmu_detr = MMU_READ_PT1_UNMAPPED; |
---|
2834 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
2835 | drsp.valid = true; |
---|
2836 | drsp.error = true; |
---|
2837 | } |
---|
2838 | r_dcache_fsm = DCACHE_IDLE; |
---|
2839 | |
---|
2840 | #if DEBUG_DCACHE |
---|
2841 | if ( m_debug_dcache_fsm ) |
---|
2842 | { |
---|
2843 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped:" |
---|
2844 | << std::dec << " way = " << way |
---|
2845 | << std::dec << " / set = " << set |
---|
2846 | << std::dec << " / word = " << word |
---|
2847 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
2848 | } |
---|
2849 | #endif |
---|
2850 | |
---|
2851 | } |
---|
2852 | else if( entry & PTE_T_MASK ) // PTD : access PT2 |
---|
2853 | { |
---|
2854 | // register bypass |
---|
2855 | if ( r_dcache_tlb_ins.read() ) // itlb |
---|
2856 | { |
---|
2857 | r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
2858 | entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), |
---|
2859 | r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2))); |
---|
2860 | } |
---|
2861 | else // dtlb |
---|
2862 | { |
---|
2863 | r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), |
---|
2864 | entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), |
---|
2865 | r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)); |
---|
2866 | } |
---|
2867 | r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | |
---|
2868 | (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); |
---|
2869 | r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
2870 | |
---|
2871 | #if DEBUG_DCACHE |
---|
2872 | if ( m_debug_dcache_fsm ) |
---|
2873 | { |
---|
2874 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache " |
---|
2875 | << std::dec << " way = " << way |
---|
2876 | << std::dec << " / set = " << set |
---|
2877 | << std::dec << " / word = " << word |
---|
2878 | << std::hex << " / PTD = " << entry << std::endl; |
---|
2879 | } |
---|
2880 | #endif |
---|
2881 | } |
---|
2882 | else // PTE1 : update the TLB |
---|
2883 | { |
---|
2884 | if ( r_dcache_tlb_ins.read() ) |
---|
2885 | r_dcache_in_itlb[m_icache_sets*way+set] = true; |
---|
2886 | else |
---|
2887 | r_dcache_in_dtlb[m_dcache_sets*way+set] = true; |
---|
2888 | r_dcache_tlb_pte_flags = entry; |
---|
2889 | r_dcache_tlb_cache_way = way; |
---|
2890 | r_dcache_tlb_cache_set = set; |
---|
2891 | r_dcache_tlb_cache_word = word; |
---|
2892 | r_dcache_fsm = DCACHE_TLB_PTE1_SELECT; |
---|
2893 | |
---|
2894 | #if DEBUG_DCACHE |
---|
2895 | if ( m_debug_dcache_fsm ) |
---|
2896 | { |
---|
2897 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache:" |
---|
2898 | << std::dec << " way = " << way |
---|
2899 | << std::dec << " / set = " << set |
---|
2900 | << std::dec << " / word = " << word |
---|
2901 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
2902 | } |
---|
2903 | #endif |
---|
2904 | } |
---|
2905 | } |
---|
2906 | else // we must load the missing cache line in dcache |
---|
2907 | { |
---|
2908 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
2909 | r_dcache_miss_type = PTE1_MISS; |
---|
2910 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
2911 | r_dcache_vci_miss_req = true; |
---|
2912 | |
---|
2913 | #if DEBUG_DCACHE |
---|
2914 | if ( m_debug_dcache_fsm ) |
---|
2915 | { |
---|
2916 | std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:" |
---|
2917 | << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
2918 | } |
---|
2919 | #endif |
---|
2920 | } |
---|
2921 | break; |
---|
2922 | } |
---|
2923 | //////////////////////////// |
---|
2924 | case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 |
---|
2925 | { |
---|
2926 | size_t way; |
---|
2927 | size_t set; |
---|
2928 | |
---|
2929 | if ( r_dcache_tlb_ins.read() ) |
---|
2930 | { |
---|
2931 | r_itlb.select( r_dcache_tlb_vaddr.read(), |
---|
2932 | true, // PTE1 |
---|
2933 | &way, |
---|
2934 | &set ); |
---|
2935 | #ifdef INSTRUMENTATION |
---|
2936 | m_cpt_itlb_read++; |
---|
2937 | #endif |
---|
2938 | } |
---|
2939 | else |
---|
2940 | { |
---|
2941 | r_dtlb.select( r_dcache_tlb_vaddr.read(), |
---|
2942 | true, // PTE1 |
---|
2943 | &way, |
---|
2944 | &set ); |
---|
2945 | #ifdef INSTRUMENTATION |
---|
2946 | m_cpt_dtlb_read++; |
---|
2947 | #endif |
---|
2948 | } |
---|
2949 | r_dcache_tlb_way = way; |
---|
2950 | r_dcache_tlb_set = set; |
---|
2951 | r_dcache_fsm = DCACHE_TLB_PTE1_UPDT; |
---|
2952 | |
---|
2953 | #if DEBUG_DCACHE |
---|
2954 | if ( m_debug_dcache_fsm ) |
---|
2955 | { |
---|
2956 | if ( r_dcache_tlb_ins.read() ) |
---|
2957 | std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:"; |
---|
2958 | else |
---|
2959 | std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:"; |
---|
2960 | std::cout << " way = " << std::dec << way |
---|
2961 | << " / set = " << set << std::endl; |
---|
2962 | } |
---|
2963 | #endif |
---|
2964 | break; |
---|
2965 | } |
---|
2966 | ////////////////////////// |
---|
2967 | case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit |
---|
2968 | // if L/R bit already set, exit the sub-fsm |
---|
2969 | // if not, the page table must be updated |
---|
2970 | { |
---|
2971 | paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
2972 | uint32_t pte = r_dcache_tlb_pte_flags.read(); |
---|
2973 | bool updt = false; |
---|
2974 | |
---|
2975 | // test the access bits L/R, depending on the physical address locality |
---|
2976 | // we must use the 10 MSB bits of the 19 bits PPN1 to obtain the target index |
---|
2977 | // we must use the 10 MSB bits of the SRCID to obtain the local index |
---|
2978 | // set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required |
---|
2979 | |
---|
2980 | uint32_t target = (pte >> 9) & 0x3FF; |
---|
2981 | uint32_t local = m_srcid_d >> 4; |
---|
2982 | |
---|
2983 | if ( local == target ) // local_address |
---|
2984 | { |
---|
2985 | if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit |
---|
2986 | { |
---|
2987 | updt = true; |
---|
2988 | r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read(); |
---|
2989 | r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() | PTE_L_MASK; |
---|
2990 | } |
---|
2991 | } |
---|
2992 | else // remote address |
---|
2993 | { |
---|
2994 | if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit |
---|
2995 | { |
---|
2996 | updt = true; |
---|
2997 | r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read(); |
---|
2998 | r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() | PTE_R_MASK; |
---|
2999 | } |
---|
3000 | } |
---|
3001 | |
---|
3002 | // update TLB |
---|
3003 | if ( r_dcache_tlb_ins.read() ) |
---|
3004 | { |
---|
3005 | r_itlb.write( true, // 2M page |
---|
3006 | pte, |
---|
3007 | 0, // argument unused for a PTE1 |
---|
3008 | r_dcache_tlb_vaddr.read(), |
---|
3009 | r_dcache_tlb_way.read(), |
---|
3010 | r_dcache_tlb_set.read(), |
---|
3011 | nline ); |
---|
3012 | #ifdef INSTRUMENTATION |
---|
3013 | m_cpt_itlb_write++; |
---|
3014 | #endif |
---|
3015 | } |
---|
3016 | else |
---|
3017 | { |
---|
3018 | r_dtlb.write( true, // 2M page |
---|
3019 | pte, |
---|
3020 | 0, // argument unused for a PTE1 |
---|
3021 | r_dcache_tlb_vaddr.read(), |
---|
3022 | r_dcache_tlb_way.read(), |
---|
3023 | r_dcache_tlb_set.read(), |
---|
3024 | nline ); |
---|
3025 | #ifdef INSTRUMENTATION |
---|
3026 | m_cpt_dtlb_write++; |
---|
3027 | #endif |
---|
3028 | } |
---|
3029 | // next state |
---|
3030 | if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update |
---|
3031 | else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm |
---|
3032 | |
---|
3033 | #if DEBUG_DCACHE |
---|
3034 | if ( m_debug_dcache_fsm ) |
---|
3035 | { |
---|
3036 | if ( r_dcache_tlb_ins.read() ) |
---|
3037 | { |
---|
3038 | std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB:"; |
---|
3039 | std::cout << " way = " << std::dec << r_dcache_tlb_way.read() |
---|
3040 | << " / set = " << r_dcache_tlb_set.read() << std::endl; |
---|
3041 | r_itlb.print(); |
---|
3042 | } |
---|
3043 | else |
---|
3044 | { |
---|
3045 | std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB:"; |
---|
3046 | std::cout << " way = " << std::dec << r_dcache_tlb_way.read() |
---|
3047 | << " / set = " << r_dcache_tlb_set.read() << std::endl; |
---|
3048 | r_dtlb.print(); |
---|
3049 | } |
---|
3050 | |
---|
3051 | } |
---|
3052 | #endif |
---|
3053 | break; |
---|
3054 | } |
---|
3055 | ///////////////////////// |
---|
3056 | case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache |
---|
3057 | { |
---|
3058 | uint32_t pte_flags; |
---|
3059 | uint32_t pte_ppn; |
---|
3060 | size_t way; |
---|
3061 | size_t set; |
---|
3062 | size_t word; |
---|
3063 | |
---|
3064 | bool hit = r_dcache.read( r_dcache_tlb_paddr.read(), |
---|
3065 | &pte_flags, |
---|
3066 | &pte_ppn, |
---|
3067 | &way, |
---|
3068 | &set, |
---|
3069 | &word ); |
---|
3070 | #ifdef INSTRUMENTATION |
---|
3071 | m_cpt_dcache_data_read++; |
---|
3072 | m_cpt_dcache_dir_read++; |
---|
3073 | #endif |
---|
3074 | if ( hit ) // request hits in dcache |
---|
3075 | { |
---|
3076 | if ( not (pte_flags & PTE_V_MASK) ) // unmapped |
---|
3077 | { |
---|
3078 | if ( r_dcache_tlb_ins.read() ) |
---|
3079 | { |
---|
3080 | r_mmu_ietr = MMU_READ_PT2_UNMAPPED; |
---|
3081 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
3082 | r_icache_tlb_miss_req = false; |
---|
3083 | r_icache_tlb_rsp_error = true; |
---|
3084 | } |
---|
3085 | else |
---|
3086 | { |
---|
3087 | r_mmu_detr = MMU_READ_PT2_UNMAPPED; |
---|
3088 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
3089 | drsp.valid = true; |
---|
3090 | drsp.error = true; |
---|
3091 | } |
---|
3092 | r_dcache_fsm = DCACHE_IDLE; |
---|
3093 | |
---|
3094 | #if DEBUG_DCACHE |
---|
3095 | if ( m_debug_dcache_fsm ) |
---|
3096 | { |
---|
3097 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped" |
---|
3098 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
3099 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
3100 | } |
---|
3101 | #endif |
---|
3102 | } |
---|
3103 | else // mapped : update the TLB |
---|
3104 | { |
---|
3105 | if ( r_dcache_tlb_ins.read() ) r_dcache_in_itlb[m_icache_sets*way+set] = true; |
---|
3106 | else r_dcache_in_dtlb[m_dcache_sets*way+set] = true; |
---|
3107 | r_dcache_tlb_pte_flags = pte_flags; |
---|
3108 | r_dcache_tlb_pte_ppn = pte_ppn; |
---|
3109 | r_dcache_tlb_cache_way = way; |
---|
3110 | r_dcache_tlb_cache_set = set; |
---|
3111 | r_dcache_tlb_cache_word = word; |
---|
3112 | r_dcache_fsm = DCACHE_TLB_PTE2_SELECT; |
---|
3113 | |
---|
3114 | #if DEBUG_DCACHE |
---|
3115 | if ( m_debug_dcache_fsm ) |
---|
3116 | { |
---|
3117 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:" |
---|
3118 | << " PTE_FLAGS = " << std::hex << pte_flags |
---|
3119 | << " PTE_PPN = " << std::hex << pte_ppn << std::endl; |
---|
3120 | } |
---|
3121 | #endif |
---|
3122 | } |
---|
3123 | } |
---|
3124 | else // we must load the missing cache line in dcache |
---|
3125 | { |
---|
3126 | r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); |
---|
3127 | r_dcache_miss_type = PTE2_MISS; |
---|
3128 | r_dcache_fsm = DCACHE_MISS_VICTIM; |
---|
3129 | r_dcache_vci_miss_req = true; |
---|
3130 | |
---|
3131 | #if DEBUG_DCACHE |
---|
3132 | if ( m_debug_dcache_fsm ) |
---|
3133 | { |
---|
3134 | std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:" |
---|
3135 | << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; |
---|
3136 | } |
---|
3137 | #endif |
---|
3138 | } |
---|
3139 | break; |
---|
3140 | } |
---|
3141 | //////////////////////////// |
---|
3142 | case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2 |
---|
3143 | { |
---|
3144 | size_t way; |
---|
3145 | size_t set; |
---|
3146 | |
---|
3147 | if ( r_dcache_tlb_ins.read() ) |
---|
3148 | { |
---|
3149 | r_itlb.select( r_dcache_tlb_vaddr.read(), |
---|
3150 | false, // PTE2 |
---|
3151 | &way, |
---|
3152 | &set ); |
---|
3153 | #ifdef INSTRUMENTATION |
---|
3154 | m_cpt_itlb_read++; |
---|
3155 | #endif |
---|
3156 | } |
---|
3157 | else |
---|
3158 | { |
---|
3159 | r_dtlb.select( r_dcache_tlb_vaddr.read(), |
---|
3160 | false, // PTE2 |
---|
3161 | &way, |
---|
3162 | &set ); |
---|
3163 | #ifdef INSTRUMENTATION |
---|
3164 | m_cpt_dtlb_read++; |
---|
3165 | #endif |
---|
3166 | } |
---|
3167 | r_dcache_tlb_way = way; |
---|
3168 | r_dcache_tlb_set = set; |
---|
3169 | r_dcache_fsm = DCACHE_TLB_PTE2_UPDT; |
---|
3170 | break; |
---|
3171 | } |
---|
3172 | ////////////////////////// |
---|
3173 | case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit |
---|
3174 | // if L/R bit already set exit the sub-fsm |
---|
3175 | // if not, the page table must be updated by an atomic access |
---|
3176 | { |
---|
3177 | paddr_t nline = r_dcache_p0_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
3178 | uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); |
---|
3179 | uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); |
---|
3180 | bool updt = false; // page table update required |
---|
3181 | |
---|
3182 | // test the access bit L/R, depending on the physical address locality |
---|
3183 | // we must use the 10 MSB bits of the 28 bits PPN2 to obtain the target cluster index |
---|
3184 | // we must use the 10 MSB bits of the SRCID to obtain the local cluster index |
---|
3185 | // set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required. |
---|
3186 | |
---|
3187 | uint32_t target = (pte_ppn >> 18) & 0x3FF; |
---|
3188 | uint32_t local = m_srcid_d >> 4; |
---|
3189 | |
---|
3190 | if ( local == target ) // local address |
---|
3191 | { |
---|
3192 | if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit |
---|
3193 | { |
---|
3194 | updt = true; |
---|
3195 | r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read(); |
---|
3196 | r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() | PTE_L_MASK; |
---|
3197 | } |
---|
3198 | } |
---|
3199 | else // remote address |
---|
3200 | { |
---|
3201 | if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit |
---|
3202 | { |
---|
3203 | updt = true; |
---|
3204 | r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read(); |
---|
3205 | r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() | PTE_R_MASK; |
---|
3206 | } |
---|
3207 | } |
---|
3208 | |
---|
3209 | // update TLB for a PTE2 |
---|
3210 | if ( r_dcache_tlb_ins.read() ) |
---|
3211 | { |
---|
3212 | r_itlb.write( false, // 2K page |
---|
3213 | pte_flags, |
---|
3214 | pte_ppn, |
---|
3215 | r_dcache_tlb_vaddr.read(), |
---|
3216 | r_dcache_tlb_way.read(), |
---|
3217 | r_dcache_tlb_set.read(), |
---|
3218 | nline ); |
---|
3219 | #ifdef INSTRUMENTATION |
---|
3220 | m_cpt_itlb_write++; |
---|
3221 | #endif |
---|
3222 | } |
---|
3223 | else |
---|
3224 | { |
---|
3225 | r_dtlb.write( false, // 2K page |
---|
3226 | pte_flags, |
---|
3227 | pte_ppn, |
---|
3228 | r_dcache_tlb_vaddr.read(), |
---|
3229 | r_dcache_tlb_way.read(), |
---|
3230 | r_dcache_tlb_set.read(), |
---|
3231 | nline ); |
---|
3232 | #ifdef INSTRUMENTATION |
---|
3233 | m_cpt_dtlb_write++; |
---|
3234 | #endif |
---|
3235 | } |
---|
3236 | |
---|
3237 | #if DEBUG_DCACHE |
---|
3238 | if ( m_debug_dcache_fsm ) |
---|
3239 | { |
---|
3240 | if ( r_dcache_tlb_ins.read() ) |
---|
3241 | { |
---|
3242 | std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB:"; |
---|
3243 | std::cout << " way = " << std::dec << r_dcache_tlb_way.read() |
---|
3244 | << " / set = " << r_dcache_tlb_set.read() << std::endl; |
---|
3245 | r_itlb.print(); |
---|
3246 | } |
---|
3247 | else |
---|
3248 | { |
---|
3249 | std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB:"; |
---|
3250 | std::cout << " way = " << std::dec << r_dcache_tlb_way.read() |
---|
3251 | << " / set = " << r_dcache_tlb_set.read() << std::endl; |
---|
3252 | r_dtlb.print(); |
---|
3253 | } |
---|
3254 | } |
---|
3255 | #endif |
---|
3256 | // next state |
---|
3257 | if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update |
---|
3258 | else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm |
---|
3259 | break; |
---|
3260 | } |
---|
3261 | //////////////////////// |
---|
3262 | case DCACHE_TLB_SC_UPDT: // update the dcache after a tlb miss (L/R bit), |
---|
3263 | // request a SC transaction to CMD FSM |
---|
3264 | { |
---|
3265 | r_dcache.write(r_dcache_tlb_cache_way.read(), |
---|
3266 | r_dcache_tlb_cache_set.read(), |
---|
3267 | r_dcache_tlb_cache_word.read(), |
---|
3268 | r_dcache_tlb_pte_flags.read()); |
---|
3269 | #ifdef INSTRUMENTATION |
---|
3270 | m_cpt_dcache_data_write++; |
---|
3271 | #endif |
---|
3272 | // r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set |
---|
3273 | r_dcache_vci_sc_req = true; |
---|
3274 | r_dcache_fsm = DCACHE_TLB_SC_WAIT; |
---|
3275 | break; |
---|
3276 | } |
---|
3277 | //////////////////////// |
---|
3278 | case DCACHE_TLB_SC_WAIT: // wait response to SC transaction from RSP FSM |
---|
3279 | // we consume the response, and exit the sub-fsm. |
---|
3280 | // we don't analyse the response, because |
---|
3281 | // we don't care if the L/R bit update is not done |
---|
3282 | // we must take the coherence requests because |
---|
3283 | // there is a risk of dead-lock |
---|
3284 | |
---|
3285 | { |
---|
3286 | // external coherence request |
---|
3287 | if ( r_tgt_dcache_req ) |
---|
3288 | { |
---|
3289 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
3290 | r_dcache_fsm_save = r_dcache_fsm; |
---|
3291 | break; |
---|
3292 | } |
---|
3293 | |
---|
3294 | if ( not r_dcache_vci_sc_req.read() ) // response available |
---|
3295 | { |
---|
3296 | if ( r_vci_rsp_data_error.read() ) r_vci_rsp_data_error = false; |
---|
3297 | else if ( r_vci_rsp_fifo_dcache.rok() ) vci_rsp_fifo_dcache_get = true; |
---|
3298 | else |
---|
3299 | { |
---|
3300 | assert( false and "rsp_fifo should not be empty in DCACHE_TLB_SC_WAIT state" ); |
---|
3301 | } |
---|
3302 | r_dcache_fsm = DCACHE_TLB_RETURN; |
---|
3303 | } |
---|
3304 | break; |
---|
3305 | } |
---|
3306 | /////////////////////// |
---|
3307 | case DCACHE_TLB_RETURN: // return to caller state depending on the tlb miss type |
---|
3308 | { |
---|
3309 | if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false; |
---|
3310 | r_dcache_fsm = DCACHE_IDLE; |
---|
3311 | break; |
---|
3312 | } |
---|
3313 | /////////////////////// |
---|
3314 | case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed |
---|
3315 | { |
---|
3316 | if ( not r_dcache_xtn_req.read() ) |
---|
3317 | { |
---|
3318 | r_dtlb.flush(); |
---|
3319 | r_dcache_fsm = DCACHE_IDLE; |
---|
3320 | drsp.valid = true; |
---|
3321 | } |
---|
3322 | break; |
---|
3323 | } |
---|
3324 | ///////////////////// |
---|
3325 | case DCACHE_XTN_SYNC: // waiting until write buffer empty |
---|
3326 | // The coherence request must be taken |
---|
3327 | // as there is a risk of dead-lock |
---|
3328 | { |
---|
3329 | // external coherence request |
---|
3330 | if ( r_tgt_dcache_req.read() ) |
---|
3331 | { |
---|
3332 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
3333 | r_dcache_fsm_save = DCACHE_XTN_SYNC; |
---|
3334 | } |
---|
3335 | |
---|
3336 | if ( r_wbuf.empty() ) |
---|
3337 | { |
---|
3338 | drsp.valid = true; |
---|
3339 | r_dcache_fsm = DCACHE_IDLE; |
---|
3340 | } |
---|
3341 | break; |
---|
3342 | } |
---|
3343 | //////////////////////// |
---|
3344 | case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM |
---|
3345 | case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken |
---|
3346 | case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache |
---|
3347 | case DCACHE_XTN_IT_INVAL: // can generate an itlb miss... |
---|
3348 | { |
---|
3349 | // external coherence request |
---|
3350 | if ( r_tgt_dcache_req ) |
---|
3351 | { |
---|
3352 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
3353 | r_dcache_fsm_save = r_dcache_fsm; |
---|
3354 | break; |
---|
3355 | } |
---|
3356 | |
---|
3357 | // itlb miss request |
---|
3358 | if ( r_icache_tlb_miss_req.read() ) |
---|
3359 | { |
---|
3360 | r_dcache_tlb_ins = true; |
---|
3361 | r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); |
---|
3362 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
3363 | break; |
---|
3364 | } |
---|
3365 | |
---|
3366 | // test if XTN request to icache completed |
---|
3367 | if ( not r_dcache_xtn_req.read() ) |
---|
3368 | { |
---|
3369 | r_dcache_fsm = DCACHE_IDLE; |
---|
3370 | drsp.valid = true; |
---|
3371 | } |
---|
3372 | break; |
---|
3373 | } |
---|
3374 | ///////////////////////// |
---|
3375 | case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using |
---|
3376 | // the r_dcache_flush counter as a slot counter. |
---|
3377 | // We loop in this state until all slots have been visited. |
---|
3378 | // A cleanup request is generated for each valid line |
---|
3379 | // and we are blocked until the previous cleanup is completed |
---|
3380 | // Finally, both the itlb and dtlb are reset, because |
---|
3381 | // all TLB entries (including global entries) must be invalidated. |
---|
3382 | { |
---|
3383 | if ( not r_dcache_cleanup_req ) |
---|
3384 | { |
---|
3385 | paddr_t nline; |
---|
3386 | size_t way = r_dcache_flush_count.read()/m_icache_sets; |
---|
3387 | size_t set = r_dcache_flush_count.read()%m_icache_sets; |
---|
3388 | |
---|
3389 | bool cleanup_req = r_dcache.inval( way, |
---|
3390 | set, |
---|
3391 | &nline ); |
---|
3392 | if ( cleanup_req ) |
---|
3393 | { |
---|
3394 | r_dcache_cleanup_req = true; |
---|
3395 | r_dcache_cleanup_line = nline; |
---|
3396 | } |
---|
3397 | |
---|
3398 | r_dcache_flush_count = r_dcache_flush_count.read() + 1; |
---|
3399 | |
---|
3400 | if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot |
---|
3401 | { |
---|
3402 | r_dtlb.reset(); // global entries are invalidated |
---|
3403 | r_itlb.reset(); // global entries are invalidated |
---|
3404 | for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++) |
---|
3405 | { |
---|
3406 | r_dcache_in_itlb[line] = false; |
---|
3407 | r_dcache_in_dtlb[line] = false; |
---|
3408 | } |
---|
3409 | r_dcache_fsm = DCACHE_IDLE; |
---|
3410 | drsp.valid = true; |
---|
3411 | } |
---|
3412 | } |
---|
3413 | break; |
---|
3414 | } |
---|
3415 | ///////////////////////// |
---|
3416 | case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request |
---|
3417 | { |
---|
3418 | r_dtlb.inval(r_dcache_p0_wdata.read()); |
---|
3419 | r_dcache_fsm = DCACHE_IDLE; |
---|
3420 | drsp.valid = true; |
---|
3421 | break; |
---|
3422 | } |
---|
3423 | //////////////////////////// |
---|
3424 | case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address |
---|
3425 | // requires 3 cycles: access tlb, read cache, inval cache |
---|
3426 | // we compute the physical address in this state |
---|
3427 | { |
---|
3428 | paddr_t paddr; |
---|
3429 | bool hit; |
---|
3430 | |
---|
3431 | if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated |
---|
3432 | { |
---|
3433 | #ifdef INSTRUMENTATION |
---|
3434 | m_cpt_dtlb_read++; |
---|
3435 | #endif |
---|
3436 | hit = r_dtlb.translate( r_dcache_p0_wdata.read(), |
---|
3437 | &paddr ); |
---|
3438 | } |
---|
3439 | else // dtlb not activated |
---|
3440 | { |
---|
3441 | paddr = (paddr_t)r_dcache_p0_wdata.read(); |
---|
3442 | hit = true; |
---|
3443 | } |
---|
3444 | |
---|
3445 | if ( hit ) // tlb hit |
---|
3446 | { |
---|
3447 | r_dcache_p0_paddr = paddr; |
---|
3448 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; |
---|
3449 | } |
---|
3450 | else // tlb miss |
---|
3451 | { |
---|
3452 | #ifdef INSTRUMENTATION |
---|
3453 | m_cpt_dtlb_miss++; |
---|
3454 | #endif |
---|
3455 | r_dcache_tlb_ins = false; // dtlb |
---|
3456 | r_dcache_tlb_vaddr = r_dcache_p0_wdata.read(); |
---|
3457 | r_dcache_fsm = DCACHE_TLB_MISS; |
---|
3458 | } |
---|
3459 | break; |
---|
3460 | } |
---|
3461 | //////////////////////////// |
---|
3462 | case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address |
---|
3463 | // requires 2 cycles: read cache / inval cache |
---|
3464 | // In this state we read dcache. |
---|
3465 | { |
---|
3466 | uint32_t data; |
---|
3467 | size_t way; |
---|
3468 | size_t set; |
---|
3469 | size_t word; |
---|
3470 | bool hit = r_dcache.read( r_dcache_p0_paddr.read(), |
---|
3471 | &data, |
---|
3472 | &way, |
---|
3473 | &set, |
---|
3474 | &word ); |
---|
3475 | #ifdef INSTRUMENTATION |
---|
3476 | m_cpt_dcache_data_read++; |
---|
3477 | m_cpt_dcache_dir_read++; |
---|
3478 | #endif |
---|
3479 | if ( hit ) // inval to be done |
---|
3480 | { |
---|
3481 | r_dcache_xtn_way = way; |
---|
3482 | r_dcache_xtn_set = set; |
---|
3483 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; |
---|
3484 | } |
---|
3485 | else // miss : nothing to do |
---|
3486 | { |
---|
3487 | r_dcache_fsm = DCACHE_IDLE; |
---|
3488 | drsp.valid = true; |
---|
3489 | } |
---|
3490 | break; |
---|
3491 | } |
---|
3492 | //////////////////////////// |
---|
3493 | case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line & cleanup |
---|
3494 | // Blocked if previous cleanup not completed |
---|
3495 | |
---|
3496 | { |
---|
3497 | if ( not r_dcache_cleanup_req.read() ) |
---|
3498 | { |
---|
3499 | paddr_t nline; |
---|
3500 | size_t way = r_dcache_xtn_way.read(); |
---|
3501 | size_t set = r_dcache_xtn_set.read(); |
---|
3502 | bool inval_tlb = false; |
---|
3503 | |
---|
3504 | r_icache.inval( way, |
---|
3505 | set, |
---|
3506 | &nline ); |
---|
3507 | |
---|
3508 | // request cleanup |
---|
3509 | r_dcache_cleanup_req = true; |
---|
3510 | r_dcache_cleanup_line = nline; |
---|
3511 | |
---|
3512 | // possible itlb & dtlb invalidate requests |
---|
3513 | r_dcache_tlb_inval_line = nline; |
---|
3514 | |
---|
3515 | if ( (r_mmu_mode.read() & DATA_TLB_MASK) and |
---|
3516 | r_dcache_in_dtlb[way*m_dcache_sets+set] ) |
---|
3517 | { |
---|
3518 | r_dcache_dtlb_inval_req = true; |
---|
3519 | r_dcache_in_dtlb[way*m_dcache_sets+set] = false; |
---|
3520 | inval_tlb = true; |
---|
3521 | } |
---|
3522 | if ( (r_mmu_mode.read() & INS_TLB_MASK) and |
---|
3523 | r_dcache_in_itlb[m_dcache_sets*way+set] ) |
---|
3524 | { |
---|
3525 | r_dcache_itlb_inval_req = true; |
---|
3526 | r_dcache_in_itlb[way*m_dcache_sets+set] = false; |
---|
3527 | inval_tlb = true; |
---|
3528 | } |
---|
3529 | |
---|
3530 | // no valid response until itlb & dtlb invalidated |
---|
3531 | if (inval_tlb ) |
---|
3532 | { |
---|
3533 | r_dcache_fsm = DCACHE_XTN_DC_INVAL_WAIT; |
---|
3534 | } |
---|
3535 | else |
---|
3536 | { |
---|
3537 | r_dcache_fsm = DCACHE_IDLE; |
---|
3538 | drsp.valid = true; |
---|
3539 | } |
---|
3540 | } |
---|
3541 | break; |
---|
3542 | } |
---|
3543 | ////////////////////////////// |
---|
3544 | case DCACHE_XTN_DC_INVAL_WAIT: // waiting completion of itlb and dtlb invalidate |
---|
3545 | { |
---|
3546 | if ( not (r_dcache_itlb_inval_req.read() or r_dcache_dtlb_inval_req.read()) ) |
---|
3547 | { |
---|
3548 | r_dcache_fsm = DCACHE_IDLE; |
---|
3549 | drsp.valid = true; |
---|
3550 | } |
---|
3551 | break; |
---|
3552 | } |
---|
3553 | //////////////////////// |
---|
3554 | case DCACHE_MISS_VICTIM: // Selects a victim line |
---|
3555 | // Set the r_dcache_cleanup_req flip-flop |
---|
3556 | // when the selected slot is not empty |
---|
3557 | { |
---|
3558 | bool valid; |
---|
3559 | size_t way; |
---|
3560 | size_t set; |
---|
3561 | paddr_t victim; |
---|
3562 | |
---|
3563 | valid = r_dcache.victim_select( r_dcache_vci_paddr.read(), |
---|
3564 | &victim, |
---|
3565 | &way, |
---|
3566 | &set ); |
---|
3567 | r_dcache_miss_way = way; |
---|
3568 | r_dcache_miss_set = set; |
---|
3569 | |
---|
3570 | if ( valid ) |
---|
3571 | { |
---|
3572 | r_dcache_cleanup_req = true; |
---|
3573 | r_dcache_cleanup_line = victim; |
---|
3574 | r_dcache_fsm = DCACHE_MISS_INVAL; |
---|
3575 | } |
---|
3576 | else |
---|
3577 | { |
---|
3578 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
3579 | } |
---|
3580 | |
---|
3581 | #if DEBUG_DCACHE |
---|
3582 | if ( m_debug_dcache_fsm ) |
---|
3583 | { |
---|
3584 | std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" |
---|
3585 | << " / way = " << way |
---|
3586 | << " / set = " << set |
---|
3587 | << " / valid = " << valid |
---|
3588 | << " / line = " << std::hex << victim << std::endl; |
---|
3589 | } |
---|
3590 | #endif |
---|
3591 | break; |
---|
3592 | } |
---|
3593 | /////////////////////// |
---|
3594 | case DCACHE_MISS_INVAL: // invalidate the victim line |
---|
3595 | // and possibly request itlb or dtlb invalidate |
---|
3596 | { |
---|
3597 | paddr_t nline; |
---|
3598 | size_t way = r_dcache_miss_way.read(); |
---|
3599 | size_t set = r_dcache_miss_set.read(); |
---|
3600 | |
---|
3601 | r_dcache.inval( way, |
---|
3602 | set, |
---|
3603 | &nline ); |
---|
3604 | |
---|
3605 | // if itlb & dtlb invalidate are required |
---|
3606 | // the miss response is not handled before invalidate completed |
---|
3607 | if ( (r_mmu_mode.read() & DATA_TLB_MASK) and |
---|
3608 | ( r_dcache_in_itlb[way*m_dcache_sets+set] or |
---|
3609 | r_dcache_in_dtlb[m_dcache_sets*way+set] ) ) |
---|
3610 | { |
---|
3611 | r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
3612 | r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set]; |
---|
3613 | r_dcache_in_itlb[way*m_dcache_sets+set] = false; |
---|
3614 | r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set]; |
---|
3615 | r_dcache_in_dtlb[way*m_dcache_sets+set] = false; |
---|
3616 | r_dcache_fsm = DCACHE_MISS_INVAL_WAIT; |
---|
3617 | } |
---|
3618 | else |
---|
3619 | { |
---|
3620 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
3621 | } |
---|
3622 | break; |
---|
3623 | } |
---|
3624 | //////////////////////////// |
---|
3625 | case DCACHE_MISS_INVAL_WAIT: // waiting completion of itlb / dtlb invalidate |
---|
3626 | { |
---|
3627 | if ( (not r_dcache_itlb_inval_req.read()) or (not r_dcache_dtlb_inval_req.read()) ) |
---|
3628 | { |
---|
3629 | r_dcache_fsm = DCACHE_MISS_WAIT; |
---|
3630 | } |
---|
3631 | break; |
---|
3632 | } |
---|
3633 | ////////////////////// |
---|
3634 | case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM |
---|
3635 | // This state is in charge of error signaling |
---|
3636 | // There is 5 types of error depending on the requester |
---|
3637 | { |
---|
3638 | // external coherence request |
---|
3639 | if ( r_tgt_dcache_req ) |
---|
3640 | { |
---|
3641 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
3642 | r_dcache_fsm_save = r_dcache_fsm; |
---|
3643 | break; |
---|
3644 | } |
---|
3645 | |
---|
3646 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
3647 | { |
---|
3648 | switch ( r_dcache_miss_type.read() ) |
---|
3649 | { |
---|
3650 | case PROC_MISS: |
---|
3651 | { |
---|
3652 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
3653 | r_mmu_dbvar = r_dcache_p0_vaddr.read(); |
---|
3654 | drsp.valid = true; |
---|
3655 | drsp.error = true; |
---|
3656 | r_dcache_fsm = DCACHE_IDLE; |
---|
3657 | break; |
---|
3658 | } |
---|
3659 | case PTE1_MISS: |
---|
3660 | { |
---|
3661 | if ( r_dcache_tlb_ins.read() ) |
---|
3662 | { |
---|
3663 | r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
3664 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
3665 | r_icache_tlb_miss_req = false; |
---|
3666 | r_icache_tlb_rsp_error = true; |
---|
3667 | } |
---|
3668 | else |
---|
3669 | { |
---|
3670 | r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; |
---|
3671 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
3672 | drsp.valid = true; |
---|
3673 | drsp.error = true; |
---|
3674 | } |
---|
3675 | r_dcache_fsm = DCACHE_IDLE; |
---|
3676 | break; |
---|
3677 | } |
---|
3678 | case PTE2_MISS: |
---|
3679 | { |
---|
3680 | if ( r_dcache_tlb_ins.read() ) |
---|
3681 | { |
---|
3682 | r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
3683 | r_mmu_ibvar = r_dcache_tlb_vaddr.read(); |
---|
3684 | r_icache_tlb_miss_req = false; |
---|
3685 | r_icache_tlb_rsp_error = true; |
---|
3686 | } |
---|
3687 | else |
---|
3688 | { |
---|
3689 | r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
3690 | r_mmu_dbvar = r_dcache_tlb_vaddr.read(); |
---|
3691 | drsp.valid = true; |
---|
3692 | drsp.error = true; |
---|
3693 | } |
---|
3694 | r_dcache_fsm = DCACHE_IDLE; |
---|
3695 | break; |
---|
3696 | } |
---|
3697 | } // end switch type |
---|
3698 | r_vci_rsp_data_error = false; |
---|
3699 | } |
---|
3700 | else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available |
---|
3701 | { |
---|
3702 | r_dcache_miss_word = 0; |
---|
3703 | r_dcache_fsm = DCACHE_MISS_UPDT; |
---|
3704 | } |
---|
3705 | break; |
---|
3706 | } |
---|
3707 | ////////////////////// |
---|
3708 | case DCACHE_MISS_UPDT: // update the dcache (one word per cycle) |
---|
3709 | // returns the response depending on the miss type |
---|
3710 | { |
---|
3711 | if ( r_vci_rsp_fifo_dcache.rok() ) // one word available |
---|
3712 | { |
---|
3713 | if ( r_dcache_miss_inval.read() ) // Matching coherence request |
---|
3714 | // pop the FIFO, without cache update |
---|
3715 | // send a cleanup for the missing line |
---|
3716 | // if the previous cleanup is completed |
---|
3717 | { |
---|
3718 | if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last |
---|
3719 | { |
---|
3720 | vci_rsp_fifo_dcache_get = true; |
---|
3721 | r_dcache_miss_word = r_dcache_miss_word.read() + 1; |
---|
3722 | } |
---|
3723 | else // last word |
---|
3724 | { |
---|
3725 | if ( not r_dcache_cleanup_req.read() ) // no pending cleanup |
---|
3726 | { |
---|
3727 | vci_rsp_fifo_dcache_get = true; |
---|
3728 | r_dcache_cleanup_req = true; |
---|
3729 | r_dcache_cleanup_line = r_dcache_vci_paddr.read() >> |
---|
3730 | (uint32_log2(m_dcache_words)+2); |
---|
3731 | r_dcache_miss_inval = false; |
---|
3732 | r_dcache_fsm = DCACHE_IDLE; |
---|
3733 | } |
---|
3734 | } |
---|
3735 | } |
---|
3736 | else // No matching coherence request |
---|
3737 | // pop the FIFO and update the cache |
---|
3738 | // update the directory at the last word |
---|
3739 | // send a response to ICACHE FSM |
---|
3740 | // in case of itlb miss |
---|
3741 | { |
---|
3742 | |
---|
3743 | #ifdef INSTRUMENTATION |
---|
3744 | m_cpt_dcache_data_write++; |
---|
3745 | #endif |
---|
3746 | r_dcache.write( r_dcache_miss_way.read(), |
---|
3747 | r_dcache_miss_set.read(), |
---|
3748 | r_dcache_miss_word.read(), |
---|
3749 | r_vci_rsp_fifo_dcache.read()); |
---|
3750 | |
---|
3751 | vci_rsp_fifo_dcache_get = true; |
---|
3752 | r_dcache_miss_word = r_dcache_miss_word.read() + 1; |
---|
3753 | |
---|
3754 | // if last word, update directory, set in_itlb & in_dtlb bits |
---|
3755 | if ( r_dcache_miss_word.read() == (m_dcache_words - 1) ) |
---|
3756 | { |
---|
3757 | |
---|
3758 | #ifdef INSTRUMENTATION |
---|
3759 | m_cpt_dcache_dir_write++; |
---|
3760 | #endif |
---|
3761 | r_dcache.victim_update_tag( r_dcache_vci_paddr.read(), |
---|
3762 | r_dcache_miss_way.read(), |
---|
3763 | r_dcache_miss_set.read() ); |
---|
3764 | |
---|
3765 | if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; |
---|
3766 | else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; |
---|
3767 | else r_dcache_fsm = DCACHE_IDLE; |
---|
3768 | } |
---|
3769 | } |
---|
3770 | |
---|
3771 | #if DEBUG_DCACHE |
---|
3772 | if ( m_debug_dcache_fsm ) |
---|
3773 | { |
---|
3774 | if ( r_dcache_miss_inval.read() ) |
---|
3775 | { |
---|
3776 | if ( r_dcache_miss_word.read() < m_dcache_words-1 ) |
---|
3777 | { |
---|
3778 | std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:" |
---|
3779 | << " pop the FIFO, don't update the cache" << std::endl; |
---|
3780 | } |
---|
3781 | else |
---|
3782 | { |
---|
3783 | std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:" |
---|
3784 | << " last word : send a cleanup request " << std::endl; |
---|
3785 | } |
---|
3786 | } |
---|
3787 | else |
---|
3788 | { |
---|
3789 | std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:" |
---|
3790 | << " address = " << r_dcache_vci_paddr.read() |
---|
3791 | << " / data = " << r_vci_rsp_fifo_dcache.read() |
---|
3792 | << " / way = " << r_dcache_miss_way.read() |
---|
3793 | << " / set = " << r_dcache_miss_set.read() |
---|
3794 | << " / word = " << r_dcache_miss_word.read() << std::endl; |
---|
3795 | } |
---|
3796 | } |
---|
3797 | #endif |
---|
3798 | |
---|
3799 | } // end if rok |
---|
3800 | break; |
---|
3801 | } |
---|
3802 | ///////////////////// |
---|
3803 | case DCACHE_UNC_WAIT: |
---|
3804 | { |
---|
3805 | // external coherence request |
---|
3806 | if ( r_tgt_dcache_req.read() ) |
---|
3807 | { |
---|
3808 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
3809 | r_dcache_fsm_save = r_dcache_fsm; |
---|
3810 | break; |
---|
3811 | } |
---|
3812 | |
---|
3813 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
3814 | { |
---|
3815 | r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; |
---|
3816 | r_mmu_dbvar = dreq.addr; |
---|
3817 | r_vci_rsp_data_error = false; |
---|
3818 | drsp.error = true; |
---|
3819 | drsp.valid = true; |
---|
3820 | r_dcache_fsm = DCACHE_IDLE; |
---|
3821 | break; |
---|
3822 | } |
---|
3823 | else if ( r_vci_rsp_fifo_dcache.rok() ) // data available |
---|
3824 | { |
---|
3825 | vci_rsp_fifo_dcache_get = true; |
---|
3826 | r_dcache_fsm = DCACHE_IDLE; |
---|
3827 | // we acknowledge the processor request if it has not been modified |
---|
3828 | if ( dreq.valid and (dreq.addr == r_dcache_p0_vaddr.read()) ) |
---|
3829 | { |
---|
3830 | drsp.valid = true; |
---|
3831 | drsp.rdata = r_vci_rsp_fifo_dcache.read(); |
---|
3832 | } |
---|
3833 | } |
---|
3834 | break; |
---|
3835 | } |
---|
3836 | //////////////////////////// |
---|
3837 | case DCACHE_WRITE_TLB_DIRTY: // set PTE dirty bit in dtlb |
---|
3838 | { |
---|
3839 | // set dirty bit in dtlb |
---|
3840 | r_dtlb.set_dirty( r_dcache_p2_tlb_way.read(), |
---|
3841 | r_dcache_p2_tlb_set.read() ); |
---|
3842 | |
---|
3843 | // get PTE in dcache |
---|
3844 | uint32_t pte_flags = 0; |
---|
3845 | size_t way; |
---|
3846 | size_t set; |
---|
3847 | size_t word; |
---|
3848 | bool hit = r_dcache.read( r_dcache_p2_pte_paddr.read(), |
---|
3849 | &pte_flags, |
---|
3850 | &way, |
---|
3851 | &set, |
---|
3852 | &word ); |
---|
3853 | #ifdef INSTRUMENTATION |
---|
3854 | m_cpt_dcache_data_read++; |
---|
3855 | m_cpt_dcache_dir_read++; |
---|
3856 | #endif; |
---|
3857 | |
---|
3858 | #if DEBUG_DCACHE |
---|
3859 | if ( m_debug_dcache_fsm ) |
---|
3860 | { |
---|
3861 | std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set PTE dirty bit in dtlb:" |
---|
3862 | << " paddr = " << r_dcache_p2_pte_paddr.read() |
---|
3863 | << " / tlb_way = " << r_dcache_p2_tlb_way.read() |
---|
3864 | << " / tlb_set = " << r_dcache_p2_tlb_set.read() << std::endl; |
---|
3865 | } |
---|
3866 | #endif |
---|
3867 | assert( hit and "error in DCACHE_WRITE_TLB_DIRTY: the PTE should be in dcache" ); |
---|
3868 | |
---|
3869 | r_dcache_p2_pte_way = way; // register pte way in dcache |
---|
3870 | r_dcache_p2_pte_set = set; // register pte set in dcache; |
---|
3871 | r_dcache_p2_pte_word = word; // register pte word in dcache; |
---|
3872 | r_dcache_p2_pte_flags = pte_flags; // register pte value |
---|
3873 | r_dcache_fsm = DCACHE_WRITE_CACHE_DIRTY; |
---|
3874 | break; |
---|
3875 | } |
---|
3876 | ////////////////////////////// |
---|
3877 | case DCACHE_WRITE_CACHE_DIRTY: // set PTE dirty bit in dcache |
---|
3878 | // request SC tranansaction to CMD FSM |
---|
3879 | { |
---|
3880 | // set PTE dirty bit in dcache |
---|
3881 | r_dcache.write( r_dcache_p2_pte_way.read(), |
---|
3882 | r_dcache_p2_pte_set.read(), |
---|
3883 | r_dcache_p2_pte_word.read(), |
---|
3884 | r_dcache_p2_pte_flags.read() | PTE_D_MASK, |
---|
3885 | 0xF ); |
---|
3886 | |
---|
3887 | #ifdef INSTRUMENTATION |
---|
3888 | m_cpt_dcache_data_write++; |
---|
3889 | #endif |
---|
3890 | |
---|
3891 | #if DEBUG_DCACHE |
---|
3892 | if ( m_debug_dcache_fsm ) |
---|
3893 | { |
---|
3894 | std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache:" |
---|
3895 | << " / way = " << r_dcache_p2_pte_way.read() |
---|
3896 | << " / set = " << r_dcache_p2_pte_set.read() |
---|
3897 | << " / word = " << r_dcache_p2_pte_word.read() << std::endl; |
---|
3898 | } |
---|
3899 | #endif |
---|
3900 | // request sc transaction to CMD_FSM |
---|
3901 | r_dcache_vci_sc_req = true; |
---|
3902 | r_dcache_vci_sc_old = r_dcache_p2_pte_flags.read(); |
---|
3903 | r_dcache_vci_sc_new = r_dcache_p2_pte_flags.read() | PTE_D_MASK; |
---|
3904 | r_dcache_fsm = DCACHE_WRITE_SC_WAIT; |
---|
3905 | break; |
---|
3906 | } |
---|
3907 | ////////////////////////// |
---|
3908 | case DCACHE_WRITE_SC_WAIT: // wait completion of SC |
---|
3909 | // if atomic, write completed : return to IDLE state |
---|
3910 | // else, makes an uncacheable read to retry the SC |
---|
3911 | { |
---|
3912 | // external coherence request |
---|
3913 | if ( r_tgt_dcache_req ) |
---|
3914 | { |
---|
3915 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
3916 | r_dcache_fsm_save = r_dcache_fsm; |
---|
3917 | break; |
---|
3918 | } |
---|
3919 | |
---|
3920 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
3921 | { |
---|
3922 | r_mmu_detr = MMU_WRITE_PT2_ILLEGAL_ACCESS; |
---|
3923 | r_mmu_dbvar = r_dcache_p2_vaddr; |
---|
3924 | drsp.valid = true; |
---|
3925 | drsp.error = true; |
---|
3926 | r_dcache_fsm = DCACHE_IDLE; |
---|
3927 | break; |
---|
3928 | } |
---|
3929 | else if ( r_vci_rsp_fifo_dcache.rok() ) // response available |
---|
3930 | { |
---|
3931 | if ( r_vci_rsp_fifo_dcache.read() == 0 ) // atomic |
---|
3932 | { |
---|
3933 | drsp.valid = true; // acknowledge the initial write |
---|
3934 | r_dcache_fsm = DCACHE_IDLE; |
---|
3935 | } |
---|
3936 | else |
---|
3937 | { |
---|
3938 | r_dcache_vci_paddr = r_dcache_p2_pte_paddr; |
---|
3939 | r_dcache_vci_unc_req = true; |
---|
3940 | r_dcache_vci_unc_be = 0xF; |
---|
3941 | r_dcache_fsm = DCACHE_WRITE_UNC_WAIT; |
---|
3942 | } |
---|
3943 | } |
---|
3944 | break; |
---|
3945 | } |
---|
3946 | /////////////////////////// |
---|
3947 | case DCACHE_WRITE_UNC_WAIT: // wait completion of uncacheable read |
---|
3948 | // in case of success we retry a SC request to |
---|
3949 | // set the dirty bit in the PTE |
---|
3950 | { |
---|
3951 | // external coherence request |
---|
3952 | if ( r_tgt_dcache_req ) |
---|
3953 | { |
---|
3954 | r_dcache_fsm = DCACHE_CC_CHECK; |
---|
3955 | r_dcache_fsm_save = r_dcache_fsm; |
---|
3956 | break; |
---|
3957 | } |
---|
3958 | |
---|
3959 | if ( r_vci_rsp_data_error.read() ) // bus error |
---|
3960 | { |
---|
3961 | r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; |
---|
3962 | r_mmu_dbvar = r_dcache_p2_vaddr; |
---|
3963 | drsp.valid = true; |
---|
3964 | drsp.error = true; |
---|
3965 | r_dcache_fsm = DCACHE_IDLE; |
---|
3966 | break; |
---|
3967 | } |
---|
3968 | if ( r_vci_rsp_fifo_dcache.rok() ) // PTE available |
---|
3969 | { |
---|
3970 | r_dcache_vci_sc_req = true; |
---|
3971 | r_dcache_vci_sc_old = r_vci_rsp_fifo_dcache.read(); |
---|
3972 | r_dcache_vci_sc_new = r_vci_rsp_fifo_dcache.read() | PTE_D_MASK; |
---|
3973 | r_dcache_fsm = DCACHE_WRITE_SC_WAIT; |
---|
3974 | } |
---|
3975 | break; |
---|
3976 | } |
---|
3977 | ///////////////////// |
---|
3978 | case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM |
---|
3979 | // handling coherence requests. |
---|
3980 | // If there is a matching pending miss on the modified cache |
---|
3981 | // line this is signaled in the r_dcache_miss inval flip-flop. |
---|
3982 | // If the updated (or invalidated) cache line has copies in TLBs |
---|
3983 | // these TLB copies are invalidated. |
---|
3984 | // The return state is defined in r_dcache_fsm_save |
---|
3985 | { |
---|
3986 | paddr_t paddr = r_tgt_paddr.read(); |
---|
3987 | paddr_t mask = ~((m_dcache_words<<2)-1); |
---|
3988 | |
---|
3989 | |
---|
3990 | if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and |
---|
3991 | ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss |
---|
3992 | { |
---|
3993 | r_dcache_miss_inval = true; // signaling the match |
---|
3994 | r_tgt_dcache_req = false; // coherence request completed |
---|
3995 | r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update |
---|
3996 | r_dcache_fsm = r_dcache_fsm_save; |
---|
3997 | |
---|
3998 | #if DEBUG_DCACHE |
---|
3999 | if ( m_debug_dcache_fsm ) |
---|
4000 | { |
---|
4001 | std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:" |
---|
4002 | << " address = " << std::hex << paddr << std::endl; |
---|
4003 | } |
---|
4004 | #endif |
---|
4005 | |
---|
4006 | } |
---|
4007 | else // no match |
---|
4008 | { |
---|
4009 | uint32_t rdata; |
---|
4010 | size_t way; |
---|
4011 | size_t set; |
---|
4012 | size_t word; |
---|
4013 | |
---|
4014 | bool hit = r_dcache.read(paddr, |
---|
4015 | &rdata, // unused |
---|
4016 | &way, |
---|
4017 | &set, |
---|
4018 | &word); // unused |
---|
4019 | #ifdef INSTRUMENTATION |
---|
4020 | m_cpt_dcache_data_read++; |
---|
4021 | m_cpt_dcache_dir_read++; |
---|
4022 | #endif |
---|
4023 | r_dcache_cc_way = way; |
---|
4024 | r_dcache_cc_set = set; |
---|
4025 | |
---|
4026 | if ( hit and r_tgt_update.read() ) // hit update |
---|
4027 | { |
---|
4028 | r_dcache_fsm = DCACHE_CC_UPDT; |
---|
4029 | r_dcache_cc_word = r_tgt_word_min.read(); |
---|
4030 | } |
---|
4031 | else if ( hit and not r_tgt_update.read() ) // hit inval |
---|
4032 | { |
---|
4033 | r_dcache_fsm = DCACHE_CC_INVAL; |
---|
4034 | } |
---|
4035 | else // miss can happen |
---|
4036 | { |
---|
4037 | r_tgt_dcache_req = false; |
---|
4038 | r_tgt_dcache_rsp = r_tgt_update.read(); |
---|
4039 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
4040 | } |
---|
4041 | |
---|
4042 | #if DEBUG_DCACHE |
---|
4043 | if ( m_debug_dcache_fsm ) |
---|
4044 | { |
---|
4045 | |
---|
4046 | std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :" |
---|
4047 | << " address = " << std::hex << paddr << std::dec; |
---|
4048 | if ( hit ) |
---|
4049 | { |
---|
4050 | std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl; |
---|
4051 | } |
---|
4052 | else |
---|
4053 | { |
---|
4054 | std::cout << " / MISS" << std::endl; |
---|
4055 | } |
---|
4056 | } |
---|
4057 | #endif |
---|
4058 | |
---|
4059 | } |
---|
4060 | break; |
---|
4061 | } |
---|
4062 | ///////////////////// |
---|
4063 | case DCACHE_CC_INVAL: // invalidate one cache line |
---|
4064 | // and test possible copies in TLBs |
---|
4065 | { |
---|
4066 | paddr_t nline; |
---|
4067 | size_t way = r_dcache_cc_way.read(); |
---|
4068 | size_t set = r_dcache_cc_set.read(); |
---|
4069 | bool inval_tlb = false; |
---|
4070 | |
---|
4071 | r_dcache.inval( way, |
---|
4072 | set, |
---|
4073 | &nline ); |
---|
4074 | |
---|
4075 | // possible itlb & dtlb invalidate requests |
---|
4076 | r_dcache_tlb_inval_line = nline; |
---|
4077 | |
---|
4078 | if ( (r_mmu_mode.read() & DATA_TLB_MASK) and |
---|
4079 | r_dcache_in_dtlb[way*m_dcache_sets+set] ) |
---|
4080 | { |
---|
4081 | r_dcache_dtlb_inval_req = true; |
---|
4082 | r_dcache_in_dtlb[way*m_dcache_sets+set] = false; |
---|
4083 | inval_tlb = true; |
---|
4084 | } |
---|
4085 | if ( (r_mmu_mode.read() & INS_TLB_MASK) and |
---|
4086 | r_dcache_in_itlb[m_dcache_sets*way+set] ) |
---|
4087 | { |
---|
4088 | r_dcache_itlb_inval_req = true; |
---|
4089 | r_dcache_in_itlb[way*m_dcache_sets+set] = false; |
---|
4090 | inval_tlb = true; |
---|
4091 | } |
---|
4092 | |
---|
4093 | // no valid response until itlb & dtlb invalidated |
---|
4094 | if (inval_tlb ) |
---|
4095 | { |
---|
4096 | r_dcache_fsm = DCACHE_CC_WAIT; |
---|
4097 | } |
---|
4098 | else |
---|
4099 | { |
---|
4100 | r_tgt_dcache_rsp = true; |
---|
4101 | r_tgt_dcache_req = false; |
---|
4102 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
4103 | } |
---|
4104 | |
---|
4105 | #if DEBUG_DCACHE |
---|
4106 | if ( m_debug_dcache_fsm ) |
---|
4107 | { |
---|
4108 | std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line :" << std::dec |
---|
4109 | << " way = " << way |
---|
4110 | << " / set = " << set << std::endl; |
---|
4111 | } |
---|
4112 | #endif |
---|
4113 | |
---|
4114 | break; |
---|
4115 | } |
---|
4116 | /////////////////// |
---|
4117 | case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max) |
---|
4118 | // and test possible copies in TLBs |
---|
4119 | { |
---|
4120 | size_t word = r_dcache_cc_word.read(); |
---|
4121 | size_t way = r_dcache_cc_way.read(); |
---|
4122 | size_t set = r_dcache_cc_set.read(); |
---|
4123 | |
---|
4124 | r_dcache.write( way, |
---|
4125 | set, |
---|
4126 | word, |
---|
4127 | r_tgt_buf[word], |
---|
4128 | r_tgt_be[word] ); |
---|
4129 | #ifdef INSTRUMENTATION |
---|
4130 | m_cpt_dcache_data_write++; |
---|
4131 | #endif |
---|
4132 | r_dcache_cc_word = word + 1; |
---|
4133 | |
---|
4134 | if ( word == r_tgt_word_max.read() ) // last word |
---|
4135 | { |
---|
4136 | // invalidate copies in TLBs |
---|
4137 | if ( (r_mmu_mode.read() & DATA_TLB_MASK) and |
---|
4138 | ( r_dcache_in_itlb[way*m_dcache_sets+set] or |
---|
4139 | r_dcache_in_dtlb[m_dcache_sets*way+set] ) ) |
---|
4140 | { |
---|
4141 | r_dcache_tlb_inval_line = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2); |
---|
4142 | r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set]; |
---|
4143 | r_dcache_in_itlb[way*m_dcache_sets+set] = false; |
---|
4144 | r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; |
---|
4145 | r_dcache_in_dtlb[way*m_dcache_sets+set] = false; |
---|
4146 | r_dcache_fsm = DCACHE_CC_WAIT; |
---|
4147 | } |
---|
4148 | else |
---|
4149 | { |
---|
4150 | r_tgt_dcache_rsp = true; |
---|
4151 | r_tgt_dcache_req = false; |
---|
4152 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
4153 | } |
---|
4154 | } |
---|
4155 | |
---|
4156 | #if DEBUG_DCACHE |
---|
4157 | if ( m_debug_dcache_fsm ) |
---|
4158 | { |
---|
4159 | std::cout << " <PROC.DCACHE_CC_UPDT> Update one word :" << std::dec |
---|
4160 | << " way = " << way |
---|
4161 | << " / set = " << set |
---|
4162 | << " / word = " << word |
---|
4163 | << " / value = " << std::hex << r_tgt_buf[word] << std::endl; |
---|
4164 | } |
---|
4165 | #endif |
---|
4166 | |
---|
4167 | break; |
---|
4168 | } |
---|
4169 | //////////////////// |
---|
4170 | case DCACHE_CC_WAIT: // wait completion of TLB invalidate |
---|
4171 | { |
---|
4172 | if ( not r_dcache_itlb_inval_req.read() and not r_dcache_dtlb_inval_req.read() ) |
---|
4173 | { |
---|
4174 | r_tgt_dcache_rsp = true; |
---|
4175 | r_tgt_dcache_req = false; |
---|
4176 | r_dcache_fsm = r_dcache_fsm_save.read(); |
---|
4177 | } |
---|
4178 | } |
---|
4179 | } // end switch r_dcache_fsm |
---|
4180 | |
---|
4181 | |
---|
4182 | //////////////////// save DREQ and DRSP fields for print_trace() //////////////// |
---|
4183 | m_dreq_valid = dreq.valid; |
---|
4184 | m_dreq_addr = dreq.addr; |
---|
4185 | m_dreq_mode = dreq.mode; |
---|
4186 | m_dreq_type = dreq.type; |
---|
4187 | m_dreq_wdata = dreq.wdata; |
---|
4188 | m_dreq_be = dreq.be; |
---|
4189 | |
---|
4190 | m_drsp_valid = drsp.valid; |
---|
4191 | m_drsp_rdata = drsp.rdata; |
---|
4192 | m_drsp_error = drsp.error; |
---|
4193 | |
---|
4194 | ///////////////// wbuf update ////////////////////////////////////////////////////// |
---|
4195 | r_wbuf.update(); |
---|
4196 | |
---|
4197 | //////////////////////////////////////////////////////////////////////////////////// |
---|
4198 | // INVAL DTLB FSM |
---|
4199 | // This FSM works in parallel with the DCACHE FSM. |
---|
4200 | // When the r_dcache_dtlb_inval_req flip-flop is activated by the DCACHE FSM |
---|
4201 | // it scans sequencially all entries in the DTLB, and invalidates the |
---|
4202 | // entries matching the evicted line. |
---|
4203 | // It signals the completion of invalidation by reseting r_dcache_itlb_inval_req. |
---|
4204 | //////////////////////////////////////////////////////////////////////////////////// |
---|
4205 | |
---|
4206 | switch(r_inval_dtlb_fsm) |
---|
4207 | { |
---|
4208 | ///////////////////// |
---|
4209 | case INVAL_DTLB_IDLE: |
---|
4210 | { |
---|
4211 | if ( r_dcache_dtlb_inval_req.read() ) |
---|
4212 | { |
---|
4213 | r_dtlb.reset_bypass(r_dcache_tlb_inval_line.read()); |
---|
4214 | r_inval_dtlb_count = 0; |
---|
4215 | r_inval_dtlb_fsm = INVAL_DTLB_SCAN; |
---|
4216 | |
---|
4217 | #if DEBUG_INVAL_DTLB |
---|
4218 | if ( m_debug_inval_dtlb_fsm ) |
---|
4219 | { |
---|
4220 | std::cout << " <PROC.INVAL_DTLB_IDLE> Invalidate request for line " |
---|
4221 | << std::hex << r_dcache_tlb_inval_line.read() << std::endl; |
---|
4222 | r_dtlb.print(); |
---|
4223 | } |
---|
4224 | #endif |
---|
4225 | } |
---|
4226 | break; |
---|
4227 | } |
---|
4228 | ///////////////////// |
---|
4229 | case INVAL_DTLB_SCAN: |
---|
4230 | { |
---|
4231 | paddr_t line = r_dcache_tlb_inval_line.read(); // nline |
---|
4232 | size_t way = r_inval_dtlb_count.read()/m_itlb_sets; // way |
---|
4233 | size_t set = r_inval_dtlb_count.read()%m_itlb_sets; // set |
---|
4234 | |
---|
4235 | bool ok = r_dtlb.inval( line, |
---|
4236 | way, |
---|
4237 | set ); |
---|
4238 | |
---|
4239 | #if DEBUG_INVAL_DTLB |
---|
4240 | if ( m_debug_inval_dtlb_fsm ) |
---|
4241 | { |
---|
4242 | std::cout << " <PROC.INVAL_DTLB_SCAN>" << std::hex |
---|
4243 | << " line = " << line << std::dec |
---|
4244 | << " / set = " << set |
---|
4245 | << " / way = " << way; |
---|
4246 | if ( ok ) std::cout << " / HIT" << std::endl; |
---|
4247 | else std::cout << " / MISS" << std::endl; |
---|
4248 | } |
---|
4249 | #endif |
---|
4250 | |
---|
4251 | r_inval_dtlb_count = r_inval_dtlb_count.read() + 1; |
---|
4252 | if ( r_inval_dtlb_count.read() == (m_dtlb_sets*m_dtlb_ways - 1) ) |
---|
4253 | { |
---|
4254 | r_inval_dtlb_fsm = INVAL_DTLB_IDLE; |
---|
4255 | r_dcache_dtlb_inval_req = false; |
---|
4256 | } |
---|
4257 | break; |
---|
4258 | } |
---|
4259 | } // end switch r_inval_dtlb_fsm |
---|
4260 | |
---|
4261 | /////////// test processor frozen ///////////////////////////////////////////// |
---|
4262 | // The simulation exit if the number of consecutive frozen cycles |
---|
4263 | // is larger than the m_max_frozen_cycles (constructor parameter) |
---|
4264 | if ( (ireq.valid and not irsp.valid) or (dreq.valid and not drsp.valid) ) |
---|
4265 | { |
---|
4266 | m_cpt_frz_cycles++; // used for instrumentation |
---|
4267 | m_cpt_stop_simulation++; // used for debug |
---|
4268 | if ( m_cpt_stop_simulation > m_max_frozen_cycles ) |
---|
4269 | { |
---|
4270 | std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl |
---|
4271 | << " stop at cycle " << m_cpt_total_cycles << std::endl |
---|
4272 | << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles |
---|
4273 | << std::endl; |
---|
4274 | exit(1); |
---|
4275 | } |
---|
4276 | } |
---|
4277 | else |
---|
4278 | { |
---|
4279 | m_cpt_stop_simulation = 0; |
---|
4280 | } |
---|
4281 | |
---|
4282 | /////////// execute one iss cycle ///////////////////////////////// |
---|
4283 | { |
---|
4284 | uint32_t it = 0; |
---|
4285 | for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i); |
---|
4286 | r_iss.executeNCycles(1, irsp, drsp, it); |
---|
4287 | } |
---|
4288 | |
---|
4289 | //////////////////////////////////////////////////////////////////////////// |
---|
4290 | // The VCI_CMD FSM controls the following ressources: |
---|
4291 | // - r_vci_cmd_fsm |
---|
4292 | // - r_vci_cmd_min |
---|
4293 | // - r_vci_cmd_max |
---|
4294 | // - r_vci_cmd_cpt |
---|
4295 | // - r_vci_cmd_imiss_prio |
---|
4296 | // - wbuf (reset) |
---|
4297 | // - r_icache_miss_req (reset) |
---|
4298 | // - r_icache_unc_req (reset) |
---|
4299 | // - r_dcache_vci_miss_req (reset) |
---|
4300 | // - r_dcache_vci_unc_req (reset) |
---|
4301 | // - r_dcache_vci_sc_req (reset) |
---|
4302 | // |
---|
4303 | // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM. |
---|
4304 | // There is 6 request types, with the following priorities : |
---|
4305 | // 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer |
---|
4306 | // 2 - Data Read Uncachable : r_dcache_vci_unc_req |
---|
4307 | // 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer |
---|
4308 | // 4 - Instruction Uncachable : r_icache_unc_req |
---|
4309 | // 5 - Data Write : r_wbuf.rok() |
---|
4310 | // 6 - Data Store Conditionnal: r_dcache_vci_sc_req |
---|
4311 | // |
---|
4312 | // As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM |
---|
4313 | // and the VCI_RSP_FSM are fully desynchronized. |
---|
4314 | // |
---|
4315 | // VCI formats: |
---|
4316 | // According to the VCI advanced specification, all read requests packets |
---|
4317 | // (data Uncached, Miss data, instruction Uncached, Miss instruction) |
---|
4318 | // are one word packets. |
---|
4319 | // For write burst packets, all words are in the same cache line, |
---|
4320 | // and addresses must be contiguous (the BE field is 0 in case of "holes"). |
---|
4321 | // The sc command packet implements actually a compare-and-swap mechanism |
---|
4322 | // and the packet contains two flits. |
---|
4323 | //////////////////////////////////////////////////////////////////////////////////// |
---|
4324 | |
---|
4325 | switch ( r_vci_cmd_fsm.read() ) |
---|
4326 | { |
---|
4327 | ////////////// |
---|
4328 | case CMD_IDLE: |
---|
4329 | { |
---|
4330 | // r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access |
---|
4331 | // to check a possible pending write on the same cache line. |
---|
4332 | // As there is only one possible access per cycle to write buffer, we implement |
---|
4333 | // a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop. |
---|
4334 | |
---|
4335 | size_t wbuf_min; |
---|
4336 | size_t wbuf_max; |
---|
4337 | |
---|
4338 | bool dcache_miss_req = r_dcache_vci_miss_req.read() |
---|
4339 | and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); |
---|
4340 | bool icache_miss_req = r_icache_miss_req.read() |
---|
4341 | and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() ); |
---|
4342 | |
---|
4343 | // 1 - Data Read Miss |
---|
4344 | if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) |
---|
4345 | { |
---|
4346 | r_vci_cmd_fsm = CMD_DATA_MISS; |
---|
4347 | r_dcache_vci_miss_req = false; |
---|
4348 | r_vci_cmd_imiss_prio = true; |
---|
4349 | // m_cpt_dmiss_transaction++; |
---|
4350 | } |
---|
4351 | // 2 - Data Read Uncachable |
---|
4352 | else if ( r_dcache_vci_unc_req.read() ) |
---|
4353 | { |
---|
4354 | r_vci_cmd_fsm = CMD_DATA_UNC; |
---|
4355 | r_dcache_vci_unc_req = false; |
---|
4356 | // m_cpt_dunc_transaction++; |
---|
4357 | } |
---|
4358 | // 3 - Instruction Miss |
---|
4359 | else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) ) |
---|
4360 | { |
---|
4361 | r_vci_cmd_fsm = CMD_INS_MISS; |
---|
4362 | r_icache_miss_req = false; |
---|
4363 | r_vci_cmd_imiss_prio = false; |
---|
4364 | // m_cpt_imiss_transaction++; |
---|
4365 | } |
---|
4366 | // 4 - Instruction Uncachable |
---|
4367 | else if ( r_icache_unc_req.read() ) |
---|
4368 | { |
---|
4369 | r_vci_cmd_fsm = CMD_INS_UNC; |
---|
4370 | r_icache_unc_req = false; |
---|
4371 | // m_cpt_iunc_transaction++; |
---|
4372 | } |
---|
4373 | // 5 - Data Write |
---|
4374 | else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) ) |
---|
4375 | { |
---|
4376 | r_vci_cmd_fsm = CMD_DATA_WRITE; |
---|
4377 | r_vci_cmd_cpt = wbuf_min; |
---|
4378 | r_vci_cmd_min = wbuf_min; |
---|
4379 | r_vci_cmd_max = wbuf_max; |
---|
4380 | // m_cpt_write_transaction++; |
---|
4381 | // m_length_write_transaction += (wbuf_max-wbuf_min+1); |
---|
4382 | } |
---|
4383 | // 6 - Data Store Conditionnal |
---|
4384 | else if ( r_dcache_vci_sc_req.read() ) |
---|
4385 | { |
---|
4386 | r_vci_cmd_fsm = CMD_DATA_SC; |
---|
4387 | r_dcache_vci_sc_req = false; |
---|
4388 | r_vci_cmd_cpt = 0; |
---|
4389 | // m_cpt_sc_transaction++; |
---|
4390 | } |
---|
4391 | break; |
---|
4392 | } |
---|
4393 | //////////////////// |
---|
4394 | case CMD_DATA_WRITE: |
---|
4395 | { |
---|
4396 | if ( p_vci_ini_d.cmdack.read() ) |
---|
4397 | { |
---|
4398 | // m_conso_wbuf_read++; |
---|
4399 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
4400 | if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent |
---|
4401 | { |
---|
4402 | r_vci_cmd_fsm = CMD_IDLE ; |
---|
4403 | r_wbuf.sent() ; |
---|
4404 | } |
---|
4405 | } |
---|
4406 | break; |
---|
4407 | } |
---|
4408 | ///////////////// |
---|
4409 | case CMD_DATA_SC: |
---|
4410 | { |
---|
4411 | // The SC VCI command contains two flits |
---|
4412 | if ( p_vci_ini_d.cmdack.read() ) |
---|
4413 | { |
---|
4414 | r_vci_cmd_cpt = r_vci_cmd_cpt + 1; |
---|
4415 | if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ; |
---|
4416 | } |
---|
4417 | break; |
---|
4418 | } |
---|
4419 | ////////////////// |
---|
4420 | case CMD_INS_MISS: |
---|
4421 | case CMD_INS_UNC: |
---|
4422 | case CMD_DATA_MISS: |
---|
4423 | case CMD_DATA_UNC: |
---|
4424 | { |
---|
4425 | // all read VCI commands contain one single flit |
---|
4426 | if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE; |
---|
4427 | break; |
---|
4428 | } |
---|
4429 | |
---|
4430 | } // end switch r_vci_cmd_fsm |
---|
4431 | |
---|
4432 | ////////////////////////////////////////////////////////////////////////// |
---|
4433 | // The VCI_RSP FSM controls the following ressources: |
---|
4434 | // - r_vci_rsp_fsm: |
---|
4435 | // - r_vci_rsp_fifo_icache (push) |
---|
4436 | // - r_vci_rsp_fifo_dcache (push) |
---|
4437 | // - r_vci_rsp_data_error (set) |
---|
4438 | // - r_vci_rsp_ins_error (set) |
---|
4439 | // - r_vci_rsp_cpt |
---|
4440 | // |
---|
4441 | // As the VCI_RSP and VCI_CMD are fully desynchronized to support several |
---|
4442 | // simultaneous VCI transactions, this FSM uses the VCI TRDID field |
---|
4443 | // to identify the transactions. |
---|
4444 | // |
---|
4445 | // VCI vormat: |
---|
4446 | // This component checks the response packet length and accepts only |
---|
4447 | // single word packets for write response packets. |
---|
4448 | // |
---|
4449 | // Error handling: |
---|
4450 | // This FSM analyzes the VCI error code and signals directly the Write Bus Error. |
---|
4451 | // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error |
---|
4452 | // flip_flop and the error is signaled by the DCACHE FSM. |
---|
4453 | // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error |
---|
4454 | // flip_flop and the error is signaled by the ICACHE FSM. |
---|
4455 | // In case of Cleanup Error, the simulation stops with an error message... |
---|
4456 | ////////////////////////////////////////////////////////////////////////// |
---|
4457 | |
---|
4458 | switch ( r_vci_rsp_fsm.read() ) |
---|
4459 | { |
---|
4460 | ////////////// |
---|
4461 | case RSP_IDLE: |
---|
4462 | { |
---|
4463 | if ( p_vci_ini_d.rspval.read() ) |
---|
4464 | { |
---|
4465 | r_vci_rsp_cpt = 0; |
---|
4466 | |
---|
4467 | if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction |
---|
4468 | { |
---|
4469 | r_vci_rsp_fsm = RSP_DATA_WRITE; |
---|
4470 | } |
---|
4471 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS ) |
---|
4472 | { |
---|
4473 | r_vci_rsp_fsm = RSP_INS_MISS; |
---|
4474 | } |
---|
4475 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC ) |
---|
4476 | { |
---|
4477 | r_vci_rsp_fsm = RSP_INS_UNC; |
---|
4478 | } |
---|
4479 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS ) |
---|
4480 | { |
---|
4481 | r_vci_rsp_fsm = RSP_DATA_MISS; |
---|
4482 | } |
---|
4483 | else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC ) |
---|
4484 | { |
---|
4485 | r_vci_rsp_fsm = RSP_DATA_UNC; |
---|
4486 | } |
---|
4487 | else |
---|
4488 | { |
---|
4489 | assert(false and "Unexpected VCI response"); |
---|
4490 | } |
---|
4491 | } |
---|
4492 | break; |
---|
4493 | } |
---|
4494 | ////////////////// |
---|
4495 | case RSP_INS_MISS: |
---|
4496 | { |
---|
4497 | if ( p_vci_ini_d.rspval.read() ) |
---|
4498 | { |
---|
4499 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
4500 | { |
---|
4501 | r_vci_rsp_ins_error = true; |
---|
4502 | if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; |
---|
4503 | } |
---|
4504 | else // no error reported |
---|
4505 | { |
---|
4506 | if ( r_vci_rsp_fifo_icache.wok() ) |
---|
4507 | { |
---|
4508 | assert( (r_vci_rsp_cpt.read() < m_icache_words) and |
---|
4509 | "The VCI response packet for instruction miss is too long" ); |
---|
4510 | |
---|
4511 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
4512 | vci_rsp_fifo_icache_put = true, |
---|
4513 | vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); |
---|
4514 | if ( p_vci_ini_d.reop.read() ) |
---|
4515 | { |
---|
4516 | assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and |
---|
4517 | "The VCI response packet for instruction miss is too short"); |
---|
4518 | |
---|
4519 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4520 | } |
---|
4521 | } |
---|
4522 | } |
---|
4523 | } |
---|
4524 | break; |
---|
4525 | } |
---|
4526 | ///////////////// |
---|
4527 | case RSP_INS_UNC: |
---|
4528 | { |
---|
4529 | if (p_vci_ini_d.rspval.read() ) |
---|
4530 | { |
---|
4531 | assert( p_vci_ini_d.reop.read() and |
---|
4532 | "illegal VCI response packet for uncachable instruction"); |
---|
4533 | |
---|
4534 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
4535 | { |
---|
4536 | r_vci_rsp_ins_error = true; |
---|
4537 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4538 | } |
---|
4539 | else // no error reported |
---|
4540 | { |
---|
4541 | if ( r_vci_rsp_fifo_icache.wok()) |
---|
4542 | { |
---|
4543 | vci_rsp_fifo_icache_put = true; |
---|
4544 | vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); |
---|
4545 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4546 | } |
---|
4547 | } |
---|
4548 | } |
---|
4549 | break; |
---|
4550 | } |
---|
4551 | /////////////////// |
---|
4552 | case RSP_DATA_MISS: |
---|
4553 | { |
---|
4554 | if ( p_vci_ini_d.rspval.read() ) |
---|
4555 | { |
---|
4556 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
4557 | { |
---|
4558 | r_vci_rsp_data_error = true; |
---|
4559 | if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; |
---|
4560 | } |
---|
4561 | else // no error reported |
---|
4562 | { |
---|
4563 | if ( r_vci_rsp_fifo_dcache.wok() ) |
---|
4564 | { |
---|
4565 | assert( (r_vci_rsp_cpt.read() < m_dcache_words) and |
---|
4566 | "The VCI response packet for data miss is too long"); |
---|
4567 | |
---|
4568 | r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; |
---|
4569 | vci_rsp_fifo_dcache_put = true, |
---|
4570 | vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); |
---|
4571 | if ( p_vci_ini_d.reop.read() ) |
---|
4572 | { |
---|
4573 | assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and |
---|
4574 | "The VCI response packet for data miss is too short"); |
---|
4575 | |
---|
4576 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4577 | } |
---|
4578 | } |
---|
4579 | } |
---|
4580 | } |
---|
4581 | break; |
---|
4582 | } |
---|
4583 | ////////////////// |
---|
4584 | case RSP_DATA_UNC: |
---|
4585 | { |
---|
4586 | if (p_vci_ini_d.rspval.read() ) |
---|
4587 | { |
---|
4588 | assert( p_vci_ini_d.reop.read() and |
---|
4589 | "illegal VCI response packet for uncachable read data"); |
---|
4590 | |
---|
4591 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported |
---|
4592 | { |
---|
4593 | r_vci_rsp_data_error = true; |
---|
4594 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4595 | } |
---|
4596 | else // no error reported |
---|
4597 | { |
---|
4598 | if ( r_vci_rsp_fifo_dcache.wok()) |
---|
4599 | { |
---|
4600 | vci_rsp_fifo_dcache_put = true; |
---|
4601 | vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); |
---|
4602 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4603 | } |
---|
4604 | } |
---|
4605 | } |
---|
4606 | break; |
---|
4607 | } |
---|
4608 | //////////////////// |
---|
4609 | case RSP_DATA_WRITE: |
---|
4610 | { |
---|
4611 | if (p_vci_ini_d.rspval.read()) |
---|
4612 | { |
---|
4613 | assert( p_vci_ini_d.reop.read() and |
---|
4614 | "a VCI response packet must contain one flit for a write transaction"); |
---|
4615 | |
---|
4616 | r_vci_rsp_fsm = RSP_IDLE; |
---|
4617 | uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1)); |
---|
4618 | bool cacheable = r_wbuf.completed(wbuf_index); |
---|
4619 | if ( not cacheable ) r_dcache_pending_unc_write = false; |
---|
4620 | if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); |
---|
4621 | } |
---|
4622 | break; |
---|
4623 | } |
---|
4624 | } // end switch r_vci_rsp_fsm |
---|
4625 | |
---|
4626 | //////////////////////////////////////////////////////////////////////////////// |
---|
4627 | // The CLEANUP FSM send the cleanup commands on the coherence network, |
---|
4628 | // and supports simultaneous cleanup transactions, but two simultaneous |
---|
4629 | // transactions mut address different cache lines. |
---|
4630 | // Therefore, the line number is registered in an associative |
---|
4631 | // registration buffer (Content Adressable Memory) by the CLEANUP FSM, |
---|
4632 | // and the corresponding slot (identified by the VCI TRDID field) is cleared |
---|
4633 | // when the cleanup transaction response is received. |
---|
4634 | // It handles cleanup requests from both the DCACHE FSM & ICACHE FSM |
---|
4635 | // with a round robin priority, and can support up to 4 simultaneous |
---|
4636 | // cleanup transactions (4 slots in the registration buffer). |
---|
4637 | // The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset |
---|
4638 | // when the command has been sent. |
---|
4639 | // The VCI TRDID field is used to distinguish data/instruction cleanups: |
---|
4640 | // - if data cleanup : TRDID = 2*index + 0 |
---|
4641 | // - if instruction cleanup : TRDID = 2*index + 1 |
---|
4642 | //////////////////////////////////////////////////////////////////////////// |
---|
4643 | |
---|
4644 | switch ( r_cleanup_fsm.read() ) |
---|
4645 | { |
---|
4646 | /////////////////////// |
---|
4647 | case CLEANUP_DATA_IDLE: // dcache has highest priority |
---|
4648 | { |
---|
4649 | size_t index = 0; |
---|
4650 | bool ok; |
---|
4651 | if ( r_dcache_cleanup_req.read() ) // dcache request |
---|
4652 | { |
---|
4653 | ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(), |
---|
4654 | &index ); |
---|
4655 | if ( ok ) // successful registration |
---|
4656 | { |
---|
4657 | r_cleanup_fsm = CLEANUP_DATA_GO; |
---|
4658 | r_cleanup_trdid = index<<1; |
---|
4659 | } |
---|
4660 | } |
---|
4661 | else if ( r_icache_cleanup_req.read() ) // icache request |
---|
4662 | { |
---|
4663 | ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(), |
---|
4664 | &index ); |
---|
4665 | if ( ok ) // successful registration |
---|
4666 | { |
---|
4667 | r_cleanup_fsm = CLEANUP_INS_GO; |
---|
4668 | r_cleanup_trdid = (index<<1) + 1; |
---|
4669 | } |
---|
4670 | } |
---|
4671 | break; |
---|
4672 | } |
---|
4673 | ////////////////////// |
---|
4674 | case CLEANUP_INS_IDLE: // icache has highest priority |
---|
4675 | { |
---|
4676 | size_t index = 0; |
---|
4677 | bool ok; |
---|
4678 | if ( r_icache_cleanup_req.read() ) // icache request |
---|
4679 | { |
---|
4680 | ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(), |
---|
4681 | &index ); |
---|
4682 | if ( ok ) // successful registration |
---|
4683 | { |
---|
4684 | r_cleanup_fsm = CLEANUP_INS_GO; |
---|
4685 | r_cleanup_trdid = (index<<1) + 1; |
---|
4686 | } |
---|
4687 | } |
---|
4688 | else if ( r_dcache_cleanup_req.read() ) // dcache request |
---|
4689 | { |
---|
4690 | ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(), |
---|
4691 | &index ); |
---|
4692 | if ( ok ) // successful registration |
---|
4693 | { |
---|
4694 | r_cleanup_fsm = CLEANUP_DATA_GO; |
---|
4695 | r_cleanup_trdid = index<<1; |
---|
4696 | } |
---|
4697 | } |
---|
4698 | break; |
---|
4699 | } |
---|
4700 | ///////////////////// |
---|
4701 | case CLEANUP_DATA_GO: |
---|
4702 | { |
---|
4703 | if ( p_vci_ini_c.cmdack.read() ) |
---|
4704 | { |
---|
4705 | r_dcache_cleanup_req = false; |
---|
4706 | r_cleanup_fsm = CLEANUP_INS_IDLE; |
---|
4707 | |
---|
4708 | #if DEBUG_CLEANUP |
---|
4709 | if ( m_debug_cleanup_fsm ) |
---|
4710 | { |
---|
4711 | std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex |
---|
4712 | << " address = " << (r_dcache_cleanup_line.read()*m_dcache_words*4) |
---|
4713 | << " / trdid = " << r_cleanup_trdid.read() << std::endl; |
---|
4714 | } |
---|
4715 | #endif |
---|
4716 | } |
---|
4717 | } |
---|
4718 | //////////////////////// |
---|
4719 | case CLEANUP_INS_GO: |
---|
4720 | { |
---|
4721 | if ( p_vci_ini_c.cmdack.read() ) |
---|
4722 | { |
---|
4723 | r_icache_cleanup_req = false; |
---|
4724 | r_cleanup_fsm = CLEANUP_DATA_IDLE; |
---|
4725 | |
---|
4726 | #if DEBUG_CLEANUP |
---|
4727 | if ( m_debug_cleanup_fsm ) |
---|
4728 | { |
---|
4729 | std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex |
---|
4730 | << " address = " << (r_icache_cleanup_line.read()*m_icache_words*4) |
---|
4731 | << " / trdid = " << r_cleanup_trdid.read() << std::endl; |
---|
4732 | } |
---|
4733 | #endif |
---|
4734 | } |
---|
4735 | } |
---|
4736 | } // end switch CLEANUP FSM |
---|
4737 | |
---|
4738 | //////////////// Handling cleanup responses ////////////////// |
---|
4739 | if ( p_vci_ini_c.rspval.read() ) // valid response |
---|
4740 | { |
---|
4741 | r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1); |
---|
4742 | } |
---|
4743 | |
---|
4744 | ///////////////// Response FIFOs update ////////////////////// |
---|
4745 | r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, |
---|
4746 | vci_rsp_fifo_icache_put, |
---|
4747 | vci_rsp_fifo_icache_data); |
---|
4748 | |
---|
4749 | r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get, |
---|
4750 | vci_rsp_fifo_dcache_put, |
---|
4751 | vci_rsp_fifo_dcache_data); |
---|
4752 | } // end transition() |
---|
4753 | |
---|
4754 | /////////////////////// |
---|
4755 | tmpl(void)::genMoore() |
---|
4756 | /////////////////////// |
---|
4757 | { |
---|
4758 | //////////////////////////////////////////////////////////////// |
---|
4759 | // VCI initiator command on the coherence network (cleanup) |
---|
4760 | // it depends on the CLEANUP FSM state |
---|
4761 | |
---|
4762 | paddr_t address; |
---|
4763 | |
---|
4764 | if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO ) |
---|
4765 | address = r_dcache_cleanup_line.read()*m_dcache_words*4; |
---|
4766 | else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO ) |
---|
4767 | address = r_icache_cleanup_line.read()*m_icache_words*4; |
---|
4768 | else |
---|
4769 | address = 0; |
---|
4770 | |
---|
4771 | p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or |
---|
4772 | (r_cleanup_fsm.read() == CLEANUP_INS_GO) ); |
---|
4773 | p_vci_ini_c.address = address; |
---|
4774 | p_vci_ini_c.wdata = 0; |
---|
4775 | p_vci_ini_c.be = 0xF; |
---|
4776 | p_vci_ini_c.plen = 4; |
---|
4777 | p_vci_ini_c.cmd = vci_param::CMD_WRITE; |
---|
4778 | p_vci_ini_c.trdid = r_cleanup_trdid.read(); |
---|
4779 | p_vci_ini_c.pktid = 0; |
---|
4780 | p_vci_ini_c.srcid = m_srcid_c; |
---|
4781 | p_vci_ini_c.cons = false; |
---|
4782 | p_vci_ini_c.wrap = false; |
---|
4783 | p_vci_ini_c.contig = false; |
---|
4784 | p_vci_ini_c.clen = 0; |
---|
4785 | p_vci_ini_c.cfixed = false; |
---|
4786 | p_vci_ini_c.eop = true; |
---|
4787 | |
---|
4788 | ///////////////////////////////////////////////////////////////// |
---|
4789 | // VCI initiator response on the coherence network (cleanup) |
---|
4790 | // We always consume the response, and we don't use it. |
---|
4791 | |
---|
4792 | p_vci_ini_c.rspack = true; |
---|
4793 | |
---|
4794 | ///////////////////////////////////////////////////////////////// |
---|
4795 | // VCI initiator command on the direct network |
---|
4796 | // it depends on the CMD FSM state |
---|
4797 | |
---|
4798 | p_vci_ini_d.pktid = 0; |
---|
4799 | p_vci_ini_d.srcid = m_srcid_d; |
---|
4800 | p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC); |
---|
4801 | p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC); |
---|
4802 | p_vci_ini_d.wrap = false; |
---|
4803 | p_vci_ini_d.clen = 0; |
---|
4804 | p_vci_ini_d.cfixed = false; |
---|
4805 | |
---|
4806 | switch ( r_vci_cmd_fsm.read() ) { |
---|
4807 | |
---|
4808 | case CMD_IDLE: |
---|
4809 | p_vci_ini_d.cmdval = false; |
---|
4810 | p_vci_ini_d.address = 0; |
---|
4811 | p_vci_ini_d.wdata = 0; |
---|
4812 | p_vci_ini_d.be = 0; |
---|
4813 | p_vci_ini_d.trdid = 0; |
---|
4814 | p_vci_ini_d.plen = 0; |
---|
4815 | p_vci_ini_d.cmd = vci_param::CMD_NOP; |
---|
4816 | p_vci_ini_d.eop = false; |
---|
4817 | break; |
---|
4818 | |
---|
4819 | case CMD_INS_MISS: |
---|
4820 | p_vci_ini_d.cmdval = true; |
---|
4821 | p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask; |
---|
4822 | p_vci_ini_d.wdata = 0; |
---|
4823 | p_vci_ini_d.be = 0xF; |
---|
4824 | p_vci_ini_d.trdid = TYPE_INS_MISS; |
---|
4825 | p_vci_ini_d.plen = m_icache_words<<2; |
---|
4826 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
4827 | p_vci_ini_d.eop = true; |
---|
4828 | break; |
---|
4829 | |
---|
4830 | case CMD_INS_UNC: |
---|
4831 | p_vci_ini_d.cmdval = true; |
---|
4832 | p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3; |
---|
4833 | p_vci_ini_d.wdata = 0; |
---|
4834 | p_vci_ini_d.be = 0xF; |
---|
4835 | p_vci_ini_d.trdid = TYPE_INS_UNC; |
---|
4836 | p_vci_ini_d.plen = 4; |
---|
4837 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
4838 | p_vci_ini_d.eop = true; |
---|
4839 | break; |
---|
4840 | |
---|
4841 | case CMD_DATA_MISS: |
---|
4842 | p_vci_ini_d.cmdval = true; |
---|
4843 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; |
---|
4844 | p_vci_ini_d.wdata = 0; |
---|
4845 | p_vci_ini_d.be = 0xF; |
---|
4846 | p_vci_ini_d.trdid = TYPE_DATA_MISS; |
---|
4847 | p_vci_ini_d.plen = m_dcache_words << 2; |
---|
4848 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
4849 | p_vci_ini_d.eop = true; |
---|
4850 | break; |
---|
4851 | |
---|
4852 | case CMD_DATA_UNC: |
---|
4853 | p_vci_ini_d.cmdval = true; |
---|
4854 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
4855 | p_vci_ini_d.wdata = 0; |
---|
4856 | p_vci_ini_d.be = r_dcache_vci_unc_be.read(); |
---|
4857 | p_vci_ini_d.trdid = TYPE_DATA_UNC; |
---|
4858 | p_vci_ini_d.plen = 4; |
---|
4859 | p_vci_ini_d.cmd = vci_param::CMD_READ; |
---|
4860 | p_vci_ini_d.eop = true; |
---|
4861 | break; |
---|
4862 | |
---|
4863 | case CMD_DATA_WRITE: |
---|
4864 | p_vci_ini_d.cmdval = true; |
---|
4865 | p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; |
---|
4866 | p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); |
---|
4867 | p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); |
---|
4868 | p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1)); |
---|
4869 | p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; |
---|
4870 | p_vci_ini_d.cmd = vci_param::CMD_WRITE; |
---|
4871 | p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); |
---|
4872 | break; |
---|
4873 | |
---|
4874 | case CMD_DATA_SC: |
---|
4875 | p_vci_ini_d.cmdval = true; |
---|
4876 | p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; |
---|
4877 | if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read(); |
---|
4878 | else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read(); |
---|
4879 | p_vci_ini_d.be = 0xF; |
---|
4880 | p_vci_ini_d.trdid = TYPE_DATA_UNC; |
---|
4881 | p_vci_ini_d.plen = 8; |
---|
4882 | p_vci_ini_d.cmd = vci_param::CMD_STORE_COND; |
---|
4883 | p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); |
---|
4884 | break; |
---|
4885 | } // end switch r_vci_cmd_fsm |
---|
4886 | |
---|
4887 | ////////////////////////////////////////////////////////// |
---|
4888 | // VCI initiator response on the direct network |
---|
4889 | // it depends on the VCI RSP state |
---|
4890 | |
---|
4891 | switch (r_vci_rsp_fsm.read() ) |
---|
4892 | { |
---|
4893 | case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break; |
---|
4894 | case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
4895 | case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; |
---|
4896 | case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
4897 | case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; |
---|
4898 | case RSP_IDLE : p_vci_ini_d.rspack = false; break; |
---|
4899 | } // end switch r_vci_rsp_fsm |
---|
4900 | |
---|
4901 | //////////////////////////////////////////////////////////////// |
---|
4902 | // VCI target command and response on the coherence network |
---|
4903 | switch ( r_tgt_fsm.read() ) |
---|
4904 | { |
---|
4905 | case TGT_IDLE: |
---|
4906 | case TGT_UPDT_WORD: |
---|
4907 | case TGT_UPDT_DATA: |
---|
4908 | p_vci_tgt_c.cmdack = true; |
---|
4909 | p_vci_tgt_c.rspval = false; |
---|
4910 | break; |
---|
4911 | |
---|
4912 | case TGT_RSP_BROADCAST: |
---|
4913 | p_vci_tgt_c.cmdack = false; |
---|
4914 | p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() |
---|
4915 | and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ); |
---|
4916 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
4917 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
4918 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
4919 | p_vci_tgt_c.rdata = 0; |
---|
4920 | p_vci_tgt_c.rerror = 0; |
---|
4921 | p_vci_tgt_c.reop = true; |
---|
4922 | break; |
---|
4923 | |
---|
4924 | case TGT_RSP_ICACHE: |
---|
4925 | p_vci_tgt_c.cmdack = false; |
---|
4926 | p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read(); |
---|
4927 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
4928 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
4929 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
4930 | p_vci_tgt_c.rdata = 0; |
---|
4931 | p_vci_tgt_c.rerror = 0; |
---|
4932 | p_vci_tgt_c.reop = true; |
---|
4933 | break; |
---|
4934 | |
---|
4935 | case TGT_RSP_DCACHE: |
---|
4936 | p_vci_tgt_c.cmdack = false; |
---|
4937 | p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read(); |
---|
4938 | p_vci_tgt_c.rsrcid = r_tgt_srcid.read(); |
---|
4939 | p_vci_tgt_c.rpktid = r_tgt_pktid.read(); |
---|
4940 | p_vci_tgt_c.rtrdid = r_tgt_trdid.read(); |
---|
4941 | p_vci_tgt_c.rdata = 0; |
---|
4942 | p_vci_tgt_c.rerror = 0; |
---|
4943 | p_vci_tgt_c.reop = true; |
---|
4944 | break; |
---|
4945 | |
---|
4946 | case TGT_REQ_BROADCAST: |
---|
4947 | case TGT_REQ_ICACHE: |
---|
4948 | case TGT_REQ_DCACHE: |
---|
4949 | p_vci_tgt_c.cmdack = false; |
---|
4950 | p_vci_tgt_c.rspval = false; |
---|
4951 | break; |
---|
4952 | |
---|
4953 | } // end switch TGT_FSM |
---|
4954 | } // end genMoore |
---|
4955 | |
---|
4956 | }} |
---|
4957 | |
---|
4958 | // Local Variables: |
---|
4959 | // tab-width: 4 |
---|
4960 | // c-basic-offset: 4 |
---|
4961 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
4962 | // indent-tabs-mode: nil |
---|
4963 | // End: |
---|
4964 | |
---|
4965 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
4966 | |
---|
4967 | |
---|
4968 | |
---|
4969 | |
---|
4970 | |
---|
4971 | |
---|
4972 | |
---|
4973 | |
---|
4974 | |
---|
4975 | |
---|