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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 227

Last change on this file since 227 was 227, checked in by alain, 13 years ago
Fixinng a bug in the handling of the generic_cam to support pipelined cleanups.
File size: 187.6 KB

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1	/* i- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_PTE_GET",
91	"DCACHE_DIRTY_SC_WAIT",
92
93	"DCACHE_MISS_VICTIM",
94	"DCACHE_MISS_INVAL",
95	"DCACHE_MISS_WAIT",
96	"DCACHE_MISS_UPDT",
97
98	"DCACHE_UNC_WAIT",
99	"DCACHE_SC_WAIT",
100
101	"DCACHE_CC_CHECK",
102	"DCACHE_CC_INVAL",
103	"DCACHE_CC_UPDT",
104
105	"DCACHE_INVAL_TLB_SCAN",
106	};
107	const char *cmd_fsm_state_str[] = {
108	"CMD_IDLE",
109	"CMD_INS_MISS",
110	"CMD_INS_UNC",
111	"CMD_DATA_MISS",
112	"CMD_DATA_UNC",
113	"CMD_DATA_WRITE",
114	"CMD_DATA_SC",
115	};
116	const char *rsp_fsm_state_str[] = {
117	"RSP_IDLE",
118	"RSP_INS_MISS",
119	"RSP_INS_UNC",
120	"RSP_DATA_MISS",
121	"RSP_DATA_UNC",
122	"RSP_DATA_WRITE",
123	};
124	const char *cleanup_fsm_state_str[] = {
125	"CLEANUP_DATA_IDLE",
126	"CLEANUP_DATA_GO",
127	"CLEANUP_INS_IDLE",
128	"CLEANUP_INS_GO",
129	};
130	const char *tgt_fsm_state_str[] = {
131	"TGT_IDLE",
132	"TGT_UPDT_WORD",
133	"TGT_UPDT_DATA",
134	"TGT_REQ_BROADCAST",
135	"TGT_REQ_ICACHE",
136	"TGT_REQ_DCACHE",
137	"TGT_RSP_BROADCAST",
138	"TGT_RSP_ICACHE",
139	"TGT_RSP_DCACHE",
140	};
141	}
142
143	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
144
145	using soclib::common::uint32_log2;
146
147	/////////////////////////////////
148	tmpl(/**/)::VciCcVCacheWrapperV4(
149	sc_module_name name,
150	int proc_id,
151	const soclib::common::MappingTable &mtp,
152	const soclib::common::MappingTable &mtc,
153	const soclib::common::IntTab &initiator_index_d,
154	const soclib::common::IntTab &initiator_index_c,
155	const soclib::common::IntTab &target_index_d,
156	size_t itlb_ways,
157	size_t itlb_sets,
158	size_t dtlb_ways,
159	size_t dtlb_sets,
160	size_t icache_ways,
161	size_t icache_sets,
162	size_t icache_words,
163	size_t dcache_ways,
164	size_t dcache_sets,
165	size_t dcache_words,
166	size_t wbuf_nlines,
167	size_t wbuf_nwords,
168	uint32_t max_frozen_cycles,
169	uint32_t debug_start_cycle,
170	bool debug_ok)
171	: soclib::caba::BaseModule(name),
172
173	p_clk("clk"),
174	p_resetn("resetn"),
175	p_vci_ini_d("vci_ini_d"),
176	p_vci_ini_c("vci_ini_c"),
177	p_vci_tgt_c("vci_tgt_d"),
178
179	m_cacheability_table(mtp.getCacheabilityTable()),
180	m_segment(mtc.getSegment(target_index_d)),
181	m_srcid_d(mtp.indexForId(initiator_index_d)),
182	m_srcid_c(mtp.indexForId(initiator_index_c)),
183
184	m_itlb_ways(itlb_ways),
185	m_itlb_sets(itlb_sets),
186
187	m_dtlb_ways(dtlb_ways),
188	m_dtlb_sets(dtlb_sets),
189
190	m_icache_ways(icache_ways),
191	m_icache_sets(icache_sets),
192	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
193	m_icache_words(icache_words),
194
195	m_dcache_ways(dcache_ways),
196	m_dcache_sets(dcache_sets),
197	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
198	m_dcache_words(dcache_words),
199
200	m_proc_id(proc_id),
201
202	m_max_frozen_cycles(max_frozen_cycles),
203
204	m_paddr_nbits(vci_param::N),
205
206	m_debug_start_cycle(debug_start_cycle),
207	m_debug_ok(debug_ok),
208
209	r_mmu_ptpr("r_mmu_ptpr"),
210	r_mmu_mode("r_mmu_mode"),
211	r_mmu_word_lo("r_mmu_word_lo"),
212	r_mmu_word_hi("r_mmu_word_hi"),
213	r_mmu_ibvar("r_mmu_ibvar"),
214	r_mmu_dbvar("r_mmu_dbvar"),
215	r_mmu_ietr("r_mmu_ietr"),
216	r_mmu_detr("r_mmu_detr"),
217
218	r_icache_fsm("r_icache_fsm"),
219	r_icache_fsm_save("r_icache_fsm_save"),
220
221	r_icache_vci_paddr("r_icache_vci_paddr"),
222	r_icache_vaddr_save("r_icache_vaddr_save"),
223
224	r_icache_miss_way("r_icache_miss_way"),
225	r_icache_miss_set("r_icache_miss_set"),
226	r_icache_miss_word("r_icache_miss_word"),
227	r_icache_miss_inval("r_icache_miss_inval"),
228
229	r_icache_cc_way("r_icache_cc_way"),
230	r_icache_cc_set("r_icache_cc_set"),
231	r_icache_cc_word("r_icache_cc_word"),
232
233	r_icache_flush_count("r_icache_flush_count"),
234
235	r_icache_miss_req("r_icache_miss_req"),
236	r_icache_unc_req("r_icache_unc_req"),
237
238	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
239	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
240
241	r_icache_cleanup_req("r_icache_cleanup_req"),
242	r_icache_cleanup_line("r_icache_cleanup_line"),
243
244	r_dcache_fsm("r_dcache_fsm"),
245	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
246	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
247
248	r_dcache_p0_valid("r_dcache_p0_valid"),
249	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
250	r_dcache_p0_wdata("r_dcache_p0_wdata"),
251	r_dcache_p0_be("r_dcache_p0_be"),
252	r_dcache_p0_paddr("r_dcache_p0_paddr"),
253	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
254
255	r_dcache_p1_valid("r_dcache_p1_valid"),
256	r_dcache_p1_wdata("r_dcache_p1_wdata"),
257	r_dcache_p1_be("r_dcache_p1_be"),
258	r_dcache_p1_paddr("r_dcache_p1_paddr"),
259	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
260	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
261	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
262
263	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
264	r_dcache_dirty_way("r_dcache_dirty_way"),
265	r_dcache_dirty_set("r_dcache_dirty_set"),
266
267	r_dcache_vci_paddr("r_dcache_vci_paddr"),
268	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
269	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
270	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
271	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
272	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
273	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
274
275	r_dcache_xtn_way("r_dcache_xtn_way"),
276	r_dcache_xtn_set("r_dcache_xtn_set"),
277
278	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
279
280	r_dcache_miss_type("r_dcache_miss_type"),
281	r_dcache_miss_word("r_dcache_miss_word"),
282	r_dcache_miss_way("r_dcache_miss_way"),
283	r_dcache_miss_set("r_dcache_miss_set"),
284	r_dcache_miss_inval("r_dcache_miss_inval"),
285
286	r_dcache_cc_way("r_dcache_cc_way"),
287	r_dcache_cc_set("r_dcache_cc_set"),
288	r_dcache_cc_word("r_dcache_cc_word"),
289
290	r_dcache_flush_count("r_dcache_flush_count"),
291
292	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
293	r_dcache_tlb_ins("r_dcache_tlb_ins"),
294	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
295	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
296	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
297	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
298	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
299	r_dcache_tlb_way("r_dcache_tlb_way"),
300	r_dcache_tlb_set("r_dcache_tlb_set"),
301
302	r_dcache_ll_valid("r_dcache_ll_valid"),
303	r_dcache_ll_data("r_dcache_ll_data"),
304	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
305
306	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
307	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
308
309	r_dcache_xtn_req("r_dcache_xtn_req"),
310	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
311
312	r_dcache_cleanup_req("r_dcache_cleanup_req"),
313	r_dcache_cleanup_line("r_dcache_cleanup_line"),
314
315	r_vci_cmd_fsm("r_vci_cmd_fsm"),
316	r_vci_cmd_min("r_vci_cmd_min"),
317	r_vci_cmd_max("r_vci_cmd_max"),
318	r_vci_cmd_cpt("r_vci_cmd_cpt"),
319	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
320
321	r_vci_rsp_fsm("r_vci_rsp_fsm"),
322	r_vci_rsp_cpt("r_vci_rsp_cpt"),
323	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
324	r_vci_rsp_data_error("r_vci_rsp_data_error"),
325	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
326	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
327
328	r_cleanup_fsm("r_cleanup_fsm"),
329	r_cleanup_trdid("r_cleanup_trdid"),
330	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
331
332	r_tgt_fsm("r_tgt_fsm"),
333	r_tgt_paddr("r_tgt_paddr"),
334	r_tgt_word_count("r_tgt_word_count"),
335	r_tgt_word_min("r_tgt_word_min"),
336	r_tgt_word_max("r_tgt_word_max"),
337	r_tgt_update("r_tgt_update"),
338	r_tgt_update_data("r_tgt_update_data"),
339	r_tgt_srcid("r_tgt_srcid"),
340	r_tgt_pktid("r_tgt_pktid"),
341	r_tgt_trdid("r_tgt_trdid"),
342
343	r_tgt_icache_req("r_tgt_icache_req"),
344	r_tgt_dcache_req("r_tgt_dcache_req"),
345	r_tgt_icache_rsp("r_tgt_icache_rsp"),
346	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
347
348	r_iss(this->name(), proc_id),
349	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
350	r_icache("icache", icache_ways, icache_sets, icache_words),
351	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
352	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
353	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
354	{
355	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
356	"Need more PLEN bits.");
357
358	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
359	"Need more TRDID bits.");
360
361	assert( (icache_words == dcache_words) and
362	"icache_words and dcache_words parameters must be equal");
363
364	assert( (itlb_sets == dtlb_sets) and
365	"itlb_sets and dtlb_sets parameters must be etqual");
366
367	assert( (itlb_ways == dtlb_ways) and
368	"itlb_ways and dtlb_ways parameters must be etqual");
369
370	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
371	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
372	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
373	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
374	(uint32_log2(m_icache_words<<2));
375
376	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
377
378	r_tgt_buf = new uint32_t[dcache_words];
379	r_tgt_be = new vci_be_t[dcache_words];
380	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
381	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
382
383	SC_METHOD(transition);
384	dont_initialize();
385	sensitive << p_clk.pos();
386
387	SC_METHOD(genMoore);
388	dont_initialize();
389	sensitive << p_clk.neg();
390
391	typename iss_t::CacheInfo cache_info;
392	cache_info.has_mmu = true;
393	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
394	cache_info.icache_assoc = icache_ways;
395	cache_info.icache_n_lines = icache_sets;
396	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
397	cache_info.dcache_assoc = dcache_ways;
398	cache_info.dcache_n_lines = dcache_sets;
399	r_iss.setCacheInfo(cache_info);
400	}
401
402	/////////////////////////////////////
403	tmpl(/**/)::~VciCcVCacheWrapperV4()
404	/////////////////////////////////////
405	{
406	delete [] r_tgt_be;
407	delete [] r_tgt_buf;
408	delete [] r_dcache_in_tlb;
409	delete [] r_dcache_contains_ptd;
410	}
411
412	////////////////////////
413	tmpl(void)::print_cpi()
414	////////////////////////
415	{
416	std::cout << name() << " CPI = "
417	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
418	}
419
420	////////////////////////////////////
421	tmpl(void)::print_trace(size_t mode)
422	////////////////////////////////////
423	{
424	// b0 : write buffer trace
425	// b1 : write buffer verbose
426	// b2 : dcache trace
427	// b3 : icache trace
428	// b4 : dtlb trace
429	// b5 : itlb trace
430
431	std::cout << std::dec << "PROC " << name() << std::endl;
432
433	std::cout << " " << m_ireq << std::endl;
434	std::cout << " " << m_irsp << std::endl;
435	std::cout << " " << m_dreq << std::endl;
436	std::cout << " " << m_drsp << std::endl;
437
438	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
439	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
440	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
441	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
442	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
443	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
444	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
445	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
446	std::cout << std::endl;
447
448	if(mode & 0x01)
449	{
450	r_wbuf.printTrace((mode>>1)&1);
451	}
452	if(mode & 0x04)
453	{
454	std::cout << " Data Cache" << std::endl;
455	r_dcache.printTrace();
456	}
457	if(mode & 0x08)
458	{
459	std::cout << " Instruction Cache" << std::endl;
460	r_icache.printTrace();
461	}
462	if(mode & 0x10)
463	{
464	std::cout << " Data TLB" << std::endl;
465	r_dtlb.printTrace();
466	}
467	if(mode & 0x20)
468	{
469	std::cout << " Instruction TLB" << std::endl;
470	r_itlb.printTrace();
471	}
472	}
473
474	//////////////////////////////////////////
475	tmpl(void)::cache_monitor( paddr_t addr )
476	//////////////////////////////////////////
477	{
478	size_t cache_way;
479	size_t cache_set;
480	size_t cache_word;
481	uint32_t cache_rdata;
482	bool cache_hit = r_dcache.read_neutral( addr,
483	&cache_rdata,
484	&cache_way,
485	&cache_set,
486	&cache_word );
487	bool icache_hit = r_icache.read_neutral( addr,
488	&cache_rdata,
489	&cache_way,
490	&cache_set,
491	&cache_word );
492	if ( cache_hit != m_debug_previous_hit )
493	{
494	std::cout << "PROC " << name()
495	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
496	<< " for adresse " << std::hex << addr
497	<< " / HIT = " << std::dec << cache_hit << std::endl;
498	m_debug_previous_hit = cache_hit;
499	}
500	if ( icache_hit != m_idebug_previous_hit )
501	{
502	std::cout << "PROC " << name()
503	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
504	<< " for adresse " << std::hex << addr
505	<< " / HIT = " << icache_hit << std::endl;
506	m_idebug_previous_hit = icache_hit;
507	}
508	}
509
510	/*
511	////////////////////////
512	tmpl(void)::print_stats()
513	////////////////////////
514	{
515	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
516	std::cout << name() << std::endl
517	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
518	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
519	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
520	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
521	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
522	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
523	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
524	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
525	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
526	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
527	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
528	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
529	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
530	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
531	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
532	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
533	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
534	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
535	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
536	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
537	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
538	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
539	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
540	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
541	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
542	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
543	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
544	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
545	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
546	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
547	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
548	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
549	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
550	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
551	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
552	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
553	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
554	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
555	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
556	}
557
558	////////////////////////
559	tmpl(void)::clear_stats()
560	////////////////////////
561	{
562	m_cpt_dcache_data_read = 0;
563	m_cpt_dcache_data_write = 0;
564	m_cpt_dcache_dir_read = 0;
565	m_cpt_dcache_dir_write = 0;
566	m_cpt_icache_data_read = 0;
567	m_cpt_icache_data_write = 0;
568	m_cpt_icache_dir_read = 0;
569	m_cpt_icache_dir_write = 0;
570
571	m_cpt_frz_cycles = 0;
572	m_cpt_dcache_frz_cycles = 0;
573	m_cpt_total_cycles = 0;
574
575	m_cpt_read = 0;
576	m_cpt_write = 0;
577	m_cpt_data_miss = 0;
578	m_cpt_ins_miss = 0;
579	m_cpt_unc_read = 0;
580	m_cpt_write_cached = 0;
581	m_cpt_ins_read = 0;
582
583	m_cost_write_frz = 0;
584	m_cost_data_miss_frz = 0;
585	m_cost_unc_read_frz = 0;
586	m_cost_ins_miss_frz = 0;
587
588	m_cpt_imiss_transaction = 0;
589	m_cpt_dmiss_transaction = 0;
590	m_cpt_unc_transaction = 0;
591	m_cpt_write_transaction = 0;
592	m_cpt_icache_unc_transaction = 0;
593
594	m_cost_imiss_transaction = 0;
595	m_cost_dmiss_transaction = 0;
596	m_cost_unc_transaction = 0;
597	m_cost_write_transaction = 0;
598	m_cost_icache_unc_transaction = 0;
599	m_length_write_transaction = 0;
600
601	m_cpt_ins_tlb_read = 0;
602	m_cpt_ins_tlb_miss = 0;
603	m_cpt_ins_tlb_update_acc = 0;
604
605	m_cpt_data_tlb_read = 0;
606	m_cpt_data_tlb_miss = 0;
607	m_cpt_data_tlb_update_acc = 0;
608	m_cpt_data_tlb_update_dirty = 0;
609	m_cpt_ins_tlb_hit_dcache = 0;
610	m_cpt_data_tlb_hit_dcache = 0;
611	m_cpt_ins_tlb_occup_cache = 0;
612	m_cpt_data_tlb_occup_cache = 0;
613
614	m_cost_ins_tlb_miss_frz = 0;
615	m_cost_data_tlb_miss_frz = 0;
616	m_cost_ins_tlb_update_acc_frz = 0;
617	m_cost_data_tlb_update_acc_frz = 0;
618	m_cost_data_tlb_update_dirty_frz = 0;
619	m_cost_ins_tlb_occup_cache_frz = 0;
620	m_cost_data_tlb_occup_cache_frz = 0;
621
622	m_cpt_itlbmiss_transaction = 0;
623	m_cpt_itlb_ll_transaction = 0;
624	m_cpt_itlb_sc_transaction = 0;
625	m_cpt_dtlbmiss_transaction = 0;
626	m_cpt_dtlb_ll_transaction = 0;
627	m_cpt_dtlb_sc_transaction = 0;
628	m_cpt_dtlb_ll_dirty_transaction = 0;
629	m_cpt_dtlb_sc_dirty_transaction = 0;
630
631	m_cost_itlbmiss_transaction = 0;
632	m_cost_itlb_ll_transaction = 0;
633	m_cost_itlb_sc_transaction = 0;
634	m_cost_dtlbmiss_transaction = 0;
635	m_cost_dtlb_ll_transaction = 0;
636	m_cost_dtlb_sc_transaction = 0;
637	m_cost_dtlb_ll_dirty_transaction = 0;
638	m_cost_dtlb_sc_dirty_transaction = 0;
639
640	m_cpt_cc_update_data = 0;
641	m_cpt_cc_inval_ins = 0;
642	m_cpt_cc_inval_data = 0;
643	m_cpt_cc_broadcast = 0;
644
645	m_cost_updt_data_frz = 0;
646	m_cost_inval_ins_frz = 0;
647	m_cost_inval_data_frz = 0;
648	m_cost_broadcast_frz = 0;
649
650	m_cpt_cc_cleanup_data = 0;
651	m_cpt_cc_cleanup_ins = 0;
652	}
653
654	*/
655
656	/////////////////////////
657	tmpl(void)::transition()
658	/////////////////////////
659	{
660	if ( not p_resetn.read() )
661	{
662	r_iss.reset();
663	r_wbuf.reset();
664	r_icache.reset();
665	r_dcache.reset();
666	r_itlb.reset();
667	r_dtlb.reset();
668
669	r_dcache_fsm = DCACHE_IDLE;
670	r_icache_fsm = ICACHE_IDLE;
671	r_vci_cmd_fsm = CMD_IDLE;
672	r_vci_rsp_fsm = RSP_IDLE;
673	r_tgt_fsm = TGT_IDLE;
674	r_cleanup_fsm = CLEANUP_DATA_IDLE;
675
676	// reset dcache directory extension
677	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
678	{
679	r_dcache_in_tlb[i] = false;
680	r_dcache_contains_ptd[i] = false;
681	}
682
683	// Response FIFOs and cleanup buffer
684	r_vci_rsp_fifo_icache.init();
685	r_vci_rsp_fifo_dcache.init();
686	r_cleanup_buffer.reset();
687
688	// ICACHE & DCACHE activated
689	r_mmu_mode = 0x3;
690
691	// No request from ICACHE FSM to CMD FSM
692	r_icache_miss_req = false;
693	r_icache_unc_req = false;
694
695	// No request from ICACHE_FSM to DCACHE FSM
696	r_icache_tlb_miss_req = false;
697
698	// No request from ICACHE_FSM to CLEANUP FSMs
699	r_icache_cleanup_req = false;
700
701	// No pending write in pipeline
702	r_dcache_p0_valid = false;
703	r_dcache_p1_valid = false;
704
705	// No request from DCACHE_FSM to CMD_FSM
706	r_dcache_vci_miss_req = false;
707	r_dcache_vci_unc_req = false;
708	r_dcache_vci_sc_req = false;
709
710	// No uncacheable write pending
711	r_dcache_pending_unc_write = false;
712
713	// No LL reservation
714	r_dcache_ll_valid = false;
715
716	// No processor XTN request pending
717	r_dcache_xtn_req = false;
718
719	// No request from DCACHE FSM to CLEANUP FSMs
720	r_dcache_cleanup_req = false;
721
722	// No request from TGT FSM to ICACHE/DCACHE FSMs
723	r_tgt_icache_req = false;
724	r_tgt_dcache_req = false;
725
726	// No signalisation of a coherence request matching a pending miss
727	r_icache_miss_inval = false;
728	r_dcache_miss_inval = false;
729
730	// No signalisation of errors
731	r_vci_rsp_ins_error = false;
732	r_vci_rsp_data_error = false;
733
734	// Debug variables
735	m_debug_previous_hit = false;
736	m_idebug_previous_hit = false;
737	m_debug_dcache_fsm = false;
738	m_debug_icache_fsm = false;
739	m_debug_cleanup_fsm = false;
740
741	// activity counters
742	m_cpt_dcache_data_read = 0;
743	m_cpt_dcache_data_write = 0;
744	m_cpt_dcache_dir_read = 0;
745	m_cpt_dcache_dir_write = 0;
746	m_cpt_icache_data_read = 0;
747	m_cpt_icache_data_write = 0;
748	m_cpt_icache_dir_read = 0;
749	m_cpt_icache_dir_write = 0;
750
751	m_cpt_frz_cycles = 0;
752	m_cpt_total_cycles = 0;
753	m_cpt_stop_simulation = 0;
754
755	m_cpt_data_miss = 0;
756	m_cpt_ins_miss = 0;
757	m_cpt_unc_read = 0;
758	m_cpt_write_cached = 0;
759	m_cpt_ins_read = 0;
760
761	m_cost_write_frz = 0;
762	m_cost_data_miss_frz = 0;
763	m_cost_unc_read_frz = 0;
764	m_cost_ins_miss_frz = 0;
765
766	m_cpt_imiss_transaction = 0;
767	m_cpt_dmiss_transaction = 0;
768	m_cpt_unc_transaction = 0;
769	m_cpt_write_transaction = 0;
770	m_cpt_icache_unc_transaction = 0;
771
772	m_cost_imiss_transaction = 0;
773	m_cost_dmiss_transaction = 0;
774	m_cost_unc_transaction = 0;
775	m_cost_write_transaction = 0;
776	m_cost_icache_unc_transaction = 0;
777	m_length_write_transaction = 0;
778
779	m_cpt_ins_tlb_read = 0;
780	m_cpt_ins_tlb_miss = 0;
781	m_cpt_ins_tlb_update_acc = 0;
782
783	m_cpt_data_tlb_read = 0;
784	m_cpt_data_tlb_miss = 0;
785	m_cpt_data_tlb_update_acc = 0;
786	m_cpt_data_tlb_update_dirty = 0;
787	m_cpt_ins_tlb_hit_dcache = 0;
788	m_cpt_data_tlb_hit_dcache = 0;
789	m_cpt_ins_tlb_occup_cache = 0;
790	m_cpt_data_tlb_occup_cache = 0;
791
792	m_cost_ins_tlb_miss_frz = 0;
793	m_cost_data_tlb_miss_frz = 0;
794	m_cost_ins_tlb_update_acc_frz = 0;
795	m_cost_data_tlb_update_acc_frz = 0;
796	m_cost_data_tlb_update_dirty_frz = 0;
797	m_cost_ins_tlb_occup_cache_frz = 0;
798	m_cost_data_tlb_occup_cache_frz = 0;
799
800	m_cpt_ins_tlb_inval = 0;
801	m_cpt_data_tlb_inval = 0;
802	m_cost_ins_tlb_inval_frz = 0;
803	m_cost_data_tlb_inval_frz = 0;
804
805	m_cpt_cc_broadcast = 0;
806
807	m_cost_updt_data_frz = 0;
808	m_cost_inval_ins_frz = 0;
809	m_cost_inval_data_frz = 0;
810	m_cost_broadcast_frz = 0;
811
812	m_cpt_cc_cleanup_data = 0;
813	m_cpt_cc_cleanup_ins = 0;
814
815	m_cpt_itlbmiss_transaction = 0;
816	m_cpt_itlb_ll_transaction = 0;
817	m_cpt_itlb_sc_transaction = 0;
818	m_cpt_dtlbmiss_transaction = 0;
819	m_cpt_dtlb_ll_transaction = 0;
820	m_cpt_dtlb_sc_transaction = 0;
821	m_cpt_dtlb_ll_dirty_transaction = 0;
822	m_cpt_dtlb_sc_dirty_transaction = 0;
823
824	m_cost_itlbmiss_transaction = 0;
825	m_cost_itlb_ll_transaction = 0;
826	m_cost_itlb_sc_transaction = 0;
827	m_cost_dtlbmiss_transaction = 0;
828	m_cost_dtlb_ll_transaction = 0;
829	m_cost_dtlb_sc_transaction = 0;
830	m_cost_dtlb_ll_dirty_transaction = 0;
831	m_cost_dtlb_sc_dirty_transaction = 0;
832	/*
833	m_cpt_dcache_frz_cycles = 0;
834	m_cpt_read = 0;
835	m_cpt_write = 0;
836	m_cpt_cc_update_data = 0;
837	m_cpt_cc_inval_ins = 0;
838	m_cpt_cc_inval_data = 0;
839	*/
840
841	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
842	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
843	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
844	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
845	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
846	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
847	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
848
849	return;
850	}
851
852	// Response FIFOs default values
853	bool vci_rsp_fifo_icache_get = false;
854	bool vci_rsp_fifo_icache_put = false;
855	uint32_t vci_rsp_fifo_icache_data = 0;
856
857	bool vci_rsp_fifo_dcache_get = false;
858	bool vci_rsp_fifo_dcache_put = false;
859	uint32_t vci_rsp_fifo_dcache_data = 0;
860
861	#ifdef INSTRUMENTATION
862	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
863	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
864	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
865	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
866	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
867	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
868	#endif
869
870	m_cpt_total_cycles++;
871
872	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
873	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
874	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
875
876	/////////////////////////////////////////////////////////////////////
877	// The TGT_FSM controls the following ressources:
878	// - r_tgt_fsm
879	// - r_tgt_buf[nwords]
880	// - r_tgt_be[nwords]
881	// - r_tgt_update
882	// - r_tgt_word_min
883	// - r_tgt_word_max
884	// - r_tgt_word_count
885	// - r_tgt_paddr
886	// - r_tgt_srcid
887	// - r_tgt_trdid
888	// - r_tgt_pktid
889	// - r_tgt_icache_req (set)
890	// - r_tgt_dcache_req (set)
891	//
892	// All VCI commands must be CMD_WRITE.
893	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
894	// It is a multicast request otherwise.
895	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
896	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
897	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
898	//
899	// For all types of coherence request, the line index (i.e. the Z & Y fields)
900	// is coded on 34 bits, and is contained in the WDATA and BE fields
901	// of the first VCI flit.
902	// - for a multicast invalidate or for a broadcast invalidate request
903	// the VCI packet length is 1 word.
904	// - for an update request the VCI packet length is (n+2) words.
905	// The WDATA field of the second VCI word contains the word index.
906	// The WDATA field of the n following words contains the values.
907	// - for all transaction types, the VCI response is one single word.
908	// In case of errors in the VCI command packet, the simulation
909	// is stopped with an error message.
910	//
911	// This FSM is NOT pipelined : It consumes a new coherence request
912	// on the VCI port only when the previous request is completed.
913	//
914	// The VCI_TGT FSM stores the external request arguments in the
915	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
916	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
917	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
918	// states. It waits the completion of the coherence request by polling the
919	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
920	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
921	// These two FSMs signal if a VCI answer must be send by setting
922	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
923	///////////////////////////////////////////////////////////////////////////////
924
925	switch( r_tgt_fsm.read() )
926	{
927	//////////////
928	case TGT_IDLE:
929	{
930	if ( p_vci_tgt_c.cmdval.read() )
931	{
932	paddr_t address = p_vci_tgt_c.address.read();
933
934	// command checking
935	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
936	{
937	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
938	std::cout << "the received VCI coherence command is not a write" << std::endl;
939	exit(0);
940	}
941
942	// address checking
943	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
944	{
945	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
946	std::cout << "out of segment VCI coherence command received" << std::endl;
947	exit(0);
948	}
949
950	r_tgt_srcid = p_vci_tgt_c.srcid.read();
951	r_tgt_trdid = p_vci_tgt_c.trdid.read();
952	r_tgt_pktid = p_vci_tgt_c.pktid.read();
953
954	if (sizeof(paddr_t) <= 32) {
955	assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr");
956	r_tgt_paddr =
957	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
958	} else {
959	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
960	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
961	}
962
963	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
964	{
965	if ( not p_vci_tgt_c.eop.read() )
966	{
967	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
968	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
969	exit(0);
970	}
971	r_tgt_update = false;
972	r_tgt_fsm = TGT_REQ_BROADCAST;
973
974	#ifdef INSTRUMENTATION
975	m_cpt_cc_broadcast++;
976	#endif
977	}
978	else // multi-update or multi-invalidate for data type
979	{
980	paddr_t cell = address - m_segment.baseAddress();
981
982	if (cell == 0) // invalidate data
983	{
984	if ( not p_vci_tgt_c.eop.read() )
985	{
986	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
987	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
988	exit(0);
989	}
990	r_tgt_update = false;
991	r_tgt_fsm = TGT_REQ_DCACHE;
992
993	#ifdef INSTRUMENTATION
994	m_cpt_cc_inval_dcache++;
995	#endif
996	}
997	else if (cell == 4) // invalidate instruction
998	{
999	if ( not p_vci_tgt_c.eop.read() )
1000	{
1001	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1002	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1003	exit(0);
1004	}
1005	r_tgt_update = false;
1006	r_tgt_fsm = TGT_REQ_ICACHE;
1007
1008	#ifdef INSTRUMENTATION
1009	m_cpt_cc_inval_icache++;
1010	#endif
1011	}
1012	else if (cell == 8) // update data
1013	{
1014	if ( p_vci_tgt_c.eop.read() )
1015	{
1016	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1017	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1018	exit(0);
1019	}
1020	r_tgt_update = true;
1021	r_tgt_update_data = true;
1022	r_tgt_fsm = TGT_UPDT_WORD;
1023
1024	#ifdef INSTRUMENTATION
1025	m_cpt_cc_update_dcache++;
1026	#endif
1027	}
1028	else // update instruction
1029	{
1030	if ( p_vci_tgt_c.eop.read() )
1031	{
1032	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1033	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1034	exit(0);
1035	}
1036	r_tgt_update = true;
1037	r_tgt_update_data = false;
1038	r_tgt_fsm = TGT_UPDT_WORD;
1039
1040	#ifdef INSTRUMENTATION
1041	m_cpt_cc_update_icache++;
1042	#endif
1043	}
1044	} // end if multi
1045	} // end if cmdval
1046	break;
1047	}
1048	///////////////////
1049	case TGT_UPDT_WORD: // first word index acquisition
1050	{
1051	if (p_vci_tgt_c.cmdval.read())
1052	{
1053	if ( p_vci_tgt_c.eop.read() )
1054	{
1055	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1056	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1057	exit(0);
1058	}
1059	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1060
1061	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1062	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1063	r_tgt_fsm = TGT_UPDT_DATA;
1064	}
1065	break;
1066	}
1067	///////////////////
1068	case TGT_UPDT_DATA:
1069	{
1070	if (p_vci_tgt_c.cmdval.read())
1071	{
1072	size_t word = r_tgt_word_count.read();
1073	if (word >= m_dcache_words)
1074	{
1075	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1076	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1077	exit(0);
1078	}
1079	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1080	r_tgt_be[word] = p_vci_tgt_c.be.read();
1081	r_tgt_word_count = word + 1;
1082
1083	if (p_vci_tgt_c.eop.read()) // last word
1084	{
1085	r_tgt_word_max = word;
1086	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1087	else r_tgt_fsm = TGT_REQ_ICACHE;
1088	}
1089	}
1090	break;
1091	}
1092	///////////////////////
1093	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1094	{
1095	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1096	{
1097	r_tgt_fsm = TGT_RSP_BROADCAST;
1098	r_tgt_icache_req = true;
1099	r_tgt_dcache_req = true;
1100	}
1101	break;
1102	}
1103	/////////////////////
1104	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1105	{
1106	if ( not r_tgt_icache_req.read() )
1107	{
1108	r_tgt_fsm = TGT_RSP_ICACHE;
1109	r_tgt_icache_req = true;
1110	}
1111	break;
1112	}
1113	////////////////////
1114	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1115	{
1116	if ( not r_tgt_dcache_req.read() )
1117	{
1118	r_tgt_fsm = TGT_RSP_DCACHE;
1119	r_tgt_dcache_req = true;
1120	}
1121	break;
1122	}
1123	///////////////////////
1124	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1125	// no response when r_tgt_*cache_rsp is false
1126	{
1127	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1128	{
1129	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1130	{
1131	if ( p_vci_tgt_c.rspack.read() )
1132	{
1133	// reset dcache first if activated
1134	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1135	else r_tgt_icache_rsp = false;
1136	}
1137	}
1138	else
1139	{
1140	r_tgt_fsm = TGT_IDLE;
1141	}
1142	}
1143	break;
1144	}
1145	////////////////////
1146	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1147	{
1148	// no response when r_tgt_icache_rsp is false
1149	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1150	{
1151	r_tgt_fsm = TGT_IDLE;
1152	r_tgt_icache_rsp = false;
1153	}
1154	break;
1155	}
1156	////////////////////
1157	case TGT_RSP_DCACHE:
1158	{
1159	// no response when r_tgt_dcache_rsp is false
1160	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1161	{
1162	r_tgt_fsm = TGT_IDLE;
1163	r_tgt_dcache_rsp = false;
1164	}
1165	break;
1166	}
1167	} // end switch TGT_FSM
1168
1169	/////////////////////////////////////////////////////////////////////
1170	// Get data and instruction requests from processor
1171	///////////////////////////////////////////////////////////////////////
1172
1173	r_iss.getRequests(m_ireq, m_dreq);
1174
1175	////////////////////////////////////////////////////////////////////////////////////
1176	// ICACHE_FSM
1177	//
1178	// There is 9 conditions to exit the IDLE state:
1179	// One condition is a coherence request from TGT FSM :
1180	// - Coherence operation => ICACHE_CC_CHEK
1181	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1182	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1183	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1184	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1185	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1186	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1187	// three configurations corresponding to instruction processor requests :
1188	// - tlb miss => ICACHE_TLB_WAIT
1189	// - cacheable read miss => ICACHE_MISS_VICTIM
1190	// - uncacheable read miss => ICACHE_UNC_REQ
1191	//
1192	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1193	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1194	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1195	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1196	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1197	// The availability of the missing cache line is signaled by the response fifo,
1198	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1199	//
1200	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1201	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1202	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1203	// the response from the RSP FSM, through the response fifo. The missing instruction
1204	// is directly returned to processor in this state.
1205	//
1206	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1207	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1208	// and goes to the ICACHE_TLB_WAIT state.
1209	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1210	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1211	//
1212	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1213	// using the r_dcache_xtn_req flip-flop.
1214	// The request opcode and the address to be invalidated are transmitted
1215	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1216	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1217	// is completed.
1218	//
1219	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1220	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1221	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1222	////////////////////////////////////////////////////////////////////////////////////////
1223
1224	// default value for m_irsp
1225	m_irsp.valid = false;
1226	m_irsp.error = false;
1227	m_irsp.instruction = 0;
1228
1229	switch( r_icache_fsm.read() )
1230	{
1231	/////////////////
1232	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1233	// by DCACHE FSM, and coherence requests with a fixed priority:
1234	// coherence > XTN > instruction
1235	// We access the itlb and dcache in parallel with the virtual address
1236	// for itlb, and with a speculative physical address for icache,
1237	// computed during the previous cycle.
1238	{
1239	// coherence request from the target FSM
1240	if ( r_tgt_icache_req.read() )
1241	{
1242	r_icache_fsm = ICACHE_CC_CHECK;
1243	r_icache_fsm_save = r_icache_fsm.read();
1244	break;
1245	}
1246
1247	// Decoding processor XTN requests sent by DCACHE FSM
1248	// These request are not executed in this IDLE state, because
1249	// they require access to icache or itlb, that are already accessed
1250	if ( r_dcache_xtn_req.read() )
1251	{
1252	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1253	{
1254	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1255	break;
1256	}
1257	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1258	{
1259	r_icache_flush_count = 0;
1260	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1261	break;
1262	}
1263	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1264	{
1265	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1266	break;
1267	}
1268	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1269	{
1270	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1271	break;
1272	}
1273	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1274	{
1275	if (sizeof(paddr_t) <= 32) {
1276	assert(r_mmu_word_hi.read() == 0 &&
1277	"high bits should be 0 for 32bit paddr");
1278	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1279	} else {
1280	r_icache_vci_paddr =
1281	(paddr_t)r_mmu_word_hi.read() << 32 \|
1282	(paddr_t)r_mmu_word_lo.read();
1283	}
1284	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1285	break;
1286	}
1287	} // end if xtn_req
1288
1289	// processor request
1290	if ( m_ireq.valid )
1291	{
1292	bool cacheable;
1293	paddr_t paddr;
1294
1295	// We register processor request
1296	r_icache_vaddr_save = m_ireq.addr;
1297
1298	// speculative icache access (if cache activated)
1299	// we use the speculative PPN computed during the previous cycle
1300
1301	uint32_t cache_inst = 0;
1302	bool cache_hit = false;
1303
1304	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1305	{
1306	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1307	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1308
1309	#ifdef INSTRUMENTATION
1310	m_cpt_icache_data_read++;
1311	m_cpt_icache_dir_read++;
1312	#endif
1313	cache_hit = r_icache.read( spc_paddr,
1314	&cache_inst );
1315	}
1316
1317	// systematic itlb access (if tlb activated)
1318	// we use the virtual address
1319
1320	paddr_t tlb_paddr;
1321	pte_info_t tlb_flags;
1322	size_t tlb_way;
1323	size_t tlb_set;
1324	paddr_t tlb_nline;
1325	bool tlb_hit = false;;
1326
1327	if ( r_mmu_mode.read() & INS_TLB_MASK )
1328	{
1329
1330	#ifdef INSTRUMENTATION
1331	m_cpt_itlb_read++;
1332	#endif
1333	tlb_hit = r_itlb.translate( m_ireq.addr,
1334	&tlb_paddr,
1335	&tlb_flags,
1336	&tlb_nline, // unused
1337	&tlb_way, // unused
1338	&tlb_set ); // unused
1339	}
1340
1341	// We compute cacheability, physical address and check access rights:
1342	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1343	// the physical address is obtained from the TLB, and the access rights are
1344	// defined by the U and X bits in the PTE.
1345	// - If MMU not activated : cacheability is defined by the segment table,
1346	// the physical address is equal to the virtual address (identity mapping)
1347	// and there is no access rights checking
1348
1349	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1350	{
1351	// cacheability
1352	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1353	else cacheable = m_cacheability_table[m_ireq.addr];
1354
1355	// physical address
1356	paddr = (paddr_t)m_ireq.addr;
1357	}
1358	else // itlb activated
1359	{
1360	if ( tlb_hit ) // tlb hit
1361	{
1362	// cacheability
1363	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1364	else cacheable = tlb_flags.c;
1365
1366	// physical address
1367	paddr = tlb_paddr;
1368
1369	// access rights checking
1370	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1371	{
1372	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1373	r_mmu_ibvar = m_ireq.addr;
1374	m_irsp.valid = true;
1375	m_irsp.error = true;
1376	m_irsp.instruction = 0;
1377	break;
1378	}
1379	else if ( not tlb_flags.x )
1380	{
1381	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1382	r_mmu_ibvar = m_ireq.addr;
1383	m_irsp.valid = true;
1384	m_irsp.error = true;
1385	m_irsp.instruction = 0;
1386	break;
1387	}
1388	}
1389	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1390	else
1391	{
1392
1393	#ifdef INSTRUMENTATION
1394	m_cpt_itlb_miss++;
1395	#endif
1396	r_icache_fsm = ICACHE_TLB_WAIT;
1397	r_icache_tlb_miss_req = true;
1398	break;
1399	}
1400	} // end if itlb activated
1401
1402	// physical address registration (for next cycle)
1403	r_icache_vci_paddr = paddr;
1404
1405	// We enter this section only in case of TLB hit:
1406	// Finally, we get the instruction depending on cacheability,
1407	// we send the response to processor, and compute next state
1408	if ( cacheable ) // cacheable read
1409	{
1410	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1411	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1412	{
1413
1414	#ifdef INSTRUMENTATION
1415	m_cpt_icache_spc_miss++;
1416	#endif
1417	// we return an invalid response and stay in IDLE state
1418	// the cache access will cost one extra cycle.
1419	break;
1420	}
1421
1422	if ( not cache_hit ) // cache miss
1423	{
1424
1425	#ifdef INSTRUMENTATION
1426	m_cpt_icache_miss++;
1427	#endif
1428	r_icache_fsm = ICACHE_MISS_VICTIM;
1429	r_icache_miss_req = true;
1430	}
1431	else // cache hit
1432	{
1433
1434	#ifdef INSTRUMENTATION
1435	m_cpt_ins_read++;
1436	#endif
1437	m_irsp.valid = true;
1438	m_irsp.instruction = cache_inst;
1439	}
1440	}
1441	else // non cacheable read
1442	{
1443	r_icache_unc_req = true;
1444	r_icache_fsm = ICACHE_UNC_WAIT;
1445	}
1446	} // end if m_ireq.valid
1447	break;
1448	}
1449	/////////////////////
1450	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1451	// the itlb is udated by the DCACHE FSM, as well as the
1452	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1453	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1454	// reset the r_icache_tlb_miss_req flip-flop
1455	// external coherence request are accepted in this state.
1456	{
1457	// external coherence request
1458	if ( r_tgt_icache_req.read() )
1459	{
1460	r_icache_fsm = ICACHE_CC_CHECK;
1461	r_icache_fsm_save = r_icache_fsm.read();
1462	break;
1463	}
1464
1465	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1466
1467	// DCACHE FSM signals response by reseting the request flip-flop
1468	if ( not r_icache_tlb_miss_req.read() )
1469	{
1470	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1471	{
1472	r_icache_tlb_rsp_error = false;
1473	m_irsp.error = true;
1474	m_irsp.valid = true;
1475	r_icache_fsm = ICACHE_IDLE;
1476	}
1477	else // tlb updated : return to IDLE state
1478	{
1479	r_icache_fsm = ICACHE_IDLE;
1480	}
1481	}
1482	break;
1483	}
1484	//////////////////////////
1485	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1486	{
1487	r_itlb.flush();
1488	r_dcache_xtn_req = false;
1489	r_icache_fsm = ICACHE_IDLE;
1490	break;
1491	}
1492	////////////////////////////
1493	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1494	// the r_icache_flush_count register as a slot counter.
1495	// We loop in this state until all slots have been visited.
1496	// A cleanup request is generated for each valid line
1497	// and we are blocked until the previous cleanup is completed
1498	{
1499	if ( not r_icache_cleanup_req.read() )
1500	{
1501	size_t way = r_icache_flush_count.read()/m_icache_sets;
1502	size_t set = r_icache_flush_count.read()%m_icache_sets;
1503	paddr_t nline;
1504	bool cleanup_req = r_icache.inval( way,
1505	set,
1506	&nline );
1507	if ( cleanup_req )
1508	{
1509	r_icache_cleanup_req = true;
1510	r_icache_cleanup_line = nline;
1511	}
1512	r_icache_flush_count = r_icache_flush_count.read() + 1;
1513	}
1514
1515	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1516	{
1517	r_dcache_xtn_req = false;
1518	r_icache_fsm = ICACHE_IDLE;
1519	}
1520	break;
1521	}
1522	//////////////////////////
1523	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1524	// stored in the r_dcache_p0_wdata register
1525	{
1526	r_itlb.inval(r_dcache_p0_wdata.read());
1527	r_dcache_xtn_req = false;
1528	r_icache_fsm = ICACHE_IDLE;
1529	break;
1530	}
1531	///////////////////////////////
1532	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1533	// requires 3 cycles (in case of hit on itlb and icache).
1534	// In this state, we access TLB to translate virtual address
1535	// stored in the r_dcache_p0_wdata register.
1536	{
1537	paddr_t paddr;
1538	bool hit;
1539
1540	// read physical address in TLB when MMU activated
1541	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1542	{
1543
1544	#ifdef INSTRUMENTATION
1545	m_cpt_itlb_read++;
1546	#endif
1547	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1548	&paddr);
1549	}
1550	else // itlb not activated
1551	{
1552	paddr = (paddr_t)r_dcache_p0_wdata.read();
1553	hit = true;
1554	}
1555
1556	if ( hit ) // continue the selective inval process
1557	{
1558	r_icache_vci_paddr = paddr;
1559	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1560	}
1561	else // miss : send a request to DCACHE FSM
1562	{
1563
1564	#ifdef INSTRUMENTATION
1565	m_cpt_itlb_miss++;
1566	#endif
1567	r_icache_tlb_miss_req = true;
1568	r_icache_fsm = ICACHE_TLB_WAIT;
1569	}
1570	break;
1571	}
1572	///////////////////////////////
1573	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1574	// require 2 cycles. In this state, we read dcache,
1575	// with address stored in r_icache_vci_paddr register.
1576	{
1577	uint32_t data;
1578	size_t way;
1579	size_t set;
1580	size_t word;
1581	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1582	&data,
1583	&way,
1584	&set,
1585	&word);
1586	if ( hit ) // inval to be done
1587	{
1588	r_icache_miss_way = way;
1589	r_icache_miss_set = set;
1590	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1591	}
1592	else // miss : acknowlege the XTN request and return
1593	{
1594	r_dcache_xtn_req = false;
1595	r_icache_fsm = ICACHE_IDLE;
1596	}
1597	break;
1598	}
1599	///////////////////////////////
1600	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1601	// We are blocked if the previous cleanup is not completed
1602	{
1603	paddr_t nline;
1604
1605	if ( not r_icache_cleanup_req.read() )
1606	{
1607	bool hit;
1608	hit = r_icache.inval( r_icache_miss_way.read(),
1609	r_icache_miss_set.read(),
1610	&nline );
1611	assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
1612
1613	// request cleanup
1614	r_icache_cleanup_req = true;
1615	r_icache_cleanup_line = nline;
1616	// acknowledge the XTN request and return
1617	r_dcache_xtn_req = false;
1618	r_icache_fsm = ICACHE_IDLE;
1619	}
1620	break;
1621	}
1622
1623	////////////////////////
1624	case ICACHE_MISS_VICTIM: // Selects a victim line
1625	// Set the r_icache_cleanup_req flip-flop
1626	// when the selected slot is not empty
1627	{
1628	m_cost_ins_miss_frz++;
1629
1630	size_t index; // unused
1631	bool hit = r_cleanup_buffer.hit( r_icache_vci_paddr.read()>>(uint32_log2(m_icache_words)+2), &index );
1632	if ( not hit and not r_icache_cleanup_req.read() )
1633	{
1634	bool valid;
1635	size_t way;
1636	size_t set;
1637	paddr_t victim;
1638
1639	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1640	&victim,
1641	&way,
1642	&set);
1643	r_icache_miss_way = way;
1644	r_icache_miss_set = set;
1645
1646	if ( valid )
1647	{
1648	r_icache_cleanup_req = true;
1649	r_icache_cleanup_line = victim;
1650	r_icache_fsm = ICACHE_MISS_INVAL;
1651	}
1652	else
1653	{
1654	r_icache_fsm = ICACHE_MISS_WAIT;
1655	}
1656	}
1657	break;
1658	}
1659	///////////////////////
1660	case ICACHE_MISS_INVAL: // invalidate the victim line
1661	{
1662	paddr_t nline;
1663	bool hit;
1664
1665	hit = r_icache.inval( r_icache_miss_way.read(),
1666	r_icache_miss_set.read(),
1667	&nline ); // unused
1668	assert(hit && "selected way/set line should be in icache");
1669
1670	r_icache_fsm = ICACHE_MISS_WAIT;
1671	break;
1672	}
1673	//////////////////////
1674	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1675	{
1676	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1677
1678	// external coherence request
1679	if ( r_tgt_icache_req.read() )
1680	{
1681	r_icache_fsm = ICACHE_CC_CHECK;
1682	r_icache_fsm_save = r_icache_fsm.read();
1683	break;
1684	}
1685
1686	if ( r_vci_rsp_ins_error.read() ) // bus error
1687	{
1688	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1689	r_mmu_ibvar = r_icache_vaddr_save.read();
1690	m_irsp.valid = true;
1691	m_irsp.error = true;
1692	r_vci_rsp_ins_error = false;
1693	r_icache_fsm = ICACHE_IDLE;
1694	}
1695	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1696	{
1697	r_icache_miss_word = 0;
1698	r_icache_fsm = ICACHE_MISS_UPDT;
1699	}
1700	break;
1701	}
1702	//////////////////////
1703	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1704	{
1705	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1706
1707	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1708	{
1709	if ( r_icache_miss_inval ) // Matching coherence request
1710	// We pop the response FIFO, without updating the cache
1711	// We send a cleanup for the missing line at the last word
1712	// Blocked if the previous cleanup is not completed
1713	{
1714	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1715	{
1716	vci_rsp_fifo_icache_get = true;
1717	r_icache_miss_word = r_icache_miss_word.read() + 1;
1718	}
1719	else // last word
1720	{
1721	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1722	{
1723	vci_rsp_fifo_icache_get = true;
1724	r_icache_cleanup_req = true;
1725	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1726	r_icache_miss_inval = false;
1727	r_icache_fsm = ICACHE_IDLE;
1728	}
1729	}
1730	}
1731	else // No matching coherence request
1732	// We pop the FIFO and update the cache
1733	// We update the directory at the last word
1734	{
1735
1736	#ifdef INSTRUMENTATION
1737	m_cpt_icache_data_write++;
1738	#endif
1739	r_icache.write( r_icache_miss_way.read(),
1740	r_icache_miss_set.read(),
1741	r_icache_miss_word.read(),
1742	r_vci_rsp_fifo_icache.read() );
1743	vci_rsp_fifo_icache_get = true;
1744	r_icache_miss_word = r_icache_miss_word.read() + 1;
1745	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1746	{
1747
1748	#ifdef INSTRUMENTATION
1749	m_cpt_icache_dir_write++;
1750	#endif
1751	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1752	r_icache_miss_way.read(),
1753	r_icache_miss_set.read() );
1754	r_icache_fsm = ICACHE_IDLE;
1755	}
1756	}
1757	}
1758	break;
1759	}
1760	////////////////////
1761	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1762	//
1763	{
1764	// external coherence request
1765	if ( r_tgt_icache_req.read() )
1766	{
1767	r_icache_fsm = ICACHE_CC_CHECK;
1768	r_icache_fsm_save = r_icache_fsm.read();
1769	break;
1770	}
1771
1772	if ( r_vci_rsp_ins_error.read() ) // bus error
1773	{
1774	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1775	r_mmu_ibvar = m_ireq.addr;
1776	r_vci_rsp_ins_error = false;
1777	m_irsp.valid = true;
1778	m_irsp.error = true;
1779	r_icache_fsm = ICACHE_IDLE;
1780	}
1781	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1782	{
1783	vci_rsp_fifo_icache_get = true;
1784	r_icache_fsm = ICACHE_IDLE;
1785	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1786	{
1787	m_irsp.valid = true;
1788	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1789	}
1790	}
1791	break;
1792	}
1793	/////////////////////
1794	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1795	// handling coherence requests.
1796	// the return state is defined in r_icache_fsm_save.
1797	{
1798	paddr_t paddr = r_tgt_paddr.read();
1799	paddr_t mask = ~((m_icache_words<<2)-1);
1800
1801	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1802	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1803	{
1804	r_icache_miss_inval = true; // signaling the matching
1805	r_tgt_icache_req = false; // coherence request completed
1806	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1807	r_icache_fsm = r_icache_fsm_save.read();
1808	}
1809	else // no match
1810	{
1811
1812	#ifdef INSTRUMENTATION
1813	m_cpt_icache_dir_read++;
1814	#endif
1815	uint32_t inst;
1816	size_t way;
1817	size_t set;
1818	size_t word;
1819	bool hit = r_icache.read(paddr,
1820	&inst,
1821	&way,
1822	&set,
1823	&word);
1824	r_icache_cc_way = way;
1825	r_icache_cc_set = set;
1826
1827	if ( hit and r_tgt_update.read() ) // hit update
1828	{
1829	r_icache_fsm = ICACHE_CC_UPDT;
1830	r_icache_cc_word = r_tgt_word_min.read();
1831	}
1832	else if ( hit and not r_tgt_update.read() ) // hit inval
1833	{
1834	r_icache_fsm = ICACHE_CC_INVAL;
1835	}
1836	else // miss can happen
1837	{
1838	r_tgt_icache_req = false;
1839	r_tgt_icache_rsp = r_tgt_update.read();
1840	r_icache_fsm = r_icache_fsm_save.read();
1841	}
1842	}
1843	break;
1844	}
1845
1846	/////////////////////
1847	case ICACHE_CC_INVAL: // invalidate a cache line
1848	{
1849	paddr_t nline;
1850	bool hit;
1851	hit = r_icache.inval( r_icache_cc_way.read(),
1852	r_icache_cc_set.read(),
1853	&nline );
1854	assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
1855	r_tgt_icache_req = false;
1856	r_tgt_icache_rsp = true;
1857	r_icache_fsm = r_icache_fsm_save.read();
1858	break;
1859	}
1860	////////////////////
1861	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1862	{
1863	size_t word = r_icache_cc_word.read();
1864	size_t way = r_icache_cc_way.read();
1865	size_t set = r_icache_cc_set.read();
1866
1867	r_icache.write( way,
1868	set,
1869	word,
1870	r_tgt_buf[word],
1871	r_tgt_be[word] );
1872
1873	r_icache_cc_word = word+1;
1874
1875	if ( word == r_tgt_word_max.read() ) // last word
1876	{
1877	r_tgt_icache_req = false;
1878	r_tgt_icache_rsp = true;
1879	r_icache_fsm = r_icache_fsm_save.read();
1880	}
1881	break;
1882	}
1883
1884	} // end switch r_icache_fsm
1885
1886	////////////////////////////////////////////////////////////////////////////////////
1887	// DCACHE FSM
1888	//
1889	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1890	// the cacheability, depending on the MMU mode.
1891	//
1892	// 1/ Coherence requests :
1893	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1894	// requesting a line invalidation or a line update.
1895	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1896	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1897	// goes to the CC_CHECK state to execute the requested action, and returns to the
1898	// pre-empted state.
1899	//
1900	// 2/ TLB miss
1901	// The page tables can be cacheable.
1902	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1903	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1904	// this sub-fsm implement the table-walk...
1905	//
1906	// 3/ processor requests :
1907	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1908	// The IDLE state implements a three stages pipe-line to handle write bursts:
1909	// - The physical address is computed by dtlb in stage P0.
1910	// - The registration in wbuf and the dcache hit are computed in stage P1.
1911	// - The dcache update is done in stage P2.
1912	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1913	// that is done (before handling the processor request) by a dedicated sub-fsm
1914	// (DCACHE_DIRTY_TLB_SET state).
1915	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1916	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1917	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1918	// (virtual address for itlb, and speculative physical address computed during
1919	// previous cycle for dcache) in order to return the data in one cycle for a READ
1920	// request. We just pay an extra cycle when the speculative access is failing.
1921	//
1922	// 4/ Atomic instructions LL/SC
1923	// The LL/SC address can be cacheable or non cacheable.
1924	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1925	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1926	// memory controller.
1927	// - LL requests from the processor are transmitted as standard VCI
1928	// READ transactions (one word / one line, depending on the cacheability).
1929	// - SC requests from the processor are systematically transmitted to the
1930	// memory cache as Compare&swap requests (both the data value stored in the
1931	// r_dcache_ll_data register and the new value).
1932	// The cache is not updated, as this is done in case of success by the
1933	// coherence transaction.
1934	//
1935	// 5/ Non cacheable access:
1936	// This component implement a strong order between non cacheable access
1937	// (read or write) : A new non cacheable VCI transaction starts only when
1938	// the previous non cacheable transaction is completed. Both cacheable and
1939	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1940	// a non cacheable write transaction posted in the write buffer by setting the
1941	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1942	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1943	// pending non cacheable write transaction completes).
1944	//
1945	// 6/ Error handling:
1946	// When the MMU is not activated, Read Bus Errors are synchronous events,
1947	// but Write Bus Errors are asynchronous events (processor is not frozen).
1948	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1949	// r_vci_rsp_data_error flip-flop, without writing any data in the
1950	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1951	// by the DCACHE FSM.
1952	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1953	// the asynchronous error using the setWriteBerr() method.
1954	// When the MMU is activated bus error are rare events, as the MMU
1955	// checks the physical address before the VCI transaction starts.
1956	////////////////////////////////////////////////////////////////////////////////////////
1957
1958	// default value for m_drsp
1959	m_drsp.valid = false;
1960	m_drsp.error = false;
1961	m_drsp.rdata = 0;
1962
1963	switch ( r_dcache_fsm.read() )
1964	{
1965	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1966	// 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1967	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1968	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1969	// 4) XTN request (processor) => DCACHE_XTN_*
1970	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1971	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1972	// 7) Uncacheable read (processor) => DCACHE_UNC_WAIT
1973	// 8) SC access (processor) => DCACHE_SC_WAIT
1974	//
1975	// The dtlb is unconditionally accessed to translate the
1976	// virtual adress from processor.
1977	//
1978	// There is 4 configurations to access the cache,
1979	// depending on the pipe-line state, defined
1980	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1981	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1982	// V0 / V1 / Data / Directory / comment
1983	// 0 / 0 / read(A0) / read(A0) / read speculative access
1984	// 0 / 1 / write(A2) / nop / read request delayed
1985	// 1 / 0 / nop / read(A1) / read request delayed
1986	// 1 / 1 / write(A2) / read(A1) / read request delayed
1987	{
1988	////////////////////////////////////////////////////////////////////////////////
1989	// Handling P2 pipe-line stage
1990	// Inputs are r_dcache_p1_* registers.
1991	// If r_dcache_p1_valid is true, we update the local copy in dcache.
1992	// If the modified cache line has copies in TLBs, we launch a TLB invalidate
1993	// operation, going to DCACHE_INVAL_TLB_SCAN state.
1994
1995	bool tlb_inval_required = false;
1996
1997	if ( r_dcache_p1_valid.read() ) // P2 stage activated
1998	{
1999	size_t way = r_dcache_p1_cache_way.read();
2000	size_t set = r_dcache_p1_cache_set.read();
2001	size_t word = r_dcache_p1_cache_word.read();
2002	uint32_t wdata = r_dcache_p1_wdata.read();
2003	vci_be_t be = r_dcache_p1_be.read();
2004
2005	r_dcache.write( way,
2006	set,
2007	word,
2008	wdata,
2009	be );
2010	#ifdef INSTRUMENTATION
2011	m_cpt_dcache_data_write++;
2012	#endif
2013	// cache update after a WRITE hit can require itlb & dtlb inval or flush
2014	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2015	{
2016	tlb_inval_required = true;
2017	r_dcache_tlb_inval_count = 0;
2018	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>
2019	(uint32_log2(m_dcache_words<<2));
2020	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2021	}
2022	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2023	{
2024	r_itlb.reset();
2025	r_dtlb.reset();
2026	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2027	}
2028
2029	#if DEBUG_DCACHE
2030	if ( m_debug_dcache_fsm )
2031	{
2032	std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
2033	<< " / WAY = " << way
2034	<< " / SET = " << set
2035	<< " / WORD = " << word << std::hex
2036	<< " / DATA = " << wdata
2037	<< " / BE = " << be << std::endl;
2038	}
2039	#endif
2040	} // end P2 stage
2041
2042	///////////////////////////////////////////////////////////////////////////
2043	// Handling P1 pipe-line stage
2044	// Inputs are r_dcache_p0_* registers.
2045	// We must write into wbuf and test the hit in dcache.
2046	// If the write request is non cacheable, and there is a pending
2047	// non cacheable write, or if the write buffer is full, we break,
2048	// because the P0 and P1 pipe-line stages are frozen until the write
2049	// request registration is possible, but he P2 stage is not frozen.
2050	// The r_dcache_p1_valid bit must be computed at all cycles, and
2051	// the P2 stage must be activated if there is local copy in dcache.
2052
2053	if ( r_dcache_p0_valid.read() ) // P1 stage activated
2054	{
2055	// write not cacheable, and previous non cacheable write registered
2056	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2057	{
2058	r_dcache_p1_valid = false;
2059	break;
2060	}
2061
2062	// try a registration into write buffer
2063	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2064	r_dcache_p0_be.read(),
2065	r_dcache_p0_wdata.read(),
2066	r_dcache_p0_cacheable.read() );
2067	#ifdef INSTRUMENTATION
2068	m_cpt_wbuf_write++;
2069	#endif
2070	// write buffer full
2071	if ( not wok )
2072	{
2073	r_dcache_p1_valid = false;
2074	break;
2075	}
2076	// update the write_buffer state extension
2077	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2078
2079	// read directory to check local copy
2080	size_t cache_way;
2081	size_t cache_set;
2082	size_t cache_word;
2083	bool local_copy;
2084	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2085	{
2086	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2087	&cache_way,
2088	&cache_set,
2089	&cache_word );
2090	#ifdef INSTRUMENTATION
2091	m_cpt_dcache_dir_read++;
2092	#endif
2093	}
2094	else
2095	{
2096	local_copy = false;
2097	}
2098
2099	// store values for P2 pipe stage
2100	if ( local_copy )
2101	{
2102	r_dcache_p1_valid = true;
2103	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2104	r_dcache_p1_be = r_dcache_p0_be.read();
2105	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2106	r_dcache_p1_cache_way = cache_way;
2107	r_dcache_p1_cache_set = cache_set;
2108	r_dcache_p1_cache_word = cache_word;
2109	}
2110	else
2111	{
2112	r_dcache_p1_valid = false;
2113	}
2114	}
2115	else // P1 stage not activated
2116	{
2117	r_dcache_p1_valid = false;
2118	} // end P1 stage
2119
2120	/////////////////////////////////////////////////////////////////////////////////
2121	// handling P0 pipe-line stage
2122	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2123	// The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
2124	// - the TLB invalidate requests have the highest priority,
2125	// - then the external coherence requests,
2126	// - then the itlb miss requests,
2127	// - and finally the processor requests.
2128	// If dtlb is activated, there is an unconditionnal access to dtlb,
2129	// for address translation.
2130	// 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if
2131	// dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully
2132	// handled by the IDLE state), and the processor request is acknowledged.
2133	// 2) A processor READ or LL request generate a simultaneouss access to
2134	// both dcache data and dcache directoty, using speculative PPN, but
2135	// is delayed if the write pipe-line is not empty.
2136	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2137	// DCACHE_MISS_WAIT states.
2138	// 3) A processor SC request is delayed until the write pipe-line is empty.
2139	// A VCI SC transaction is launched, and we wait the VCI response in
2140	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2141	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2142	// The data is not modified in dcache, as it will be done by the
2143	// coherence transaction.
2144
2145	// TLB inval required after a write hit
2146	if ( tlb_inval_required )
2147	{
2148	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2149	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2150	r_dcache_p0_valid = false;
2151	}
2152	// external coherence request
2153	else if ( r_tgt_dcache_req.read() )
2154	{
2155	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2156	r_dcache_fsm = DCACHE_CC_CHECK;
2157	r_dcache_p0_valid = false;
2158	}
2159
2160	// itlb miss request
2161	else if ( r_icache_tlb_miss_req.read() )
2162	{
2163	r_dcache_tlb_ins = true;
2164	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2165	r_dcache_fsm = DCACHE_TLB_MISS;
2166	r_dcache_p0_valid = false;
2167	}
2168
2169	// processor request
2170	else if ( m_dreq.valid )
2171	{
2172	// dcache access using speculative PPN only if pipe-line empty
2173	paddr_t cache_paddr;
2174	size_t cache_way;
2175	size_t cache_set;
2176	size_t cache_word;
2177	uint32_t cache_rdata;
2178	bool cache_hit;
2179
2180	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2181	not r_dcache_p0_valid.read() and
2182	not r_dcache_p1_valid.read() ) // pipe-line empty
2183	{
2184	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2185	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2186
2187	cache_hit = r_dcache.read( cache_paddr,
2188	&cache_rdata,
2189	&cache_way,
2190	&cache_set,
2191	&cache_word );
2192	#ifdef INSTRUMENTATION
2193	m_cpt_dcache_dir_read++;
2194	m_cpt_dcache_data_read++;
2195	#endif
2196	}
2197	else
2198	{
2199	cache_hit = false;
2200	} // end dcache access
2201
2202	// systematic dtlb access using virtual address
2203	paddr_t tlb_paddr;
2204	pte_info_t tlb_flags;
2205	size_t tlb_way;
2206	size_t tlb_set;
2207	paddr_t tlb_nline;
2208	bool tlb_hit;
2209
2210	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2211	{
2212	tlb_hit = r_dtlb.translate( m_dreq.addr,
2213	&tlb_paddr,
2214	&tlb_flags,
2215	&tlb_nline,
2216	&tlb_way,
2217	&tlb_set );
2218	#ifdef INSTRUMENTATION
2219	m_cpt_dtlb_read++;
2220	#endif
2221	}
2222	else
2223	{
2224	tlb_hit = false;
2225	} // end dtlb access
2226
2227	// register the processor request
2228	r_dcache_p0_vaddr = m_dreq.addr;
2229	r_dcache_p0_be = m_dreq.be;
2230	r_dcache_p0_wdata = m_dreq.wdata;
2231
2232	// Handling READ XTN requests from processor
2233	// They are executed in this DCACHE_IDLE state.
2234	// The processor must not be in user mode
2235	if (m_dreq.type == iss_t::XTN_READ)
2236	{
2237	int xtn_opcode = (int)m_dreq.addr/4;
2238
2239	// checking processor mode:
2240	if (m_dreq.mode == iss_t::MODE_USER)
2241	{
2242	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2243	r_mmu_dbvar = m_dreq.addr;
2244	m_drsp.valid = true;
2245	m_drsp.error = true;
2246	r_dcache_fsm = DCACHE_IDLE;
2247	}
2248	else
2249	{
2250	switch( xtn_opcode )
2251	{
2252	case iss_t::XTN_INS_ERROR_TYPE:
2253	m_drsp.rdata = r_mmu_ietr.read();
2254	m_drsp.valid = true;
2255	break;
2256
2257	case iss_t::XTN_DATA_ERROR_TYPE:
2258	m_drsp.rdata = r_mmu_detr.read();
2259	m_drsp.valid = true;
2260	break;
2261
2262	case iss_t::XTN_INS_BAD_VADDR:
2263	m_drsp.rdata = r_mmu_ibvar.read();
2264	m_drsp.valid = true;
2265	break;
2266
2267	case iss_t::XTN_DATA_BAD_VADDR:
2268	m_drsp.rdata = r_mmu_dbvar.read();
2269	m_drsp.valid = true;
2270	break;
2271
2272	case iss_t::XTN_PTPR:
2273	m_drsp.rdata = r_mmu_ptpr.read();
2274	m_drsp.valid = true;
2275	break;
2276
2277	case iss_t::XTN_TLB_MODE:
2278	m_drsp.rdata = r_mmu_mode.read();
2279	m_drsp.valid = true;
2280	break;
2281
2282	case iss_t::XTN_MMU_PARAMS:
2283	m_drsp.rdata = r_mmu_params;
2284	m_drsp.valid = true;
2285	break;
2286
2287	case iss_t::XTN_MMU_RELEASE:
2288	m_drsp.rdata = r_mmu_release;
2289	m_drsp.valid = true;
2290	break;
2291
2292	case iss_t::XTN_MMU_WORD_LO:
2293	m_drsp.rdata = r_mmu_word_lo.read();
2294	m_drsp.valid = true;
2295	break;
2296
2297	case iss_t::XTN_MMU_WORD_HI:
2298	m_drsp.rdata = r_mmu_word_hi.read();
2299	m_drsp.valid = true;
2300	break;
2301
2302	default:
2303	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2304	r_mmu_dbvar = m_dreq.addr;
2305	m_drsp.valid = true;
2306	m_drsp.error = true;
2307	break;
2308	} // end switch xtn_opcode
2309	} // end else
2310	r_dcache_p0_valid = false;
2311	} // end if XTN_READ
2312
2313	// Handling WRITE XTN requests from processor.
2314	// They are not executed in this DCACHE_IDLE state,
2315	// if they require access to the caches or the TLBs
2316	// that are already accessed for speculative read.
2317	// Caches can be invalidated or flushed in user mode,
2318	// and the sync instruction can be executed in user mode
2319	else if (m_dreq.type == iss_t::XTN_WRITE)
2320	{
2321	int xtn_opcode = (int)m_dreq.addr/4;
2322	r_dcache_xtn_opcode = xtn_opcode;
2323
2324	// checking processor mode:
2325	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2326	(xtn_opcode != iss_t:: XTN_SYNC) &&
2327	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2328	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2329	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2330	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2331	{
2332	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2333	r_mmu_dbvar = m_dreq.addr;
2334	m_drsp.valid = true;
2335	m_drsp.error = true;
2336	r_dcache_fsm = DCACHE_IDLE;
2337	}
2338	else
2339	{
2340	switch( xtn_opcode )
2341	{
2342	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2343	r_mmu_ptpr = m_dreq.wdata;
2344	r_dcache_xtn_req = true;
2345	r_dcache_fsm = DCACHE_XTN_SWITCH;
2346	break;
2347
2348	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2349	r_mmu_mode = m_dreq.wdata;
2350	m_drsp.valid = true;
2351	r_dcache_fsm = DCACHE_IDLE;
2352	break;
2353
2354	case iss_t::XTN_DTLB_INVAL: // dtlb access
2355	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2356	break;
2357
2358	case iss_t::XTN_ITLB_INVAL: // itlb access
2359	r_dcache_xtn_req = true;
2360	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2361	break;
2362
2363	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2364	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2365	break;
2366
2367	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2368	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2369	if (sizeof(paddr_t) <= 32) {
2370	assert(r_mmu_word_hi.read() == 0 &&
2371	"high bits should be 0 for 32bit paddr");
2372	r_dcache_p0_paddr =
2373	(paddr_t)r_mmu_word_lo.read();
2374	} else {
2375	r_dcache_p0_paddr =
2376	(paddr_t)r_mmu_word_hi.read() << 32 \|
2377	(paddr_t)r_mmu_word_lo.read();
2378	}
2379	break;
2380
2381	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2382	r_dcache_flush_count = 0;
2383	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2384	break;
2385
2386	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2387	r_dcache_xtn_req = true;
2388	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2389	break;
2390
2391	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2392	r_dcache_xtn_req = true;
2393	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2394	break;
2395
2396	case iss_t::XTN_ICACHE_FLUSH: // icache access
2397	r_dcache_xtn_req = true;
2398	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2399	break;
2400
2401	case iss_t::XTN_SYNC: // wait until write buffer empty
2402	r_dcache_fsm = DCACHE_XTN_SYNC;
2403	break;
2404
2405	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2406	r_mmu_word_lo = m_dreq.wdata;
2407	m_drsp.valid = true;
2408	r_dcache_fsm = DCACHE_IDLE;
2409	break;
2410
2411	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2412	r_mmu_word_hi = m_dreq.wdata;
2413	m_drsp.valid = true;
2414	r_dcache_fsm = DCACHE_IDLE;
2415	break;
2416
2417	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2418	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2419	m_drsp.valid = true;
2420	r_dcache_fsm = DCACHE_IDLE;
2421	break;
2422
2423	default:
2424	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2425	r_mmu_dbvar = m_dreq.addr;
2426	m_drsp.valid = true;
2427	m_drsp.error = true;
2428	r_dcache_fsm = DCACHE_IDLE;
2429	break;
2430	} // end switch xtn_opcode
2431	} // end else
2432	r_dcache_p0_valid = false;
2433	} // end if XTN_WRITE
2434
2435	// Handling read/write/ll/sc processor requests.
2436	// The dtlb and dcache can be activated or not.
2437	// We compute the physical address, the cacheability, and check processor request.
2438	// - If DTLB not activated : cacheability is defined by the segment table,
2439	// the physical address is equal to the virtual address (identity mapping)
2440	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2441	// the physical address is obtained from the TLB, and the U & W bits
2442	// of the PTE are checked.
2443	// The processor request is decoded only if the TLB is not activated or if
2444	// the virtual address hits in tLB and access rights are OK.
2445	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2446	else
2447	{
2448	bool valid_req = false;
2449	bool cacheable = false;
2450	paddr_t paddr = 0;
2451
2452	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2453	{
2454	valid_req = true;
2455
2456	// cacheability
2457	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2458	else cacheable = m_cacheability_table[m_dreq.addr];
2459
2460	// physical address
2461	paddr = (paddr_t)m_dreq.addr;
2462	}
2463	else // dtlb activated
2464	{
2465	if ( tlb_hit ) // tlb hit
2466	{
2467	// cacheability
2468	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2469	else cacheable = tlb_flags.c;
2470
2471	// access rights checking
2472	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2473	{
2474	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2475	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2476	else
2477	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2478
2479	r_mmu_dbvar = m_dreq.addr;
2480	m_drsp.valid = true;
2481	m_drsp.error = true;
2482	m_drsp.rdata = 0;
2483	#if DEBUG_DCACHE
2484	if ( m_debug_dcache_fsm )
2485	{
2486	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2487	}
2488	#endif
2489	}
2490	else if ( not tlb_flags.w and
2491	((m_dreq.type == iss_t::DATA_WRITE) or
2492	(m_dreq.type == iss_t::DATA_SC)) )
2493	{
2494	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2495	r_mmu_dbvar = m_dreq.addr;
2496	m_drsp.valid = true;
2497	m_drsp.error = true;
2498	m_drsp.rdata = 0;
2499	#if DEBUG_DCACHE
2500	if ( m_debug_dcache_fsm )
2501	{
2502	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2503	}
2504	#endif
2505	}
2506	else
2507	{
2508	valid_req = true;
2509	}
2510
2511	// physical address
2512	paddr = tlb_paddr;
2513	}
2514	else // tlb miss
2515	{
2516	r_dcache_tlb_vaddr = m_dreq.addr;
2517	r_dcache_tlb_ins = false;
2518	r_dcache_fsm = DCACHE_TLB_MISS;
2519	}
2520	} // end DTLB activated
2521
2522	if ( valid_req ) // processor request is valid after TLB check
2523	{
2524	// physical address and cacheability registration
2525	r_dcache_p0_paddr = paddr;
2526	r_dcache_p0_cacheable = cacheable;
2527
2528	// READ or LL request
2529	// The read requests are taken only if the write pipe-line is empty.
2530	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2531	// If speculative access is KO we just pay one extra cycle.
2532	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2533	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2534	if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL))
2535	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2536	{
2537	if ( cacheable ) // cacheable read
2538	{
2539	// if the speculative access is illegal, we pay an extra cycle
2540	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2541	!= (paddr & ~PAGE_K_MASK))
2542	{
2543	#ifdef INSTRUMENTATION
2544	m_cpt_dcache_spec_miss++;
2545	#endif
2546	#if DEBUG_DCACHE
2547	if ( m_debug_dcache_fsm )
2548	{
2549	std::cout << " <PROC.DCACHE_IDLE> Speculative access miss" << std::endl;
2550	}
2551	#endif
2552	}
2553	// if cache miss, try to get the missing line
2554	else if ( not cache_hit )
2555	{
2556	#ifdef INSTRUMENTATION
2557	m_cpt_dcache_miss++;
2558	#endif
2559	r_dcache_vci_paddr = paddr;
2560	r_dcache_vci_miss_req = true;
2561	r_dcache_miss_type = PROC_MISS;
2562	r_dcache_fsm = DCACHE_MISS_VICTIM;
2563	}
2564	// if cache hit return the data
2565	else
2566	{
2567	#ifdef INSTRUMENTATION
2568	m_cpt_data_read++;
2569	#endif
2570	m_drsp.valid = true;
2571	m_drsp.rdata = cache_rdata;
2572	#if DEBUG_DCACHE
2573	if ( m_debug_dcache_fsm )
2574	{
2575	std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
2576	}
2577	#endif
2578	}
2579	}
2580	else // uncacheable read
2581	{
2582	r_dcache_vci_paddr = paddr;
2583	r_dcache_vci_unc_be = m_dreq.be;
2584	r_dcache_vci_unc_req = true;
2585	r_dcache_fsm = DCACHE_UNC_WAIT;
2586	}
2587
2588	// makes reservation in case of LL
2589	if ( m_dreq.type == iss_t::DATA_LL )
2590	{
2591	r_dcache_ll_valid = true;
2592	r_dcache_ll_data = cache_rdata;
2593	r_dcache_ll_vaddr = m_dreq.addr;
2594	}
2595	r_dcache_p0_valid = false;
2596	} // end READ or LL
2597
2598	// WRITE request:
2599	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2600	// the processor and set the Dirty bit before handling the write request.
2601	// If we don't need to set the Dirty bit, we can acknowledge
2602	// the processor request, as the write arguments (including the
2603	// physical address) are registered in r_dcache_p0 registers:
2604	// We simply activate the P1 pipeline stage.
2605	else if ( m_dreq.type == iss_t::DATA_WRITE )
2606	{
2607	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2608	and not tlb_flags.d ) // Dirty bit must be set
2609	{
2610	// The PTE physical address is obtained from the nline value (dtlb),
2611	// and the word index (proper bits of the virtual address)
2612	if ( tlb_flags.b ) // PTE1
2613	{
2614	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2615	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2616	}
2617	else // PTE2
2618	{
2619	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2620	(paddr_t)((m_dreq.addr>>9) & 0x38);
2621	}
2622	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2623	r_dcache_p0_valid = false;
2624	}
2625	else // Write request accepted
2626	{
2627	#ifdef INSTRUMENTATION
2628	m_cpt_data_write++;
2629	#endif
2630	m_drsp.valid = true;
2631	m_drsp.rdata = 0;
2632	r_dcache_p0_valid = true;
2633	}
2634	} // end WRITE
2635
2636	// SC request:
2637	// The SC requests are taken only if the write pipe-line is empty.
2638	// - if there is no valid registered LL, we just return rdata = 1
2639	// (atomic access failed) and the SC transaction is completed.
2640	// - if a valid LL reservation (with the same address) is registered,
2641	// we test if a DIRTY bit update is required.
2642	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2643	// the processor and set the Dirty bit before handling the write request.
2644	// If we don't need to set the Dirty bit, we request a SC transaction
2645	// to CMD FSM and go to DCACHE_SC_WAIT state, that will return
2646	// the response to the processor.
2647	// We don't check a possible write hit in dcache, as the cache update
2648	// is done by the coherence transaction induced by the SC...
2649	else if ( ( m_dreq.type == iss_t::DATA_SC )
2650	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2651	{
2652	if ( (r_dcache_ll_vaddr.read() != m_dreq.addr)
2653	or not r_dcache_ll_valid.read() ) // no valid registered LL
2654	{
2655	#ifdef INSTRUMENTATION
2656	m_cpt_data_sc++;
2657	#endif
2658	m_drsp.valid = true;
2659	m_drsp.rdata = 1;
2660	r_dcache_ll_valid = false;
2661	}
2662	else // valid registered LL
2663	{
2664	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2665	and not tlb_flags.d ) // Dirty bit must be set
2666	{
2667	// The PTE physical address is obtained from the nline value (dtlb),
2668	// and the word index (proper bits of the virtual address)
2669	if ( tlb_flags.b ) // PTE1
2670	{
2671	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2672	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2673	}
2674	else // PTE2
2675	{
2676	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2677	(paddr_t)((m_dreq.addr>>9) & 0x38);
2678	}
2679	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2680	}
2681	else // SC request accepted
2682	{
2683	#ifdef INSTRUMENTATION
2684	m_cpt_data_sc++;
2685	#endif
2686
2687	r_dcache_vci_paddr = paddr;
2688	r_dcache_vci_sc_req = true;
2689	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2690	r_dcache_vci_sc_new = m_dreq.wdata;
2691	r_dcache_ll_valid = false;
2692	r_dcache_fsm = DCACHE_SC_WAIT;
2693	}
2694	}
2695	r_dcache_p0_valid = false;
2696	} // end SC
2697	else
2698	{
2699	r_dcache_p0_valid = false;
2700	}
2701	} // end valid_req
2702	else
2703	{
2704	r_dcache_p0_valid = false;
2705	}
2706	} // end if read/write/ll/sc request
2707	} // end dreq.valid
2708	else
2709	{
2710	r_dcache_p0_valid = false;
2711	} // end P0 pipe stage
2712	break;
2713	}
2714	/////////////////////
2715	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2716	// Input arguments are:
2717	// - r_dcache_tlb_vaddr
2718	// - r_dcache_tlb_ins (true when itlb miss)
2719	// The sub-fsm access the dcache to find the missing TLB entry,
2720	// and activates the cache miss procedure in case of miss.
2721	// It bypass the first level page table access if possible.
2722	// It uses atomic access to update the R/L access bits
2723	// in the page table if required.
2724	// It directly updates the itlb or dtlb, and writes into the
2725	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2726	{
2727	uint32_t ptba = 0;
2728	bool bypass;
2729	paddr_t pte_paddr;
2730
2731	// evaluate bypass in order to skip first level page table access
2732	if ( r_dcache_tlb_ins.read() ) // itlb miss
2733	{
2734	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2735	}
2736	else // dtlb miss
2737	{
2738	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2739	}
2740
2741	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2742	{
2743	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2744	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2745	r_dcache_tlb_paddr = pte_paddr;
2746	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2747	}
2748	else // Try to read PTE2 in dcache
2749	{
2750	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2751	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2752	r_dcache_tlb_paddr = pte_paddr;
2753	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2754	}
2755
2756	#if DEBUG_DCACHE
2757	if ( m_debug_dcache_fsm )
2758	{
2759	if ( r_dcache_tlb_ins.read() )
2760	{
2761	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss";
2762	}
2763	else
2764	{
2765	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss";
2766	}
2767	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2768	<< " / BYPASS = " << bypass
2769	<< " / PTE_ADR = " << pte_paddr << std::endl;
2770	}
2771	#endif
2772
2773	break;
2774	}
2775	/////////////////////////
2776	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2777	{
2778	uint32_t entry;
2779	size_t way;
2780	size_t set;
2781	size_t word;
2782
2783	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2784	&entry,
2785	&way,
2786	&set,
2787	&word );
2788	#ifdef INSTRUMENTATION
2789	m_cpt_dcache_data_read++;
2790	m_cpt_dcache_dir_read++;
2791	#endif
2792	if ( hit ) // hit in dcache
2793	{
2794	if ( not (entry & PTE_V_MASK) ) // unmapped
2795	{
2796	if ( r_dcache_tlb_ins.read() )
2797	{
2798	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2799	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2800	r_icache_tlb_miss_req = false;
2801	r_icache_tlb_rsp_error = true;
2802	}
2803	else
2804	{
2805	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2806	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2807	m_drsp.valid = true;
2808	m_drsp.error = true;
2809	}
2810	r_dcache_fsm = DCACHE_IDLE;
2811
2812	#if DEBUG_DCACHE
2813	if ( m_debug_dcache_fsm )
2814	{
2815	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2816	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2817	<< std::dec << " / way = " << way
2818	<< std::dec << " / set = " << set
2819	<< std::dec << " / word = " << word
2820	<< std::hex << " / PTE1 = " << entry << std::endl;
2821	}
2822	#endif
2823
2824	}
2825	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2826	{
2827	// mark the cache line ac containing a PTD
2828	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2829
2830	// register bypass
2831	if ( r_dcache_tlb_ins.read() ) // itlb
2832	{
2833	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2834	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2835	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2836	}
2837	else // dtlb
2838	{
2839	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2840	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2841	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2842	}
2843	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2844	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2845	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2846
2847	#if DEBUG_DCACHE
2848	if ( m_debug_dcache_fsm )
2849	{
2850	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2851	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2852	<< std::dec << " / way = " << way
2853	<< std::dec << " / set = " << set
2854	<< std::dec << " / word = " << word
2855	<< std::hex << " / PTD = " << entry << std::endl;
2856	}
2857	#endif
2858	}
2859	else // PTE1 : we must update the TLB
2860	{
2861	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2862	r_dcache_tlb_pte_flags = entry;
2863	r_dcache_tlb_cache_way = way;
2864	r_dcache_tlb_cache_set = set;
2865	r_dcache_tlb_cache_word = word;
2866	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2867
2868	#if DEBUG_DCACHE
2869	if ( m_debug_dcache_fsm )
2870	{
2871	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2872	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2873	<< std::dec << " / way = " << way
2874	<< std::dec << " / set = " << set
2875	<< std::dec << " / word = " << word
2876	<< std::hex << " / PTE1 = " << entry << std::endl;
2877	}
2878	#endif
2879	}
2880	}
2881	else // we must load the missing cache line in dcache
2882	{
2883	r_dcache_vci_miss_req = true;
2884	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2885	r_dcache_miss_type = PTE1_MISS;
2886	r_dcache_fsm = DCACHE_MISS_VICTIM;
2887
2888	#if DEBUG_DCACHE
2889	if ( m_debug_dcache_fsm )
2890	{
2891	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2892	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2893	}
2894	#endif
2895	}
2896	break;
2897	}
2898	////////////////////////////
2899	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2900	{
2901	size_t way;
2902	size_t set;
2903
2904	if ( r_dcache_tlb_ins.read() )
2905	{
2906	r_itlb.select( r_dcache_tlb_vaddr.read(),
2907	true, // PTE1
2908	&way,
2909	&set );
2910	#ifdef INSTRUMENTATION
2911	m_cpt_itlb_read++;
2912	#endif
2913	}
2914	else
2915	{
2916	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2917	true, // PTE1
2918	&way,
2919	&set );
2920	#ifdef INSTRUMENTATION
2921	m_cpt_dtlb_read++;
2922	#endif
2923	}
2924	r_dcache_tlb_way = way;
2925	r_dcache_tlb_set = set;
2926	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2927
2928	#if DEBUG_DCACHE
2929	if ( m_debug_dcache_fsm )
2930	{
2931	if ( r_dcache_tlb_ins.read() )
2932	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2933	else
2934	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2935	std::cout << " way = " << std::dec << way
2936	<< " / set = " << set << std::endl;
2937	}
2938	#endif
2939	break;
2940	}
2941	//////////////////////////
2942	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2943	// if L/R bit already set, exit the sub-fsm
2944	// if not, the page table must be updated
2945	{
2946	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2947	uint32_t pte = r_dcache_tlb_pte_flags.read();
2948	bool updt = false;
2949	bool local = true;
2950
2951	// We should compute the access locality:
2952	// The PPN MSB bits define the destination cluster index.
2953	// The m_srcid_d MSB bits define the source cluster index.
2954	// The number of bits to compare depends on the number of clusters,
2955	// and can be obtained in the mapping table.
2956	// As long as this computation is not done, all access are local.
2957
2958	if ( local ) // local access
2959	{
2960	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2961	{
2962	updt = true;
2963	r_dcache_vci_sc_old = pte;
2964	r_dcache_vci_sc_new = pte \| PTE_L_MASK;
2965	pte = pte \| PTE_L_MASK;
2966	}
2967	}
2968	else // remote access
2969	{
2970	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2971	{
2972	updt = true;
2973	r_dcache_vci_sc_old = pte;
2974	r_dcache_vci_sc_new = pte \| PTE_R_MASK;
2975	pte = pte \| PTE_R_MASK;
2976	}
2977	}
2978
2979	// update TLB
2980	if ( r_dcache_tlb_ins.read() )
2981	{
2982	r_itlb.write( true, // 2M page
2983	pte,
2984	0, // argument unused for a PTE1
2985	r_dcache_tlb_vaddr.read(),
2986	r_dcache_tlb_way.read(),
2987	r_dcache_tlb_set.read(),
2988	nline );
2989	#ifdef INSTRUMENTATION
2990	m_cpt_itlb_write++;
2991	#endif
2992	}
2993	else
2994	{
2995	r_dtlb.write( true, // 2M page
2996	pte,
2997	0, // argument unused for a PTE1
2998	r_dcache_tlb_vaddr.read(),
2999	r_dcache_tlb_way.read(),
3000	r_dcache_tlb_set.read(),
3001	nline );
3002	#ifdef INSTRUMENTATION
3003	m_cpt_dtlb_write++;
3004	#endif
3005	}
3006	// next state
3007	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3008	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3009
3010	#if DEBUG_DCACHE
3011	if ( m_debug_dcache_fsm )
3012	{
3013	if ( r_dcache_tlb_ins.read() )
3014	{
3015	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3016	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3017	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3018	r_itlb.printTrace();
3019	}
3020	else
3021	{
3022	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3023	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3024	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3025	r_dtlb.printTrace();
3026	}
3027
3028	}
3029	#endif
3030	break;
3031	}
3032	/////////////////////////
3033	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3034	{
3035	uint32_t pte_flags;
3036	uint32_t pte_ppn;
3037	size_t way;
3038	size_t set;
3039	size_t word;
3040
3041	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3042	&pte_flags,
3043	&pte_ppn,
3044	&way,
3045	&set,
3046	&word );
3047	#ifdef INSTRUMENTATION
3048	m_cpt_dcache_data_read++;
3049	m_cpt_dcache_dir_read++;
3050	#endif
3051	if ( hit ) // request hits in dcache
3052	{
3053	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3054	{
3055	if ( r_dcache_tlb_ins.read() )
3056	{
3057	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3058	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3059	r_icache_tlb_miss_req = false;
3060	r_icache_tlb_rsp_error = true;
3061	}
3062	else
3063	{
3064	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3065	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3066	m_drsp.valid = true;
3067	m_drsp.error = true;
3068	}
3069	r_dcache_fsm = DCACHE_IDLE;
3070
3071	#if DEBUG_DCACHE
3072	if ( m_debug_dcache_fsm )
3073	{
3074	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3075	<< " PTE_FLAGS = " << std::hex << pte_flags
3076	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3077	}
3078	#endif
3079	}
3080	else // mapped : we must update the TLB
3081	{
3082	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3083	r_dcache_tlb_pte_flags = pte_flags;
3084	r_dcache_tlb_pte_ppn = pte_ppn;
3085	r_dcache_tlb_cache_way = way;
3086	r_dcache_tlb_cache_set = set;
3087	r_dcache_tlb_cache_word = word;
3088	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3089
3090	#if DEBUG_DCACHE
3091	if ( m_debug_dcache_fsm )
3092	{
3093	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3094	<< " PTE_FLAGS = " << std::hex << pte_flags
3095	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3096	}
3097	#endif
3098	}
3099	}
3100	else // we must load the missing cache line in dcache
3101	{
3102	r_dcache_fsm = DCACHE_MISS_VICTIM;
3103	r_dcache_vci_miss_req = true;
3104	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3105	r_dcache_miss_type = PTE2_MISS;
3106
3107	#if DEBUG_DCACHE
3108	if ( m_debug_dcache_fsm )
3109	{
3110	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3111	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3112	}
3113	#endif
3114	}
3115	break;
3116	}
3117	////////////////////////////
3118	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3119	{
3120	size_t way;
3121	size_t set;
3122
3123	if ( r_dcache_tlb_ins.read() )
3124	{
3125	r_itlb.select( r_dcache_tlb_vaddr.read(),
3126	false, // PTE2
3127	&way,
3128	&set );
3129	#ifdef INSTRUMENTATION
3130	m_cpt_itlb_read++;
3131	#endif
3132	}
3133	else
3134	{
3135	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3136	false, // PTE2
3137	&way,
3138	&set );
3139	#ifdef INSTRUMENTATION
3140	m_cpt_dtlb_read++;
3141	#endif
3142	}
3143
3144	#if DEBUG_DCACHE
3145	if ( m_debug_dcache_fsm )
3146	{
3147	if ( r_dcache_tlb_ins.read() )
3148	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3149	else
3150	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3151	std::cout << " way = " << std::dec << way
3152	<< " / set = " << set << std::endl;
3153	}
3154	#endif
3155	r_dcache_tlb_way = way;
3156	r_dcache_tlb_set = set;
3157	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3158	break;
3159	}
3160	//////////////////////////
3161	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3162	// if L/R bit already set, exit the sub-fsm
3163	// if not, the page table must be updated by an atomic access
3164	{
3165	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3166	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3167	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3168	bool updt = false;
3169	bool local = true;
3170
3171	// We should compute the access locality:
3172	// The PPN MSB bits define the destination cluster index.
3173	// The m_srcid_d MSB bits define the source cluster index.
3174	// The number of bits to compare depends on the number of clusters,
3175	// and can be obtained in the mapping table.
3176	// As long as this computation is not done, all access are local.
3177
3178	if ( local ) // local access
3179	{
3180	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3181	{
3182	updt = true;
3183	r_dcache_vci_sc_old = pte_flags;
3184	r_dcache_vci_sc_new = pte_flags \| PTE_L_MASK;
3185	pte_flags = pte_flags \| PTE_L_MASK;
3186	}
3187	}
3188	else // remote access
3189	{
3190	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3191	{
3192	updt = true;
3193	r_dcache_vci_sc_old = pte_flags;
3194	r_dcache_vci_sc_new = pte_flags \| PTE_R_MASK;
3195	pte_flags = pte_flags \| PTE_R_MASK;
3196	}
3197	}
3198
3199	// update TLB for a PTE2
3200	if ( r_dcache_tlb_ins.read() )
3201	{
3202	r_itlb.write( false, // 4K page
3203	pte_flags,
3204	pte_ppn,
3205	r_dcache_tlb_vaddr.read(),
3206	r_dcache_tlb_way.read(),
3207	r_dcache_tlb_set.read(),
3208	nline );
3209	#ifdef INSTRUMENTATION
3210	m_cpt_itlb_write++;
3211	#endif
3212	}
3213	else
3214	{
3215	r_dtlb.write( false, // 4K page
3216	pte_flags,
3217	pte_ppn,
3218	r_dcache_tlb_vaddr.read(),
3219	r_dcache_tlb_way.read(),
3220	r_dcache_tlb_set.read(),
3221	nline );
3222	#ifdef INSTRUMENTATION
3223	m_cpt_dtlb_write++;
3224	#endif
3225	}
3226
3227	#if DEBUG_DCACHE
3228	if ( m_debug_dcache_fsm )
3229	{
3230	if ( r_dcache_tlb_ins.read() )
3231	{
3232	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3233	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3234	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3235	r_itlb.printTrace();
3236	}
3237	else
3238	{
3239	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3240	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3241	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3242	r_dtlb.printTrace();
3243	}
3244	}
3245	#endif
3246	// next state
3247	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3248	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3249	break;
3250	}
3251	////////////////////////
3252	case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit),
3253	// request a SC transaction to CMD FSM
3254	{
3255	#if DEBUG_DCACHE
3256	if ( m_debug_dcache_fsm )
3257	{
3258	std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3259	}
3260	#endif
3261	r_dcache.write(r_dcache_tlb_cache_way.read(),
3262	r_dcache_tlb_cache_set.read(),
3263	r_dcache_tlb_cache_word.read(),
3264	r_dcache_tlb_pte_flags.read());
3265	#ifdef INSTRUMENTATION
3266	m_cpt_dcache_data_write++;
3267	#endif
3268	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3269	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3270	r_dcache_vci_sc_req = true;
3271	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3272	break;
3273	}
3274	////////////////////////
3275	case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction.
3276	// We consume the response in rsp FIFO,
3277	// and exit the sub-fsm, but we don't
3278	// analyse the response, because we don't
3279	// care if the L/R bit update is not done.
3280	// We must take the coherence requests because
3281	// there is a risk of dead-lock
3282
3283	{
3284	// external coherence request
3285	if ( r_tgt_dcache_req )
3286	{
3287	r_dcache_fsm = DCACHE_CC_CHECK;
3288	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3289	break;
3290	}
3291
3292	if ( r_vci_rsp_data_error.read() ) // bus error
3293	{
3294	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3295	std::cout << "This should not happen in this state" << std::endl;
3296	exit(0);
3297	}
3298	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3299	{
3300	#if DEBUG_DCACHE
3301	if ( m_debug_dcache_fsm )
3302	{
3303	std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3304	}
3305	#endif
3306	vci_rsp_fifo_dcache_get = true;
3307	r_dcache_fsm = DCACHE_TLB_RETURN;
3308	}
3309	break;
3310	}
3311	///////////////////////
3312	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3313	{
3314	#if DEBUG_DCACHE
3315	if ( m_debug_dcache_fsm )
3316	{
3317	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3318	}
3319	#endif
3320	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3321	r_dcache_fsm = DCACHE_IDLE;
3322	break;
3323	}
3324	///////////////////////
3325	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3326	{
3327	if ( not r_dcache_xtn_req.read() )
3328	{
3329	r_dtlb.flush();
3330	r_dcache_fsm = DCACHE_IDLE;
3331	m_drsp.valid = true;
3332	}
3333	break;
3334	}
3335	/////////////////////
3336	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3337	// The coherence request must be taken
3338	// as there is a risk of dead-lock
3339	{
3340	// external coherence request
3341	if ( r_tgt_dcache_req.read() )
3342	{
3343	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3344	r_dcache_fsm = DCACHE_CC_CHECK;
3345	}
3346
3347	if ( r_wbuf.empty() )
3348	{
3349	m_drsp.valid = true;
3350	r_dcache_fsm = DCACHE_IDLE;
3351	}
3352	break;
3353	}
3354	////////////////////////
3355	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3356	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3357	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3358	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3359	{
3360	// external coherence request
3361	if ( r_tgt_dcache_req )
3362	{
3363	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3364	r_dcache_fsm = DCACHE_CC_CHECK;
3365	break;
3366	}
3367
3368	// itlb miss request
3369	if ( r_icache_tlb_miss_req.read() )
3370	{
3371	r_dcache_tlb_ins = true;
3372	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3373	r_dcache_fsm = DCACHE_TLB_MISS;
3374	break;
3375	}
3376
3377	// test if XTN request to icache completed
3378	if ( not r_dcache_xtn_req.read() )
3379	{
3380	r_dcache_fsm = DCACHE_IDLE;
3381	m_drsp.valid = true;
3382	}
3383	break;
3384	}
3385	/////////////////////////
3386	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3387	// the r_dcache_flush counter as a slot counter.
3388	// We loop in this state until all slots have been visited.
3389	// A cleanup request is generated for each valid line
3390	// and we are blocked until the previous cleanup is completed
3391	// Finally, both the itlb and dtlb are flushed
3392	// (including global entries)
3393	{
3394	if ( not r_dcache_cleanup_req )
3395	{
3396	paddr_t nline;
3397	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3398	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3399
3400	bool cleanup_req = r_dcache.inval( way,
3401	set,
3402	&nline );
3403	if ( cleanup_req )
3404	{
3405	r_dcache_cleanup_req = true;
3406	r_dcache_cleanup_line = nline;
3407	}
3408
3409	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3410	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3411
3412	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3413
3414	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last
3415	{
3416	r_dtlb.reset();
3417	r_itlb.reset();
3418	r_dcache_fsm = DCACHE_IDLE;
3419	m_drsp.valid = true;
3420	}
3421	}
3422	break;
3423	}
3424	/////////////////////////
3425	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3426	{
3427	r_dtlb.inval(r_dcache_p0_wdata.read());
3428	r_dcache_fsm = DCACHE_IDLE;
3429	m_drsp.valid = true;
3430	break;
3431	}
3432	////////////////////////////
3433	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3434	// requires 3 cycles: access tlb, read cache, inval cache
3435	// we compute the physical address in this state
3436	{
3437	paddr_t paddr;
3438	bool hit;
3439
3440	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3441	{
3442	#ifdef INSTRUMENTATION
3443	m_cpt_dtlb_read++;
3444	#endif
3445	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3446	&paddr );
3447	}
3448	else // dtlb not activated
3449	{
3450	paddr = (paddr_t)r_dcache_p0_wdata.read();
3451	hit = true;
3452	}
3453
3454	if ( hit ) // tlb hit
3455	{
3456	r_dcache_p0_paddr = paddr;
3457	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3458	}
3459	else // tlb miss
3460	{
3461	#ifdef INSTRUMENTATION
3462	m_cpt_dtlb_miss++;
3463	#endif
3464	r_dcache_tlb_ins = false; // dtlb
3465	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3466	r_dcache_fsm = DCACHE_TLB_MISS;
3467	}
3468
3469	#if DEBUG_DCACHE
3470	if ( m_debug_dcache_fsm )
3471	{
3472	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3473	<< " / VADDR = " << r_dcache_p0_wdata.read()
3474	<< " / PADDR = " << paddr << std::endl;
3475	}
3476	#endif
3477
3478	break;
3479	}
3480	////////////////////////////
3481	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3482	// requires 2 cycles: read cache / inval cache
3483	// In this state we read dcache.
3484	{
3485	uint32_t data;
3486	size_t way;
3487	size_t set;
3488	size_t word;
3489	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3490	&data,
3491	&way,
3492	&set,
3493	&word );
3494	#ifdef INSTRUMENTATION
3495	m_cpt_dcache_data_read++;
3496	m_cpt_dcache_dir_read++;
3497	#endif
3498	if ( hit ) // inval to be done
3499	{
3500	r_dcache_xtn_way = way;
3501	r_dcache_xtn_set = set;
3502	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3503	}
3504	else // miss : nothing to do
3505	{
3506	r_dcache_fsm = DCACHE_IDLE;
3507	m_drsp.valid = true;
3508	}
3509
3510	#if DEBUG_DCACHE
3511	if ( m_debug_dcache_fsm )
3512	{
3513	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3514	<< " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
3515	<< " / HIT = " << hit
3516	<< " / SET = " << set
3517	<< " / WAY = " << way << std::endl;
3518	}
3519	#endif
3520	break;
3521	}
3522	////////////////////////////
3523	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3524	// Blocked if previous cleanup not completed
3525	// Test if itlb or dtlb inval is required
3526	{
3527	if ( not r_dcache_cleanup_req.read() )
3528	{
3529	paddr_t nline;
3530	size_t way = r_dcache_xtn_way.read();
3531	size_t set = r_dcache_xtn_set.read();
3532	bool hit;
3533
3534	hit = r_dcache.inval( way,
3535	set,
3536	&nline );
3537	assert(hit && "XTN_DC_INVAL way/set should still be in cache");
3538
3539	// request cleanup
3540	r_dcache_cleanup_req = true;
3541	r_dcache_cleanup_line = nline;
3542
3543	// possible itlb & dtlb invalidate
3544	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3545	{
3546	r_dcache_tlb_inval_line = nline;
3547	r_dcache_tlb_inval_count = 0;
3548	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3549	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3550	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3551	}
3552	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3553	{
3554	r_itlb.reset();
3555	r_dtlb.reset();
3556	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3557	r_dcache_fsm = DCACHE_IDLE;
3558	m_drsp.valid = true;
3559	}
3560	else
3561	{
3562	r_dcache_fsm = DCACHE_IDLE;
3563	m_drsp.valid = true;
3564	}
3565
3566	#if DEBUG_DCACHE
3567	if ( m_debug_dcache_fsm )
3568	{
3569	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3570	<< " / NLINE = " << nline << std::endl;
3571	}
3572	#endif
3573	}
3574	break;
3575	}
3576	//////////////////////////////
3577	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3578	{
3579	r_dcache_fsm = DCACHE_IDLE;
3580	m_drsp.valid = true;
3581	break;
3582	}
3583	////////////////////////
3584	case DCACHE_MISS_VICTIM: // Selects a victim line if there is no pending cleanup
3585	// on the missing line, and if a new cleanup can be posted.
3586	// Set the r_dcache_cleanup_req flip-flop if required
3587	{
3588	size_t index; // unused
3589	bool hit = r_cleanup_buffer.hit( r_dcache_vci_paddr.read()>>(uint32_log2(m_dcache_words)+2), &index );
3590	if ( not hit and not r_dcache_cleanup_req.read() )
3591	{
3592	bool valid;
3593	size_t way;
3594	size_t set;
3595	paddr_t victim;
3596
3597	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3598	&victim,
3599	&way,
3600	&set );
3601	r_dcache_miss_way = way;
3602	r_dcache_miss_set = set;
3603
3604	if ( valid )
3605	{
3606	r_dcache_cleanup_req = true;
3607	r_dcache_cleanup_line = victim;
3608	r_dcache_fsm = DCACHE_MISS_INVAL;
3609	}
3610	else
3611	{
3612	r_dcache_fsm = DCACHE_MISS_WAIT;
3613	}
3614
3615	#if DEBUG_DCACHE
3616	if ( m_debug_dcache_fsm )
3617	{
3618	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::dec
3619	<< " / WAY = " << way
3620	<< " / SET = " << set
3621	<< " / VALID = " << valid
3622	<< " / LINE = " << std::hex << victim << std::endl;
3623	}
3624	#endif
3625	}
3626	break;
3627	}
3628	///////////////////////
3629	case DCACHE_MISS_INVAL: // invalidate the victim line
3630	// and possibly request itlb or dtlb invalidate
3631	{
3632	paddr_t nline;
3633	size_t way = r_dcache_miss_way.read();
3634	size_t set = r_dcache_miss_set.read();
3635	bool hit;
3636
3637	hit = r_dcache.inval( way,
3638	set,
3639	&nline );
3640
3641	assert(hit && "selected way/set line should be in dcache");
3642
3643	#if DEBUG_DCACHE
3644	if ( m_debug_dcache_fsm )
3645	{
3646	std::cout << " <PROC.DCACHE_MISS_INVAL> inval line:" << std::dec
3647	<< " / way = " << way
3648	<< " / set = " << set
3649	<< " / nline = " << std::hex << nline << std::endl;
3650	}
3651	#endif
3652	// if selective itlb & dtlb invalidate are required
3653	// the miss response is not handled before invalidate completed
3654	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3655	{
3656	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3657	r_dcache_tlb_inval_line = nline;
3658	r_dcache_tlb_inval_count = 0;
3659	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3660	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3661	}
3662	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3663	{
3664	r_itlb.reset();
3665	r_dtlb.reset();
3666	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3667	r_dcache_fsm = DCACHE_MISS_WAIT;
3668	}
3669	else
3670	{
3671	r_dcache_fsm = DCACHE_MISS_WAIT;
3672	}
3673	break;
3674	}
3675	//////////////////////
3676	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3677	// This state is in charge of error signaling
3678	// There is 5 types of error depending on the requester
3679	{
3680	// external coherence request
3681	if ( r_tgt_dcache_req )
3682	{
3683	r_dcache_fsm_cc_save = r_dcache_fsm;
3684	r_dcache_fsm = DCACHE_CC_CHECK;
3685	break;
3686	}
3687
3688	if ( r_vci_rsp_data_error.read() ) // bus error
3689	{
3690	switch ( r_dcache_miss_type.read() )
3691	{
3692	case PROC_MISS:
3693	{
3694	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3695	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3696	m_drsp.valid = true;
3697	m_drsp.error = true;
3698	r_dcache_fsm = DCACHE_IDLE;
3699	break;
3700	}
3701	case PTE1_MISS:
3702	{
3703	if ( r_dcache_tlb_ins.read() )
3704	{
3705	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3706	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3707	r_icache_tlb_miss_req = false;
3708	r_icache_tlb_rsp_error = true;
3709	}
3710	else
3711	{
3712	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3713	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3714	m_drsp.valid = true;
3715	m_drsp.error = true;
3716	}
3717	r_dcache_fsm = DCACHE_IDLE;
3718	break;
3719	}
3720	case PTE2_MISS:
3721	{
3722	if ( r_dcache_tlb_ins.read() )
3723	{
3724	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3725	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3726	r_icache_tlb_miss_req = false;
3727	r_icache_tlb_rsp_error = true;
3728	}
3729	else
3730	{
3731	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3732	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3733	m_drsp.valid = true;
3734	m_drsp.error = true;
3735	}
3736	r_dcache_fsm = DCACHE_IDLE;
3737	break;
3738	}
3739	} // end switch type
3740	r_vci_rsp_data_error = false;
3741	}
3742	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3743	{
3744	r_dcache_miss_word = 0;
3745	r_dcache_fsm = DCACHE_MISS_UPDT;
3746	}
3747	break;
3748	}
3749	//////////////////////
3750	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3751	// returns the response depending on the miss type
3752	{
3753	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3754	{
3755	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3756	// pop the FIFO, without cache update
3757	// send a cleanup for the missing line
3758	// if the previous cleanup is completed
3759	{
3760	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3761	{
3762	vci_rsp_fifo_dcache_get = true;
3763	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3764	}
3765	else // last word
3766	{
3767	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3768	{
3769	vci_rsp_fifo_dcache_get = true;
3770	r_dcache_cleanup_req = true;
3771	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3772	(uint32_log2(m_dcache_words)+2);
3773	r_dcache_miss_inval = false;
3774	r_dcache_fsm = DCACHE_IDLE;
3775	}
3776	}
3777	}
3778	else // No matching coherence request
3779	// pop the FIFO and update the cache
3780	// update the directory at the last word
3781	{
3782	size_t way = r_dcache_miss_way.read();
3783	size_t set = r_dcache_miss_set.read();
3784	size_t word = r_dcache_miss_word.read();
3785
3786	#ifdef INSTRUMENTATION
3787	m_cpt_dcache_data_write++;
3788	#endif
3789	r_dcache.write( way,
3790	set,
3791	word,
3792	r_vci_rsp_fifo_dcache.read());
3793
3794	vci_rsp_fifo_dcache_get = true;
3795	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3796
3797	// if last word, update directory, set in_tlb & contains_ptd bits
3798	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3799	{
3800
3801	#ifdef INSTRUMENTATION
3802	m_cpt_dcache_dir_write++;
3803	#endif
3804	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3805	r_dcache_miss_way.read(),
3806	r_dcache_miss_set.read() );
3807
3808	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3809	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3810
3811	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3812	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3813	else r_dcache_fsm = DCACHE_IDLE;
3814	}
3815	}
3816
3817	#if DEBUG_DCACHE
3818	if ( m_debug_dcache_fsm )
3819	{
3820	if ( r_dcache_miss_inval.read() )
3821	{
3822	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3823	{
3824	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3825	<< " pop the FIFO, don't update the cache" << std::endl;
3826	}
3827	else
3828	{
3829	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3830	<< " last word : send a cleanup request " << std::endl;
3831	}
3832	}
3833	else
3834	{
3835	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3836	<< " address = " << std::hex << r_dcache_vci_paddr.read()
3837	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3838	<< " / way = " << std::dec << r_dcache_miss_way.read()
3839	<< " / set = " << r_dcache_miss_set.read()
3840	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3841	}
3842	}
3843	#endif
3844
3845	} // end if rok
3846	break;
3847	}
3848	/////////////////////
3849	case DCACHE_UNC_WAIT:
3850	{
3851	// external coherence request
3852	if ( r_tgt_dcache_req.read() )
3853	{
3854	r_dcache_fsm_cc_save = r_dcache_fsm;
3855	r_dcache_fsm = DCACHE_CC_CHECK;
3856	break;
3857	}
3858
3859	if ( r_vci_rsp_data_error.read() ) // bus error
3860	{
3861	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3862	r_mmu_dbvar = m_dreq.addr;
3863	r_vci_rsp_data_error = false;
3864	m_drsp.error = true;
3865	m_drsp.valid = true;
3866	r_dcache_fsm = DCACHE_IDLE;
3867	break;
3868	}
3869	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3870	{
3871	vci_rsp_fifo_dcache_get = true;
3872	r_dcache_fsm = DCACHE_IDLE;
3873	// we acknowledge the processor request if it has not been modified
3874	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
3875	{
3876	m_drsp.valid = true;
3877	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3878	}
3879	}
3880	break;
3881	}
3882	////////////////////
3883	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
3884	{
3885	// external coherence request
3886	if ( r_tgt_dcache_req.read() )
3887	{
3888	r_dcache_fsm_cc_save = r_dcache_fsm;
3889	r_dcache_fsm = DCACHE_CC_CHECK;
3890	break;
3891	}
3892
3893	if ( r_vci_rsp_data_error.read() ) // bus error
3894	{
3895	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3896	r_mmu_dbvar = m_dreq.addr;
3897	r_vci_rsp_data_error = false;
3898	m_drsp.error = true;
3899	m_drsp.valid = true;
3900	r_dcache_fsm = DCACHE_IDLE;
3901	break;
3902	}
3903	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3904	{
3905	vci_rsp_fifo_dcache_get = true;
3906	m_drsp.valid = true;
3907	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3908	r_dcache_fsm = DCACHE_IDLE;
3909	}
3910	break;
3911	}
3912	//////////////////////////
3913	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
3914	// before handling a processor WRITE or SC request
3915	// Input argument is r_dcache_dirty_paddr
3916	// In this first state, we get PTE value in dcache
3917	// and post a SC request to CMD FSM
3918	{
3919	// get PTE in dcache
3920	uint32_t pte;
3921	size_t way;
3922	size_t set;
3923	size_t word; // unused
3924	bool hit = r_dcache.read( r_dcache_dirty_paddr.read(),
3925	&pte,
3926	&way,
3927	&set,
3928	&word );
3929	#ifdef INSTRUMENTATION
3930	m_cpt_dcache_data_read++;
3931	m_cpt_dcache_dir_read++;
3932	#endif
3933	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
3934
3935	// request sc transaction to CMD_FSM
3936	r_dcache_dirty_way = way;
3937	r_dcache_dirty_set = set;
3938	r_dcache_vci_sc_req = true;
3939	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
3940	r_dcache_vci_sc_old = pte;
3941	r_dcache_vci_sc_new = pte \| PTE_D_MASK;
3942	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
3943
3944	#if DEBUG_DCACHE
3945	if ( m_debug_dcache_fsm )
3946	{
3947	std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
3948	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
3949	<< " / PTE_VALUE = " << pte << std::dec
3950	<< " / CACHE_SET = " << set
3951	<< " / CACHE_WAY = " << way << std::endl;
3952	}
3953	#endif
3954	break;
3955	}
3956	//////////////////////////
3957	case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit
3958	// If PTE update is a success, return to IDLE state.
3959	// If PTE update is a failure, invalidate cache line
3960	// in DCACHE and invalidate the matching TLB entries.
3961	{
3962	// external coherence request
3963	if ( r_tgt_dcache_req )
3964	{
3965	r_dcache_fsm_cc_save = r_dcache_fsm;
3966	r_dcache_fsm = DCACHE_CC_CHECK;
3967	break;
3968	}
3969
3970	if ( r_vci_rsp_data_error.read() ) // bus error
3971	{
3972	std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl;
3973	std::cout << "This should not happen in this state" << std::endl;
3974	exit(0);
3975	}
3976	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3977	{
3978	vci_rsp_fifo_dcache_get = true;
3979	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic
3980	{
3981	r_dcache_fsm = DCACHE_IDLE;
3982
3983	#if DEBUG_DCACHE
3984	if ( m_debug_dcache_fsm )
3985	{
3986	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
3987	<< std::endl;
3988	}
3989	#endif
3990	}
3991	else // invalidate the cache line TLBs
3992	{
3993
3994	#if DEBUG_DCACHE
3995	if ( m_debug_dcache_fsm )
3996	{
3997	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
3998	<< std::endl;
3999	}
4000	#endif
4001	paddr_t nline;
4002	size_t way = r_dcache_dirty_way.read();
4003	size_t set = r_dcache_dirty_set.read();
4004	bool hit;
4005
4006	hit = r_dcache.inval( way,
4007	set,
4008	&nline );
4009
4010	assert(hit && "PTE should still be in dcache");
4011
4012	// request cleanup
4013	r_dcache_cleanup_req = true;
4014	r_dcache_cleanup_line = nline;
4015
4016	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE
4017	{
4018	r_dcache_tlb_inval_line = nline;
4019	r_dcache_tlb_inval_count = 0;
4020	r_dcache_fsm_scan_save = DCACHE_IDLE;
4021	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4022	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4023	}
4024	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD
4025	{
4026	r_itlb.reset();
4027	r_dtlb.reset();
4028	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4029	r_dcache_fsm = DCACHE_IDLE;
4030	}
4031	else
4032	{
4033	r_dcache_fsm = DCACHE_IDLE;
4034	}
4035	}
4036	}
4037	break;
4038	}
4039	/////////////////////
4040	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4041	// handling coherence requests.
4042	// If there is a matching pending miss on the modified cache
4043	// line this is signaled in the r_dcache_miss inval flip-flop.
4044	// If the updated (or invalidated) cache line has copies in TLBs
4045	// these TLB copies are invalidated.
4046	// The return state is defined in r_dcache_fsm_cc_save
4047	{
4048	paddr_t paddr = r_tgt_paddr.read();
4049	paddr_t mask = ~((m_dcache_words<<2)-1);
4050
4051
4052	if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
4053	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4054	{
4055	r_dcache_miss_inval = true; // signaling the match
4056	r_tgt_dcache_req = false; // coherence request completed
4057	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4058	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4059
4060	#if DEBUG_DCACHE
4061	if ( m_debug_dcache_fsm )
4062	{
4063	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4064	<< " address = " << std::hex << paddr << std::endl;
4065	}
4066	#endif
4067
4068	}
4069	else // no match
4070	{
4071	uint32_t rdata;
4072	size_t way;
4073	size_t set;
4074	size_t word;
4075
4076	bool hit = r_dcache.read(paddr,
4077	&rdata, // unused
4078	&way,
4079	&set,
4080	&word); // unused
4081	#ifdef INSTRUMENTATION
4082	m_cpt_dcache_data_read++;
4083	m_cpt_dcache_dir_read++;
4084	#endif
4085	r_dcache_cc_way = way;
4086	r_dcache_cc_set = set;
4087
4088	if ( hit and r_tgt_update.read() ) // hit update
4089	{
4090	r_dcache_fsm = DCACHE_CC_UPDT;
4091	r_dcache_cc_word = r_tgt_word_min.read();
4092	}
4093	else if ( hit and not r_tgt_update.read() ) // hit inval
4094	{
4095	r_dcache_fsm = DCACHE_CC_INVAL;
4096	}
4097	else // miss can happen
4098	{
4099	r_tgt_dcache_req = false;
4100	r_tgt_dcache_rsp = r_tgt_update.read();
4101	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4102	}
4103
4104	#if DEBUG_DCACHE
4105	if ( m_debug_dcache_fsm )
4106	{
4107
4108	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4109	<< " address = " << std::hex << paddr << std::dec;
4110	if ( hit )
4111	{
4112	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4113	}
4114	else
4115	{
4116	std::cout << " / MISS" << std::endl;
4117	}
4118	}
4119	#endif
4120
4121	}
4122	break;
4123	}
4124	/////////////////////
4125	case DCACHE_CC_INVAL: // invalidate one cache line
4126	// and test possible copies in TLBs
4127	{
4128	paddr_t nline;
4129	size_t way = r_dcache_cc_way.read();
4130	size_t set = r_dcache_cc_set.read();
4131	bool hit;
4132
4133	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4134	{
4135	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4136	r_dcache_tlb_inval_line = nline;
4137	r_dcache_tlb_inval_count = 0;
4138	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4139	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4140	}
4141	else // actual cache line inval
4142	{
4143	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4144	{
4145	r_itlb.reset();
4146	r_dtlb.reset();
4147	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4148	}
4149	r_tgt_dcache_rsp = true;
4150	r_tgt_dcache_req = false;
4151	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4152
4153	hit = r_dcache.inval( way,
4154	set,
4155	&nline );
4156	#if DEBUG_DCACHE
4157	if ( m_debug_dcache_fsm )
4158	{
4159	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
4160	<< " / WAY = " << way
4161	<< " / SET = " << set << std::endl;
4162	}
4163	#endif
4164
4165	assert(hit && "CC_INVAL way/set should still be in dcache");
4166	}
4167	break;
4168	}
4169	///////////////////
4170	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4171	// and test possible copies in TLBs
4172	{
4173	size_t word = r_dcache_cc_word.read();
4174	size_t way = r_dcache_cc_way.read();
4175	size_t set = r_dcache_cc_set.read();
4176	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4177
4178	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4179	{
4180	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4181	r_dcache_tlb_inval_line = nline;
4182	r_dcache_tlb_inval_count = 0;
4183	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4184	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4185	}
4186	else // cache update
4187	{
4188	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4189	{
4190	r_itlb.reset();
4191	r_dtlb.reset();
4192	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4193	}
4194
4195	r_dcache.write( way,
4196	set,
4197	word,
4198	r_tgt_buf[word],
4199	r_tgt_be[word] );
4200	#ifdef INSTRUMENTATION
4201	m_cpt_dcache_data_write++;
4202	#endif
4203	r_dcache_cc_word = word + 1;
4204
4205	#if DEBUG_DCACHE
4206	if ( m_debug_dcache_fsm )
4207	{
4208	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
4209	<< " / WAY = " << way
4210	<< " / SET = " << set
4211	<< " / WORD = " << word
4212	<< " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
4213	}
4214	#endif
4215	if ( word == r_tgt_word_max.read() ) // last word
4216	{
4217	r_tgt_dcache_rsp = true;
4218	r_tgt_dcache_req = false;
4219	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4220	}
4221	}
4222
4223	break;
4224	}
4225	///////////////////////////
4226	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB
4227	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4228	// and (m_itlb_ways == m_dtlb_ways)
4229	// We enter this state when a DCACHE line is modified,
4230	// and there is a copy in itlb or dtlb.
4231	// It can be caused by:
4232	// - a coherence inval or updt transaction,
4233	// - a line inval caused by a cache miss
4234	// - a processor XTN inval request,
4235	// - a WRITE hit,
4236	// - a Dirty bit update failure
4237	// Input arguments are:
4238	// - r_dcache_tlb_inval_line
4239	// - r_dcache_tlb_inval_count
4240	// - r_dcache_fsm_cc_save
4241	{
4242	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4243	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4244	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4245	bool ok;
4246
4247	ok = r_itlb.inval( line,
4248	way,
4249	set );
4250	#if DEBUG_DCACHE
4251	if ( m_debug_dcache_fsm and ok )
4252	{
4253	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4254	<< " line = " << line << std::dec
4255	<< " / set = " << set
4256	<< " / way = " << way << std::endl;
4257	r_itlb.printTrace();
4258	}
4259	#endif
4260	ok = r_dtlb.inval( line,
4261	way,
4262	set );
4263	#if DEBUG_DCACHE
4264	if ( m_debug_dcache_fsm and ok )
4265	{
4266	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4267	<< " line = " << line << std::dec
4268	<< " / set = " << set
4269	<< " / way = " << way << std::endl;
4270	r_dtlb.printTrace();
4271	}
4272	#endif
4273
4274	// return to the calling state when TLB inval completed
4275	if ( r_dcache_tlb_inval_count.read() == ((m_dtlb_sets*m_dtlb_ways)-1) )
4276	{
4277	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4278	}
4279	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4280	break;
4281	}
4282	} // end switch r_dcache_fsm
4283
4284	///////////////// wbuf update //////////////////////////////////////////////////////
4285	r_wbuf.update();
4286
4287	//////////////// test processor frozen /////////////////////////////////////////////
4288	// The simulation exit if the number of consecutive frozen cycles
4289	// is larger than the m_max_frozen_cycles (constructor parameter)
4290	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4291	{
4292	m_cpt_frz_cycles++; // used for instrumentation
4293	m_cpt_stop_simulation++; // used for debug
4294	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4295	{
4296	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4297	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4298	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4299	<< std::endl;
4300	exit(1);
4301	}
4302	}
4303	else
4304	{
4305	m_cpt_stop_simulation = 0;
4306	}
4307
4308	/////////// execute one iss cycle /////////////////////////////////
4309	{
4310	uint32_t it = 0;
4311	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4312	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4313	}
4314
4315	////////////////////////////////////////////////////////////////////////////
4316	// The VCI_CMD FSM controls the following ressources:
4317	// - r_vci_cmd_fsm
4318	// - r_vci_cmd_min
4319	// - r_vci_cmd_max
4320	// - r_vci_cmd_cpt
4321	// - r_vci_cmd_imiss_prio
4322	// - wbuf (reset)
4323	// - r_icache_miss_req (reset)
4324	// - r_icache_unc_req (reset)
4325	// - r_dcache_vci_miss_req (reset)
4326	// - r_dcache_vci_unc_req (reset)
4327	// - r_dcache_vci_sc_req (reset)
4328	//
4329	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4330	// There is 6 request types, with the following priorities :
4331	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4332	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4333	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4334	// 4 - Instruction Uncachable : r_icache_unc_req
4335	// 5 - Data Write : r_wbuf.rok()
4336	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4337	//
4338	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4339	// and the VCI_RSP_FSM are fully desynchronized.
4340	//
4341	// VCI formats:
4342	// According to the VCI advanced specification, all read requests packets
4343	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4344	// are one word packets.
4345	// For write burst packets, all words are in the same cache line,
4346	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4347	// The sc command packet implements actually a compare-and-swap mechanism
4348	// and the packet contains two flits.
4349	////////////////////////////////////////////////////////////////////////////////////
4350
4351	switch ( r_vci_cmd_fsm.read() )
4352	{
4353	//////////////
4354	case CMD_IDLE:
4355	{
4356	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4357	// to check a possible pending write on the same cache line.
4358	// As there is only one possible access per cycle to write buffer, we implement
4359	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4360
4361	size_t wbuf_min;
4362	size_t wbuf_max;
4363
4364	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4365	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4366
4367	bool icache_miss_req = r_icache_miss_req.read()
4368	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4369
4370	// 1 - Data Read Miss
4371	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4372	{
4373	r_vci_cmd_fsm = CMD_DATA_MISS;
4374	r_dcache_vci_miss_req = false;
4375	r_vci_cmd_imiss_prio = true;
4376	// m_cpt_dmiss_transaction++;
4377	}
4378	// 2 - Data Read Uncachable
4379	else if ( r_dcache_vci_unc_req.read() )
4380	{
4381	r_vci_cmd_fsm = CMD_DATA_UNC;
4382	r_dcache_vci_unc_req = false;
4383	// m_cpt_dunc_transaction++;
4384	}
4385	// 3 - Instruction Miss
4386	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4387	{
4388	r_vci_cmd_fsm = CMD_INS_MISS;
4389	r_icache_miss_req = false;
4390	r_vci_cmd_imiss_prio = false;
4391	// m_cpt_imiss_transaction++;
4392	}
4393	// 4 - Instruction Uncachable
4394	else if ( r_icache_unc_req.read() )
4395	{
4396	r_vci_cmd_fsm = CMD_INS_UNC;
4397	r_icache_unc_req = false;
4398	// m_cpt_iunc_transaction++;
4399	}
4400	// 5 - Data Write
4401	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4402	{
4403	r_vci_cmd_fsm = CMD_DATA_WRITE;
4404	r_vci_cmd_cpt = wbuf_min;
4405	r_vci_cmd_min = wbuf_min;
4406	r_vci_cmd_max = wbuf_max;
4407	// m_cpt_write_transaction++;
4408	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4409	}
4410	// 6 - Data Store Conditionnal
4411	else if ( r_dcache_vci_sc_req.read() )
4412	{
4413	r_vci_cmd_fsm = CMD_DATA_SC;
4414	r_dcache_vci_sc_req = false;
4415	r_vci_cmd_cpt = 0;
4416	// m_cpt_sc_transaction++;
4417	}
4418	break;
4419	}
4420	////////////////////
4421	case CMD_DATA_WRITE:
4422	{
4423	if ( p_vci_ini_d.cmdack.read() )
4424	{
4425	// m_conso_wbuf_read++;
4426	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4427	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4428	{
4429	r_vci_cmd_fsm = CMD_IDLE ;
4430	r_wbuf.sent() ;
4431	}
4432	}
4433	break;
4434	}
4435	/////////////////
4436	case CMD_DATA_SC:
4437	{
4438	// The SC VCI command contains two flits
4439	if ( p_vci_ini_d.cmdack.read() )
4440	{
4441	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4442	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4443	}
4444	break;
4445	}
4446	//////////////////
4447	case CMD_INS_MISS:
4448	case CMD_INS_UNC:
4449	case CMD_DATA_MISS:
4450	case CMD_DATA_UNC:
4451	{
4452	// all read VCI commands contain one single flit
4453	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4454	break;
4455	}
4456
4457	} // end switch r_vci_cmd_fsm
4458
4459	//////////////////////////////////////////////////////////////////////////
4460	// The VCI_RSP FSM controls the following ressources:
4461	// - r_vci_rsp_fsm:
4462	// - r_vci_rsp_fifo_icache (push)
4463	// - r_vci_rsp_fifo_dcache (push)
4464	// - r_vci_rsp_data_error (set)
4465	// - r_vci_rsp_ins_error (set)
4466	// - r_vci_rsp_cpt
4467	//
4468	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4469	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4470	// to identify the transactions.
4471	//
4472	// VCI vormat:
4473	// This component checks the response packet length and accepts only
4474	// single word packets for write response packets.
4475	//
4476	// Error handling:
4477	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4478	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4479	// flip_flop and the error is signaled by the DCACHE FSM.
4480	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4481	// flip_flop and the error is signaled by the ICACHE FSM.
4482	// In case of Cleanup Error, the simulation stops with an error message...
4483	//////////////////////////////////////////////////////////////////////////
4484
4485	switch ( r_vci_rsp_fsm.read() )
4486	{
4487	//////////////
4488	case RSP_IDLE:
4489	{
4490	if ( p_vci_ini_d.rspval.read() )
4491	{
4492	r_vci_rsp_cpt = 0;
4493
4494	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4495	{
4496	r_vci_rsp_fsm = RSP_DATA_WRITE;
4497	}
4498	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4499	{
4500	r_vci_rsp_fsm = RSP_INS_MISS;
4501	}
4502	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4503	{
4504	r_vci_rsp_fsm = RSP_INS_UNC;
4505	}
4506	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4507	{
4508	r_vci_rsp_fsm = RSP_DATA_MISS;
4509	}
4510	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4511	{
4512	r_vci_rsp_fsm = RSP_DATA_UNC;
4513	}
4514	else
4515	{
4516	assert(false and "Unexpected VCI response");
4517	}
4518	}
4519	break;
4520	}
4521	//////////////////
4522	case RSP_INS_MISS:
4523	{
4524	if ( p_vci_ini_d.rspval.read() )
4525	{
4526	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4527	{
4528	r_vci_rsp_ins_error = true;
4529	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4530	}
4531	else // no error reported
4532	{
4533	if ( r_vci_rsp_fifo_icache.wok() )
4534	{
4535	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4536	"The VCI response packet for instruction miss is too long" );
4537
4538	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4539	vci_rsp_fifo_icache_put = true,
4540	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4541	if ( p_vci_ini_d.reop.read() )
4542	{
4543	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4544	"The VCI response packet for instruction miss is too short");
4545
4546	r_vci_rsp_fsm = RSP_IDLE;
4547	}
4548	}
4549	}
4550	}
4551	break;
4552	}
4553	/////////////////
4554	case RSP_INS_UNC:
4555	{
4556	if (p_vci_ini_d.rspval.read() )
4557	{
4558	assert( p_vci_ini_d.reop.read() and
4559	"illegal VCI response packet for uncachable instruction");
4560
4561	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4562	{
4563	r_vci_rsp_ins_error = true;
4564	r_vci_rsp_fsm = RSP_IDLE;
4565	}
4566	else // no error reported
4567	{
4568	if ( r_vci_rsp_fifo_icache.wok())
4569	{
4570	vci_rsp_fifo_icache_put = true;
4571	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4572	r_vci_rsp_fsm = RSP_IDLE;
4573	}
4574	}
4575	}
4576	break;
4577	}
4578	///////////////////
4579	case RSP_DATA_MISS:
4580	{
4581	if ( p_vci_ini_d.rspval.read() )
4582	{
4583	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4584	{
4585	r_vci_rsp_data_error = true;
4586	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4587	}
4588	else // no error reported
4589	{
4590	if ( r_vci_rsp_fifo_dcache.wok() )
4591	{
4592	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4593	"The VCI response packet for data miss is too long");
4594
4595	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4596	vci_rsp_fifo_dcache_put = true,
4597	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4598	if ( p_vci_ini_d.reop.read() )
4599	{
4600	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4601	"The VCI response packet for data miss is too short");
4602
4603	r_vci_rsp_fsm = RSP_IDLE;
4604	}
4605	}
4606	}
4607	}
4608	break;
4609	}
4610	//////////////////
4611	case RSP_DATA_UNC:
4612	{
4613	if (p_vci_ini_d.rspval.read() )
4614	{
4615	assert( p_vci_ini_d.reop.read() and
4616	"illegal VCI response packet for uncachable read data");
4617
4618	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4619	{
4620	r_vci_rsp_data_error = true;
4621	r_vci_rsp_fsm = RSP_IDLE;
4622	}
4623	else // no error reported
4624	{
4625	if ( r_vci_rsp_fifo_dcache.wok())
4626	{
4627	vci_rsp_fifo_dcache_put = true;
4628	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4629	r_vci_rsp_fsm = RSP_IDLE;
4630	}
4631	}
4632	}
4633	break;
4634	}
4635	////////////////////
4636	case RSP_DATA_WRITE:
4637	{
4638	if (p_vci_ini_d.rspval.read())
4639	{
4640	assert( p_vci_ini_d.reop.read() and
4641	"a VCI response packet must contain one flit for a write transaction");
4642
4643	r_vci_rsp_fsm = RSP_IDLE;
4644	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4645	bool cacheable = r_wbuf.completed(wbuf_index);
4646	if ( not cacheable ) r_dcache_pending_unc_write = false;
4647	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4648	}
4649	break;
4650	}
4651	} // end switch r_vci_rsp_fsm
4652
4653	/////////////////////////////////////////////////////////////////////////////////////
4654	// The CLEANUP FSM is in charge to send the cleanup commands on the coherence
4655	// network. It has two clients (DCACHE FSM and ICACHE FSM) that are served
4656	// with a round-robin priority. All cleanup commands are registered in the
4657	// r_cleanup_buffer, because we must avoid to send a Read Miss command
4658	// for line (X) if there is a pending cleanup for line (X): the r_cleanup_buffer
4659	// is tested by the ICACHE FSM and DCACHE FSM before posting a miss request.
4660	// The CLEANUP FSM resets the r_*cache_cleanup request flip-flops as soon as
4661	// the request has been sent and registered in the buffer.
4662	// The buffer itself is cleared when the cleanup response is received.
4663	// We use an assocative registration buffer (CAM) in order to support several
4664	// simultaneous cleanup transactions (up to 4 simultaneous clenups).
4665	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4666	// - if data cleanup : TRDID = 2*index + 0
4667	// - if instruction cleanup : TRDID = 2*index + 1
4668	/////////////////////////////////////////////////////////////////////////////////////
4669
4670	switch ( r_cleanup_fsm.read() )
4671	{
4672	///////////////////////
4673	case CLEANUP_DATA_IDLE: // dcache has highest priority
4674	{
4675	size_t index = 0;
4676	bool ok;
4677	if ( r_dcache_cleanup_req.read() ) // dcache request
4678	{
4679	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4680	&index );
4681	if ( ok ) // successful registration
4682	{
4683	r_dcache_cleanup_req = false;
4684	r_cleanup_fsm = CLEANUP_DATA_GO;
4685	r_cleanup_trdid = index<<1;
4686	}
4687	}
4688	else if ( r_icache_cleanup_req.read() ) // icache request
4689	{
4690	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4691	&index );
4692	if ( ok ) // successful registration
4693	{
4694	r_icache_cleanup_req = false;
4695	r_cleanup_fsm = CLEANUP_INS_GO;
4696	r_cleanup_trdid = (index<<1) + 1;
4697	}
4698	}
4699	break;
4700	}
4701	//////////////////////
4702	case CLEANUP_INS_IDLE: // icache has highest priority
4703	{
4704	size_t index = 0;
4705	bool ok;
4706	if ( r_icache_cleanup_req.read() ) // icache request
4707	{
4708	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4709	&index );
4710	if ( ok ) // successful registration
4711	{
4712	r_icache_cleanup_req = false;
4713	r_cleanup_fsm = CLEANUP_INS_GO;
4714	r_cleanup_trdid = (index<<1) + 1;
4715	}
4716	}
4717	else if ( r_dcache_cleanup_req.read() ) // dcache request
4718	{
4719	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4720	&index );
4721	if ( ok ) // successful registration
4722	{
4723	r_dcache_cleanup_req = false;
4724	r_cleanup_fsm = CLEANUP_DATA_GO;
4725	r_cleanup_trdid = index<<1;
4726	}
4727	}
4728	break;
4729	}
4730	/////////////////////
4731	case CLEANUP_DATA_GO:
4732	{
4733	if ( p_vci_ini_c.cmdack.read() )
4734	{
4735	r_cleanup_fsm = CLEANUP_INS_IDLE;
4736
4737	#if DEBUG_CLEANUP
4738	if ( m_debug_cleanup_fsm )
4739	{
4740	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4741	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4742	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4743	}
4744	#endif
4745	}
4746	break;
4747	}
4748	////////////////////
4749	case CLEANUP_INS_GO:
4750	{
4751	if ( p_vci_ini_c.cmdack.read() )
4752	{
4753	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4754
4755	#if DEBUG_CLEANUP
4756	if ( m_debug_cleanup_fsm )
4757	{
4758	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4759	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4760	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4761	}
4762	#endif
4763	}
4764	break;
4765	}
4766	} // end switch CLEANUP FSM
4767
4768	//////////////// Handling cleanup responses //////////////////
4769	if ( p_vci_ini_c.rspval.read() )
4770	{
4771	r_cleanup_buffer.inval( p_vci_ini_c.rtrdid.read() >> 1);
4772	}
4773
4774	///////////////// Response FIFOs update //////////////////////
4775	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4776	vci_rsp_fifo_icache_put,
4777	vci_rsp_fifo_icache_data);
4778
4779	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4780	vci_rsp_fifo_dcache_put,
4781	vci_rsp_fifo_dcache_data);
4782	} // end transition()
4783
4784	///////////////////////
4785	tmpl(void)::genMoore()
4786	///////////////////////
4787	{
4788	////////////////////////////////////////////////////////////////
4789	// VCI initiator command on the coherence network (cleanup)
4790	// it depends on the CLEANUP FSM state
4791
4792	paddr_t address;
4793
4794	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4795	address = r_dcache_cleanup_line.read()m_dcache_words4;
4796	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4797	address = r_icache_cleanup_line.read()m_icache_words4;
4798	else
4799	address = 0;
4800
4801	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4802	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4803	p_vci_ini_c.address = address;
4804	p_vci_ini_c.wdata = 0;
4805	p_vci_ini_c.be = 0xF;
4806	p_vci_ini_c.plen = 4;
4807	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4808	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4809	p_vci_ini_c.pktid = 0;
4810	p_vci_ini_c.srcid = m_srcid_c;
4811	p_vci_ini_c.cons = false;
4812	p_vci_ini_c.wrap = false;
4813	p_vci_ini_c.contig = false;
4814	p_vci_ini_c.clen = 0;
4815	p_vci_ini_c.cfixed = false;
4816	p_vci_ini_c.eop = true;
4817
4818	/////////////////////////////////////////////////////////////////
4819	// VCI initiator response on the coherence network (cleanup)
4820	// We always consume the response, and we don't use it.
4821
4822	p_vci_ini_c.rspack = true;
4823
4824	/////////////////////////////////////////////////////////////////
4825	// VCI initiator command on the direct network
4826	// it depends on the CMD FSM state
4827
4828	p_vci_ini_d.pktid = 0;
4829	p_vci_ini_d.srcid = m_srcid_d;
4830	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4831	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4832	p_vci_ini_d.wrap = false;
4833	p_vci_ini_d.clen = 0;
4834	p_vci_ini_d.cfixed = false;
4835
4836	switch ( r_vci_cmd_fsm.read() ) {
4837
4838	case CMD_IDLE:
4839	p_vci_ini_d.cmdval = false;
4840	p_vci_ini_d.address = 0;
4841	p_vci_ini_d.wdata = 0;
4842	p_vci_ini_d.be = 0;
4843	p_vci_ini_d.trdid = 0;
4844	p_vci_ini_d.plen = 0;
4845	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4846	p_vci_ini_d.eop = false;
4847	break;
4848
4849	case CMD_INS_MISS:
4850	p_vci_ini_d.cmdval = true;
4851	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4852	p_vci_ini_d.wdata = 0;
4853	p_vci_ini_d.be = 0xF;
4854	p_vci_ini_d.trdid = TYPE_INS_MISS;
4855	p_vci_ini_d.plen = m_icache_words<<2;
4856	p_vci_ini_d.cmd = vci_param::CMD_READ;
4857	p_vci_ini_d.eop = true;
4858	break;
4859
4860	case CMD_INS_UNC:
4861	p_vci_ini_d.cmdval = true;
4862	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4863	p_vci_ini_d.wdata = 0;
4864	p_vci_ini_d.be = 0xF;
4865	p_vci_ini_d.trdid = TYPE_INS_UNC;
4866	p_vci_ini_d.plen = 4;
4867	p_vci_ini_d.cmd = vci_param::CMD_READ;
4868	p_vci_ini_d.eop = true;
4869	break;
4870
4871	case CMD_DATA_MISS:
4872	p_vci_ini_d.cmdval = true;
4873	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4874	p_vci_ini_d.wdata = 0;
4875	p_vci_ini_d.be = 0xF;
4876	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4877	p_vci_ini_d.plen = m_dcache_words << 2;
4878	p_vci_ini_d.cmd = vci_param::CMD_READ;
4879	p_vci_ini_d.eop = true;
4880	break;
4881
4882	case CMD_DATA_UNC:
4883	p_vci_ini_d.cmdval = true;
4884	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4885	p_vci_ini_d.wdata = 0;
4886	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4887	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4888	p_vci_ini_d.plen = 4;
4889	p_vci_ini_d.cmd = vci_param::CMD_READ;
4890	p_vci_ini_d.eop = true;
4891	break;
4892
4893	case CMD_DATA_WRITE:
4894	p_vci_ini_d.cmdval = true;
4895	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4896	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4897	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4898	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4899	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4900	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4901	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4902	break;
4903
4904	case CMD_DATA_SC:
4905	p_vci_ini_d.cmdval = true;
4906	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4907	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4908	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4909	p_vci_ini_d.be = 0xF;
4910	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4911	p_vci_ini_d.plen = 8;
4912	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4913	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4914	break;
4915	} // end switch r_vci_cmd_fsm
4916
4917	//////////////////////////////////////////////////////////
4918	// VCI initiator response on the direct network
4919	// it depends on the VCI RSP state
4920
4921	switch (r_vci_rsp_fsm.read() )
4922	{
4923	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4924	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4925	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4926	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4927	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4928	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4929	} // end switch r_vci_rsp_fsm
4930
4931	////////////////////////////////////////////////////////////////
4932	// VCI target command and response on the coherence network
4933	switch ( r_tgt_fsm.read() )
4934	{
4935	case TGT_IDLE:
4936	case TGT_UPDT_WORD:
4937	case TGT_UPDT_DATA:
4938	p_vci_tgt_c.cmdack = true;
4939	p_vci_tgt_c.rspval = false;
4940	break;
4941
4942	case TGT_RSP_BROADCAST:
4943	p_vci_tgt_c.cmdack = false;
4944	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4945	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4946	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4947	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4948	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4949	p_vci_tgt_c.rdata = 0;
4950	p_vci_tgt_c.rerror = 0;
4951	p_vci_tgt_c.reop = true;
4952	break;
4953
4954	case TGT_RSP_ICACHE:
4955	p_vci_tgt_c.cmdack = false;
4956	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4957	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4958	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4959	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4960	p_vci_tgt_c.rdata = 0;
4961	p_vci_tgt_c.rerror = 0;
4962	p_vci_tgt_c.reop = true;
4963	break;
4964
4965	case TGT_RSP_DCACHE:
4966	p_vci_tgt_c.cmdack = false;
4967	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4968	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4969	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4970	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4971	p_vci_tgt_c.rdata = 0;
4972	p_vci_tgt_c.rerror = 0;
4973	p_vci_tgt_c.reop = true;
4974	break;
4975
4976	case TGT_REQ_BROADCAST:
4977	case TGT_REQ_ICACHE:
4978	case TGT_REQ_DCACHE:
4979	p_vci_tgt_c.cmdack = false;
4980	p_vci_tgt_c.rspval = false;
4981	break;
4982
4983	} // end switch TGT_FSM
4984	} // end genMoore
4985
4986	}}
4987
4988	// Local Variables:
4989	// tab-width: 4
4990	// c-basic-offset: 4
4991	// c-file-offsets:((innamespace . 0)(inline-open . 0))
4992	// indent-tabs-mode: nil
4993	// End:
4994
4995	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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