[2] | 1 | /* -*- c++ -*- |
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[188] | 2 | * File : vci_cc_xcache_wrapper_v4.h |
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| 3 | * Copyright (c) UPMC, Lip6, SoC |
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| 4 | * Authors : Alain GREINER |
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| 5 | * Date : 27/11/2011 |
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[2] | 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | */ |
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| 27 | |
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| 28 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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| 29 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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| 30 | |
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| 31 | #include <inttypes.h> |
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[165] | 32 | #include <fstream> |
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[2] | 33 | #include <systemc> |
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[134] | 34 | #include <queue> |
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[2] | 35 | #include "caba_base_module.h" |
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[134] | 36 | #include "multi_write_buffer.h" |
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[2] | 37 | #include "generic_cache.h" |
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[165] | 38 | #include "generic_fifo.h" |
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[188] | 39 | #include "generic_cam.h" |
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[2] | 40 | #include "vci_initiator.h" |
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| 41 | #include "vci_target.h" |
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| 42 | #include "mapping_table.h" |
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| 43 | #include "static_assert.h" |
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[188] | 44 | #include "iss2.h" |
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[2] | 45 | |
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| 46 | namespace soclib { |
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| 47 | namespace caba { |
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| 48 | |
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| 49 | using namespace sc_core; |
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| 50 | |
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| 51 | //////////////////////////////////////////// |
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| 52 | template<typename vci_param, typename iss_t> |
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| 53 | class VciCcXCacheWrapperV4 |
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| 54 | /////////////////////////////////////////// |
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| 55 | : public soclib::caba::BaseModule |
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| 56 | { |
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[188] | 57 | typedef uint32_t data_t; |
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| 58 | typedef uint32_t tag_t; |
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| 59 | typedef uint32_t be_t; |
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| 60 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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[165] | 61 | |
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[188] | 62 | enum dcache_fsm_state_e |
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| 63 | { |
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[2] | 64 | DCACHE_IDLE, |
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| 65 | DCACHE_WRITE_UPDT, |
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[134] | 66 | DCACHE_MISS_VICTIM, |
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[2] | 67 | DCACHE_MISS_WAIT, |
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| 68 | DCACHE_MISS_UPDT, |
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| 69 | DCACHE_UNC_WAIT, |
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| 70 | DCACHE_INVAL, |
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[188] | 71 | DCACHE_INVAL_GO, |
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[134] | 72 | DCACHE_SYNC, |
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[2] | 73 | DCACHE_ERROR, |
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| 74 | DCACHE_CC_CHECK, |
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| 75 | DCACHE_CC_INVAL, |
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[188] | 76 | DCACHE_CC_UPDT, |
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[2] | 77 | }; |
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| 78 | |
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[188] | 79 | enum icache_fsm_state_e |
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| 80 | { |
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[2] | 81 | ICACHE_IDLE, |
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[134] | 82 | ICACHE_MISS_VICTIM, |
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[2] | 83 | ICACHE_MISS_WAIT, |
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| 84 | ICACHE_MISS_UPDT, |
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| 85 | ICACHE_UNC_WAIT, |
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| 86 | ICACHE_ERROR, |
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| 87 | ICACHE_CC_CHECK, |
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| 88 | ICACHE_CC_INVAL, |
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[188] | 89 | ICACHE_CC_UPDT, |
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[2] | 90 | }; |
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| 91 | |
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[188] | 92 | enum cmd_fsm_state_e |
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| 93 | { |
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[2] | 94 | CMD_IDLE, |
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| 95 | CMD_INS_MISS, |
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| 96 | CMD_INS_UNC, |
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| 97 | CMD_DATA_MISS, |
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| 98 | CMD_DATA_UNC, |
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| 99 | CMD_DATA_WRITE, |
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| 100 | CMD_DATA_SC, |
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| 101 | }; |
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| 102 | |
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[188] | 103 | enum rsp_fsm_state_e |
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| 104 | { |
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[2] | 105 | RSP_IDLE, |
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| 106 | RSP_INS_MISS, |
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| 107 | RSP_INS_UNC, |
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| 108 | RSP_DATA_MISS, |
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| 109 | RSP_DATA_UNC, |
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| 110 | RSP_DATA_WRITE, |
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| 111 | RSP_DATA_SC, |
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| 112 | }; |
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| 113 | |
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[188] | 114 | enum tgt_fsm_state_e |
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| 115 | { |
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[2] | 116 | TGT_IDLE, |
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| 117 | TGT_UPDT_WORD, |
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| 118 | TGT_UPDT_DATA, |
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| 119 | TGT_REQ_BROADCAST, |
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| 120 | TGT_REQ_ICACHE, |
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| 121 | TGT_REQ_DCACHE, |
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| 122 | TGT_RSP_BROADCAST, |
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| 123 | TGT_RSP_ICACHE, |
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| 124 | TGT_RSP_DCACHE, |
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| 125 | }; |
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| 126 | |
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[188] | 127 | enum cleanup_cmd_fsm_state_e |
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| 128 | { |
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| 129 | CLEANUP_DATA_IDLE, |
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| 130 | CLEANUP_INS_IDLE, |
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| 131 | CLEANUP_DATA_GO, |
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| 132 | CLEANUP_INS_GO, |
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[134] | 133 | }; |
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| 134 | |
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[188] | 135 | enum transaction_type_d_e |
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| 136 | { |
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[134] | 137 | // convention with memcache |
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| 138 | // b0 : 1 if cached |
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| 139 | // b1 : 1 if instruction |
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| 140 | // b2 : 1 if sc |
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| 141 | TYPE_DATA_UNC = 0x0, |
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| 142 | TYPE_DATA_MISS = 0x1, |
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| 143 | TYPE_INS_UNC = 0x2, |
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| 144 | TYPE_INS_MISS = 0x3, |
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| 145 | }; |
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| 146 | |
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[2] | 147 | public: |
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| 148 | |
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| 149 | // PORTS |
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| 150 | sc_in<bool> p_clk; |
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| 151 | sc_in<bool> p_resetn; |
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[188] | 152 | sc_in<bool> * p_irq; // [iss_t::n_irq]; |
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| 153 | soclib::caba::VciInitiator<vci_param> p_vci_ini_d; |
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[2] | 154 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
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[188] | 155 | soclib::caba::VciTarget<vci_param> p_vci_tgt_c; |
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[2] | 156 | |
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| 157 | private: |
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| 158 | |
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| 159 | // STRUCTURAL PARAMETERS |
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[188] | 160 | const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; |
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| 161 | const soclib::common::Segment m_segment; |
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| 162 | |
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| 163 | const uint32_t m_srcid_d; |
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| 164 | const uint32_t m_srcid_c; |
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[2] | 165 | |
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[188] | 166 | const size_t m_dcache_ways; |
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| 167 | const size_t m_icache_ways; |
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[2] | 168 | |
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[188] | 169 | const size_t m_cache_words; |
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| 170 | const size_t m_cache_words_shift; |
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| 171 | const vci_addr_t m_cache_yzmask; |
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[134] | 172 | |
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[188] | 173 | const uint32_t m_max_frozen_cycles; |
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[2] | 174 | |
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[188] | 175 | iss_t * r_iss; |
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| 176 | MultiWriteBuffer<vci_addr_t> * r_wbuf; |
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| 177 | GenericCache<vci_addr_t> * r_icache; |
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| 178 | GenericCache<vci_addr_t> * r_dcache; |
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| 179 | |
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| 180 | sc_signal<int> r_icache_fsm; |
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| 181 | sc_signal<int> r_icache_fsm_save; // return state for coherence request |
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| 182 | sc_signal<vci_addr_t> r_icache_addr_save; // address requested by proc |
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| 183 | sc_signal<bool> r_icache_miss_req; // set by icache_fsm / reset by cmd_fsm |
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| 184 | sc_signal<bool> r_icache_unc_req; // set by icache_fsm / reset by cmd_fsm |
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| 185 | sc_signal<bool> r_icache_cleanup_req; // a victim line must be evicted |
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| 186 | sc_signal<vci_addr_t> r_icache_cleanup_line; // address of the selected victim line |
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| 187 | sc_signal<size_t> r_icache_cleanup_way; // way of the selected victim line |
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| 188 | sc_signal<size_t> r_icache_cleanup_set; // set of the selected victim line |
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| 189 | sc_signal<bool> r_icache_miss_inval; // cancellation request for pending miss |
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| 190 | sc_signal<size_t> r_icache_update_word; // word index for update (intern/extern) |
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| 191 | sc_signal<data_t> r_icache_unc_buf; // Non cacheable read buffer (one word) |
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| 192 | sc_signal<bool> r_icache_unc_valid; // Non cacheable read buffer valid |
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| 193 | sc_signal<size_t> r_icache_cc_way; // way index for coherence request |
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| 194 | sc_signal<size_t> r_icache_cc_set; // set index for coherence request |
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| 195 | |
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| 196 | sc_signal<int> r_dcache_fsm; |
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| 197 | sc_signal<int> r_dcache_fsm_save; // return state when coherence request |
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| 198 | sc_signal<vci_addr_t> r_dcache_addr_save; // address requested by proc |
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| 199 | sc_signal<data_t> r_dcache_wdata_save; // data written (for dcache update) |
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| 200 | sc_signal<be_t> r_dcache_be_save; // byte enable (for dcache update) |
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| 201 | sc_signal<be_t> r_dcache_way_save; // selected way (in case of hit) |
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| 202 | sc_signal<be_t> r_dcache_set_save; // selected set (in case of hit) |
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| 203 | sc_signal<be_t> r_dcache_word_save; // selected word (in case of hit) |
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| 204 | sc_signal<bool> r_dcache_cleanup_req; // a victim line must be evicted |
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| 205 | sc_signal<vci_addr_t> r_dcache_cleanup_line; // address of the selected victim line |
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| 206 | sc_signal<size_t> r_dcache_cleanup_way; // way of the selected victim line |
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| 207 | sc_signal<size_t> r_dcache_cleanup_set; // set of the selected victim line |
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| 208 | sc_signal<bool> r_dcache_miss_req; // set by dcache_fsm / reset by cmd_fsm |
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| 209 | sc_signal<bool> r_dcache_unc_req; // set by dcache_fsm / reset by cmd_fsm |
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| 210 | sc_signal<bool> r_dcache_sc_req; // set by dcache_fsm / reset by cmd_fsm |
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| 211 | sc_signal<bool> r_dcache_miss_inval; // cancellation of a pending miss |
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| 212 | sc_signal<size_t> r_dcache_update_word; // word index for update (intern/extern) |
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| 213 | sc_signal<data_t> r_dcache_ll_data; // LL reservation data |
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| 214 | sc_signal<vci_addr_t> r_dcache_ll_addr; // ll reservation address |
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| 215 | sc_signal<bool> r_dcache_ll_valid; // ll reservation valid |
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| 216 | sc_signal<bool> r_dcache_pending_unc_write; // Non cacheable write pending |
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| 217 | sc_signal<data_t> r_dcache_unc_buf; // Non cacheable read buffer (one word) |
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| 218 | sc_signal<bool> r_dcache_unc_valid; // Non cacheable read buffer valid |
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| 219 | sc_signal<size_t> r_dcache_cc_way; // way index for coherence request |
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| 220 | sc_signal<size_t> r_dcache_cc_set; // set index for coherence request |
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[165] | 221 | |
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[2] | 222 | sc_signal<int> r_vci_cmd_fsm; |
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[188] | 223 | sc_signal<size_t> r_vci_cmd_min; // min word index for a write burst |
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| 224 | sc_signal<size_t> r_vci_cmd_max; // max word index for a write burst |
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[2] | 225 | sc_signal<size_t> r_vci_cmd_cpt; |
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[188] | 226 | sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin flip-flop to access wbuf |
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[165] | 227 | |
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[2] | 228 | sc_signal<int> r_vci_rsp_fsm; |
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| 229 | sc_signal<size_t> r_vci_rsp_cpt; |
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[188] | 230 | sc_signal<bool> r_vci_rsp_ins_error; // set by rsp_fsm / reset by icache_fsm |
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| 231 | sc_signal<bool> r_vci_rsp_data_error; // set by rsp_fsm / reset by dcache_fsm |
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| 232 | GenericFifo<data_t> r_vci_rsp_fifo_icache; // response fifo to ICACHE FSM |
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| 233 | GenericFifo<data_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM |
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[2] | 234 | |
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[188] | 235 | sc_signal<int> r_tgt_fsm; // target port on coherence network |
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| 236 | sc_signal<bool> r_tgt_icache_rsp; // VCI response required when true |
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| 237 | sc_signal<bool> r_tgt_dcache_rsp; // VCI response required when true |
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| 238 | sc_signal<vci_addr_t> r_tgt_addr; // address of the target line |
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| 239 | sc_signal<size_t> r_tgt_word_min; // index of the first word to be updated |
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| 240 | sc_signal<size_t> r_tgt_word_max; // index of the last word to be updated |
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| 241 | sc_signal<size_t> r_tgt_word_count; // word counter to fill the tgt_buf |
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| 242 | sc_signal<bool> r_tgt_update; // update request when true |
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| 243 | sc_signal<bool> r_tgt_update_data; // update_data request when true |
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[2] | 244 | sc_signal<size_t> r_tgt_srcid; |
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| 245 | sc_signal<size_t> r_tgt_pktid; |
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| 246 | sc_signal<size_t> r_tgt_trdid; |
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[188] | 247 | sc_signal<bool> r_tgt_icache_req; // coherence request to ICACHE |
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| 248 | sc_signal<bool> r_tgt_dcache_req; // coherence request to DCACHE |
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| 249 | sc_signal<data_t> * r_tgt_buf; // [m_cache_words] |
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| 250 | sc_signal<be_t> * r_tgt_be; // [m_cache_words] |
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[2] | 251 | |
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[188] | 252 | sc_signal<int> r_cleanup_fsm; // send cleanup commands |
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| 253 | sc_signal<size_t> r_cleanup_trdid; // index for trdid |
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| 254 | GenericCam<vci_addr_t> r_cleanup_buffer; // registration buffer for cleanups |
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[134] | 255 | |
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[188] | 256 | // ISS interface variables (used for communication |
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| 257 | // between transition() and print_trace() functions |
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| 258 | bool m_ireq_valid; |
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| 259 | uint32_t m_ireq_addr; |
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| 260 | soclib::common::Iss2::ExecMode m_ireq_mode; |
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| 261 | |
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| 262 | bool m_irsp_valid; |
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| 263 | uint32_t m_irsp_instruction; |
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| 264 | bool m_irsp_error; |
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| 265 | |
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| 266 | bool m_dreq_valid; |
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| 267 | uint32_t m_dreq_addr; |
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| 268 | soclib::common::Iss2::ExecMode m_dreq_mode; |
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| 269 | soclib::common::Iss2::DataOperationType m_dreq_type; |
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| 270 | uint32_t m_dreq_wdata; |
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| 271 | uint8_t m_dreq_be; |
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[2] | 272 | |
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[188] | 273 | bool m_drsp_valid; |
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| 274 | uint32_t m_drsp_rdata; |
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| 275 | bool m_drsp_error; |
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[165] | 276 | |
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[188] | 277 | // Activity counters (for power consumption evaluation) |
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| 278 | uint32_t m_conso_dcache_data_read; // DCACHE DATA READ activity |
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| 279 | uint32_t m_conso_dcache_data_write; // DCACHE DATA WRITE activity |
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| 280 | uint32_t m_conso_dcache_dir_read; // DCACHE DIR READ activity |
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| 281 | uint32_t m_conso_dcache_dir_write; // DCACHE DIR WRITE activity |
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| 282 | |
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| 283 | uint32_t m_conso_icache_data_read; // ICACHE DATA READ activity |
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| 284 | uint32_t m_conso_icache_data_write; // ICACHE DATA WRITE activity |
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| 285 | uint32_t m_conso_icache_dir_read; // ICACHE DIR READ activity |
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| 286 | uint32_t m_conso_icache_dir_write; // ICACHE DIR WRITE activity |
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| 287 | |
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| 288 | uint32_t m_conso_wbuf_read; // WBUF READ activity |
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| 289 | uint32_t m_conso_wbuf_write; // WBUF WRITE activity |
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[134] | 290 | |
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[188] | 291 | uint32_t m_cpt_cc_update_icache; // number of coherence update packets for icache |
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| 292 | uint32_t m_cpt_cc_update_dcache; // number of coherence update packets for dcache |
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| 293 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets for icache |
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| 294 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets for dcache |
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| 295 | uint32_t m_cpt_cc_inval_broadcast; // number of coherence broadcast packets |
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[165] | 296 | |
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[188] | 297 | uint32_t m_cpt_frz_cycles; // total number of cpu frozen cycles |
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| 298 | uint32_t m_cpt_total_cycles; // total number of cycles from reset |
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| 299 | uint32_t m_cpt_stop_simulation; // consecutive frozen cycles counter |
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[165] | 300 | |
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[188] | 301 | uint32_t m_cpt_ins_cacheable; // number of cacheable instructions |
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| 302 | uint32_t m_cpt_ins_uncacheable; // number of non cacheable instructions |
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| 303 | uint32_t m_cpt_ins_miss; // number of cacheable instruction miss |
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[165] | 304 | |
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[188] | 305 | uint32_t m_cpt_data_read_cacheable; // number of cacheable data read |
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| 306 | uint32_t m_cpt_data_read_miss; // number of cacheable data read miss |
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| 307 | uint32_t m_cpt_data_read_uncacheable; // number of non cacheable data read |
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| 308 | uint32_t m_cpt_data_write_cacheable; // number of cacheable write |
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| 309 | uint32_t m_cpt_data_write_uncacheable; // number of non cacheable write |
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| 310 | uint32_t m_cpt_data_write_hit; // number of cacheable write making hit |
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| 311 | uint32_t m_cpt_data_ll; // number of LL requests |
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| 312 | uint32_t m_cpt_data_sc; // number of SC requests |
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| 313 | |
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| 314 | uint32_t m_cpt_xtn_dcache_inval; // dcache line invalidation request |
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| 315 | uint32_t m_cpt_xtn_sync; // write buffer flush request |
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| 316 | |
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| 317 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
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| 318 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
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| 319 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
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[165] | 320 | |
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[188] | 321 | uint32_t m_cpt_imiss_transaction; // number of VCI inst read miss transactions |
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| 322 | uint32_t m_cpt_dmiss_transaction; // number of VCI data read miss transactions |
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| 323 | uint32_t m_cpt_iunc_transaction; // number of VCI uncacheable inst read transactions |
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| 324 | uint32_t m_cpt_dunc_transaction; // number of VCI uncacheable data read transactions |
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| 325 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
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| 326 | uint32_t m_cpt_sc_transaction; // number of VCI sc transactions |
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[165] | 327 | |
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[188] | 328 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
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| 329 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
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| 330 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
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| 331 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
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| 332 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
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[2] | 333 | |
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| 334 | |
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[188] | 335 | uint32_t * m_cpt_fsm_dcache; // array of number of cycles per state |
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| 336 | uint32_t * m_cpt_fsm_icache; // array of number of cycles per state |
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| 337 | uint32_t * m_cpt_fsm_cmd; // array of number of cycles per state |
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| 338 | uint32_t * m_cpt_fsm_rsp; // array of number of cycles per state |
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| 339 | uint32_t * m_cpt_fsm_tgt; // array of number of cycles per state |
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| 340 | uint32_t * m_cpt_fsm_cleanup; // array of number of cycles per state |
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[2] | 341 | |
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| 342 | protected: |
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| 343 | SC_HAS_PROCESS(VciCcXCacheWrapperV4); |
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| 344 | |
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| 345 | public: |
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| 346 | |
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| 347 | VciCcXCacheWrapperV4( |
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[188] | 348 | sc_module_name insname, |
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| 349 | int proc_id, |
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| 350 | const soclib::common::MappingTable &mtd, |
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| 351 | const soclib::common::MappingTable &mtc, |
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| 352 | const soclib::common::IntTab &initiator_index_d, |
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| 353 | const soclib::common::IntTab &initiator_index_c, |
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| 354 | const soclib::common::IntTab &target_index_c, |
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| 355 | size_t icache_ways, |
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| 356 | size_t icache_sets, |
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| 357 | size_t icache_words, |
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| 358 | size_t dcache_ways, |
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| 359 | size_t dcache_sets, |
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| 360 | size_t dcache_words, |
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| 361 | size_t wbuf_nwords, |
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| 362 | size_t wbuf_nlines, |
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| 363 | uint32_t max_frozen_cycles = 1000); |
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[2] | 364 | |
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| 365 | ~VciCcXCacheWrapperV4(); |
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| 366 | |
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[188] | 367 | void print_trace(size_t mode = 0); |
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| 368 | void print_cpi(); |
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| 369 | void print_stats(bool print_wbuf=true, bool print_fsm=true); |
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[2] | 370 | |
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| 371 | private: |
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| 372 | |
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| 373 | void transition(); |
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| 374 | void genMoore(); |
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| 375 | |
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[165] | 376 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
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[2] | 377 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
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| 378 | }; |
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| 379 | |
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| 380 | }} |
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| 381 | |
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[188] | 382 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ |
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[2] | 383 | |
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| 384 | // Local Variables: |
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| 385 | // tab-width: 4 |
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| 386 | // c-basic-offset: 4 |
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| 387 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 388 | // indent-tabs-mode: nil |
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| 389 | // End: |
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| 390 | |
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| 391 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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