1 | /* -*- c++ -*- |
---|
2 | * |
---|
3 | * SOCLIB_LGPL_HEADER_BEGIN |
---|
4 | * |
---|
5 | * This file is part of SoCLib, GNU LGPLv2.1. |
---|
6 | * |
---|
7 | * SoCLib is free software; you can redistribute it and/or modify it |
---|
8 | * under the terms of the GNU Lesser General Public License as published |
---|
9 | * by the Free Software Foundation; version 2.1 of the License. |
---|
10 | * |
---|
11 | * SoCLib is distributed in the hope that it will be useful, but |
---|
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
14 | * Lesser General Public License for more details. |
---|
15 | * |
---|
16 | * You should have received a copy of the GNU Lesser General Public |
---|
17 | * License along with SoCLib; if not, write to the Free Software |
---|
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
---|
19 | * 02110-1301 USA |
---|
20 | * |
---|
21 | * SOCLIB_LGPL_HEADER_END |
---|
22 | * |
---|
23 | * Copyright (c) UPMC, Lip6, SoC |
---|
24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
---|
25 | * |
---|
26 | * Maintainers: alain |
---|
27 | */ |
---|
28 | |
---|
29 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
---|
30 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
---|
31 | |
---|
32 | #include <inttypes.h> |
---|
33 | #include <systemc> |
---|
34 | #include "caba_base_module.h" |
---|
35 | #include "write_buffer.h" |
---|
36 | #include "generic_cache.h" |
---|
37 | #include "vci_initiator.h" |
---|
38 | #include "vci_target.h" |
---|
39 | #include "mapping_table.h" |
---|
40 | #include "static_assert.h" |
---|
41 | |
---|
42 | |
---|
43 | namespace soclib { |
---|
44 | namespace caba { |
---|
45 | |
---|
46 | using namespace sc_core; |
---|
47 | |
---|
48 | //////////////////////////////////////////// |
---|
49 | template<typename vci_param, typename iss_t> |
---|
50 | class VciCcXCacheWrapperV4 |
---|
51 | /////////////////////////////////////////// |
---|
52 | : public soclib::caba::BaseModule |
---|
53 | { |
---|
54 | typedef sc_dt::sc_uint<40> addr_40; |
---|
55 | typedef sc_dt::sc_uint<64> data_64; |
---|
56 | typedef uint32_t data_t; |
---|
57 | typedef uint32_t tag_t; |
---|
58 | typedef uint32_t be_t; |
---|
59 | typedef typename vci_param::fast_addr_t vci_addr_t; |
---|
60 | enum dcache_fsm_state_e { |
---|
61 | DCACHE_IDLE, |
---|
62 | DCACHE_WRITE_UPDT, |
---|
63 | DCACHE_WRITE_REQ, |
---|
64 | DCACHE_MISS_WAIT, |
---|
65 | DCACHE_MISS_UPDT, |
---|
66 | DCACHE_UNC_WAIT, |
---|
67 | DCACHE_SC_WAIT, |
---|
68 | DCACHE_INVAL, |
---|
69 | DCACHE_ERROR, |
---|
70 | DCACHE_CC_CHECK, |
---|
71 | DCACHE_CC_INVAL, |
---|
72 | DCACHE_CC_UPDT, |
---|
73 | DCACHE_CC_CLEANUP, |
---|
74 | }; |
---|
75 | |
---|
76 | enum icache_fsm_state_e { |
---|
77 | ICACHE_IDLE, |
---|
78 | ICACHE_MISS_WAIT, |
---|
79 | ICACHE_MISS_UPDT, |
---|
80 | ICACHE_UNC_WAIT, |
---|
81 | ICACHE_ERROR, |
---|
82 | ICACHE_CC_CLEANUP, |
---|
83 | ICACHE_CC_CHECK, |
---|
84 | ICACHE_CC_INVAL, |
---|
85 | ICACHE_CC_UPDT, |
---|
86 | }; |
---|
87 | |
---|
88 | enum cmd_fsm_state_e { |
---|
89 | CMD_IDLE, |
---|
90 | CMD_INS_MISS, |
---|
91 | CMD_INS_UNC, |
---|
92 | CMD_DATA_MISS, |
---|
93 | CMD_DATA_UNC, |
---|
94 | CMD_DATA_WRITE, |
---|
95 | CMD_DATA_SC, |
---|
96 | CMD_INS_CLEANUP, |
---|
97 | CMD_DATA_CLEANUP, |
---|
98 | }; |
---|
99 | |
---|
100 | enum rsp_fsm_state_e { |
---|
101 | RSP_IDLE, |
---|
102 | RSP_INS_MISS, |
---|
103 | RSP_INS_UNC, |
---|
104 | RSP_DATA_MISS, |
---|
105 | RSP_DATA_UNC, |
---|
106 | RSP_DATA_WRITE, |
---|
107 | RSP_DATA_SC, |
---|
108 | RSP_INS_CLEANUP, |
---|
109 | RSP_DATA_CLEANUP, |
---|
110 | }; |
---|
111 | |
---|
112 | enum tgt_fsm_state_e { |
---|
113 | TGT_IDLE, |
---|
114 | TGT_UPDT_WORD, |
---|
115 | TGT_UPDT_DATA, |
---|
116 | TGT_REQ_BROADCAST, |
---|
117 | TGT_REQ_ICACHE, |
---|
118 | TGT_REQ_DCACHE, |
---|
119 | TGT_RSP_BROADCAST, |
---|
120 | TGT_RSP_ICACHE, |
---|
121 | TGT_RSP_DCACHE, |
---|
122 | }; |
---|
123 | |
---|
124 | public: |
---|
125 | |
---|
126 | // PORTS |
---|
127 | sc_in<bool> p_clk; |
---|
128 | sc_in<bool> p_resetn; |
---|
129 | sc_in<bool> p_irq[iss_t::n_irq]; |
---|
130 | soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; |
---|
131 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
---|
132 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
---|
133 | |
---|
134 | private: |
---|
135 | |
---|
136 | // STRUCTURAL PARAMETERS |
---|
137 | const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; |
---|
138 | const soclib::common::Segment m_segment; |
---|
139 | iss_t m_iss; |
---|
140 | const uint32_t m_srcid_rw; |
---|
141 | const uint32_t m_srcid_c; |
---|
142 | |
---|
143 | const size_t m_dcache_ways; |
---|
144 | const size_t m_dcache_words; |
---|
145 | const size_t m_dcache_yzmask; |
---|
146 | const size_t m_icache_ways; |
---|
147 | const size_t m_icache_words; |
---|
148 | const size_t m_icache_yzmask; |
---|
149 | |
---|
150 | // REGISTERS |
---|
151 | sc_signal<int> r_dcache_fsm; |
---|
152 | sc_signal<int> r_dcache_fsm_save; |
---|
153 | sc_signal<addr_40> r_dcache_addr_save; |
---|
154 | sc_signal<data_t> r_dcache_wdata_save; |
---|
155 | sc_signal<data_t> r_dcache_rdata_save; |
---|
156 | sc_signal<data_64> r_dcache_ll_data; |
---|
157 | sc_signal<addr_40> r_dcache_ll_addr; |
---|
158 | sc_signal<bool> r_dcache_ll_valid; |
---|
159 | sc_signal<int> r_dcache_type_save; |
---|
160 | sc_signal<be_t> r_dcache_be_save; |
---|
161 | sc_signal<bool> r_dcache_cached_save; |
---|
162 | sc_signal<bool> r_dcache_cleanup_req; |
---|
163 | sc_signal<addr_40> r_dcache_cleanup_line; |
---|
164 | sc_signal<bool> r_dcache_miss_req; |
---|
165 | sc_signal<bool> r_dcache_unc_req; |
---|
166 | sc_signal<bool> r_dcache_sc_req; |
---|
167 | sc_signal<bool> r_dcache_write_req; |
---|
168 | sc_signal<bool> r_dcache_inval_rsp; |
---|
169 | |
---|
170 | sc_signal<int> r_icache_fsm; |
---|
171 | sc_signal<int> r_icache_fsm_save; |
---|
172 | sc_signal<addr_40> r_icache_addr_save; |
---|
173 | sc_signal<bool> r_icache_miss_req; |
---|
174 | sc_signal<bool> r_icache_unc_req; |
---|
175 | sc_signal<bool> r_icache_cleanup_req; |
---|
176 | sc_signal<addr_40> r_icache_cleanup_line; |
---|
177 | sc_signal<bool> r_icache_inval_rsp; |
---|
178 | |
---|
179 | sc_signal<int> r_vci_cmd_fsm; |
---|
180 | sc_signal<size_t> r_vci_cmd_min; |
---|
181 | sc_signal<size_t> r_vci_cmd_max; |
---|
182 | sc_signal<size_t> r_vci_cmd_cpt; |
---|
183 | |
---|
184 | sc_signal<int> r_vci_rsp_fsm; |
---|
185 | sc_signal<bool> r_vci_rsp_ins_error; |
---|
186 | sc_signal<bool> r_vci_rsp_data_error; |
---|
187 | sc_signal<size_t> r_vci_rsp_cpt; |
---|
188 | |
---|
189 | data_t *r_icache_miss_buf; |
---|
190 | data_t *r_dcache_miss_buf; |
---|
191 | sc_signal<bool> r_icache_buf_unc_valid; |
---|
192 | |
---|
193 | data_t *r_tgt_buf; |
---|
194 | be_t *r_tgt_be; |
---|
195 | |
---|
196 | sc_signal<int> r_vci_tgt_fsm; |
---|
197 | sc_signal<addr_40> r_tgt_addr; |
---|
198 | sc_signal<size_t> r_tgt_word; |
---|
199 | sc_signal<bool> r_tgt_update; |
---|
200 | sc_signal<bool> r_tgt_update_data; |
---|
201 | sc_signal<bool> r_tgt_brdcast; |
---|
202 | sc_signal<size_t> r_tgt_srcid; |
---|
203 | sc_signal<size_t> r_tgt_pktid; |
---|
204 | sc_signal<size_t> r_tgt_trdid; |
---|
205 | sc_signal<size_t> r_tgt_plen; |
---|
206 | sc_signal<bool> r_tgt_icache_req; |
---|
207 | sc_signal<bool> r_tgt_dcache_req; |
---|
208 | sc_signal<bool> r_tgt_icache_rsp; |
---|
209 | sc_signal<bool> r_tgt_dcache_rsp; |
---|
210 | |
---|
211 | WriteBuffer<addr_40> r_wbuf; |
---|
212 | GenericCache<vci_addr_t> r_icache; |
---|
213 | GenericCache<vci_addr_t> r_dcache; |
---|
214 | |
---|
215 | // Activity counters |
---|
216 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
---|
217 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
---|
218 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
---|
219 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
---|
220 | |
---|
221 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
---|
222 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
---|
223 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
---|
224 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
---|
225 | |
---|
226 | uint32_t m_cpt_cc_update; // number of coherence update packets |
---|
227 | uint32_t m_cpt_cc_inval; // number of coherence inval packets |
---|
228 | |
---|
229 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
---|
230 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
231 | |
---|
232 | uint32_t m_cpt_read; // total number of read instructions |
---|
233 | uint32_t m_cpt_write; // total number of write instructions |
---|
234 | uint32_t m_cpt_data_miss; // number of read miss |
---|
235 | uint32_t m_cpt_ins_miss; // number of instruction miss |
---|
236 | uint32_t m_cpt_unc_read; // number of read uncached |
---|
237 | uint32_t m_cpt_write_cached; // number of cached write |
---|
238 | |
---|
239 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
---|
240 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
---|
241 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
---|
242 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
---|
243 | |
---|
244 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
---|
245 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
---|
246 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
---|
247 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
---|
248 | |
---|
249 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
---|
250 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
---|
251 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
---|
252 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
---|
253 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
---|
254 | |
---|
255 | protected: |
---|
256 | SC_HAS_PROCESS(VciCcXCacheWrapperV4); |
---|
257 | |
---|
258 | public: |
---|
259 | |
---|
260 | VciCcXCacheWrapperV4( |
---|
261 | sc_module_name insname, |
---|
262 | int proc_id, |
---|
263 | const soclib::common::MappingTable &mtp, |
---|
264 | const soclib::common::MappingTable &mtc, |
---|
265 | const soclib::common::IntTab &initiator_index_rw, |
---|
266 | const soclib::common::IntTab &initiator_index_c, |
---|
267 | const soclib::common::IntTab &target_index, |
---|
268 | size_t icache_ways, |
---|
269 | size_t icache_sets, |
---|
270 | size_t icache_words, |
---|
271 | size_t dcache_ways, |
---|
272 | size_t dcache_sets, |
---|
273 | size_t dcache_words ); |
---|
274 | |
---|
275 | ~VciCcXCacheWrapperV4(); |
---|
276 | |
---|
277 | void print_trace(); |
---|
278 | void print_cpi(); |
---|
279 | void print_stats(); |
---|
280 | |
---|
281 | private: |
---|
282 | |
---|
283 | void transition(); |
---|
284 | void genMoore(); |
---|
285 | |
---|
286 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
---|
287 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
---|
288 | }; |
---|
289 | |
---|
290 | }} |
---|
291 | |
---|
292 | #endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */ |
---|
293 | |
---|
294 | // Local Variables: |
---|
295 | // tab-width: 4 |
---|
296 | // c-basic-offset: 4 |
---|
297 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
298 | // indent-tabs-mode: nil |
---|
299 | // End: |
---|
300 | |
---|
301 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
302 | |
---|
303 | |
---|
304 | |
---|