1 | /* -*- c++ -*- |
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2 | * |
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3 | * SOCLIB_LGPL_HEADER_BEGIN |
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4 | * |
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5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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6 | * |
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7 | * SoCLib is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU Lesser General Public License as published |
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9 | * by the Free Software Foundation; version 2.1 of the License. |
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10 | * |
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11 | * SoCLib is distributed in the hope that it will be useful, but |
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12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with SoCLib; if not, write to the Free Software |
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18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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19 | * 02110-1301 USA |
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20 | * |
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21 | * SOCLIB_LGPL_HEADER_END |
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22 | * |
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23 | * Copyright (c) UPMC, Lip6, SoC |
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24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
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25 | * |
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26 | * Maintainers: alain |
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27 | */ |
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28 | |
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29 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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30 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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31 | |
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32 | #include <inttypes.h> |
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33 | #include <systemc> |
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34 | #include <queue> |
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35 | #include "caba_base_module.h" |
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36 | #include "multi_write_buffer.h" |
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37 | #include "generic_cache.h" |
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38 | #include "vci_initiator.h" |
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39 | #include "vci_target.h" |
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40 | #include "mapping_table.h" |
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41 | #include "static_assert.h" |
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42 | |
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43 | /* |
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44 | * CC_XCACHE_WRAPPER_SELECT_VICTIM : |
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45 | * The selection and the update of cache (after a read miss) |
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46 | * are separated in two step |
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47 | * Also, the cleanup can be send in parallel at the read miss. |
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48 | * |
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49 | * CC_XCACHE_WRAPPER_FIFO_RSP |
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50 | * Two simple fifo (each 2x32 depth) receive the cache line from |
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51 | * RAM. Instead of two buffers (m_icache_words and m_dcache_words) |
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52 | * |
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53 | * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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54 | * Update cache in "2*cache_words" cycles (read+mask, write) |
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55 | * |
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56 | * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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57 | * Update cache with only modified data (be != 0) |
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58 | * |
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59 | * CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME |
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60 | * Write buffer scheme for update step : |
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61 | * 1 - multi_scan |
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62 | * 2 - round_robin_scan |
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63 | * 3 - one_scan |
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64 | * else - default scheme |
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65 | * |
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66 | * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY |
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67 | * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req |
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68 | * 1 - two access authorized |
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69 | * 2 - one access with static priority (dcache prior) |
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70 | * 3 - one access with static priority (icache prior) |
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71 | * 4 - one access with round robin priority |
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72 | * |
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73 | * CC_XCACHE_WRAPPER_STOP_SIMULATION : |
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74 | * stop simulation if processor is stall after a long time |
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75 | * (configurable with "stop_simulation" function) |
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76 | * |
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77 | * CC_XCACHE_WRAPPER_DEBUG : |
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78 | * Add log to help the debugging |
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79 | * |
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80 | * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN : |
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81 | * Number of cycle before to prinf debug message |
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82 | * |
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83 | * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION |
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84 | * Print transaction between the cpu and the cache |
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85 | */ |
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86 | |
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87 | // implementation |
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88 | #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM |
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89 | #define CC_XCACHE_WRAPPER_SELECT_VICTIM 0 |
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90 | #endif |
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91 | #ifndef CC_XCACHE_WRAPPER_FIFO_RSP |
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92 | #define CC_XCACHE_WRAPPER_FIFO_RSP 0 |
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93 | #endif |
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94 | #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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95 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 |
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96 | #endif |
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97 | #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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98 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 |
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99 | #endif |
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100 | #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME |
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101 | #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0 |
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102 | #endif |
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103 | #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY |
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104 | #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2 |
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105 | #endif |
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106 | // debugging |
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107 | #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION |
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108 | #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 |
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109 | #endif |
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110 | #ifndef CC_XCACHE_WRAPPER_DEBUG |
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111 | #define CC_XCACHE_WRAPPER_DEBUG 0 |
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112 | #endif |
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113 | #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN |
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114 | #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000 |
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115 | #endif |
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116 | #ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION |
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117 | #define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0 |
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118 | #endif |
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119 | |
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120 | namespace soclib { |
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121 | namespace caba { |
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122 | |
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123 | using namespace sc_core; |
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124 | |
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125 | //////////////////////////////////////////// |
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126 | template<typename vci_param, typename iss_t> |
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127 | class VciCcXCacheWrapperV4 |
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128 | /////////////////////////////////////////// |
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129 | : public soclib::caba::BaseModule |
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130 | { |
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131 | typedef sc_dt::sc_uint<40> addr_40; |
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132 | typedef sc_dt::sc_uint<64> data_64; |
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133 | typedef uint32_t data_t; |
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134 | typedef uint32_t tag_t; |
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135 | typedef uint32_t be_t; |
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136 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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137 | |
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138 | enum dcache_fsm_state_e { |
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139 | DCACHE_IDLE, |
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140 | DCACHE_WRITE_UPDT, |
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141 | #if CC_XCACHE_WRAPPER_SELECT_VICTIM |
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142 | DCACHE_MISS_VICTIM, |
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143 | #endif |
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144 | DCACHE_MISS_WAIT, |
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145 | DCACHE_MISS_UPDT, |
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146 | DCACHE_UNC_WAIT, |
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147 | DCACHE_SC_WAIT, |
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148 | DCACHE_INVAL, |
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149 | DCACHE_SYNC, |
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150 | DCACHE_ERROR, |
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151 | DCACHE_CC_CHECK, |
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152 | DCACHE_CC_INVAL, |
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153 | DCACHE_CC_UPDT, |
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154 | DCACHE_CC_CLEANUP, |
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155 | }; |
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156 | |
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157 | enum icache_fsm_state_e { |
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158 | ICACHE_IDLE, |
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159 | #if CC_XCACHE_WRAPPER_SELECT_VICTIM |
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160 | ICACHE_MISS_VICTIM, |
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161 | #endif |
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162 | ICACHE_MISS_WAIT, |
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163 | ICACHE_MISS_UPDT, |
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164 | ICACHE_UNC_WAIT, |
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165 | ICACHE_ERROR, |
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166 | ICACHE_CC_CLEANUP, |
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167 | ICACHE_CC_CHECK, |
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168 | ICACHE_CC_INVAL, |
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169 | ICACHE_CC_UPDT, |
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170 | }; |
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171 | |
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172 | enum cmd_fsm_state_e { |
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173 | CMD_IDLE, |
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174 | CMD_INS_MISS, |
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175 | CMD_INS_UNC, |
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176 | CMD_DATA_MISS, |
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177 | CMD_DATA_UNC, |
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178 | CMD_DATA_WRITE, |
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179 | CMD_DATA_SC, |
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180 | }; |
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181 | |
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182 | enum rsp_fsm_state_e { |
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183 | RSP_IDLE, |
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184 | RSP_INS_MISS, |
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185 | RSP_INS_UNC, |
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186 | RSP_DATA_MISS, |
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187 | RSP_DATA_UNC, |
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188 | RSP_DATA_WRITE, |
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189 | RSP_DATA_SC, |
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190 | }; |
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191 | |
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192 | enum tgt_fsm_state_e { |
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193 | TGT_IDLE, |
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194 | TGT_UPDT_WORD, |
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195 | TGT_UPDT_DATA, |
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196 | TGT_REQ_BROADCAST, |
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197 | TGT_REQ_ICACHE, |
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198 | TGT_REQ_DCACHE, |
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199 | TGT_RSP_BROADCAST, |
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200 | TGT_RSP_ICACHE, |
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201 | TGT_RSP_DCACHE, |
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202 | }; |
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203 | |
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204 | enum cleanup_fsm_state_e { |
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205 | CLEANUP_IDLE, |
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206 | CLEANUP_DCACHE, |
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207 | CLEANUP_ICACHE, |
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208 | }; |
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209 | |
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210 | enum transaction_type_c_e { |
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211 | // convention with memcache |
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212 | TYPE_DATA_CLEANUP = 0x0, |
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213 | TYPE_INS_CLEANUP = 0x1 |
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214 | }; |
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215 | |
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216 | enum transaction_type_rw_e { |
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217 | // convention with memcache |
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218 | // b0 : 1 if cached |
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219 | // b1 : 1 if instruction |
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220 | // b2 : 1 if sc |
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221 | TYPE_DATA_UNC = 0x0, |
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222 | TYPE_DATA_MISS = 0x1, |
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223 | TYPE_INS_UNC = 0x2, |
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224 | TYPE_INS_MISS = 0x3, |
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225 | TYPE_DATA_SC = 0x4, // sc is data and no cached |
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226 | }; |
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227 | |
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228 | public: |
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229 | |
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230 | // PORTS |
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231 | sc_in<bool> p_clk; |
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232 | sc_in<bool> p_resetn; |
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233 | sc_in<bool> p_irq[iss_t::n_irq]; |
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234 | soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; |
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235 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
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236 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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237 | |
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238 | private: |
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239 | |
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240 | // STRUCTURAL PARAMETERS |
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241 | const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; |
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242 | const soclib::common::Segment m_segment; |
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243 | iss_t m_iss; |
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244 | const uint32_t m_srcid_rw; |
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245 | const uint32_t m_srcid_c; |
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246 | |
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247 | const size_t m_dcache_ways; |
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248 | const size_t m_dcache_words; |
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249 | const uint32_t m_dcache_words_shift; |
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250 | const size_t m_dcache_yzmask; |
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251 | const size_t m_icache_ways; |
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252 | const size_t m_icache_words; |
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253 | const uint32_t m_icache_words_shift; |
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254 | const size_t m_icache_yzmask; |
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255 | const size_t m_cache_words; // max between m_dcache_words and m_icache_words |
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256 | |
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257 | #if CC_XCACHE_WRAPPER_STOP_SIMULATION |
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258 | bool m_stop_simulation; |
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259 | uint32_t m_stop_simulation_nb_frz_cycles_max; |
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260 | uint32_t m_stop_simulation_nb_frz_cycles; |
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261 | #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION |
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262 | |
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263 | // REGISTERS |
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264 | sc_signal<int> r_dcache_fsm; |
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265 | sc_signal<int> r_dcache_fsm_save; |
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266 | sc_signal<addr_40> r_dcache_addr_save; |
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267 | sc_signal<data_t> r_dcache_wdata_save; |
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268 | sc_signal<data_t> r_dcache_rdata_save; |
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269 | sc_signal<int> r_dcache_type_save; |
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270 | sc_signal<be_t> r_dcache_be_save; |
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271 | sc_signal<bool> r_dcache_cached_save; |
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272 | sc_signal<bool> r_dcache_cleanup_req; |
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273 | sc_signal<addr_40> r_dcache_cleanup_line; |
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274 | sc_signal<bool> r_dcache_miss_req; |
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275 | sc_signal<size_t> r_dcache_miss_way; |
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276 | sc_signal<size_t> r_dcache_miss_set; |
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277 | sc_signal<bool> r_dcache_unc_req; |
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278 | sc_signal<bool> r_dcache_sc_req; |
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279 | sc_signal<bool> r_dcache_inval_rsp; |
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280 | sc_signal<size_t> r_dcache_update_addr; |
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281 | sc_signal<data_64> r_dcache_ll_data; |
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282 | sc_signal<addr_40> r_dcache_ll_addr; |
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283 | sc_signal<bool> r_dcache_ll_valid; |
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284 | sc_signal<bool> r_dcache_previous_unc; |
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285 | |
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286 | sc_signal<int> r_icache_fsm; |
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287 | sc_signal<int> r_icache_fsm_save; |
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288 | sc_signal<addr_40> r_icache_addr_save; |
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289 | sc_signal<bool> r_icache_miss_req; |
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290 | sc_signal<size_t> r_icache_miss_way; |
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291 | sc_signal<size_t> r_icache_miss_set; |
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292 | sc_signal<bool> r_icache_unc_req; |
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293 | sc_signal<bool> r_icache_cleanup_req; |
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294 | sc_signal<addr_40> r_icache_cleanup_line; |
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295 | sc_signal<bool> r_icache_inval_rsp; |
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296 | sc_signal<size_t> r_icache_update_addr; |
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297 | |
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298 | sc_signal<int> r_vci_cmd_fsm; |
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299 | sc_signal<size_t> r_vci_cmd_min; |
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300 | sc_signal<size_t> r_vci_cmd_max; |
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301 | sc_signal<size_t> r_vci_cmd_cpt; |
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302 | sc_signal<bool> r_vci_cmd_dcache_prior; |
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303 | |
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304 | sc_signal<int> r_vci_rsp_fsm; |
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305 | sc_signal<bool> r_vci_rsp_ins_error; |
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306 | sc_signal<bool> r_vci_rsp_data_error; |
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307 | sc_signal<size_t> r_vci_rsp_cpt; |
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308 | sc_signal<bool> r_vci_rsp_ack; |
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309 | |
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310 | #if CC_XCACHE_WRAPPER_FIFO_RSP |
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311 | std::queue<data_t> r_icache_miss_buf; |
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312 | std::queue<data_t> r_dcache_miss_buf; |
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313 | #else |
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314 | bool *r_icache_miss_val; //[m_icache_words] |
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315 | data_t *r_icache_miss_buf; //[m_icache_words] |
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316 | bool *r_dcache_miss_val; //[m_dcache_words] |
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317 | data_t *r_dcache_miss_buf; //[m_dcache_words] |
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318 | #endif |
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319 | sc_signal<bool> r_icache_buf_unc_valid; |
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320 | |
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321 | data_t *r_tgt_buf; //[m_cache_words] |
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322 | be_t *r_tgt_be; //[m_cache_words] |
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323 | #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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324 | sc_signal<uint32_t> r_cache_word; |
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325 | #endif |
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326 | |
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327 | sc_signal<int> r_vci_tgt_fsm; |
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328 | sc_signal<addr_40> r_tgt_addr; |
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329 | sc_signal<size_t> r_tgt_word; |
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330 | sc_signal<bool> r_tgt_update; |
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331 | sc_signal<bool> r_tgt_update_data; |
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332 | //sc_signal<bool> r_tgt_brdcast; |
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333 | sc_signal<size_t> r_tgt_srcid; |
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334 | sc_signal<size_t> r_tgt_pktid; |
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335 | sc_signal<size_t> r_tgt_trdid; |
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336 | //sc_signal<size_t> r_tgt_plen; |
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337 | sc_signal<bool> r_tgt_icache_req; |
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338 | sc_signal<bool> r_tgt_dcache_req; |
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339 | sc_signal<bool> r_tgt_icache_rsp; |
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340 | sc_signal<bool> r_tgt_dcache_rsp; |
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341 | |
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342 | sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network |
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343 | |
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344 | MultiWriteBuffer<addr_40> r_wbuf; |
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345 | GenericCache<vci_addr_t> r_icache; |
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346 | GenericCache<vci_addr_t> r_dcache; |
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347 | |
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348 | #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION |
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349 | std::ofstream log_dcache_transaction_file; |
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350 | #endif |
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351 | |
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352 | // Activity counters |
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353 | uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ |
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354 | uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE |
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355 | uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ |
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356 | uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE |
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357 | |
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358 | uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ |
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359 | uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE |
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360 | uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ |
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361 | uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE |
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362 | |
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363 | uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) |
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364 | uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) |
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365 | uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets |
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366 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets |
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367 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets |
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368 | uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets |
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369 | uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets |
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370 | |
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371 | uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen |
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372 | uint32_t m_cpt_total_cycles; // total number of cycles |
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373 | |
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374 | uint32_t m_cpt_data_read; // number of data read |
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375 | uint32_t m_cpt_data_read_miss; // number of data read miss |
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376 | uint32_t m_cpt_data_read_uncached; // number of data read uncached |
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377 | uint32_t m_cpt_data_write; // number of data write |
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378 | uint32_t m_cpt_data_write_miss; // number of data write miss |
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379 | uint32_t m_cpt_data_write_uncached; // number of data write uncached |
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380 | uint32_t m_cpt_ins_miss; // * number of instruction miss |
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381 | |
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382 | uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer |
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383 | uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss |
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384 | uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read |
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385 | uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss |
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386 | |
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387 | uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions |
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388 | uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions |
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389 | uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions |
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390 | uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions |
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391 | |
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392 | uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions |
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393 | uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions |
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394 | uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions |
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395 | uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions |
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396 | uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions |
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397 | |
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398 | protected: |
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399 | SC_HAS_PROCESS(VciCcXCacheWrapperV4); |
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400 | |
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401 | public: |
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402 | |
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403 | VciCcXCacheWrapperV4( |
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404 | sc_module_name insname, |
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405 | int proc_id, |
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406 | const soclib::common::MappingTable &mtp, |
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407 | const soclib::common::MappingTable &mtc, |
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408 | const soclib::common::IntTab &initiator_index_rw, |
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409 | const soclib::common::IntTab &initiator_index_c, |
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410 | const soclib::common::IntTab &target_index, |
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411 | size_t icache_ways, |
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412 | size_t icache_sets, |
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413 | size_t icache_words, |
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414 | size_t dcache_ways, |
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415 | size_t dcache_sets, |
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416 | size_t dcache_words, |
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417 | size_t wbuf_nwords, |
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418 | size_t wbuf_nlines, |
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419 | size_t wbuf_timeout |
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420 | ); |
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421 | |
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422 | ~VciCcXCacheWrapperV4(); |
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423 | |
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424 | void print_trace(size_t mode = 0); |
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425 | void print_cpi(); |
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426 | void print_stats(); |
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427 | |
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428 | // #if CC_XCACHE_WRAPPER_STOP_SIMULATION |
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429 | void stop_simulation (uint32_t); |
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430 | // #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION |
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431 | |
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432 | private: |
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433 | |
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434 | void transition(); |
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435 | void genMoore(); |
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436 | |
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437 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
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438 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
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439 | }; |
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440 | |
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441 | }} |
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442 | |
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443 | #endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */ |
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444 | |
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445 | // Local Variables: |
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446 | // tab-width: 4 |
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447 | // c-basic-offset: 4 |
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448 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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449 | // indent-tabs-mode: nil |
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450 | // End: |
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451 | |
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452 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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