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vci_cc_xcache_wrapper_v4.h @ 144

Last change on this file since 144 was 144, checked in by kane, 13 years ago
in vci_cc_xcache_wrapper_v4 : (1) Fix bug in MISS_VICTIM state, (2) add HIT after MISS, (3) add STORE after STORE
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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain
27	*/
28
29	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
30	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
31
32	#include <inttypes.h>
33	#include <fstream>
34	#include <systemc>
35	#include <queue>
36	#include "caba_base_module.h"
37	#include "multi_write_buffer.h"
38	#include "generic_cache.h"
39	#include "vci_initiator.h"
40	#include "vci_target.h"
41	#include "mapping_table.h"
42	#include "static_assert.h"
43
44	/*
45	* CC_XCACHE_WRAPPER_FIFO_RSP
46	* Two simple fifo (each 2x32 depth) receive the cache line from
47	* RAM. Instead of two buffers (m_icache_words and m_dcache_words)
48	* 1 - nb_icache+nb_dcache simple fifo
49	* 2 - 2 simple fifo
50	* else - two buffers (m_icache_words and m_dcache_words)
51	*
52	* CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
53	* Update cache in "2*cache_words" cycles (read+mask, write)
54	*
55	* CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
56	* Update cache with only modified data (be != 0)
57	*
58	* CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
59	* Write buffer scheme for update step :
60	* 1 - multi_scan
61	* 2 - round_robin_scan
62	* 3 - one_scan
63	* else - default scheme
64	*
65	* CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
66	* Write buffer access is conditionnal with dcache_miss_req and icache_miss_req
67	* 1 - one access with static priority (dcache prior)
68	* 2 - one access with static priority (icache prior)
69	* 3 - one access with round robin priority
70	* 4 - two access authorized
71	*
72	* CC_XCACHE_WRAPPER_MULTI_CACHE :
73	* 1 - icache static partitionnement
74	* 2 - icache dedicated
75	*
76	* CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS
77	* (In multi-cache)
78	* A dcache used by a cpu and in miss_wait state can be use by
79	* an another cpu to make a load cached access.
80	*
81	* CC_XCACHE_WRAPPER_STORE_AFTER_STORE
82	* Store access in dcache (and hit) is make in two cycle :
83	* - first read directory and read data
84	* - second make a mask with old data and write new data.
85	* If data part has a write enable per byte, read data access can be suppress
86	* and we can pipeline consecutive store access.
87	*
88	* CC_XCACHE_WRAPPER_STOP_SIMULATION :
89	* stop simulation if processor is stall after a long time
90	* (configurable with "stop_simulation" function)
91	*
92	* CC_XCACHE_WRAPPER_DEBUG :
93	* Add log to help the debugging
94	*
95	* CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN :
96	* Number of cycle before to prinf debug message
97	*
98	* CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
99	* Print transaction between :
100	* - the cpu and the cache (icache and dcache)
101	* - vci
102	* - cleanup
103	* - coherency
104	*/
105
106	// implementation
107	#ifndef CC_XCACHE_WRAPPER_FIFO_RSP
108	#define CC_XCACHE_WRAPPER_FIFO_RSP 2
109	#endif
110	#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
111	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1
112	#endif
113	#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
114	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1
115	#endif
116	#ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
117	#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 2
118	#endif
119	#ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
120	#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3
121	#endif
122	#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
123	#define CC_XCACHE_WRAPPER_MULTI_CACHE 2
124	// if multi_cache :
125	// <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1
126	// <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1
127	#endif
128	#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS
129	#define CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1
130	#endif
131	#ifndef CC_XCACHE_WRAPPER_STORE_AFTER_STORE
132	#define CC_XCACHE_WRAPPER_STORE_AFTER_STORE 1
133	#endif
134
135	// debugging
136	#ifndef CC_XCACHE_WRAPPER_VERBOSE
137	#define CC_XCACHE_WRAPPER_VERBOSE 1
138	#endif
139	#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
140	#define CC_XCACHE_WRAPPER_STOP_SIMULATION 1
141	#endif
142	#ifndef CC_XCACHE_WRAPPER_DEBUG
143	#define CC_XCACHE_WRAPPER_DEBUG 0
144	#endif
145	#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
146	#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500
147	#endif
148	#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
149	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0
150	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log"
151	#endif
152
153	// don't change
154	#if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
155	#undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
156	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0
157	#endif
158
159	namespace soclib {
160	namespace caba {
161
162	using namespace sc_core;
163
164	////////////////////////////////////////////
165	template<typename vci_param, typename iss_t>
166	class VciCcXCacheWrapperV4
167	///////////////////////////////////////////
168	: public soclib::caba::BaseModule
169	{
170	typedef sc_dt::sc_uint<40> addr_40;
171	typedef sc_dt::sc_uint<64> data_64;
172	typedef uint32_t data_t;
173	typedef uint32_t tag_t;
174	typedef uint32_t be_t;
175	typedef typename vci_param::fast_addr_t vci_addr_t;
176
177	enum dcache_fsm_state_e {
178	DCACHE_IDLE,
179	DCACHE_WRITE_UPDT,
180	DCACHE_MISS_VICTIM,
181	DCACHE_MISS_WAIT,
182	DCACHE_MISS_UPDT,
183	DCACHE_UNC_WAIT,
184	DCACHE_SC_WAIT,
185	DCACHE_INVAL,
186	DCACHE_SYNC,
187	DCACHE_ERROR,
188	DCACHE_CC_CHECK,
189	DCACHE_CC_INVAL,
190	DCACHE_CC_UPDT,
191	DCACHE_CC_CLEANUP,
192	};
193
194	enum icache_fsm_state_e {
195	ICACHE_IDLE,
196	ICACHE_MISS_VICTIM,
197	ICACHE_MISS_WAIT,
198	ICACHE_MISS_UPDT,
199	ICACHE_UNC_WAIT,
200	ICACHE_ERROR,
201	ICACHE_CC_CLEANUP,
202	ICACHE_CC_CHECK,
203	ICACHE_CC_INVAL,
204	ICACHE_CC_UPDT,
205	};
206
207	enum cmd_fsm_state_e {
208	CMD_IDLE,
209	CMD_INS_MISS,
210	CMD_INS_UNC,
211	CMD_DATA_MISS,
212	CMD_DATA_UNC,
213	CMD_DATA_WRITE,
214	CMD_DATA_SC,
215	};
216
217	enum rsp_fsm_state_e {
218	RSP_IDLE,
219	RSP_INS_MISS,
220	RSP_INS_UNC,
221	RSP_DATA_MISS,
222	RSP_DATA_UNC,
223	RSP_DATA_WRITE,
224	RSP_DATA_SC,
225	};
226
227	enum tgt_fsm_state_e {
228	TGT_IDLE,
229	TGT_UPDT_WORD,
230	TGT_UPDT_DATA,
231	TGT_REQ_BROADCAST,
232	TGT_REQ_ICACHE,
233	TGT_REQ_DCACHE,
234	TGT_RSP_BROADCAST,
235	TGT_RSP_ICACHE,
236	TGT_RSP_DCACHE,
237	};
238
239	enum cleanup_fsm_state_e {
240	CLEANUP_IDLE,
241	CLEANUP_REQ,
242	CLEANUP_RSP_DCACHE,
243	CLEANUP_RSP_ICACHE,
244	};
245
246	enum transaction_type_c_e {
247	// convention with memcache
248	TYPE_DATA_CLEANUP = 0x0,
249	TYPE_INS_CLEANUP = 0x1
250	};
251
252	enum transaction_type_rw_e {
253	// convention with memcache
254	// b0 : 1 if cached
255	// b1 : 1 if instruction
256	// b2 : 1 if sc
257	TYPE_DATA_UNC = 0x0,
258	TYPE_DATA_MISS = 0x1,
259	TYPE_INS_UNC = 0x2,
260	TYPE_INS_MISS = 0x3,
261	TYPE_DATA_SC = 0x4, // sc is data and no cached
262	};
263
264	public:
265
266	// PORTS
267	sc_in<bool> p_clk;
268	sc_in<bool> p_resetn;
269	sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq];
270	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
271	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
272	soclib::caba::VciTarget<vci_param> p_vci_tgt;
273
274	private:
275
276	// STRUCTURAL PARAMETERS
277	const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table;
278	const soclib::common::Segment m_segment;
279	iss_t ** m_iss; //[m_nb_cpu]
280	const uint32_t m_srcid_rw;
281	const uint32_t m_srcid_c;
282
283	const size_t m_nb_cpu;
284	const size_t m_nb_icache;
285	const size_t m_nb_dcache;
286	const size_t m_nb_cache;
287	const size_t m_dcache_ways;
288	const size_t m_dcache_words;
289	const uint32_t m_dcache_words_shift;
290	const size_t m_dcache_yzmask;
291	const size_t m_icache_ways;
292	const size_t m_icache_words;
293	const uint32_t m_icache_words_shift;
294	const size_t m_icache_yzmask;
295	const size_t m_cache_words; // max between m_dcache_words and m_icache_words
296
297	#if CC_XCACHE_WRAPPER_STOP_SIMULATION
298	bool m_stop_simulation;
299	uint32_t m_stop_simulation_nb_frz_cycles_max;
300	uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]
301	#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
302
303	// REGISTERS
304	sc_signal<uint32_t> r_cpu_prior;
305	sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache]
306	sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache]
307	sc_signal<bool> * r_dcache_sync;//[m_nb_dcache]
308
309	sc_signal<int> * r_dcache_fsm; //[m_nb_dcache]
310	sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache]
311	sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache]
312	sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache]
313	sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache]
314	sc_signal<int> * r_dcache_type_save; //[m_nb_dcache]
315	sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache]
316	sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache]
317	sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache]
318	sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache]
319	sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache]
320	sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache]
321	sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache]
322	sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache]
323	sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache]
324	sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache]
325	sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache]
326	sc_signal<data_64> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu]
327	sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu]
328	sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu]
329	sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache]
330	sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache]
331
332	sc_signal<int> * r_icache_fsm; //[m_nb_icache]
333	sc_signal<int> * r_icache_fsm_save; //[m_nb_icache]
334	sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache]
335	sc_signal<bool> * r_icache_miss_req; //[m_nb_icache]
336	sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache]
337	sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache]
338	sc_signal<bool> * r_icache_unc_req; //[m_nb_icache]
339	sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache]
340	sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache]
341	sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache]
342	sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache]
343	sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache]
344
345	sc_signal<int> r_vci_cmd_fsm;
346	sc_signal<size_t> r_vci_cmd_min;
347	sc_signal<size_t> r_vci_cmd_max;
348	sc_signal<size_t> r_vci_cmd_cpt;
349	sc_signal<bool> r_vci_cmd_dcache_prior;
350	sc_signal<uint32_t> r_vci_cmd_num_cache;
351
352	sc_signal<int> r_vci_rsp_fsm;
353	sc_signal<size_t> r_vci_rsp_cpt;
354	bool s_vci_rsp_ack;
355	sc_signal<uint32_t> r_vci_rsp_num_cache;
356	sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache]
357	sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache]
358
359	#if (CC_XCACHE_WRAPPER_FIFO_RSP==1)
360	std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache]
361	std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache]
362	#elif (CC_XCACHE_WRAPPER_FIFO_RSP==2)
363	typedef struct
364	{
365	data_t data;
366	uint32_t num_cache;
367	} miss_buf_t;
368
369	std::queue<miss_buf_t> r_icache_miss_buf;
370	std::queue<miss_buf_t> r_dcache_miss_buf;
371	#else
372	bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words]
373	data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words]
374	bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words]
375	data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words]
376	#endif
377	data_t * r_tgt_buf; //[m_cache_words]
378	be_t * r_tgt_be; //[m_cache_words]
379	#if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
380	sc_signal<uint32_t> r_cache_word;
381	#endif
382
383	sc_signal<int> r_vci_tgt_fsm;
384	sc_signal<addr_40> r_tgt_iaddr;
385	sc_signal<addr_40> r_tgt_daddr;
386	sc_signal<size_t> r_tgt_word;
387	sc_signal<bool> r_tgt_update;
388	sc_signal<bool> r_tgt_update_data;
389	//sc_signal<bool> r_tgt_brdcast;
390	sc_signal<size_t> r_tgt_srcid;
391	sc_signal<size_t> r_tgt_pktid;
392	sc_signal<size_t> r_tgt_trdid;
393	//sc_signal<size_t> r_tgt_plen;
394	sc_signal<uint32_t> r_tgt_num_cache;
395	sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache]
396	sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache]
397	sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache]
398	sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache]
399
400	sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network
401	sc_signal<uint32_t> r_cleanup_num_cache;
402	sc_signal<bool> r_cleanup_icache;
403
404	MultiWriteBuffer<addr_40>** r_wbuf;
405	GenericCache<vci_addr_t> ** r_icache;
406	GenericCache<vci_addr_t> ** r_dcache;
407
408	#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
409	std::ofstream * log_transaction_file_icache; //[m_nb_cpu]
410	std::ofstream * log_transaction_file_dcache; //[m_nb_cpu]
411	std::ofstream log_transaction_file_cmd;
412	std::ofstream log_transaction_file_tgt;
413	std::ofstream log_transaction_file_cleanup;
414	#endif
415
416	// Activity counters
417	uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ
418	uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE
419	uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ
420	uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE
421
422	uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ
423	uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE
424	uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ
425	uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE
426
427	uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache)
428	uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache)
429	uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets
430	uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets
431	uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets
432	uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
433	uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
434
435	uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen
436	uint32_t m_cpt_total_cycles; // total number of cycles
437
438	uint32_t m_cpt_data_read; // number of data read
439	uint32_t m_cpt_data_read_miss; // number of data read miss
440	uint32_t m_cpt_data_read_uncached; // number of data read uncached
441	uint32_t m_cpt_data_write; // number of data write
442	uint32_t m_cpt_data_write_miss; // number of data write miss
443	uint32_t m_cpt_data_write_uncached; // number of data write uncached
444	uint32_t m_cpt_ins_miss; // * number of instruction miss
445
446	uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer
447	uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss
448	uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read
449	uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss
450
451	uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions
452	uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions
453	uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions
454	uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions
455
456	uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions
457	uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions
458	uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions
459	uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions
460	uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions
461
462	uint32_t * m_cpt_icache_access; //[m_nb_icache]
463	uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
464	uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache]
465	uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache]
466	uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache]
467	uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache]
468	uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache]
469
470	uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache]
471	uint32_t ** m_cpt_fsm_icache; //[m_nb_icache]
472	uint32_t * m_cpt_fsm_cmd;
473	uint32_t * m_cpt_fsm_rsp;
474	uint32_t * m_cpt_fsm_tgt;
475	uint32_t * m_cpt_fsm_cleanup;
476
477	// Non blocking multi-cache
478	typename iss_t::InstructionRequest * ireq ; //[m_nb_icache]
479	typename iss_t::InstructionResponse * irsp ; //[m_nb_icache]
480	bool * ireq_cached ; //[m_nb_icache]
481	uint32_t * ireq_num_cpu; //[m_nb_dcache]
482	typename iss_t::DataRequest * dreq ; //[m_nb_dcache]
483	typename iss_t::DataResponse * drsp ; //[m_nb_dcache]
484	bool * dreq_cached ; //[m_nb_dcache]
485	uint32_t * dreq_num_cpu; //[m_nb_dcache]
486
487	const uint32_t m_num_cache_LSB;
488	const uint32_t m_num_cache_MSB;
489	addr_40 m_num_cache_LSB_mask;
490	addr_40 m_num_cache_mask;
491
492	protected:
493	SC_HAS_PROCESS(VciCcXCacheWrapperV4);
494
495	public:
496
497	VciCcXCacheWrapperV4(
498	sc_module_name insname,
499	int proc_id,
500	const soclib::common::MappingTable &mtp,
501	const soclib::common::MappingTable &mtc,
502	const soclib::common::IntTab &initiator_index_rw,
503	const soclib::common::IntTab &initiator_index_c,
504	const soclib::common::IntTab &target_index,
505	size_t nb_cpu,
506	size_t nb_cache,
507	size_t icache_ways,
508	size_t icache_sets,
509	size_t icache_words,
510	size_t dcache_ways,
511	size_t dcache_sets,
512	size_t dcache_words,
513	size_t wbuf_nwords,
514	size_t wbuf_nlines,
515	size_t wbuf_timeout
516	);
517
518	~VciCcXCacheWrapperV4();
519
520	void print_trace(size_t mode = 0);
521	void print_cpi();
522	void print_stats(bool print_wbuf=true, bool print_fsm=true);
523
524	// #if CC_XCACHE_WRAPPER_STOP_SIMULATION
525	void stop_simulation (uint32_t);
526	// #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
527
528	private:
529
530	void transition();
531	void genMoore();
532
533	uint32_t get_num_cache (addr_40 & addr);
534	uint32_t get_num_cache_only(addr_40 addr);
535	void set_num_cache (addr_40 & addr, uint32_t num_cache);
536	addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache);
537
538	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
539	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
540	};
541
542	}}
543
544	#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */
545
546	// Local Variables:
547	// tab-width: 4
548	// c-basic-offset: 4
549	// c-file-offsets:((innamespace . 0)(inline-open . 0))
550	// indent-tabs-mode: nil
551	// End:
552
553	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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