1 | /* -*- c++ -*- |
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2 | * |
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3 | * SOCLIB_LGPL_HEADER_BEGIN |
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4 | * |
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5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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6 | * |
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7 | * SoCLib is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU Lesser General Public License as published |
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9 | * by the Free Software Foundation; version 2.1 of the License. |
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10 | * |
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11 | * SoCLib is distributed in the hope that it will be useful, but |
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12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with SoCLib; if not, write to the Free Software |
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18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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19 | * 02110-1301 USA |
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20 | * |
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21 | * SOCLIB_LGPL_HEADER_END |
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22 | * |
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23 | * Copyright (c) UPMC, Lip6, SoC |
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24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
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25 | * |
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26 | * Maintainers: alain |
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27 | */ |
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28 | |
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29 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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30 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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31 | |
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32 | #include <inttypes.h> |
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33 | #include <fstream> |
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34 | #include <systemc> |
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35 | #include <queue> |
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36 | #include "caba_base_module.h" |
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37 | #include "multi_write_buffer.h" |
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38 | #include "generic_cache.h" |
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39 | #include "generic_fifo.h" |
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40 | #include "vci_initiator.h" |
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41 | #include "vci_target.h" |
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42 | #include "mapping_table.h" |
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43 | #include "static_assert.h" |
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44 | |
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45 | /* |
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46 | * ---------------------------------------------------------- |
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47 | * Implementation |
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48 | * ---------------------------------------------------------- |
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49 | * |
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50 | * CC_XCACHE_WRAPPER_MULTI_CACHE |
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51 | * 1 - icache static partitionnement |
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52 | * 2 - icache dedicated |
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53 | * |
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54 | * ---------------------------------------------------------- |
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55 | * Debug |
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56 | * ---------------------------------------------------------- |
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57 | * |
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58 | * CC_XCACHE_WRAPPER_STOP_SIMULATION |
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59 | * stop simulation if processor is stall after a long time |
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60 | * (configurable with "stop_simulation" function) |
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61 | * |
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62 | * CC_XCACHE_WRAPPER_DEBUG |
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63 | * Add log to help the debugging |
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64 | * |
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65 | * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN |
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66 | * Number of cycle before to prinf debug message |
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67 | * |
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68 | * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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69 | * Print transaction between : |
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70 | * - the cpu and the cache (icache and dcache) |
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71 | * - vci |
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72 | * - cleanup |
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73 | * - coherency |
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74 | * |
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75 | * MWBUF_VHDL_TESTBENCH |
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76 | * generate a vhdl testbench for multi write buffer |
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77 | */ |
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78 | |
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79 | // implementation |
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80 | #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE |
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81 | #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 |
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82 | // if multi_cache : |
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83 | // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 |
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84 | #endif |
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85 | |
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86 | // debug |
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87 | #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION |
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88 | #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 |
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89 | #endif |
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90 | #ifndef CC_XCACHE_WRAPPER_DEBUG |
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91 | #define CC_XCACHE_WRAPPER_DEBUG 0 |
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92 | #endif |
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93 | #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN |
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94 | #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 4725000 |
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95 | #endif |
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96 | #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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97 | #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 |
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98 | #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" |
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99 | #endif |
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100 | #ifndef MWBUF_VHDL_TESTBENCH |
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101 | #define MWBUF_VHDL_TESTBENCH 0 |
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102 | #endif |
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103 | |
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104 | namespace soclib { |
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105 | namespace caba { |
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106 | |
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107 | using namespace sc_core; |
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108 | |
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109 | //////////////////////////////////////////// |
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110 | template<typename vci_param, typename iss_t> |
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111 | class VciCcXCacheWrapperV4 |
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112 | /////////////////////////////////////////// |
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113 | : public soclib::caba::BaseModule |
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114 | { |
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115 | typedef uint64_t vhdl_tb_t; |
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116 | typedef sc_dt::sc_uint<40> addr_40; |
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117 | typedef uint32_t data_t; |
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118 | typedef uint32_t tag_t; |
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119 | typedef uint32_t be_t; |
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120 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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121 | |
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122 | enum dcache_fsm_state_e { |
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123 | DCACHE_IDLE, |
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124 | DCACHE_WRITE_UPDT, |
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125 | DCACHE_MISS_VICTIM, |
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126 | DCACHE_MISS_WAIT, |
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127 | DCACHE_MISS_UPDT, |
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128 | DCACHE_UNC_WAIT, |
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129 | DCACHE_SC_WAIT, |
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130 | DCACHE_INVAL, |
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131 | DCACHE_SYNC, |
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132 | DCACHE_ERROR, |
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133 | DCACHE_CC_CHECK, |
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134 | DCACHE_CC_INVAL, |
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135 | DCACHE_CC_UPDT, |
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136 | DCACHE_CC_CLEANUP, |
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137 | }; |
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138 | |
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139 | enum icache_fsm_state_e { |
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140 | ICACHE_IDLE, |
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141 | ICACHE_MISS_VICTIM, |
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142 | ICACHE_MISS_WAIT, |
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143 | ICACHE_MISS_UPDT, |
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144 | ICACHE_UNC_WAIT, |
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145 | ICACHE_ERROR, |
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146 | ICACHE_CC_CLEANUP, |
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147 | ICACHE_CC_CHECK, |
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148 | ICACHE_CC_INVAL, |
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149 | ICACHE_CC_UPDT, |
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150 | }; |
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151 | |
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152 | enum cmd_fsm_state_e { |
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153 | CMD_IDLE, |
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154 | CMD_INS_MISS, |
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155 | CMD_INS_UNC, |
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156 | CMD_DATA_MISS, |
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157 | CMD_DATA_UNC, |
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158 | CMD_DATA_WRITE, |
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159 | CMD_DATA_SC, |
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160 | }; |
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161 | |
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162 | enum rsp_fsm_state_e { |
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163 | RSP_IDLE, |
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164 | RSP_INS_MISS, |
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165 | RSP_INS_UNC, |
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166 | RSP_DATA_MISS, |
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167 | RSP_DATA_UNC, |
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168 | RSP_DATA_WRITE, |
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169 | RSP_DATA_SC, |
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170 | }; |
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171 | |
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172 | enum tgt_fsm_state_e { |
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173 | TGT_IDLE, |
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174 | TGT_UPDT_WORD, |
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175 | TGT_UPDT_DATA, |
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176 | TGT_REQ_BROADCAST, |
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177 | TGT_REQ_ICACHE, |
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178 | TGT_REQ_DCACHE, |
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179 | TGT_RSP_BROADCAST, |
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180 | TGT_RSP_ICACHE, |
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181 | TGT_RSP_DCACHE, |
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182 | }; |
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183 | |
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184 | enum cleanup_fsm_state_e { |
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185 | CLEANUP_IDLE, |
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186 | CLEANUP_REQ, |
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187 | CLEANUP_RSP_DCACHE, |
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188 | CLEANUP_RSP_ICACHE, |
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189 | }; |
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190 | |
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191 | enum transaction_type_c_e { |
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192 | // convention with memcache |
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193 | TYPE_DATA_CLEANUP = 0x0, |
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194 | TYPE_INS_CLEANUP = 0x1 |
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195 | }; |
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196 | |
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197 | enum transaction_type_rw_e { |
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198 | // convention with memcache |
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199 | // b0 : 1 if cached |
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200 | // b1 : 1 if instruction |
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201 | // b2 : 1 if sc |
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202 | TYPE_DATA_UNC = 0x0, |
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203 | TYPE_DATA_MISS = 0x1, |
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204 | TYPE_INS_UNC = 0x2, |
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205 | TYPE_INS_MISS = 0x3, |
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206 | TYPE_DATA_SC = 0x4, // sc is data and no cached |
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207 | }; |
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208 | |
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209 | public: |
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210 | |
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211 | // PORTS |
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212 | sc_in<bool> p_clk; |
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213 | sc_in<bool> p_resetn; |
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214 | sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq]; |
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215 | soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; |
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216 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
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217 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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218 | |
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219 | private: |
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220 | |
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221 | // STRUCTURAL PARAMETERS |
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222 | const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; |
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223 | const soclib::common::Segment m_segment; |
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224 | iss_t ** m_iss; //[m_nb_cpu] |
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225 | const uint32_t m_srcid_rw; |
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226 | const uint32_t m_srcid_c; |
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227 | |
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228 | const size_t m_nb_cpu; |
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229 | const size_t m_nb_icache; |
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230 | const size_t m_nb_dcache; |
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231 | const size_t m_nb_cache; |
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232 | const size_t m_dcache_ways; |
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233 | const size_t m_dcache_words; |
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234 | const uint32_t m_dcache_words_shift; |
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235 | const size_t m_dcache_yzmask; |
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236 | const size_t m_icache_ways; |
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237 | const size_t m_icache_words; |
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238 | const uint32_t m_icache_words_shift; |
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239 | const size_t m_icache_yzmask; |
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240 | const size_t m_cache_words; // max between m_dcache_words and m_icache_words |
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241 | |
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242 | #if CC_XCACHE_WRAPPER_STOP_SIMULATION |
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243 | bool m_stop_simulation; |
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244 | uint32_t m_stop_simulation_nb_frz_cycles_max; |
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245 | uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu] |
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246 | #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION |
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247 | |
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248 | // REGISTERS |
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249 | sc_signal<uint32_t> r_cpu_prior; |
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250 | sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] |
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251 | sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] |
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252 | sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] |
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253 | |
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254 | sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] |
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255 | sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] |
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256 | sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] |
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257 | sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] |
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258 | sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] |
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259 | sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] |
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260 | sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] |
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261 | sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] |
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262 | sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] |
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263 | sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] |
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264 | sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] |
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265 | sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] |
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266 | sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] |
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267 | sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] |
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268 | sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] |
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269 | sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] |
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270 | sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] |
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271 | sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] |
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272 | sc_signal<data_t> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] |
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273 | sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] |
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274 | sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] |
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275 | sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] |
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276 | |
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277 | sc_signal<int> * r_icache_fsm; //[m_nb_icache] |
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278 | sc_signal<int> * r_icache_fsm_save; //[m_nb_icache] |
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279 | sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache] |
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280 | sc_signal<bool> * r_icache_miss_req; //[m_nb_icache] |
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281 | sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache] |
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282 | sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache] |
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283 | sc_signal<bool> * r_icache_unc_req; //[m_nb_icache] |
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284 | sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache] |
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285 | sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache] |
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286 | sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache] |
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287 | sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache] |
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288 | sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache] |
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289 | |
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290 | sc_signal<int> r_vci_cmd_fsm; |
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291 | sc_signal<size_t> r_vci_cmd_min; |
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292 | sc_signal<size_t> r_vci_cmd_max; |
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293 | sc_signal<size_t> r_vci_cmd_cpt; |
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294 | sc_signal<bool> r_vci_cmd_dcache_prior; |
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295 | sc_signal<uint32_t> r_vci_cmd_num_icache_prior; |
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296 | sc_signal<uint32_t> r_vci_cmd_num_dcache_prior; |
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297 | sc_signal<uint32_t> r_vci_cmd_num_cache; |
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298 | |
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299 | sc_signal<int> r_vci_rsp_fsm; |
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300 | sc_signal<size_t> r_vci_rsp_cpt; |
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301 | sc_signal<uint32_t> r_vci_rsp_num_cache; |
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302 | sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] |
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303 | sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] |
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304 | |
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305 | GenericFifo<data_t> r_vci_rsp_fifo_icache_data; |
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306 | GenericFifo<uint32_t> r_vci_rsp_fifo_icache_num_cache; |
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307 | GenericFifo<data_t> r_vci_rsp_fifo_dcache_data; |
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308 | GenericFifo<uint32_t> r_vci_rsp_fifo_dcache_num_cache; |
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309 | |
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310 | data_t * r_tgt_buf; //[m_cache_words] |
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311 | be_t * r_tgt_be; //[m_cache_words] |
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312 | sc_signal<uint32_t> r_cache_word; |
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313 | |
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314 | sc_signal<int> r_vci_tgt_fsm; |
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315 | sc_signal<addr_40> r_tgt_iaddr; |
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316 | sc_signal<addr_40> r_tgt_daddr; |
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317 | sc_signal<size_t> r_tgt_word; |
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318 | sc_signal<bool> r_tgt_update; |
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319 | sc_signal<bool> r_tgt_update_data; |
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320 | //sc_signal<bool> r_tgt_brdcast; |
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321 | sc_signal<size_t> r_tgt_srcid; |
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322 | sc_signal<size_t> r_tgt_pktid; |
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323 | sc_signal<size_t> r_tgt_trdid; |
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324 | //sc_signal<size_t> r_tgt_plen; |
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325 | sc_signal<uint32_t> r_tgt_num_cache; |
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326 | sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] |
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327 | sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] |
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328 | sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] |
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329 | sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] |
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330 | |
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331 | sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network |
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332 | sc_signal<uint32_t> r_cleanup_num_cache; |
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333 | sc_signal<bool> r_cleanup_icache; |
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334 | |
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335 | MultiWriteBuffer<addr_40>** r_wbuf; |
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336 | GenericCache<vci_addr_t> ** r_icache; |
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337 | GenericCache<vci_addr_t> ** r_dcache; |
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338 | |
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339 | #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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340 | bool generate_log_transaction_file_icache; |
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341 | bool generate_log_transaction_file_dcache; |
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342 | bool generate_log_transaction_file_cmd; |
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343 | bool generate_log_transaction_file_tgt; |
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344 | bool generate_log_transaction_file_cleanup; |
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345 | |
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346 | std::ofstream * log_transaction_file_icache; //[m_nb_cpu] |
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347 | std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] |
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348 | std::ofstream log_transaction_file_cmd; |
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349 | std::ofstream log_transaction_file_tgt; |
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350 | std::ofstream log_transaction_file_cleanup; |
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351 | #endif |
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352 | |
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353 | #if MWBUF_VHDL_TESTBENCH |
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354 | bool simulation_started; |
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355 | bool generate_vhdl_testbench_mwbuf; |
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356 | std::ofstream * vhdl_testbench_mwbuf; //[m_nb_dcache] |
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357 | #endif |
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358 | |
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359 | // Activity counters |
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360 | uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ |
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361 | uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE |
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362 | uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ |
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363 | uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE |
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364 | |
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365 | uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ |
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366 | uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE |
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367 | uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ |
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368 | uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE |
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369 | |
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370 | uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) |
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371 | uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) |
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372 | uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets |
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373 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets |
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374 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets |
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375 | uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets |
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376 | uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets |
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377 | |
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378 | uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen |
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379 | uint32_t m_cpt_total_cycles; // total number of cycles |
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380 | |
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381 | uint32_t m_cpt_data_read; // number of data read |
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382 | uint32_t m_cpt_data_read_miss; // number of data read miss |
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383 | uint32_t m_cpt_data_read_uncached; // number of data read uncached |
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384 | uint32_t m_cpt_data_write; // number of data write |
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385 | uint32_t m_cpt_data_write_miss; // number of data write miss |
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386 | uint32_t m_cpt_data_write_uncached; // number of data write uncached |
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387 | uint32_t m_cpt_ins_miss; // * number of instruction miss |
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388 | |
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389 | uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer |
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390 | uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss |
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391 | uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read |
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392 | uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss |
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393 | |
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394 | uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions |
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395 | uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions |
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396 | uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions |
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397 | uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions |
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398 | |
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399 | uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions |
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400 | uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions |
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401 | uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions |
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402 | uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions |
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403 | uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions |
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404 | |
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405 | uint32_t * m_cpt_icache_access; //[m_nb_icache] |
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406 | uint32_t * m_cpt_dcache_access; //[m_nb_dcache] |
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407 | uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] |
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408 | uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] |
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409 | uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] |
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410 | uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] |
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411 | uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] |
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412 | |
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413 | uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] |
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414 | uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] |
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415 | uint32_t * m_cpt_fsm_cmd; |
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416 | uint32_t * m_cpt_fsm_rsp; |
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417 | uint32_t * m_cpt_fsm_tgt; |
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418 | uint32_t * m_cpt_fsm_cleanup; |
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419 | |
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420 | // Non blocking multi-cache |
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421 | typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] |
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422 | typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] |
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423 | bool * ireq_cached ; //[m_nb_icache] |
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424 | uint32_t * ireq_num_cpu; //[m_nb_dcache] |
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425 | typename iss_t::DataRequest * dreq ; //[m_nb_dcache] |
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426 | typename iss_t::DataResponse * drsp ; //[m_nb_dcache] |
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427 | bool * dreq_cached ; //[m_nb_dcache] |
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428 | uint32_t * dreq_num_cpu; //[m_nb_dcache] |
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429 | |
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430 | const uint32_t m_num_cache_LSB; |
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431 | const uint32_t m_num_cache_MSB; |
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432 | addr_40 m_num_cache_LSB_mask; |
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433 | addr_40 m_num_cache_mask; |
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434 | |
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435 | protected: |
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436 | SC_HAS_PROCESS(VciCcXCacheWrapperV4); |
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437 | |
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438 | public: |
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439 | |
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440 | VciCcXCacheWrapperV4( |
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441 | sc_module_name insname, |
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442 | int proc_id, |
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443 | const soclib::common::MappingTable &mtp, |
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444 | const soclib::common::MappingTable &mtc, |
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445 | const soclib::common::IntTab &initiator_index_rw, |
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446 | const soclib::common::IntTab &initiator_index_c, |
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447 | const soclib::common::IntTab &target_index, |
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448 | size_t nb_cpu, |
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449 | size_t nb_dcache, |
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450 | size_t icache_ways, |
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451 | size_t icache_sets, |
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452 | size_t icache_words, |
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453 | size_t dcache_ways, |
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454 | size_t dcache_sets, |
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455 | size_t dcache_words, |
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456 | size_t wbuf_nwords, |
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457 | size_t wbuf_nlines |
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458 | ); |
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459 | |
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460 | ~VciCcXCacheWrapperV4(); |
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461 | |
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462 | void print_trace(size_t mode = 0); |
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463 | void print_cpi(); |
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464 | void print_stats(bool print_wbuf=true, bool print_fsm=true); |
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465 | |
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466 | void stop_simulation (uint32_t); |
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467 | void log_transaction ( bool generate_file_icache |
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468 | ,bool generate_file_dcache |
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469 | ,bool generate_file_cmd |
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470 | ,bool generate_file_tgt |
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471 | ,bool generate_file_cleanup); |
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472 | |
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473 | void vhdl_testbench (bool generate_file_mwbuf); |
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474 | |
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475 | private: |
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476 | |
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477 | void transition(); |
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478 | void genMoore(); |
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479 | |
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480 | uint32_t get_num_cache (addr_40 & addr); |
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481 | uint32_t get_num_cache_only(addr_40 addr); |
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482 | void set_num_cache (addr_40 & addr, uint32_t num_cache); |
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483 | addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); |
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484 | |
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485 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
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486 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
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487 | }; |
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488 | |
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489 | }} |
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490 | |
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491 | #endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */ |
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492 | |
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493 | // Local Variables: |
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494 | // tab-width: 4 |
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495 | // c-basic-offset: 4 |
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496 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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497 | // indent-tabs-mode: nil |
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498 | // End: |
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499 | |
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500 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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