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vci_cc_xcache_wrapper_v4.cpp @ 113

Last change on this file since 113 was 113, checked in by alain, 14 years ago
Improving the print_trace() function
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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain eric.guthmuller@polytechnique.edu nipo
27	*/
28
29	/////////////////////////////////////////////////////////////////////////////
30	// History
31	// - 25/04/2008
32	// The existing vci_xcache component has been extended to include
33	// a VCI target port to support a directory based coherence protocol.
34	// Two types of packets can be send by the L2 cache to the L1 cache
35	// * INVALIDATE packets : length = 1
36	// * UPDATE packets : length = n + 2
37	// The CLEANUP packets are sent by the L1 cache to the L2 cache,
38	// to signal a replaced cache line.
39	// - 12/08/2008
40	// The vci_cc_xcache_wrapper component instanciates directly the processsor
41	// iss, in order to supress the processor/cache interface.
42	// According to the VCI advanced specification, this component uses one
43	// word VCI CMD packets for MISS transactions, and accept one word VCI RSP
44	// packets for Write burst transactions.
45	// The write buffer has been modified to use the WriteBuffer object.
46	// A VCI write burst is constructed when two conditions are satisfied :
47	// The processor make strictly successive write requests, and they are
48	// in the same cache line. The write buffer performs re-ordering, to
49	// respect the contiguous addresses VCI constraint. In case of several
50	// WRITE_WORD requests in the same word, only the last request is conserved.
51	// In case of several WRITE_HALF or WRITE_WORD requests in the same word,
52	// the requests are merged in the same word. In case of uncached write
53	// requests, each request is transmited as a single VCI transaction.
54	// Both the data & instruction caches can be flushed in one single cycle.
55	///////////////////////////////////////////////////////////////////////////////
56
57	#include <cassert>
58	#include "arithmetics.h"
59	#include "../include/vci_cc_xcache_wrapper_v4.h"
60
61	//#define DEBUG_CC_XCACHE_WRAPPER 1
62
63	namespace soclib {
64	namespace caba {
65
66	namespace {
67	const char *dcache_fsm_state_str[] = {
68	"DCACHE_IDLE",
69	"DCACHE_WRITE_UPDT",
70	"DCACHE_WRITE_REQ",
71	"DCACHE_MISS_WAIT",
72	"DCACHE_MISS_UPDT",
73	"DCACHE_UNC_WAIT",
74	"DCACHE_SC_WAIT",
75	"DCACHE_INVAL",
76	"DCACHE_ERROR",
77	"DCACHE_CC_CHECK",
78	"DCACHE_CC_INVAL",
79	"DCACHE_CC_UPDT",
80	"DCACHE_CC_CLEANUP",
81	};
82	const char *icache_fsm_state_str[] = {
83	"ICACHE_IDLE",
84	"ICACHE_MISS_WAIT",
85	"ICACHE_MISS_UPDT",
86	"ICACHE_UNC_WAIT",
87	"ICACHE_ERROR",
88	"ICACHE_CC_CLEANUP",
89	"ICACHE_CC_CHECK",
90	"ICACHE_CC_INVAL",
91	"ICACHE_CC_UPDT",
92	};
93	const char *cmd_fsm_state_str[] = {
94	"CMD_IDLE",
95	"CMD_INS_MISS",
96	"CMD_INS_UNC",
97	"CMD_DATA_MISS",
98	"CMD_DATA_UNC",
99	"CMD_DATA_WRITE",
100	"CMD_DATA_SC",
101	"CMD_INS_CLEANUP",
102	"CMD_DATA_CLEANUP",
103	};
104	const char *rsp_fsm_state_str[] = {
105	"RSP_IDLE",
106	"RSP_INS_MISS",
107	"RSP_INS_UNC",
108	"RSP_DATA_MISS",
109	"RSP_DATA_UNC",
110	"RSP_DATA_WRITE",
111	"RSP_DATA_SC",
112	"RSP_INS_CLEANUP",
113	"RSP_DATA_CLEANUP",
114	};
115	const char *tgt_fsm_state_str[] = {
116	"TGT_IDLE",
117	"TGT_UPDT_WORD",
118	"TGT_UPDT_DATA",
119	"TGT_REQ_BROADCAST",
120	"TGT_REQ_ICACHE",
121	"TGT_REQ_DCACHE",
122	"TGT_RSP_BROADCAST",
123	"TGT_RSP_ICACHE",
124	"TGT_RSP_DCACHE",
125	};
126	}
127
128	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperV4<vci_param, iss_t>
129
130	using soclib::common::uint32_log2;
131
132	/////////////////////////////////
133	tmpl(/**/)::VciCcXCacheWrapperV4(
134	/////////////////////////////////
135	sc_module_name name,
136	int proc_id,
137	const soclib::common::MappingTable &mtp,
138	const soclib::common::MappingTable &mtc,
139	const soclib::common::IntTab &initiator_index_rw,
140	const soclib::common::IntTab &initiator_index_c,
141	const soclib::common::IntTab &target_index,
142	size_t icache_ways,
143	size_t icache_sets,
144	size_t icache_words,
145	size_t dcache_ways,
146	size_t dcache_sets,
147	size_t dcache_words )
148	:
149	soclib::caba::BaseModule(name),
150
151	p_clk("clk"),
152	p_resetn("resetn"),
153	p_vci_ini_rw("vci_ini_rw"),
154	p_vci_ini_c("vci_ini_c"),
155	p_vci_tgt("vci_tgt"),
156
157	m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()),
158	m_segment(mtc.getSegment(target_index)),
159	m_iss(this->name(), proc_id),
160	m_srcid_rw(mtp.indexForId(initiator_index_rw)),
161	m_srcid_c(mtc.indexForId(initiator_index_c)),
162
163	m_dcache_ways(dcache_ways),
164	m_dcache_words(dcache_words),
165	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
166	m_icache_ways(icache_ways),
167	m_icache_words(icache_words),
168	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
169
170	r_dcache_fsm("r_dcache_fsm"),
171	r_dcache_fsm_save("r_dcache_fsm_save"),
172	r_dcache_addr_save("r_dcache_addr_save"),
173	r_dcache_wdata_save("r_dcache_wdata_save"),
174	r_dcache_rdata_save("r_dcache_rdata_save"),
175	r_dcache_ll_data("r_dcache_ll_data"),
176	r_dcache_ll_addr("r_dcache_ll_addr"),
177	r_dcache_ll_valid("r_dcache_ll_valid"),
178	r_dcache_type_save("r_dcache_type_save"),
179	r_dcache_be_save("r_dcache_be_save"),
180	r_dcache_cached_save("r_dcache_cached_save"),
181	r_dcache_cleanup_req("r_dcache_cleanup_req"),
182	r_dcache_cleanup_line("r_dcache_cleanup_line"),
183	r_dcache_miss_req("r_dcache_miss_req"),
184	r_dcache_unc_req("r_dcache_unc_req"),
185	r_dcache_write_req("r_dcache_write_req"),
186
187	r_icache_fsm("r_icache_fsm"),
188	r_icache_fsm_save("r_icache_fsm_save"),
189	r_icache_addr_save("r_icache_addr_save"),
190	r_icache_miss_req("r_icache_miss_req"),
191	r_icache_cleanup_req("r_icache_cleanup_req"),
192	r_icache_cleanup_line("r_icache_cleanup_line"),
193
194	r_vci_cmd_fsm("r_vci_cmd_fsm"),
195	r_vci_cmd_min("r_vci_cmd_min"),
196	r_vci_cmd_max("r_vci_cmd_max"),
197	r_vci_cmd_cpt("r_vci_cmd_cpt"),
198
199	r_vci_rsp_fsm("r_vci_rsp_fsm"),
200	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
201	r_vci_rsp_data_error("r_vci_rsp_data_error"),
202	r_vci_rsp_cpt("r_vci_rsp_cpt"),
203
204	r_icache_buf_unc_valid("r_icache_buf_unc_valid"),
205
206	r_vci_tgt_fsm("r_vci_tgt_fsm"),
207	r_tgt_addr("r_tgt_addr"),
208	r_tgt_word("r_tgt_word"),
209	r_tgt_update("r_tgt_update"),
210	r_tgt_srcid("r_tgt_srcid"),
211	r_tgt_pktid("r_tgt_pktid"),
212	r_tgt_trdid("r_tgt_trdid"),
213	r_tgt_icache_req("r_tgt_icache_req"),
214	r_tgt_dcache_req("r_tgt_dcache_req"),
215
216	r_wbuf("r_wbuf", dcache_words ),
217	r_icache("icache", icache_ways, icache_sets, icache_words),
218	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
219
220	{
221	r_icache_miss_buf = new data_t[icache_words];
222	r_dcache_miss_buf = new data_t[dcache_words];
223	r_tgt_buf = new data_t[dcache_words];
224	r_tgt_be = new be_t[dcache_words];
225
226	SC_METHOD(transition);
227	dont_initialize();
228	sensitive << p_clk.pos();
229
230	SC_METHOD(genMoore);
231	dont_initialize();
232	sensitive << p_clk.neg();
233
234
235	typename iss_t::CacheInfo cache_info;
236	cache_info.has_mmu = false;
237	cache_info.icache_line_size = icache_words*sizeof(data_t);
238	cache_info.icache_assoc = icache_ways;
239	cache_info.icache_n_lines = icache_sets;
240	cache_info.dcache_line_size = dcache_words*sizeof(data_t);
241	cache_info.dcache_assoc = dcache_ways;
242	cache_info.dcache_n_lines = dcache_sets;
243	m_iss.setCacheInfo(cache_info);
244	} // end constructor
245
246	///////////////////////////////////
247	tmpl(/**/)::~VciCcXCacheWrapperV4()
248	///////////////////////////////////
249	{
250	delete [] r_icache_miss_buf;
251	delete [] r_dcache_miss_buf;
252	delete [] r_tgt_be;
253	delete [] r_tgt_buf;
254	}
255
256	////////////////////////
257	tmpl(void)::print_cpi()
258	////////////////////////
259	{
260	std::cout << "CPU " << m_srcid_rw << " : CPI = "
261	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
262	}
263	////////////////////////
264	tmpl(void)::print_stats()
265	////////////////////////
266	{
267	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
268	std::cout << "------------------------------------" << std:: dec << std::endl;
269	std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
270	std::cout << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl ;
271	std::cout << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl ;
272	std::cout << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl;
273	std::cout << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl ;
274	std::cout << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl ;
275	std::cout << "- IMISS_RATE = " << (float)m_cpt_ins_miss/run_cycles << std::endl;
276	std::cout << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl ;
277	std::cout << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl;
278	std::cout << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl;
279	std::cout << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl;
280	std::cout << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl;
281	std::cout << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl;
282	std::cout << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl;
283	std::cout << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl;
284	std::cout << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl;
285	std::cout << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl;
286	}
287	/////////////////////////
288	tmpl(void)::print_trace()
289	/////////////////////////
290	{
291	typename iss_t::InstructionRequest ireq;
292	typename iss_t::DataRequest dreq;
293	m_iss.getRequests( ireq, dreq );
294
295	std::cout << std::dec << "CC_XCACHE_WRAPPER " << name() << std::endl;
296	std::cout << " cache state : " << icache_fsm_state_str[r_icache_fsm] << " / "
297	<< dcache_fsm_state_str[r_dcache_fsm] << " / "
298	<< cmd_fsm_state_str[r_vci_cmd_fsm] << " / "
299	<< rsp_fsm_state_str[r_vci_rsp_fsm] << " / "
300	<< tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl;
301	std::cout << " proc state : PC = " << std::hex << ireq.addr << " / AD = " << dreq.addr
302	<< std::dec << " / V = " << dreq.valid << " / TYPE = " << dreq.type << std::endl;
303	}
304	//////////////////////////
305	tmpl(void)::transition()
306	//////////////////////////
307	{
308	if ( ! p_resetn.read() ) {
309
310	m_iss.reset();
311
312	// FSM states
313	r_dcache_fsm = DCACHE_IDLE;
314	r_icache_fsm = ICACHE_IDLE;
315	r_vci_cmd_fsm = CMD_IDLE;
316	r_vci_rsp_fsm = RSP_IDLE;
317	r_vci_tgt_fsm = TGT_IDLE;
318
319	// write buffer & caches
320	r_wbuf.reset();
321	r_icache.reset();
322	r_dcache.reset();
323
324	// synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs
325	r_icache_miss_req = false;
326	r_icache_unc_req = false;
327	r_icache_cleanup_req = false;
328	r_dcache_miss_req = false;
329	r_dcache_unc_req = false;
330	r_dcache_sc_req = false;
331	r_dcache_write_req = false;
332	r_dcache_cleanup_req = false;
333
334	// synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
335	r_tgt_icache_req = false;
336	r_tgt_dcache_req = false;
337
338	// internal messages in DCACHE et ICACHE FSMs
339	r_icache_inval_rsp = false;
340	r_dcache_inval_rsp = false;
341
342	// error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
343	r_dcache_ll_valid = false;
344	r_icache_buf_unc_valid = false;
345	r_vci_rsp_data_error = false;
346	r_vci_rsp_ins_error = false;
347
348	// activity counters
349	m_cpt_dcache_data_read = 0;
350	m_cpt_dcache_data_write = 0;
351	m_cpt_dcache_dir_read = 0;
352	m_cpt_dcache_dir_write = 0;
353	m_cpt_icache_data_read = 0;
354	m_cpt_icache_data_write = 0;
355	m_cpt_icache_dir_read = 0;
356	m_cpt_icache_dir_write = 0;
357
358	m_cpt_cc_update = 0;
359	m_cpt_cc_inval = 0;
360
361	m_cpt_frz_cycles = 0;
362	m_cpt_total_cycles = 0;
363
364	m_cpt_read = 0;
365	m_cpt_write = 0;
366	m_cpt_data_miss = 0;
367	m_cpt_ins_miss = 0;
368	m_cpt_unc_read = 0;
369	m_cpt_write_cached = 0;
370
371	m_cost_write_frz = 0;
372	m_cost_data_miss_frz = 0;
373	m_cost_unc_read_frz = 0;
374	m_cost_ins_miss_frz = 0;
375
376	m_cpt_imiss_transaction = 0;
377	m_cpt_dmiss_transaction = 0;
378	m_cpt_unc_transaction = 0;
379	m_cpt_write_transaction = 0;
380
381	m_cost_imiss_transaction = 0;
382	m_cost_dmiss_transaction = 0;
383	m_cost_unc_transaction = 0;
384	m_cost_write_transaction = 0;
385	m_length_write_transaction = 0;
386
387	return;
388	}
389
390	#if DEBUG_CC_XCACHE_WRAPPER
391	std::cout << "--------------------------------------------" << std::endl;
392	std::cout << std::dec << "CC_XCACHE_WRAPPER " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
393	std::cout << " tgt fsm = " << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl
394	<< " dcache fsm = " << dcache_fsm_state_str[r_dcache_fsm] << std::endl
395	<< " icache fsm = " << icache_fsm_state_str[r_icache_fsm] << std::endl
396	<< " cmd fsm = " << cmd_fsm_state_str[r_vci_cmd_fsm] << std::endl
397	<< " rsp fsm = " << rsp_fsm_state_str[r_vci_rsp_fsm] << std::endl;
398	#endif
399
400	m_cpt_total_cycles++;
401
402	/////////////////////////////////////////////////////////////////////
403	// The TGT_FSM controls the following ressources:
404	// - r_vci_tgt_fsm
405	// - r_tgt_buf[nwords]
406	// - r_tgt_be[nwords]
407	// - r_tgt_update
408	// - r_tgt_word
409	// - r_tgt_addr
410	// - r_tgt_srcid
411	// - r_tgt_trdid
412	// - r_tgt_pktid
413	// All VCI commands must be CMD_WRITE.
414	// If the VCI address offset is null, the command is an invalidate
415	// request. It is an update request otherwise.
416	// The VCI_TGT FSM stores the external request arguments in the
417	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
418	// & r_tgt_dcache_req flip-flops to signal the external request to
419	// the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
420	// of the update or invalidate request in the RSP state.
421	// - for an invalidate request the VCI packet length is 1 word.
422	// The WDATA field contains the line index (i.e. the Z & Y fields).
423	// - for an update request the VCI packet length is (n+2) words.
424	// The WDATA field of the first VCI word contains the line number.
425	// The WDATA field of the second VCI word contains the word index.
426	// The WDATA field of the n following words contains the values.
427	// - for both invalidate & update requests, the VCI response
428	// is one single word.
429	// In case of errors in the VCI command packet, the simulation
430	// is stopped with an error message.
431	/////////////////////////////////////////////////////////////////////
432
433	switch(r_vci_tgt_fsm) {
434
435	case TGT_IDLE:
436	if ( p_vci_tgt.cmdval.read() )
437	{
438	addr_40 address = p_vci_tgt.address.read();
439
440	if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE)
441	{
442	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
443	std::cout << "coherence request is not a write" << std::endl;
444	std::cout << "oddress = " << std::hex << address << std::endl;
445	std::cout << "srcid = " << std::hex << p_vci_tgt.srcid.read() << std::endl;
446	exit(0);
447	}
448
449	// multi-update or multi-invalidate for data type
450	if ( ((address&0x3) != 0x3) && (! m_segment.contains(address)) )
451	{
452	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
453	std::cout << "out of segment coherence request" << std::endl;
454	std::cout << "oddress = " << std::hex << address << std::endl;
455	std::cout << "srcid = " << std::hex << p_vci_tgt.srcid.read() << std::endl;
456	exit(0);
457	}
458
459	r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) \|
460	((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4;
461	r_tgt_srcid = p_vci_tgt.srcid.read();
462	r_tgt_trdid = p_vci_tgt.trdid.read();
463	r_tgt_pktid = p_vci_tgt.pktid.read();
464	r_tgt_plen = p_vci_tgt.plen.read();
465
466	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
467	{
468	if ( ! p_vci_tgt.eop.read() )
469	{
470	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
471	std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
472	exit(0);
473	}
474	r_tgt_update = false;
475	r_tgt_brdcast= true;
476	r_vci_tgt_fsm = TGT_REQ_BROADCAST;
477	m_cpt_cc_inval++ ;
478	}
479	else // multi-update or multi-invalidate for data type
480	{
481	uint32_t cell = address - m_segment.baseAddress(); // addr_40
482	r_tgt_brdcast = false;
483	if (cell == 0)
484	{ // invalidate data
485	if ( ! p_vci_tgt.eop.read() )
486	{
487	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
488	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
489	exit(0);
490	}
491	r_tgt_update = false;
492	r_vci_tgt_fsm = TGT_REQ_DCACHE;
493	m_cpt_cc_inval++ ;
494	}
495	else if (cell == 4) // invalidate instruction
496	{
497	if ( ! p_vci_tgt.eop.read() )
498	{
499	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
500	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
501	exit(0);
502	}
503	r_tgt_update = false;
504	r_vci_tgt_fsm = TGT_REQ_ICACHE;
505	m_cpt_cc_inval++ ;
506	}
507	else if ( (cell == 8) \|\| (cell==12) ) // update data or instruction
508	{
509	if ( p_vci_tgt.eop.read() )
510	{
511	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
512	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
513	exit(0);
514	}
515	if(cell == 8)
516	r_tgt_update_data = true;
517	else
518	r_tgt_update_data = false;
519	r_tgt_update = true;
520	r_vci_tgt_fsm = TGT_UPDT_WORD;
521	m_cpt_cc_update++ ;
522	}
523
524	} // end if address
525	} // end if cmdval
526	break;
527
528	case TGT_UPDT_WORD:
529	if (p_vci_tgt.cmdval.read())
530	{
531	if ( p_vci_tgt.eop.read() )
532	{
533	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
534	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
535	exit(0);
536	}
537	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = 0;
538	r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
539	#ifdef COHERENCE_DEBUG
540	std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_addr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl;
541	#endif
542	r_vci_tgt_fsm = TGT_UPDT_DATA;
543	}
544	break;
545
546	case TGT_UPDT_DATA:
547	if (p_vci_tgt.cmdval.read())
548	{
549	size_t word = r_tgt_word.read();
550	if ( word >= m_dcache_words )
551	{
552	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
553	std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
554	exit(0);
555	}
556	#ifdef COHERENCE_DEBUG
557	std::cout << "PROC " << m_srcid_rw << " update, data : " << p_vci_tgt.wdata.read() << " be : " << std::hex << p_vci_tgt.be.read() << std::dec << std::endl;
558	#endif
559	r_tgt_buf[word] = p_vci_tgt.wdata.read();
560	r_tgt_be[word] = p_vci_tgt.be.read();
561	r_tgt_word = word + 1;
562	if (p_vci_tgt.eop.read()){
563	if(r_tgt_update_data.read()){
564	r_vci_tgt_fsm = TGT_REQ_DCACHE;
565	} else {
566	r_vci_tgt_fsm = TGT_REQ_ICACHE;
567	}
568	}
569	}
570	break;
571
572	case TGT_REQ_BROADCAST:
573	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
574	{
575	r_vci_tgt_fsm = TGT_RSP_BROADCAST;
576	r_tgt_icache_req = true;
577	r_tgt_dcache_req = true;
578	}
579	break;
580	////////////////////
581	case TGT_REQ_ICACHE:
582	{
583	if ( !r_tgt_icache_req.read() )
584	{
585	r_vci_tgt_fsm = TGT_RSP_ICACHE;
586	r_tgt_icache_req = true;
587	}
588	break;
589	}
590
591	case TGT_REQ_DCACHE:
592	if ( !r_tgt_dcache_req.read() )
593	{
594	r_vci_tgt_fsm = TGT_RSP_DCACHE;
595	r_tgt_dcache_req = true;
596	}
597	break;
598
599	case TGT_RSP_BROADCAST:
600	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
601	{
602	// one response
603	if ( !r_tgt_icache_rsp \|\| !r_tgt_dcache_rsp )
604	{
605	if ( p_vci_tgt.rspack.read() )
606	{
607	r_vci_tgt_fsm = TGT_IDLE;
608	r_tgt_icache_rsp = false;
609	r_tgt_dcache_rsp = false;
610	}
611	}
612
613	// if data and instruction have the inval line, need two responses
614	if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
615	{
616	if ( p_vci_tgt.rspack.read() )
617	{
618	r_tgt_icache_rsp = false; // only reset one for respond the second time
619	}
620	}
621
622	// if there is no need for a response
623	if ( !r_tgt_icache_rsp && !r_tgt_dcache_rsp )
624	{
625	r_vci_tgt_fsm = TGT_IDLE;
626	}
627
628	}
629	break;
630	////////////////////
631	case TGT_RSP_ICACHE:
632	{
633	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() )
634	{
635	r_vci_tgt_fsm = TGT_IDLE;
636	r_tgt_icache_rsp = false;
637	}
638	break;
639	}
640
641	case TGT_RSP_DCACHE:
642	{
643	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
644	{
645	r_vci_tgt_fsm = TGT_IDLE;
646	r_tgt_dcache_rsp = false;
647	}
648	break;
649	}
650	} // end switch TGT_FSM
651
652	/////////////////////////////////////////////////////////////////////
653	// The ICACHE FSM controls the following ressources:
654	// - r_icache_fsm
655	// - r_icache_fsm_save
656	// - r_icache instruction cache access
657	// - r_icache_addr_save
658	// - r_icache_miss_req set
659	// - r_icache_unc_req set
660	// - r_icache_buf_unc_valid set
661	// - r_vci_rsp_ins_error reset
662	// - r_tgt_icache_req reset
663	// - ireq & irsp structures for communication with the processor
664	//
665	// 1/ External requests (update or invalidate) have highest priority.
666	// They are taken into account in the IDLE and WAIT states.
667	// As external hit should be extremly rare on the ICACHE,
668	// all external requests are handled as invalidate...
669	// In case of external request the ICACHE FSM goes to the CC_CHECK
670	// state to test the external hit, and returns in the
671	// pre-empted state after completion.
672	// 2/ Processor requests are taken into account only in the IDLE state.
673	// In case of MISS, or in case of uncached instruction, the FSM
674	// writes the missing address line in the r_icache_addr_save register
675	// and sets the r_icache_miss_req or the r_icache_unc_req flip-flops.
676	// These request flip-flops are reset by the VCI_RSP FSM
677	// when the VCI transaction is completed and the r_icache_buf_unc_valid
678	// is set in case of uncached access.
679	// In case of bus error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
680	// flip-flop. It is reset by the ICACHE FSM.
681	///////////////////////////////////////////////////////////////////////
682
683	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
684	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
685
686	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
687	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
688
689	m_iss.getRequests( ireq, dreq );
690
691	#if DEBUG_CC_XCACHE_WRAPPER
692	std::cout << " Instruction Request: " << ireq << std::endl;
693	#endif
694
695	switch(r_icache_fsm) {
696	/////////////////
697	case ICACHE_IDLE:
698	{
699	if ( r_tgt_icache_req ) { // external request
700	if ( ireq.valid ) m_cost_ins_miss_frz++;
701	r_icache_fsm = ICACHE_CC_CHECK;
702	r_icache_fsm_save = r_icache_fsm.read();
703	break;
704	}
705	if ( ireq.valid ) {
706	data_t icache_ins = 0;
707	bool icache_hit = false;
708	bool icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr];
709	// icache_hit & icache_ins evaluation
710	if ( icache_cached ) {
711	icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins);
712	} else {
713	icache_hit = ( r_icache_buf_unc_valid && ((addr_40) ireq.addr == (addr_40)r_icache_addr_save) );
714	icache_ins = r_icache_miss_buf[0];
715	}
716	if ( ! icache_hit ) {
717	m_cpt_ins_miss++;
718	m_cost_ins_miss_frz++;
719	r_icache_addr_save = (addr_40) ireq.addr;
720	if ( icache_cached ) {
721	r_icache_fsm = ICACHE_MISS_WAIT;
722	r_icache_miss_req = true;
723	} else {
724	r_icache_fsm = ICACHE_UNC_WAIT;
725	r_icache_unc_req = true;
726	}
727	} else {
728	r_icache_buf_unc_valid = false;
729	}
730	m_cpt_icache_dir_read += m_icache_ways;
731	m_cpt_icache_data_read += m_icache_ways;
732	irsp.valid = icache_hit;
733	irsp.instruction = icache_ins;
734	}
735	break;
736	}
737	//////////////////////
738	case ICACHE_MISS_WAIT:
739	{
740	m_cost_ins_miss_frz++;
741	if ( r_tgt_icache_req ) { // external request
742	r_icache_fsm = ICACHE_CC_CHECK;
743	r_icache_fsm_save = r_icache_fsm.read();
744	break;
745	}
746	if ( !r_icache_miss_req && !r_icache_inval_rsp ) { // Miss read response and no invalidation
747	if ( r_vci_rsp_ins_error ) {
748	r_icache_fsm = ICACHE_ERROR;
749	} else {
750	r_icache_fsm = ICACHE_MISS_UPDT;
751	}
752	}
753	if ( !r_icache_miss_req && r_icache_inval_rsp ) { // Miss read response and invalidation
754	if ( r_vci_rsp_ins_error ) {
755	r_icache_inval_rsp = false;
756	r_icache_fsm = ICACHE_ERROR;
757	} else {
758	r_icache_inval_rsp = false;
759	r_icache_fsm = ICACHE_CC_CLEANUP;
760	}
761	}
762	break;
763	}
764	/////////////////////
765	case ICACHE_UNC_WAIT:
766	{
767	m_cost_ins_miss_frz++;
768	if ( r_tgt_icache_req ) { // external request
769	r_icache_fsm = ICACHE_CC_CHECK;
770	r_icache_fsm_save = r_icache_fsm.read();
771	break;
772	}
773	if ( !r_icache_unc_req ) {
774	if ( r_vci_rsp_ins_error ) {
775	r_icache_fsm = ICACHE_ERROR;
776	} else {
777	r_icache_fsm = ICACHE_IDLE;
778	r_icache_buf_unc_valid = true;
779	}
780	}
781	break;
782	}
783	//////////////////
784	case ICACHE_ERROR:
785	{
786	if ( (addr_40)ireq.addr == (addr_40)r_icache_addr_save ) {
787	irsp.error = true;
788	irsp.valid = true;
789	}
790	r_icache_fsm = ICACHE_IDLE;
791	r_vci_rsp_ins_error = false;
792	break;
793	}
794	//////////////////////
795	case ICACHE_MISS_UPDT:
796	{
797	if ( r_tgt_icache_req ) { // external request
798	r_icache_fsm = ICACHE_CC_CHECK;
799	r_icache_fsm_save = r_icache_fsm.read();
800	break;
801	}
802	if(!r_icache_cleanup_req.read() && !r_icache_inval_rsp){
803	vci_addr_t ad = 0;
804	ad = (vci_addr_t) r_icache_addr_save.read();
805	data_t* buf = r_icache_miss_buf;
806	vci_addr_t victim_index = 0;
807	m_cpt_icache_dir_write++;
808	m_cpt_icache_data_write++;
809	if ( ireq.valid ) m_cost_ins_miss_frz++;
810
811	r_icache_cleanup_req = r_icache.update(ad, buf, &victim_index);
812	r_icache_cleanup_line = (addr_40) victim_index;
813
814	r_icache_fsm = ICACHE_IDLE;
815	break;
816	}
817	if(r_icache_inval_rsp){
818	if ( ireq.valid ) m_cost_ins_miss_frz++;
819	r_icache_inval_rsp = false;
820	r_icache_fsm = ICACHE_CC_CLEANUP;
821	break;
822	}
823	if ( ireq.valid ) m_cost_ins_miss_frz++;
824	}
825	////////////////////
826	case ICACHE_CC_CLEANUP:
827	{
828	// external cache invalidate request
829	if ( r_tgt_icache_req )
830	{
831	r_icache_fsm = ICACHE_CC_CHECK;
832	r_icache_fsm_save = r_icache_fsm.read();
833	break;
834	}
835	// cleanup
836	if(!r_icache_cleanup_req){
837	r_icache_cleanup_req = true;
838	r_icache_cleanup_line = r_icache_addr_save.read() >> (uint32_log2(m_icache_words) + 2);
839	r_icache_fsm = ICACHE_IDLE;
840	}
841	break;
842	}
843	/////////////////////
844	case ICACHE_CC_CHECK: // read directory in case of invalidate or update request
845	{
846
847	m_cpt_icache_dir_read += m_icache_ways;
848	m_cpt_icache_data_read += m_icache_ways;
849	addr_40 ad = r_tgt_addr;
850	data_t icache_rdata = 0;
851
852	if(( ( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) &&
853	( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) {
854	r_icache_inval_rsp = true;
855	r_tgt_icache_req = false;
856	if(r_tgt_update){ // Also send a cleanup and answer
857	r_tgt_icache_rsp = true;
858	} else { // Also send a cleanup but don't answer
859	r_tgt_icache_rsp = false;
860	}
861	r_icache_fsm = r_icache_fsm_save;
862	} else {
863	bool icache_hit = r_icache.read(ad, &icache_rdata);
864	if ( icache_hit && r_tgt_update ) {
865	r_icache_fsm = ICACHE_CC_UPDT;
866	// complete the line buffer in case of update
867	for(size_t i=0; i<m_icache_words; i++){
868	data_t rdata = 0;
869	r_icache.read(ad + i*4,&rdata);
870	data_t mask = vci_param::be2mask(r_tgt_be[i]);
871	r_tgt_buf[i] = (mask & r_tgt_buf[i]) \| (~mask & rdata);
872	}
873	} else if ( icache_hit && !r_tgt_update ) {
874	r_icache_fsm = ICACHE_CC_INVAL;
875	} else { // instruction not found (can happen)
876	r_tgt_icache_req = false;
877	if(r_tgt_update){
878	r_tgt_icache_rsp = true;
879	} else {
880	r_tgt_icache_rsp = false;
881	}
882	r_icache_fsm = r_icache_fsm_save;
883	}
884	}
885	break;
886	}
887	/////////////////////
888	case ICACHE_CC_INVAL:
889	{
890	addr_40 ad = r_tgt_addr;
891	if ( ireq.valid ) m_cost_ins_miss_frz++;
892	m_cpt_icache_dir_read += m_icache_ways;
893	r_tgt_icache_rsp = true;
894	r_icache.inval(ad);
895	r_tgt_icache_req = false;
896	r_icache_fsm = r_icache_fsm_save;
897	break;
898	}
899	/////////////////////
900	case ICACHE_CC_UPDT:
901	{
902	m_cpt_icache_dir_write++;
903	m_cpt_icache_data_write++;
904	addr_40 ad = r_tgt_addr.read();
905	data_t* buf = r_tgt_buf;
906	for(size_t i=0; i<m_icache_words;i++){
907	if(r_tgt_be[i]) r_icache.write( ad + i*4, buf[i]);
908	}
909	r_tgt_icache_req = false;
910	r_tgt_icache_rsp = true;
911	r_icache_fsm = r_icache_fsm_save.read();
912	break;
913	}
914
915	} // end switch r_icache_fsm
916
917	#if DEBUG_CC_XCACHE_WRAPPER
918	std::cout << " Instruction Response: " << irsp << std::endl;
919	#endif
920
921	//////////////////////////////////////////////////////////////////////://///////////
922	// The DCACHE FSM controls the following ressources:
923	// - r_dcache_fsm
924	// - r_dcache_fsm_save
925	// - r_dcache (data cache access)
926	// - r_dcache_addr_save
927	// - r_dcache_wdata_save
928	// - r_dcache_rdata_save
929	// - r_dcache_type_save
930	// - r_dcache_be_save
931	// - r_dcache_cached_save
932	// - r_dcache_miss_req set
933	// - r_dcache_unc_req set
934	// - r_dcache_write_req set
935	// - r_dcache_cleanup_req set
936	// - r_vci_rsp_data_error reset
937	// - r_tgt_dcache_req reset
938	// - r_wbuf write
939	// - dreq & drsp structures for communication with the processor
940	//
941	// 1/ EXTERNAL REQUEST :
942	// There is an external request when the tgt_dcache req flip-flop is set,
943	// requesting a line invalidation or a line update.
944	// External requests are taken into account in the states IDLE, WRITE_REQ,
945	// UNC_WAIT, MISS_WAIT, and have the highest priority :
946	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
947	// goes to the CC_CHECK state to execute the requested action, and returns to the
948	// pre-empted state.
949	// 2/ PROCESSOR REQUEST :
950	// In order to support VCI write burst, the processor requests are taken into account
951	// in the WRITE_REQ state as well as in the IDLE state.
952	// - In the IDLE state, the processor request cannot be satisfied if
953	// there is a cached read miss, or an uncached read.
954	// - In the WRITE_REQ state, the request cannot be satisfied if
955	// there is a cached read miss, or an uncached read,
956	// or when the write buffer is full.
957	// - In all other states, the processor request is not satisfied.
958	//
959	// The cache access takes into account the cacheability_table.
960	// In case of processor request, there is five conditions to exit the IDLE state:
961	// - CACHED READ MISS => to the MISS_WAIT state (waiting the r_miss_ok signal),
962	// then to the MISS_UPDT state, and finally to the IDLE state.
963	// - UNCACHED READ => to the UNC_WAIT state (waiting the r_miss_ok signal),
964	// and to the IDLE state.
965	// - CACHE INVALIDATE HIT => to the INVAL state for one cycle, then to IDLE state.
966	// - WRITE MISS => directly to the WRITE_REQ state to access the write buffer.
967	// - WRITE HIT => to the WRITE_UPDT state, then to the WRITE_REQ state.
968	//
969	// Error handling : Read Bus Errors are synchronous events, but
970	// Write Bus Errors are asynchronous events (processor is not frozen).
971	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
972	// r_vci_rsp_data_error flip-flop, and the synchronous error is signaled
973	// by the DCACHE FSM.
974	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
975	// the asynchronous error using the setWriteBerr() method.
976	///////////////////////////////////////////////////////////////////////////////////
977
978	#if DEBUG_CC_XCACHE_WRAPPER
979	std::cout << " Data Request: " << dreq << std::endl;
980	#endif
981
982	//if( (m_cpt_total_cycles % 10000) ==0 ) std::cout << std::dec << "Proc " << m_srcid << " Data Request: " << dreq << std::endl;
983
984	switch ( r_dcache_fsm ) {
985
986	/////////////////////
987	case DCACHE_WRITE_REQ:
988	{
989	if ( r_tgt_dcache_req ) { // external request
990	r_dcache_fsm = DCACHE_CC_CHECK;
991	r_dcache_fsm_save = r_dcache_fsm;
992	break;
993	}
994	// try to post the write request in the write buffer
995	if ( !r_dcache_write_req ) { // no previous write transaction
996	if ( r_wbuf.wok(r_dcache_addr_save) ) { // write request in the same cache line
997	r_wbuf.write(r_dcache_addr_save, r_dcache_be_save, r_dcache_wdata_save);
998	// close the write packet if uncached
999	if ( !r_dcache_cached_save ){
1000	r_dcache_write_req = true ;
1001	}
1002	} else {
1003	// close the write packet if write request not in the same cache line
1004	r_dcache_write_req = true;
1005	if(!m_srcid_rw) {
1006	}
1007	m_cost_write_frz++;
1008	break; // posting request not possible : stay in DCACHE_WRITEREQ state
1009	}
1010	} else { // previous write transaction not completed
1011	m_cost_write_frz++;
1012	break; // posting request not possible : stay in DCACHE_WRITEREQ state
1013	}
1014
1015	// close the write packet if the next processor request is not a write
1016	if ( !dreq.valid \|\| (dreq.type != iss_t::DATA_WRITE) ) {
1017	r_dcache_write_req = true ;
1018	}
1019
1020	// The next state and the processor request parameters are computed
1021	// as in the DCACHE_IDLE state (see below ...)
1022	}
1023	/////////////////
1024	case DCACHE_IDLE:
1025	{
1026	if ( r_tgt_dcache_req ) { // external request
1027	r_dcache_fsm = DCACHE_CC_CHECK;
1028	r_dcache_fsm_save = r_dcache_fsm;
1029	break;
1030	}
1031
1032	if ( dreq.valid ) {
1033	bool dcache_hit = false;
1034	data_t dcache_rdata = 0;
1035	bool dcache_cached;
1036	m_cpt_dcache_data_read += m_dcache_ways;
1037	m_cpt_dcache_dir_read += m_dcache_ways;
1038
1039	// dcache_cached evaluation
1040	switch (dreq.type) {
1041	case iss_t::DATA_SC:
1042	case iss_t::XTN_READ:
1043	case iss_t::XTN_WRITE:
1044	dcache_cached = false;
1045	break;
1046	default:
1047	dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr];
1048	}
1049
1050	// dcache_hit & dcache_rdata evaluation
1051	if ( dcache_cached ) {
1052	dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
1053	} else {
1054	dcache_hit = false;
1055	}
1056
1057	switch( dreq.type ) {
1058	case iss_t::DATA_READ:
1059	case iss_t::DATA_LL:
1060	m_cpt_read++;
1061	if ( dcache_hit ) {
1062	r_dcache_fsm = DCACHE_IDLE;
1063	drsp.valid = true;
1064	drsp.rdata = dcache_rdata;
1065	if(dreq.type == iss_t::DATA_LL){
1066	r_dcache_ll_valid = true;
1067	r_dcache_ll_data = dcache_rdata;
1068	r_dcache_ll_addr = (vci_addr_t) dreq.addr;
1069	#ifdef COHERENCE_DEBUG
1070	std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
1071	r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
1072	std::cout << "Value stored at this address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
1073	#endif
1074	}
1075	} else {
1076	if ( dcache_cached ) {
1077	m_cpt_data_miss++;
1078	m_cost_data_miss_frz++;
1079	r_dcache_miss_req = true;
1080	r_dcache_fsm = DCACHE_MISS_WAIT;
1081	} else {
1082	m_cpt_unc_read++;
1083	m_cost_unc_read_frz++;
1084	r_dcache_unc_req = true;
1085	r_dcache_fsm = DCACHE_UNC_WAIT;
1086	}
1087	}
1088	break;
1089	case iss_t::DATA_SC:
1090	{
1091	m_cpt_unc_read++;
1092	m_cost_unc_read_frz++;
1093	if(r_dcache_ll_valid.read() && (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){
1094	r_dcache_sc_req = true;
1095	r_dcache_fsm = DCACHE_SC_WAIT;
1096	} else {
1097	drsp.valid = true;
1098	drsp.rdata = 1; // SC rsp NOK
1099	r_dcache_ll_valid = false;
1100	}
1101	break;
1102	}
1103	case iss_t::XTN_READ:
1104	case iss_t::XTN_WRITE:
1105	// only DCACHE INVALIDATE request are supported
1106	if ( dreq.addr/4 == iss_t::XTN_DCACHE_INVAL ){
1107	r_dcache_fsm = DCACHE_INVAL;
1108	} else {
1109	r_dcache_fsm = DCACHE_IDLE;
1110	}
1111	drsp.valid = true;
1112	drsp.rdata = 0;
1113	break;
1114	case iss_t::DATA_WRITE:
1115	m_cpt_write++;
1116	if ( dcache_hit && dcache_cached ) {
1117	r_dcache_fsm = DCACHE_WRITE_UPDT;
1118	m_cpt_write_cached++;
1119	} else {
1120	r_dcache_fsm = DCACHE_WRITE_REQ;
1121	}
1122	drsp.valid = true;
1123	drsp.rdata = 0;
1124	break;
1125	} // end switch dreq.type
1126
1127	r_dcache_addr_save = (addr_40) dreq.addr;
1128	r_dcache_type_save = dreq.type;
1129	r_dcache_wdata_save = dreq.wdata;
1130	r_dcache_be_save = dreq.be;
1131	r_dcache_rdata_save = dcache_rdata;
1132	r_dcache_cached_save = dcache_cached;
1133
1134	} else { // end if dreq.valid
1135	r_dcache_fsm = DCACHE_IDLE;
1136	}
1137	// processor request are not accepted in the WRITE_REQUEST state
1138	// when the write buffer is not writeable
1139	if ( (r_dcache_fsm == DCACHE_WRITE_REQ) &&
1140	(r_dcache_write_req \|\| !r_wbuf.wok(r_dcache_addr_save)) ) {
1141	drsp.valid = false;
1142	drsp.rdata = 0;
1143	}
1144	break;
1145	}
1146	///////////////////////
1147	case DCACHE_WRITE_UPDT:
1148	{
1149	m_cpt_dcache_data_write++;
1150	data_t mask = vci_param::be2mask(r_dcache_be_save);
1151	data_t wdata = (mask & r_dcache_wdata_save) \| (~mask & r_dcache_rdata_save);
1152	vci_addr_t ad = r_dcache_addr_save.read();
1153	r_dcache.write(ad, wdata);
1154	r_dcache_fsm = DCACHE_WRITE_REQ;
1155	break;
1156	}
1157	//////////////////////
1158	case DCACHE_MISS_WAIT:
1159	{
1160
1161	if ( dreq.valid ) m_cost_data_miss_frz++;
1162	if ( r_tgt_dcache_req.read() ) { // external request
1163	r_dcache_fsm = DCACHE_CC_CHECK;
1164	r_dcache_fsm_save = r_dcache_fsm;
1165	break;
1166	}
1167	if ( !r_dcache_miss_req && !r_dcache_inval_rsp ) { // Miss read response and no invalidation
1168	if ( r_vci_rsp_data_error ) {
1169	r_dcache_fsm = DCACHE_ERROR;
1170	} else {
1171	r_dcache_fsm = DCACHE_MISS_UPDT;
1172	}
1173	break;
1174	}
1175	if ( !r_dcache_miss_req && r_dcache_inval_rsp ) { // Miss read response and invalidation
1176	if ( r_vci_rsp_data_error ) {
1177	r_dcache_inval_rsp = false;
1178	r_dcache_fsm = DCACHE_ERROR;
1179	} else {
1180	r_dcache_inval_rsp = false;
1181	r_dcache_fsm = DCACHE_CC_CLEANUP;
1182	}
1183	break;
1184	}
1185	break;
1186	}
1187	//////////////////////
1188	case DCACHE_MISS_UPDT:
1189
1190	{
1191	if ( r_tgt_dcache_req.read() ) { // external request
1192	r_dcache_fsm = DCACHE_CC_CHECK;
1193	r_dcache_fsm_save = r_dcache_fsm;
1194	break;
1195	}
1196	if( !r_dcache_cleanup_req.read() && !r_dcache_inval_rsp ){
1197	vci_addr_t ad = 0;
1198	ad = (vci_addr_t) r_dcache_addr_save.read();
1199	data_t* buf = new data_t[m_dcache_words];
1200	for(size_t i=0; i<m_dcache_words; i++) {
1201	buf[i] = r_dcache_miss_buf[i];
1202	}
1203	vci_addr_t victim_index = 0;
1204	if ( dreq.valid ) m_cost_data_miss_frz++;
1205	m_cpt_dcache_data_write++;
1206	m_cpt_dcache_dir_write++;
1207
1208	r_dcache_cleanup_req = r_dcache.update(ad, buf, &victim_index);
1209	r_dcache_cleanup_line = (addr_40) victim_index;
1210
1211	r_dcache_fsm = DCACHE_IDLE;
1212	delete [] buf;
1213	break;
1214	}
1215	if( r_dcache_inval_rsp ){
1216	r_dcache_inval_rsp = false;
1217	r_dcache_fsm = DCACHE_CC_CLEANUP;
1218	break;
1219	}
1220	break;
1221	}
1222	////////////////////
1223	case DCACHE_UNC_WAIT:
1224	{
1225	if ( dreq.valid ) m_cost_unc_read_frz++;
1226	if ( r_tgt_dcache_req ) { // external request
1227	r_dcache_fsm = DCACHE_CC_CHECK;
1228	r_dcache_fsm_save = r_dcache_fsm;
1229	break;
1230	}
1231	if ( !r_dcache_unc_req ) {
1232	if ( r_vci_rsp_data_error ) {
1233	r_dcache_fsm = DCACHE_ERROR;
1234	} else {
1235	if(dreq.type == iss_t::DATA_LL){
1236	r_dcache_ll_valid = true;
1237	r_dcache_ll_data = r_dcache_miss_buf[0];
1238	r_dcache_ll_addr = (vci_addr_t) dreq.addr;
1239	}
1240	r_dcache_fsm = DCACHE_IDLE;
1241	drsp.valid = true;
1242	drsp.rdata = r_dcache_miss_buf[0];
1243	}
1244	}
1245	break;
1246	}
1247	////////////////////
1248	case DCACHE_SC_WAIT:
1249	{
1250	if ( dreq.valid ) m_cost_unc_read_frz++;
1251	if ( r_tgt_dcache_req ) { // external request
1252	r_dcache_fsm = DCACHE_CC_CHECK;
1253	r_dcache_fsm_save = r_dcache_fsm;
1254	break;
1255	}
1256	if ( !r_dcache_sc_req ) {
1257	if ( r_vci_rsp_data_error ) {
1258	r_dcache_fsm = DCACHE_ERROR;
1259	} else {
1260	r_dcache_fsm = DCACHE_IDLE;
1261	drsp.valid = true;
1262	drsp.rdata = r_dcache_miss_buf[0];
1263	r_dcache_ll_valid = false;
1264	}
1265	}
1266	break;
1267	}
1268
1269	//////////////////
1270	case DCACHE_ERROR:
1271	{
1272	r_dcache_fsm = DCACHE_IDLE;
1273	r_vci_rsp_data_error = false;
1274	drsp.error = true;
1275	drsp.valid = true;
1276	break;
1277	}
1278	/////////////////
1279	case DCACHE_INVAL:
1280	{
1281	if ( r_tgt_dcache_req.read() ) { // external request
1282	r_dcache_fsm = DCACHE_CC_CHECK;
1283	r_dcache_fsm_save = r_dcache_fsm;
1284	break;
1285	}
1286	if( !r_dcache_cleanup_req.read() ){
1287	m_cpt_dcache_dir_read += m_dcache_ways;
1288	vci_addr_t ad = r_dcache_addr_save.read();
1289	r_dcache_cleanup_req = r_dcache.inval(ad);
1290	r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words)+2);
1291
1292	r_dcache_fsm = DCACHE_IDLE;
1293	}
1294	break;
1295	}
1296	/////////////////////
1297	case DCACHE_CC_CHECK: // read directory in case of invalidate or update request
1298	{
1299
1300	m_cpt_dcache_dir_read += m_dcache_ways;
1301	m_cpt_dcache_data_read += m_dcache_ways;
1302	addr_40 ad = r_tgt_addr;
1303	data_t dcache_rdata = 0;
1304
1305	if(( ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) &&
1306	( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) {
1307	r_dcache_inval_rsp = true;
1308	r_tgt_dcache_req = false;
1309	if(r_tgt_update){ // Also send a cleanup and answer
1310	r_tgt_dcache_rsp = true;
1311	} else { // Also send a cleanup but don't answer
1312	r_tgt_dcache_rsp = false;
1313	}
1314	r_dcache_fsm = r_dcache_fsm_save;
1315	} else {
1316	bool dcache_hit = r_dcache.read(ad, &dcache_rdata);
1317	#ifdef COHERENCE_DEBUG
1318	std::cout << "PROC " << m_srcid_rw << " DCACHE_CC_CHECK, hit ? : " << dcache_hit << std::endl;
1319	#endif
1320	if ( dcache_hit && r_tgt_update ) {
1321	// complete the line buffer in case of update
1322	for(size_t i=0; i<m_dcache_words; i++){
1323	data_t rdata = 0;
1324	r_dcache.read(ad + i*4,&rdata);
1325	data_t mask = vci_param::be2mask(r_tgt_be[i]);
1326	r_tgt_buf[i] = (mask & r_tgt_buf[i]) \| (~mask & rdata);
1327	}
1328	r_dcache_fsm = DCACHE_CC_UPDT;
1329	} else if ( dcache_hit && !r_tgt_update ) {
1330	r_dcache_fsm = DCACHE_CC_INVAL;
1331	} else {
1332	if(r_tgt_update){
1333	r_tgt_dcache_rsp = true;
1334	} else {
1335	r_tgt_dcache_rsp = false;
1336	}
1337	r_tgt_dcache_req = false;
1338	r_dcache_fsm = r_dcache_fsm_save;
1339	}
1340	}
1341	break;
1342	}
1343	///////////////////
1344	case DCACHE_CC_UPDT: // update directory and data cache
1345	{
1346	m_cpt_dcache_dir_write++;
1347	m_cpt_dcache_data_write++;
1348	addr_40 ad = r_tgt_addr;
1349	data_t* buf = r_tgt_buf;
1350	#ifdef COHERENCE_DEBUG
1351	std::cout << "PROC " << m_srcid_rw << " DCACHE_CC_UPDT, update : " << std::endl;
1352	#endif
1353	for(size_t i=0; i<m_dcache_words; i++){
1354	if(r_tgt_be[i]) {
1355	r_dcache.write( ad + i*4, buf[i]);
1356	#ifdef COHERENCE_DEBUG
1357	std::cout << " address " << std::hex << ad+i*4 << " data " << std::dec << buf[i] << std::endl;
1358	data_t rdata = 0xAAAAAAAA;
1359	r_dcache.read(ad + i*4,&rdata);
1360	std::cout << "data written " << rdata << std::endl;
1361	#endif
1362	}
1363	}
1364	r_tgt_dcache_req = false;
1365	r_tgt_dcache_rsp = true;
1366	r_dcache_fsm = r_dcache_fsm_save;
1367	break;
1368	}
1369	/////////////////////
1370	case DCACHE_CC_INVAL: // invalidate a cache line
1371	{
1372	addr_40 ad = r_tgt_addr;
1373	r_tgt_dcache_rsp = true;
1374	r_dcache.inval(ad);
1375	r_tgt_dcache_req = false;
1376	r_dcache_fsm = r_dcache_fsm_save;
1377	break;
1378	}
1379	///////////////////
1380	case DCACHE_CC_CLEANUP:
1381	{
1382	// external cache invalidate request
1383	if ( r_tgt_dcache_req )
1384	{
1385	r_dcache_fsm = DCACHE_CC_CHECK;
1386	r_dcache_fsm_save = r_dcache_fsm;
1387	break;
1388	}
1389	// cleanup
1390	if(!r_dcache_cleanup_req){
1391	r_dcache_cleanup_req = true;
1392	r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words) + 2);
1393	r_dcache_fsm = DCACHE_IDLE;
1394	}
1395	break;
1396	}
1397
1398	} // end switch r_dcache_fsm
1399
1400	#if DEBUG_CC_XCACHE_WRAPPER
1401	std::cout << " Data Response: " << drsp << std::endl;
1402	#endif
1403
1404	/////////// execute one iss cycle /////////////////////////////////////////////
1405	{
1406	uint32_t it = 0;
1407	for (size_t i=0; i<(size_t)iss_t::n_irq; i++)
1408	if(p_irq[i].read()) it \|= (1<<i);
1409	m_iss.executeNCycles(1, irsp, drsp, it);
1410	}
1411
1412	if ( (ireq.valid && !irsp.valid) \|\| (dreq.valid && !drsp.valid) ) m_cpt_frz_cycles++;
1413
1414
1415	////////////////////////////////////////////////////////////////////////////
1416	// The VCI_CMD FSM controls the following ressources:
1417	// - r_vci_cmd_fsm
1418	// - r_vci_cmd_min
1419	// - r_vci_cmd_max
1420	// - r_vci_cmd_cpt
1421	// - wbuf reset
1422	//
1423	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
1424	// There is 7 request types, with the following priorities :
1425	// 1 - Instruction Miss : r_icache_miss_req
1426	// 2 - Data Write : r_dcache_write_req
1427	// 3 - Data Read Miss : r_dcache_miss_req
1428	// 4 - Data Read Uncached : r_dcache_unc_req
1429	// 5 - Instruction Cleanup : r_icache_cleanup_req
1430	// 6 - Data Cleanup : r_dcache_cleanup_req
1431	// There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM
1432	// and RSP_FSM exit simultaneously the IDLE state.
1433	//
1434	// VCI formats:
1435	// According to the VCI advanced specification, all read requests packets
1436	// (read Uncached, Miss data, Miss instruction) are one word packets.
1437	// For write burst packets, all words must be in the same cache line,
1438	// and addresses must be contiguous (the BE field is 0 in case of "holes").
1439	//////////////////////////////////////////////////////////////////////////////
1440
1441	switch (r_vci_cmd_fsm) {
1442
1443	case CMD_IDLE:
1444	if (r_vci_rsp_fsm != RSP_IDLE) break;
1445
1446	r_vci_cmd_cpt = 0;
1447	if ( r_icache_cleanup_req ) {
1448	r_vci_cmd_fsm = CMD_INS_CLEANUP;
1449	} else if ( r_dcache_cleanup_req ) {
1450	r_vci_cmd_fsm = CMD_DATA_CLEANUP;
1451	} else if ( r_icache_miss_req ) {
1452	r_vci_cmd_fsm = CMD_INS_MISS;
1453	m_cpt_imiss_transaction++;
1454	} else if ( r_icache_unc_req ) {
1455	r_vci_cmd_fsm = CMD_INS_UNC;
1456	m_cpt_imiss_transaction++;
1457	} else if ( r_dcache_write_req ) {
1458	r_vci_cmd_fsm = CMD_DATA_WRITE;
1459	r_vci_cmd_cpt = r_wbuf.getMin();
1460	r_vci_cmd_min = r_wbuf.getMin();
1461	r_vci_cmd_max = r_wbuf.getMax();
1462	m_cpt_write_transaction++;
1463	m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
1464	} else if ( r_dcache_miss_req ) {
1465	r_vci_cmd_fsm = CMD_DATA_MISS;
1466	m_cpt_dmiss_transaction++;
1467	} else if ( r_dcache_unc_req ) {
1468	r_vci_cmd_fsm = CMD_DATA_UNC;
1469	m_cpt_unc_transaction++;
1470	} else if ( r_dcache_sc_req ) {
1471	r_vci_cmd_fsm = CMD_DATA_SC;
1472	r_vci_cmd_max = 1;
1473	m_cpt_unc_transaction++;
1474	}
1475	break;
1476
1477	case CMD_DATA_WRITE:
1478	if ( p_vci_ini_rw.cmdack.read() ) {
1479	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
1480	if (r_vci_cmd_cpt == r_vci_cmd_max) {
1481	r_vci_cmd_fsm = CMD_IDLE ;
1482	r_wbuf.reset() ;
1483	}
1484	}
1485	break;
1486
1487	case CMD_DATA_SC:
1488	if ( p_vci_ini_rw.cmdack.read() ) {
1489	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
1490	if (r_vci_cmd_cpt == r_vci_cmd_max) {
1491	r_vci_cmd_fsm = CMD_IDLE ;
1492	}
1493	}
1494	break;
1495	case CMD_INS_MISS:
1496	case CMD_INS_UNC:
1497	case CMD_DATA_MISS:
1498	case CMD_DATA_UNC:
1499	if ( p_vci_ini_rw.cmdack.read() ) {
1500	r_vci_cmd_fsm = CMD_IDLE;
1501	}
1502	break;
1503	case CMD_INS_CLEANUP:
1504	case CMD_DATA_CLEANUP:
1505	if ( p_vci_ini_c.cmdack.read() ) {
1506	r_vci_cmd_fsm = CMD_IDLE;
1507	}
1508	break;
1509
1510	} // end switch r_vci_cmd_fsm
1511
1512	//////////////////////////////////////////////////////////////////////////
1513	// The VCI_RSP FSM controls the following ressources:
1514	// - r_vci_rsp_fsm:
1515	// - r_icache_miss_buf[m_icache_words]
1516	// - r_dcache_miss_buf[m_dcache_words]
1517	// - r_icache_miss_req reset
1518	// - r_icache_unc_req reset
1519	// - r_dcache_miss_req reset
1520	// - r_icache_cleanup_req reset
1521	// - r_dcache_cleanup_req reset
1522	// - r_vci_rsp_data_error set
1523	// - r_vci_rsp_ins_error set
1524	// - r_vci_rsp_cpt
1525	// In order to have only one active VCI transaction, this VCI_RSP_FSM
1526	// is synchronized with the VCI_CMD FSM, and both FSMs exit the
1527	// IDLE state simultaneously.
1528	//
1529	// VCI formats:
1530	// This component accepts single word or multi-word response packets for
1531	// write response packets.
1532	//
1533	// Error handling:
1534	// This FSM analyzes the VCI error code and signals directly the
1535	// Write Bus Error.
1536	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
1537	// flip_flop and the error is signaled by the DCACHE FSM.
1538	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
1539	// flip_flop and the error is signaled by the DCACHE FSM.
1540	// In case of Cleanup Error, the simulation stops with an error message...
1541	//////////////////////////////////////////////////////////////////////////
1542
1543	switch (r_vci_rsp_fsm) {
1544
1545	case RSP_IDLE:
1546	if(p_vci_ini_rw.rspval.read()\|\|
1547	p_vci_ini_c.rspval.read())
1548	{
1549	std::cout << "CC_XCache " << m_srcid_rw << " Unexpected response" << std::endl;
1550	}
1551	assert( ! p_vci_ini_rw.rspval.read() && ! p_vci_ini_c.rspval.read() && "Unexpected response" );
1552	if (r_vci_cmd_fsm != CMD_IDLE) break;
1553
1554	r_vci_rsp_cpt = 0;
1555	if ( r_icache_cleanup_req ) r_vci_rsp_fsm = RSP_INS_CLEANUP;
1556	else if ( r_dcache_cleanup_req ) r_vci_rsp_fsm = RSP_DATA_CLEANUP;
1557	else if ( r_icache_miss_req ) r_vci_rsp_fsm = RSP_INS_MISS;
1558	else if ( r_icache_unc_req ) r_vci_rsp_fsm = RSP_INS_UNC;
1559	else if ( r_dcache_write_req ) r_vci_rsp_fsm = RSP_DATA_WRITE;
1560	else if ( r_dcache_miss_req ) r_vci_rsp_fsm = RSP_DATA_MISS;
1561	else if ( r_dcache_unc_req ) r_vci_rsp_fsm = RSP_DATA_UNC;
1562	else if ( r_dcache_sc_req ) r_vci_rsp_fsm = RSP_DATA_SC;
1563	break;
1564
1565	case RSP_INS_MISS:
1566	m_cost_imiss_transaction++;
1567	if ( ! p_vci_ini_rw.rspval.read() )
1568	break;
1569	assert( (r_vci_rsp_cpt < m_icache_words) &&
1570	"The VCI response packet for instruction miss is too long" );
1571	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
1572	r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
1573
1574	if ( p_vci_ini_rw.reop.read() ) {
1575	assert( ((r_vci_rsp_cpt == m_icache_words - 1) \|\|
1576	p_vci_ini_rw.rerror.read() \|\|
1577	(r_vci_rsp_ins_error.read()&0x1))&&
1578	"The VCI response packet for instruction miss is too short");
1579	r_icache_miss_req = false;
1580	r_vci_rsp_fsm = RSP_IDLE;
1581	}
1582	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
1583	break;
1584
1585	case RSP_INS_UNC:
1586	m_cost_imiss_transaction++;
1587	if ( ! p_vci_ini_rw.rspval.read() )
1588	break;
1589	assert(p_vci_ini_rw.reop.read() &&
1590	"illegal VCI response packet for uncached instruction");
1591	r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1592	r_vci_rsp_fsm = RSP_IDLE;
1593	r_icache_unc_req = false;
1594	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
1595	break;
1596
1597	case RSP_DATA_MISS:
1598	m_cost_dmiss_transaction++;
1599	if ( ! p_vci_ini_rw.rspval.read() )
1600	break;
1601	assert(r_vci_rsp_cpt != m_dcache_words &&
1602	"illegal VCI response packet for data read miss");
1603	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
1604	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
1605	if ( p_vci_ini_rw.reop.read() ) {
1606	assert( ((r_vci_rsp_cpt == m_dcache_words - 1)
1607	\|\| (p_vci_ini_rw.rerror.read()&0x1)
1608	\|\| r_vci_rsp_data_error.read()) &&
1609	"illegal VCI response packet for data read miss");
1610	r_dcache_miss_req = false;
1611	r_vci_rsp_fsm = RSP_IDLE;
1612	}
1613	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1614	break;
1615
1616	case RSP_DATA_WRITE:
1617	m_cost_write_transaction++;
1618	if ( ! p_vci_ini_rw.rspval.read() )
1619	break;
1620	if ( p_vci_ini_rw.reop.read() ) {
1621	r_vci_rsp_fsm = RSP_IDLE;
1622	r_dcache_write_req = false;
1623	}
1624	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
1625	break;
1626
1627	case RSP_DATA_UNC:
1628	m_cost_unc_transaction++;
1629	if ( ! p_vci_ini_rw.rspval.read() )
1630	break;
1631	assert(p_vci_ini_rw.reop.read() &&
1632	"illegal VCI response packet for data read uncached");
1633	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1634	r_vci_rsp_fsm = RSP_IDLE;
1635	r_dcache_unc_req = false;
1636	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1637	break;
1638
1639	case RSP_DATA_SC:
1640	m_cost_unc_transaction++;
1641	if ( ! p_vci_ini_rw.rspval.read() )
1642	break;
1643	assert(p_vci_ini_rw.reop.read() &&
1644	"illegal VCI response packet for data SC");
1645	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1646	r_vci_rsp_fsm = RSP_IDLE;
1647	r_dcache_sc_req = false;
1648	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1649	break;
1650
1651	case RSP_INS_CLEANUP:
1652	case RSP_DATA_CLEANUP:
1653	if ( ! p_vci_ini_c.rspval.read() )
1654	break;
1655	assert( p_vci_ini_c.reop.read() &&
1656	"illegal VCI response packet for icache cleanup");
1657	assert( ((p_vci_ini_c.rerror.read()&0x1) == vci_param::ERR_NORMAL) &&
1658	"error in response packet for icache cleanup");
1659	if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false;
1660	else r_dcache_cleanup_req = false;
1661	r_vci_rsp_fsm = RSP_IDLE;
1662	break;
1663
1664	} // end switch r_vci_rsp_fsm
1665
1666	} // end transition()
1667
1668	//////////////////////////////////////////////////////////////////////////////////
1669	tmpl(void)::genMoore()
1670	//////////////////////////////////////////////////////////////////////////////////
1671	{
1672	// VCI initiator response
1673
1674	p_vci_ini_rw.rspack = true;
1675	p_vci_ini_c.rspack = true;
1676
1677	// VCI initiator command
1678
1679	switch (r_vci_cmd_fsm.read() ) {
1680
1681	case CMD_IDLE:
1682	p_vci_ini_rw.cmdval = false;
1683	p_vci_ini_rw.address = 0;
1684	p_vci_ini_rw.wdata = 0;
1685	p_vci_ini_rw.be = 0;
1686	p_vci_ini_rw.plen = 0;
1687	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1688	p_vci_ini_rw.trdid = 0;
1689	p_vci_ini_rw.pktid = 0;
1690	p_vci_ini_rw.srcid = 0;
1691	p_vci_ini_rw.cons = false;
1692	p_vci_ini_rw.wrap = false;
1693	p_vci_ini_rw.contig = false;
1694	p_vci_ini_rw.clen = 0;
1695	p_vci_ini_rw.cfixed = false;
1696	p_vci_ini_rw.eop = false;
1697
1698	p_vci_ini_c.cmdval = false;
1699	p_vci_ini_c.address = 0;
1700	p_vci_ini_c.wdata = 0;
1701	p_vci_ini_c.be = 0;
1702	p_vci_ini_c.plen = 0;
1703	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1704	p_vci_ini_c.trdid = 0;
1705	p_vci_ini_c.pktid = 0;
1706	p_vci_ini_c.srcid = 0;
1707	p_vci_ini_c.cons = false;
1708	p_vci_ini_c.wrap = false;
1709	p_vci_ini_c.contig = false;
1710	p_vci_ini_c.clen = 0;
1711	p_vci_ini_c.cfixed = false;
1712	p_vci_ini_c.eop = false;
1713
1714	break;
1715
1716	case CMD_DATA_UNC:
1717	p_vci_ini_rw.cmdval = true;
1718	p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
1719	switch( r_dcache_type_save ) {
1720	case iss_t::DATA_READ:
1721	p_vci_ini_rw.wdata = 0;
1722	p_vci_ini_rw.be = r_dcache_be_save.read();
1723	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1724	break;
1725	case iss_t::DATA_LL:
1726	p_vci_ini_rw.wdata = 0;
1727	p_vci_ini_rw.be = 0xF;
1728	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
1729	break;
1730	default:
1731	assert("this should not happen");
1732	}
1733	p_vci_ini_rw.plen = 4;
1734	p_vci_ini_rw.trdid = 0; // data cache uncached read
1735	p_vci_ini_rw.pktid = 0;
1736	p_vci_ini_rw.srcid = m_srcid_rw;
1737	p_vci_ini_rw.cons = false;
1738	p_vci_ini_rw.wrap = false;
1739	p_vci_ini_rw.contig = true;
1740	p_vci_ini_rw.clen = 0;
1741	p_vci_ini_rw.cfixed = false;
1742	p_vci_ini_rw.eop = true;
1743
1744	p_vci_ini_c.cmdval = false;
1745	p_vci_ini_c.address = 0;
1746	p_vci_ini_c.wdata = 0;
1747	p_vci_ini_c.be = 0;
1748	p_vci_ini_c.plen = 0;
1749	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1750	p_vci_ini_c.trdid = 0;
1751	p_vci_ini_c.pktid = 0;
1752	p_vci_ini_c.srcid = 0;
1753	p_vci_ini_c.cons = false;
1754	p_vci_ini_c.wrap = false;
1755	p_vci_ini_c.contig = false;
1756	p_vci_ini_c.clen = 0;
1757	p_vci_ini_c.cfixed = false;
1758	p_vci_ini_c.eop = false;
1759
1760	break;
1761
1762	case CMD_DATA_SC:
1763	p_vci_ini_rw.cmdval = true;
1764	p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
1765	if(r_vci_cmd_max.read() == 3){
1766	assert(false && "Not handled yet");
1767	} else { // r_vci_cmd_cpt == 1
1768	switch(r_vci_cmd_cpt.read()){
1769	case 0:
1770	p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data.read() & 0xFFFFFFFF);
1771	break;
1772	case 1:
1773	p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
1774	break;
1775	}
1776	}
1777	p_vci_ini_rw.be = 0xF;
1778	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
1779	p_vci_ini_rw.plen = 4*(r_vci_cmd_max.read()+1);
1780	p_vci_ini_rw.trdid = 0; // data cache uncached read
1781	p_vci_ini_rw.pktid = 0;
1782	p_vci_ini_rw.srcid = m_srcid_rw;
1783	p_vci_ini_rw.cons = true;
1784	p_vci_ini_rw.wrap = false;
1785	p_vci_ini_rw.contig = false;
1786	p_vci_ini_rw.clen = 0;
1787	p_vci_ini_rw.cfixed = false;
1788	p_vci_ini_rw.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
1789
1790	p_vci_ini_c.cmdval = false;
1791	p_vci_ini_c.address = 0;
1792	p_vci_ini_c.wdata = 0;
1793	p_vci_ini_c.be = 0;
1794	p_vci_ini_c.plen = 0;
1795	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1796	p_vci_ini_c.trdid = 0;
1797	p_vci_ini_c.pktid = 0;
1798	p_vci_ini_c.srcid = 0;
1799	p_vci_ini_c.cons = false;
1800	p_vci_ini_c.wrap = false;
1801	p_vci_ini_c.contig = false;
1802	p_vci_ini_c.clen = 0;
1803	p_vci_ini_c.cfixed = false;
1804	p_vci_ini_c.eop = false;
1805
1806	break;
1807
1808	case CMD_DATA_WRITE:
1809	p_vci_ini_rw.cmdval = true;
1810	p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt)&~0x3;
1811	p_vci_ini_rw.wdata = r_wbuf.getData(r_vci_cmd_cpt);
1812	p_vci_ini_rw.be = r_wbuf.getBe(r_vci_cmd_cpt);
1813	p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
1814	p_vci_ini_rw.cmd = vci_param::CMD_WRITE;
1815	p_vci_ini_rw.trdid = 0; // data cache write
1816	p_vci_ini_rw.pktid = 0;
1817	p_vci_ini_rw.srcid = m_srcid_rw;
1818	p_vci_ini_rw.cons = false;
1819	p_vci_ini_rw.wrap = false;
1820	p_vci_ini_rw.contig = true;
1821	p_vci_ini_rw.clen = 0;
1822	p_vci_ini_rw.cfixed = false;
1823	p_vci_ini_rw.eop = (r_vci_cmd_cpt == r_vci_cmd_max);
1824
1825	p_vci_ini_c.cmdval = false;
1826	p_vci_ini_c.address = 0;
1827	p_vci_ini_c.wdata = 0;
1828	p_vci_ini_c.be = 0;
1829	p_vci_ini_c.plen = 0;
1830	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1831	p_vci_ini_c.trdid = 0;
1832	p_vci_ini_c.pktid = 0;
1833	p_vci_ini_c.srcid = 0;
1834	p_vci_ini_c.cons = false;
1835	p_vci_ini_c.wrap = false;
1836	p_vci_ini_c.contig = false;
1837	p_vci_ini_c.clen = 0;
1838	p_vci_ini_c.cfixed = false;
1839	p_vci_ini_c.eop = false;
1840
1841	break;
1842
1843	case CMD_DATA_MISS:
1844	p_vci_ini_rw.cmdval = true;
1845	p_vci_ini_rw.address = r_dcache_addr_save.read() & (addr_40) m_dcache_yzmask;
1846	p_vci_ini_rw.be = 0xF;
1847	p_vci_ini_rw.plen = m_dcache_words << 2;
1848	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1849	p_vci_ini_rw.trdid = 1; // data cache cached read
1850	p_vci_ini_rw.pktid = 0;
1851	p_vci_ini_rw.srcid = m_srcid_rw;
1852	p_vci_ini_rw.cons = false;
1853	p_vci_ini_rw.wrap = false;
1854	p_vci_ini_rw.contig = true;
1855	p_vci_ini_rw.clen = 0;
1856	p_vci_ini_rw.cfixed = false;
1857	p_vci_ini_rw.eop = true;
1858
1859	p_vci_ini_c.cmdval = false;
1860	p_vci_ini_c.address = 0;
1861	p_vci_ini_c.wdata = 0;
1862	p_vci_ini_c.be = 0;
1863	p_vci_ini_c.plen = 0;
1864	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1865	p_vci_ini_c.trdid = 0;
1866	p_vci_ini_c.pktid = 0;
1867	p_vci_ini_c.srcid = 0;
1868	p_vci_ini_c.cons = false;
1869	p_vci_ini_c.wrap = false;
1870	p_vci_ini_c.contig = false;
1871	p_vci_ini_c.clen = 0;
1872	p_vci_ini_c.cfixed = false;
1873	p_vci_ini_c.eop = false;
1874
1875	break;
1876
1877	case CMD_INS_MISS:
1878	p_vci_ini_rw.cmdval = true;
1879	p_vci_ini_rw.address = r_icache_addr_save.read() & (addr_40) m_icache_yzmask;
1880	p_vci_ini_rw.be = 0xF;
1881	p_vci_ini_rw.plen = m_icache_words << 2;
1882	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1883	p_vci_ini_rw.trdid = 3; // ins cache cached read
1884	p_vci_ini_rw.pktid = 0;
1885	p_vci_ini_rw.srcid = m_srcid_rw;
1886	p_vci_ini_rw.cons = false;
1887	p_vci_ini_rw.wrap = false;
1888	p_vci_ini_rw.contig = true;
1889	p_vci_ini_rw.clen = 0;
1890	p_vci_ini_rw.cfixed = false;
1891	p_vci_ini_rw.eop = true;
1892
1893	p_vci_ini_c.cmdval = false;
1894	p_vci_ini_c.address = 0;
1895	p_vci_ini_c.wdata = 0;
1896	p_vci_ini_c.be = 0;
1897	p_vci_ini_c.plen = 0;
1898	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1899	p_vci_ini_c.trdid = 0;
1900	p_vci_ini_c.pktid = 0;
1901	p_vci_ini_c.srcid = 0;
1902	p_vci_ini_c.cons = false;
1903	p_vci_ini_c.wrap = false;
1904	p_vci_ini_c.contig = false;
1905	p_vci_ini_c.clen = 0;
1906	p_vci_ini_c.cfixed = false;
1907	p_vci_ini_c.eop = false;
1908
1909	break;
1910
1911	case CMD_INS_UNC:
1912	p_vci_ini_rw.cmdval = true;
1913	p_vci_ini_rw.address = r_icache_addr_save.read() & ~0x3;
1914	p_vci_ini_rw.be = 0xF;
1915	p_vci_ini_rw.plen = 4;
1916	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1917	p_vci_ini_rw.trdid = 2; // ins cache uncached read
1918	p_vci_ini_rw.pktid = 0;
1919	p_vci_ini_rw.srcid = m_srcid_rw;
1920	p_vci_ini_rw.cons = false;
1921	p_vci_ini_rw.wrap = false;
1922	p_vci_ini_rw.contig = true;
1923	p_vci_ini_rw.clen = 0;
1924	p_vci_ini_rw.cfixed = false;
1925	p_vci_ini_rw.eop = true;
1926
1927	p_vci_ini_c.cmdval = false;
1928	p_vci_ini_c.address = 0;
1929	p_vci_ini_c.wdata = 0;
1930	p_vci_ini_c.be = 0;
1931	p_vci_ini_c.plen = 0;
1932	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1933	p_vci_ini_c.trdid = 0;
1934	p_vci_ini_c.pktid = 0;
1935	p_vci_ini_c.srcid = 0;
1936	p_vci_ini_c.cons = false;
1937	p_vci_ini_c.wrap = false;
1938	p_vci_ini_c.contig = false;
1939	p_vci_ini_c.clen = 0;
1940	p_vci_ini_c.cfixed = false;
1941	p_vci_ini_c.eop = false;
1942
1943
1944	break;
1945
1946	case CMD_INS_CLEANUP:
1947	p_vci_ini_rw.cmdval = false;
1948	p_vci_ini_rw.address = 0;
1949	p_vci_ini_rw.wdata = 0;
1950	p_vci_ini_rw.be = 0;
1951	p_vci_ini_rw.plen = 0;
1952	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1953	p_vci_ini_rw.trdid = 0;
1954	p_vci_ini_rw.pktid = 0;
1955	p_vci_ini_rw.srcid = 0;
1956	p_vci_ini_rw.cons = false;
1957	p_vci_ini_rw.wrap = false;
1958	p_vci_ini_rw.contig = false;
1959	p_vci_ini_rw.clen = 0;
1960	p_vci_ini_rw.cfixed = false;
1961	p_vci_ini_rw.eop = false;
1962
1963	p_vci_ini_c.cmdval = true;
1964	p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
1965	p_vci_ini_c.wdata = 0;
1966	p_vci_ini_c.be = 0;
1967	p_vci_ini_c.plen = 4;
1968	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
1969	p_vci_ini_c.trdid = 1; // cleanup instruction
1970	p_vci_ini_c.pktid = 0;
1971	p_vci_ini_c.srcid = m_srcid_c;
1972	p_vci_ini_c.cons = false;
1973	p_vci_ini_c.wrap = false;
1974	p_vci_ini_c.contig = false;
1975	p_vci_ini_c.clen = 0;
1976	p_vci_ini_c.cfixed = false;
1977	p_vci_ini_c.eop = true;
1978
1979	break;
1980
1981
1982	case CMD_DATA_CLEANUP:
1983	p_vci_ini_rw.cmdval = false;
1984	p_vci_ini_rw.address = 0;
1985	p_vci_ini_rw.wdata = 0;
1986	p_vci_ini_rw.be = 0;
1987	p_vci_ini_rw.plen = 0;
1988	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1989	p_vci_ini_rw.trdid = 0;
1990	p_vci_ini_rw.pktid = 0;
1991	p_vci_ini_rw.srcid = 0;
1992	p_vci_ini_rw.cons = false;
1993	p_vci_ini_rw.wrap = false;
1994	p_vci_ini_rw.contig = false;
1995	p_vci_ini_rw.clen = 0;
1996	p_vci_ini_rw.cfixed = false;
1997	p_vci_ini_rw.eop = false;
1998
1999	p_vci_ini_c.cmdval = true;
2000	p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
2001	p_vci_ini_c.wdata = 0;
2002	p_vci_ini_c.be = 0;
2003	p_vci_ini_c.plen = 4;
2004	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
2005	p_vci_ini_c.trdid = 0; // cleanup data
2006	p_vci_ini_c.pktid = 0;
2007	p_vci_ini_c.srcid = m_srcid_c;
2008	p_vci_ini_c.cons = false;
2009	p_vci_ini_c.wrap = false;
2010	p_vci_ini_c.contig = false;
2011	p_vci_ini_c.clen = 0;
2012	p_vci_ini_c.cfixed = false;
2013	p_vci_ini_c.eop = true;
2014
2015	break;
2016
2017	} // end switch r_vci_cmd_fsm
2018
2019	// VCI_TGT
2020
2021	switch ( r_vci_tgt_fsm.read() ) {
2022
2023	case TGT_IDLE:
2024	case TGT_UPDT_WORD:
2025	case TGT_UPDT_DATA:
2026	p_vci_tgt.cmdack = true;
2027	p_vci_tgt.rspval = false;
2028	break;
2029
2030	case TGT_RSP_BROADCAST:
2031	p_vci_tgt.cmdack = false;
2032	p_vci_tgt.rspval = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp \| r_tgt_dcache_rsp );
2033	p_vci_tgt.rsrcid = r_tgt_srcid.read();
2034	p_vci_tgt.rpktid = r_tgt_pktid.read();
2035	p_vci_tgt.rtrdid = r_tgt_trdid.read();
2036	p_vci_tgt.rdata = 0;
2037	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
2038	p_vci_tgt.reop = true;
2039	break;
2040
2041	case TGT_RSP_ICACHE:
2042	p_vci_tgt.cmdack = false;
2043	p_vci_tgt.rspval = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
2044	p_vci_tgt.rsrcid = r_tgt_srcid.read();
2045	p_vci_tgt.rpktid = r_tgt_pktid.read();
2046	p_vci_tgt.rtrdid = r_tgt_trdid.read();
2047	p_vci_tgt.rdata = 0;
2048	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
2049	p_vci_tgt.reop = true;
2050	break;
2051
2052	case TGT_RSP_DCACHE:
2053	p_vci_tgt.cmdack = false;
2054	p_vci_tgt.rspval = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
2055	p_vci_tgt.rsrcid = r_tgt_srcid.read();
2056	p_vci_tgt.rpktid = r_tgt_pktid.read();
2057	p_vci_tgt.rtrdid = r_tgt_trdid.read();
2058	p_vci_tgt.rdata = 0;
2059	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
2060	p_vci_tgt.reop = true;
2061	break;
2062
2063	case TGT_REQ_BROADCAST:
2064	case TGT_REQ_ICACHE:
2065	case TGT_REQ_DCACHE:
2066	p_vci_tgt.cmdack = false;
2067	p_vci_tgt.rspval = false;
2068	break;
2069
2070	} // end switch TGT_FSM
2071	} // end genMoore()
2072
2073	}} // end namespace
2074
2075	// Local Variables:
2076	// tab-width: 4
2077	// c-basic-offset: 4
2078	// c-file-offsets:((innamespace . 0)(inline-open . 0))
2079	// indent-tabs-mode: nil
2080	// End:
2081
2082	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2083
2084
2085
2086

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