[152] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, SoC |
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| 24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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| 29 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_CMP_H |
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| 30 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_CMP_H |
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| 31 | |
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| 32 | #include <inttypes.h> |
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| 33 | #include <fstream> |
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| 34 | #include <systemc> |
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| 35 | #include <queue> |
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| 36 | #include "caba_base_module.h" |
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| 37 | #include "multi_write_buffer.h" |
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| 38 | #include "generic_cache.h" |
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| 39 | #include "vci_initiator.h" |
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| 40 | #include "vci_target.h" |
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| 41 | #include "mapping_table.h" |
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| 42 | #include "static_assert.h" |
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| 43 | |
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| 44 | /* |
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| 45 | * ---------------------------------------------------------- |
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| 46 | * Implementation |
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| 47 | * ---------------------------------------------------------- |
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| 48 | * |
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| 49 | * CC_XCACHE_WRAPPER_FIFO_RSP |
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| 50 | * Two simple fifo (each 2x32 depth) receive the cache line from |
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| 51 | * RAM. Instead of two buffers (m_icache_words and m_dcache_words) |
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| 52 | * 1 - nb_icache+nb_dcache simple fifo |
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| 53 | * 2 - 2 simple fifo |
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| 54 | * else - two buffers (m_icache_words and m_dcache_words) |
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| 55 | * |
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| 56 | * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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| 57 | * Update cache in "2*cache_words" cycles (read+mask, write) |
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| 58 | * |
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| 59 | * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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| 60 | * Update cache with only modified data (be != 0) |
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| 61 | * |
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| 62 | * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY |
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| 63 | * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req |
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| 64 | * 1 - one access with static priority (dcache prior) |
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| 65 | * 2 - one access with static priority (icache prior) |
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| 66 | * 3 - one access with round robin priority |
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| 67 | * 4 - two access authorized |
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| 68 | * |
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| 69 | * CC_XCACHE_WRAPPER_MULTI_CACHE |
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| 70 | * 1 - icache static partitionnement |
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| 71 | * 2 - icache dedicated |
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| 72 | * |
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| 73 | * CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS |
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| 74 | * (In multi-cache) |
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| 75 | * A dcache used by a cpu and in miss_wait state can be use by |
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| 76 | * an another cpu to make a load cached access. |
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| 77 | * |
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| 78 | * CC_XCACHE_WRAPPER_STORE_AFTER_STORE |
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| 79 | * Store access in dcache (and hit) is make in two cycle : |
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| 80 | * - first read directory and read data |
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| 81 | * - second make a mask with old data and write new data. |
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| 82 | * If data part has a write enable per byte, read data access can be suppress |
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| 83 | * and we can pipeline consecutive store access. |
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| 84 | * |
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| 85 | * ---------------------------------------------------------- |
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| 86 | * Debug |
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| 87 | * ---------------------------------------------------------- |
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| 88 | * |
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| 89 | * CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 90 | * stop simulation if processor is stall after a long time |
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| 91 | * (configurable with "stop_simulation" function) |
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| 92 | * |
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| 93 | * CC_XCACHE_WRAPPER_DEBUG |
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| 94 | * Add log to help the debugging |
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| 95 | * |
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| 96 | * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN |
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| 97 | * Number of cycle before to prinf debug message |
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| 98 | * |
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| 99 | * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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| 100 | * Print transaction between : |
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| 101 | * - the cpu and the cache (icache and dcache) |
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| 102 | * - vci |
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| 103 | * - cleanup |
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| 104 | * - coherency |
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| 105 | * |
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| 106 | * MWBUF_VHDL_TESTBENCH |
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| 107 | * generate a vhdl testbench for multi write buffer |
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| 108 | */ |
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| 109 | |
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| 110 | // implementation |
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| 111 | #ifndef CC_XCACHE_WRAPPER_FIFO_RSP |
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| 112 | #define CC_XCACHE_WRAPPER_FIFO_RSP 2 |
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| 113 | #endif |
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| 114 | #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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| 115 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 |
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| 116 | #endif |
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| 117 | #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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| 118 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 |
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| 119 | #endif |
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| 120 | #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY |
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| 121 | #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 |
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| 122 | #endif |
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| 123 | #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE |
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| 124 | #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 |
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| 125 | // if multi_cache : |
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| 126 | // <tsar toplevel>/modules/vci_mem_cache_v4_cmp/caba/source/include/mem_cache_directory_v4_cmp.h : L1_MULTI_CACHE 1 |
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| 127 | // <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 |
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| 128 | #endif |
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| 129 | #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS |
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| 130 | #define CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1 |
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| 131 | #endif |
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| 132 | #ifndef CC_XCACHE_WRAPPER_STORE_AFTER_STORE |
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| 133 | #define CC_XCACHE_WRAPPER_STORE_AFTER_STORE 1 |
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| 134 | #endif |
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| 135 | |
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| 136 | // debug |
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| 137 | #ifndef CC_XCACHE_WRAPPER_VERBOSE |
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| 138 | #define CC_XCACHE_WRAPPER_VERBOSE 0 |
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| 139 | #endif |
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| 140 | #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 141 | #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 |
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| 142 | #endif |
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| 143 | #ifndef CC_XCACHE_WRAPPER_DEBUG |
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| 144 | #define CC_XCACHE_WRAPPER_DEBUG 0 |
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| 145 | #endif |
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| 146 | #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN |
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| 147 | #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 0 |
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| 148 | #endif |
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| 149 | #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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| 150 | #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 |
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| 151 | #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" |
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| 152 | #endif |
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| 153 | #ifndef MWBUF_VHDL_TESTBENCH |
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| 154 | #define MWBUF_VHDL_TESTBENCH 0 |
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| 155 | #endif |
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| 156 | |
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| 157 | // don't change |
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| 158 | #if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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| 159 | #undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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| 160 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0 |
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| 161 | #endif |
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| 162 | |
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| 163 | namespace soclib { |
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| 164 | namespace caba { |
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| 165 | |
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| 166 | using namespace sc_core; |
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| 167 | |
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| 168 | //////////////////////////////////////////// |
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| 169 | template<typename vci_param, typename iss_t> |
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| 170 | class VciCcXCacheWrapperV4_CMP |
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| 171 | /////////////////////////////////////////// |
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| 172 | : public soclib::caba::BaseModule |
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| 173 | { |
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| 174 | typedef uint64_t vhdl_tb_t; |
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| 175 | typedef sc_dt::sc_uint<40> addr_40; |
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| 176 | typedef sc_dt::sc_uint<64> data_64; |
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| 177 | typedef uint32_t data_t; |
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| 178 | typedef uint32_t tag_t; |
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| 179 | typedef uint32_t be_t; |
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| 180 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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| 181 | typedef enum |
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| 182 | { |
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| 183 | WRITE_THROUGH, |
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| 184 | RELEASE_WRITE_THROUGH |
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| 185 | } write_policy_t; |
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| 186 | |
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| 187 | enum dcache_fsm_state_e { |
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| 188 | DCACHE_IDLE, |
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| 189 | DCACHE_WRITE_UPDT, |
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| 190 | DCACHE_MISS_VICTIM, |
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| 191 | DCACHE_MISS_WAIT, |
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| 192 | DCACHE_MISS_UPDT, |
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| 193 | DCACHE_UNC_WAIT, |
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| 194 | DCACHE_SC_WAIT, |
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| 195 | DCACHE_INVAL, |
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| 196 | DCACHE_SYNC, |
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| 197 | DCACHE_ERROR, |
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| 198 | DCACHE_CC_CHECK, |
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| 199 | DCACHE_CC_INVAL, |
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| 200 | DCACHE_CC_UPDT, |
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| 201 | DCACHE_CC_CLEANUP, |
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| 202 | }; |
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| 203 | |
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| 204 | enum icache_fsm_state_e { |
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| 205 | ICACHE_IDLE, |
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| 206 | ICACHE_MISS_VICTIM, |
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| 207 | ICACHE_MISS_WAIT, |
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| 208 | ICACHE_MISS_UPDT, |
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| 209 | ICACHE_UNC_WAIT, |
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| 210 | ICACHE_ERROR, |
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| 211 | ICACHE_CC_CLEANUP, |
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| 212 | ICACHE_CC_CHECK, |
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| 213 | ICACHE_CC_INVAL, |
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| 214 | ICACHE_CC_UPDT, |
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| 215 | }; |
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| 216 | |
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| 217 | enum cmd_fsm_state_e { |
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| 218 | CMD_IDLE, |
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| 219 | CMD_INS_MISS, |
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| 220 | CMD_INS_UNC, |
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| 221 | CMD_DATA_MISS, |
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| 222 | CMD_DATA_UNC, |
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| 223 | CMD_DATA_WRITE, |
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| 224 | CMD_DATA_SC, |
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| 225 | }; |
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| 226 | |
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| 227 | enum rsp_fsm_state_e { |
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| 228 | RSP_IDLE, |
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| 229 | RSP_INS_MISS, |
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| 230 | RSP_INS_UNC, |
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| 231 | RSP_DATA_MISS, |
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| 232 | RSP_DATA_UNC, |
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| 233 | RSP_DATA_WRITE, |
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| 234 | RSP_DATA_SC, |
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| 235 | }; |
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| 236 | |
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| 237 | enum tgt_fsm_state_e { |
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| 238 | TGT_IDLE, |
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| 239 | TGT_UPDT_WORD, |
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| 240 | TGT_UPDT_DATA, |
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| 241 | TGT_REQ_BROADCAST, |
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| 242 | TGT_REQ_ICACHE, |
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| 243 | TGT_REQ_DCACHE, |
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| 244 | TGT_RSP_BROADCAST, |
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| 245 | TGT_RSP_ICACHE, |
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| 246 | TGT_RSP_DCACHE, |
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| 247 | }; |
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| 248 | |
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| 249 | enum cleanup_fsm_state_e { |
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| 250 | CLEANUP_IDLE, |
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| 251 | CLEANUP_REQ, |
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| 252 | CLEANUP_RSP_DCACHE, |
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| 253 | CLEANUP_RSP_ICACHE, |
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| 254 | }; |
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| 255 | |
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| 256 | enum transaction_type_c_e { |
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| 257 | // convention with memcache |
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| 258 | TYPE_DATA_CLEANUP = 0x0, |
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| 259 | TYPE_INS_CLEANUP = 0x1 |
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| 260 | }; |
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| 261 | |
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| 262 | enum transaction_type_rw_e { |
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| 263 | // convention with memcache |
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| 264 | // b0 : 1 if cached |
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| 265 | // b1 : 1 if instruction |
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| 266 | // b2 : 1 if sc |
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| 267 | TYPE_DATA_UNC = 0x0, |
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| 268 | TYPE_DATA_MISS = 0x1, |
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| 269 | TYPE_INS_UNC = 0x2, |
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| 270 | TYPE_INS_MISS = 0x3, |
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| 271 | TYPE_DATA_SC = 0x4, // sc is data and no cached |
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| 272 | }; |
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| 273 | |
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| 274 | public: |
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| 275 | |
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| 276 | // PORTS |
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| 277 | sc_in<bool> p_clk; |
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| 278 | sc_in<bool> p_resetn; |
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| 279 | sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq]; |
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| 280 | soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; |
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| 281 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
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| 282 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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| 283 | |
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| 284 | private: |
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| 285 | |
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| 286 | // STRUCTURAL PARAMETERS |
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| 287 | const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; |
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| 288 | const soclib::common::Segment m_segment; |
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| 289 | iss_t ** m_iss; //[m_nb_cpu] |
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| 290 | const uint32_t m_srcid_rw; |
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| 291 | const uint32_t m_srcid_c; |
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| 292 | |
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| 293 | const size_t m_nb_cpu; |
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| 294 | const size_t m_nb_icache; |
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| 295 | const size_t m_nb_dcache; |
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| 296 | const size_t m_nb_cache; |
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| 297 | const size_t m_dcache_ways; |
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| 298 | const size_t m_dcache_words; |
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| 299 | const uint32_t m_dcache_words_shift; |
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| 300 | const size_t m_dcache_yzmask; |
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| 301 | const size_t m_icache_ways; |
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| 302 | const size_t m_icache_words; |
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| 303 | const uint32_t m_icache_words_shift; |
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| 304 | const size_t m_icache_yzmask; |
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| 305 | const write_policy_t m_write_policy; |
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| 306 | const size_t m_cache_words; // max between m_dcache_words and m_icache_words |
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| 307 | |
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| 308 | #if CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 309 | bool m_stop_simulation; |
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| 310 | uint32_t m_stop_simulation_nb_frz_cycles_max; |
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| 311 | uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu] |
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| 312 | #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 313 | |
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| 314 | // REGISTERS |
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| 315 | sc_signal<uint32_t> r_cpu_prior; |
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| 316 | sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] |
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| 317 | sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] |
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| 318 | sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] |
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| 319 | |
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| 320 | sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] |
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| 321 | sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] |
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| 322 | sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] |
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| 323 | sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] |
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| 324 | sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] |
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| 325 | sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] |
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| 326 | sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] |
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| 327 | sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] |
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| 328 | sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] |
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| 329 | sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] |
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| 330 | sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] |
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| 331 | sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] |
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| 332 | sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] |
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| 333 | sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] |
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| 334 | sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] |
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| 335 | sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] |
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| 336 | sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] |
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| 337 | sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] |
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| 338 | sc_signal<data_64> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] |
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| 339 | sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] |
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| 340 | sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] |
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| 341 | sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] |
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| 342 | |
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| 343 | sc_signal<int> * r_icache_fsm; //[m_nb_icache] |
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| 344 | sc_signal<int> * r_icache_fsm_save; //[m_nb_icache] |
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| 345 | sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache] |
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| 346 | sc_signal<bool> * r_icache_miss_req; //[m_nb_icache] |
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| 347 | sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache] |
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| 348 | sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache] |
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| 349 | sc_signal<bool> * r_icache_unc_req; //[m_nb_icache] |
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| 350 | sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache] |
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| 351 | sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache] |
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| 352 | sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache] |
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| 353 | sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache] |
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| 354 | sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache] |
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| 355 | |
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| 356 | sc_signal<int> r_vci_cmd_fsm; |
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| 357 | sc_signal<size_t> r_vci_cmd_min; |
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| 358 | sc_signal<size_t> r_vci_cmd_max; |
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| 359 | sc_signal<size_t> r_vci_cmd_cpt; |
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| 360 | sc_signal<bool> r_vci_cmd_dcache_prior; |
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| 361 | sc_signal<uint32_t> r_vci_cmd_num_cache; |
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| 362 | |
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| 363 | sc_signal<int> r_vci_rsp_fsm; |
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| 364 | sc_signal<size_t> r_vci_rsp_cpt; |
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| 365 | bool s_vci_rsp_ack; |
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| 366 | sc_signal<uint32_t> r_vci_rsp_num_cache; |
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| 367 | sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] |
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| 368 | sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] |
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| 369 | |
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| 370 | #if (CC_XCACHE_WRAPPER_FIFO_RSP==1) |
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| 371 | std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache] |
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| 372 | std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache] |
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| 373 | #elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) |
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| 374 | typedef struct |
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| 375 | { |
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| 376 | data_t data; |
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| 377 | uint32_t num_cache; |
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| 378 | } miss_buf_t; |
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| 379 | |
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| 380 | std::queue<miss_buf_t> r_icache_miss_buf; |
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| 381 | std::queue<miss_buf_t> r_dcache_miss_buf; |
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| 382 | #else |
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| 383 | bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] |
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| 384 | data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words] |
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| 385 | bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words] |
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| 386 | data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words] |
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| 387 | #endif |
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| 388 | data_t * r_tgt_buf; //[m_cache_words] |
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| 389 | be_t * r_tgt_be; //[m_cache_words] |
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| 390 | #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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| 391 | sc_signal<uint32_t> r_cache_word; |
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| 392 | #endif |
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| 393 | |
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| 394 | sc_signal<int> r_vci_tgt_fsm; |
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| 395 | sc_signal<addr_40> r_tgt_iaddr; |
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| 396 | sc_signal<addr_40> r_tgt_daddr; |
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| 397 | sc_signal<size_t> r_tgt_word; |
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| 398 | sc_signal<bool> r_tgt_update; |
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| 399 | sc_signal<bool> r_tgt_update_data; |
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| 400 | //sc_signal<bool> r_tgt_brdcast; |
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| 401 | sc_signal<size_t> r_tgt_srcid; |
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| 402 | sc_signal<size_t> r_tgt_pktid; |
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| 403 | sc_signal<size_t> r_tgt_trdid; |
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| 404 | //sc_signal<size_t> r_tgt_plen; |
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| 405 | sc_signal<uint32_t> r_tgt_num_cache; |
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| 406 | sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] |
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| 407 | sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] |
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| 408 | sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] |
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| 409 | sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] |
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| 410 | |
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| 411 | sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network |
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| 412 | sc_signal<uint32_t> r_cleanup_num_cache; |
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| 413 | sc_signal<bool> r_cleanup_icache; |
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| 414 | |
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| 415 | MultiWriteBuffer<addr_40>** r_wbuf; |
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| 416 | GenericCache<vci_addr_t> ** r_icache; |
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| 417 | GenericCache<vci_addr_t> ** r_dcache; |
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| 418 | |
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| 419 | #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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| 420 | bool generate_log_transaction_file_icache; |
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| 421 | bool generate_log_transaction_file_dcache; |
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| 422 | bool generate_log_transaction_file_cmd; |
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| 423 | bool generate_log_transaction_file_tgt; |
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| 424 | bool generate_log_transaction_file_cleanup; |
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| 425 | |
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| 426 | std::ofstream * log_transaction_file_icache; //[m_nb_cpu] |
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| 427 | std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] |
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| 428 | std::ofstream log_transaction_file_cmd; |
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| 429 | std::ofstream log_transaction_file_tgt; |
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| 430 | std::ofstream log_transaction_file_cleanup; |
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| 431 | #endif |
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| 432 | |
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| 433 | #if MWBUF_VHDL_TESTBENCH |
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| 434 | bool simulation_started; |
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| 435 | bool generate_vhdl_testbench_mwbuf; |
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| 436 | std::ofstream * vhdl_testbench_mwbuf; //[m_nb_dcache] |
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| 437 | #endif |
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| 438 | |
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| 439 | // Activity counters |
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| 440 | uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ |
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| 441 | uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE |
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| 442 | uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ |
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| 443 | uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE |
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| 444 | |
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| 445 | uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ |
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| 446 | uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE |
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| 447 | uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ |
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| 448 | uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE |
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| 449 | |
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| 450 | uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) |
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| 451 | uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) |
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| 452 | uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets |
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| 453 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets |
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| 454 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets |
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| 455 | uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets |
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| 456 | uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets |
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| 457 | |
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| 458 | uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen |
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| 459 | uint32_t m_cpt_total_cycles; // total number of cycles |
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| 460 | |
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| 461 | uint32_t m_cpt_data_read; // number of data read |
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| 462 | uint32_t m_cpt_data_read_miss; // number of data read miss |
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| 463 | uint32_t m_cpt_data_read_uncached; // number of data read uncached |
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| 464 | uint32_t m_cpt_data_write; // number of data write |
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| 465 | uint32_t m_cpt_data_write_miss; // number of data write miss |
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| 466 | uint32_t m_cpt_data_write_uncached; // number of data write uncached |
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| 467 | uint32_t m_cpt_ins_miss; // * number of instruction miss |
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| 468 | |
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| 469 | uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer |
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| 470 | uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss |
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| 471 | uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read |
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| 472 | uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss |
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| 473 | |
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| 474 | uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions |
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| 475 | uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions |
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| 476 | uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions |
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| 477 | uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions |
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| 478 | |
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| 479 | uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions |
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| 480 | uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions |
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| 481 | uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions |
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| 482 | uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions |
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| 483 | uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions |
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| 484 | |
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| 485 | uint32_t * m_cpt_icache_access; //[m_nb_icache] |
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| 486 | uint32_t * m_cpt_dcache_access; //[m_nb_dcache] |
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| 487 | uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] |
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| 488 | uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] |
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| 489 | uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] |
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| 490 | uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] |
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| 491 | uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] |
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| 492 | |
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| 493 | uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] |
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| 494 | uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] |
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| 495 | uint32_t * m_cpt_fsm_cmd; |
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| 496 | uint32_t * m_cpt_fsm_rsp; |
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| 497 | uint32_t * m_cpt_fsm_tgt; |
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| 498 | uint32_t * m_cpt_fsm_cleanup; |
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| 499 | |
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| 500 | // Non blocking multi-cache |
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| 501 | typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] |
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| 502 | typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] |
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| 503 | bool * ireq_cached ; //[m_nb_icache] |
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| 504 | uint32_t * ireq_num_cpu; //[m_nb_dcache] |
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| 505 | typename iss_t::DataRequest * dreq ; //[m_nb_dcache] |
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| 506 | typename iss_t::DataResponse * drsp ; //[m_nb_dcache] |
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| 507 | bool * dreq_cached ; //[m_nb_dcache] |
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| 508 | uint32_t * dreq_num_cpu; //[m_nb_dcache] |
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| 509 | |
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| 510 | const uint32_t m_num_cache_LSB; |
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| 511 | const uint32_t m_num_cache_MSB; |
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| 512 | addr_40 m_num_cache_LSB_mask; |
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| 513 | addr_40 m_num_cache_mask; |
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| 514 | |
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| 515 | protected: |
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| 516 | SC_HAS_PROCESS(VciCcXCacheWrapperV4_CMP); |
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| 517 | |
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| 518 | public: |
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| 519 | |
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| 520 | VciCcXCacheWrapperV4_CMP( |
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| 521 | sc_module_name insname, |
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| 522 | int proc_id, |
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| 523 | const soclib::common::MappingTable &mtp, |
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| 524 | const soclib::common::MappingTable &mtc, |
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| 525 | const soclib::common::IntTab &initiator_index_rw, |
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| 526 | const soclib::common::IntTab &initiator_index_c, |
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| 527 | const soclib::common::IntTab &target_index, |
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| 528 | size_t nb_cpu, |
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| 529 | size_t nb_dcache, |
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| 530 | size_t icache_ways, |
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| 531 | size_t icache_sets, |
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| 532 | size_t icache_words, |
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| 533 | size_t dcache_ways, |
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| 534 | size_t dcache_sets, |
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| 535 | size_t dcache_words, |
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| 536 | size_t wbuf_nwords, |
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| 537 | size_t wbuf_nlines, |
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| 538 | size_t wbuf_timeout, |
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| 539 | write_policy_t write_policy=WRITE_THROUGH |
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| 540 | ); |
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| 541 | |
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| 542 | ~VciCcXCacheWrapperV4_CMP(); |
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| 543 | |
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| 544 | void print_trace(size_t mode = 0); |
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| 545 | void print_cpi(); |
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| 546 | void print_stats(bool print_wbuf=true, bool print_fsm=true); |
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| 547 | |
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| 548 | void stop_simulation (uint32_t); |
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| 549 | void log_transaction ( bool generate_file_icache |
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| 550 | ,bool generate_file_dcache |
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| 551 | ,bool generate_file_cmd |
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| 552 | ,bool generate_file_tgt |
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| 553 | ,bool generate_file_cleanup); |
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| 554 | |
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| 555 | void vhdl_testbench (bool generate_file_mwbuf); |
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| 556 | |
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| 557 | private: |
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| 558 | |
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| 559 | void transition(); |
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| 560 | void genMoore(); |
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| 561 | |
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| 562 | uint32_t get_num_cache (addr_40 & addr); |
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| 563 | uint32_t get_num_cache_only(addr_40 addr); |
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| 564 | void set_num_cache (addr_40 & addr, uint32_t num_cache); |
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| 565 | addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); |
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| 566 | |
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| 567 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
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| 568 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
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| 569 | }; |
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| 570 | |
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| 571 | }} |
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| 572 | |
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| 573 | #endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_CMP_H */ |
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| 574 | |
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| 575 | // Local Variables: |
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| 576 | // tab-width: 4 |
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| 577 | // c-basic-offset: 4 |
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| 578 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 579 | // indent-tabs-mode: nil |
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| 580 | // End: |
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| 581 | |
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| 582 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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