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Last change
on this file was
528,
checked in by lambert, 11 years ago
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Introduicing VciEthernetTsar?
This component is modified version of VciEthernet? from soclib
Main differences are :
- DMA access avoid overlapinging cache line boundaries
- Pktid is now 0x4 in write cmd
- IRQ can be reset with the status register
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File size:
425 bytes
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| 1 | This files describes the differences between vci_ethernet_tsar and |
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| 2 | vci_ethernet |
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| 3 | |
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| 4 | * Added f->wr_req->setPacket(0x4); for every Write command from vci_ethernet in |
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| 5 | order to respect overloading of vci CMD in pktid of Tsar architecture |
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| 6 | |
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| 7 | * Added overlapping detection in read and write vci CMD. First, vci CMD is now |
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| 8 | made at maximum with the boundary of a cache line (64 alignement) |
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| 9 | |
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| 10 | * Added set and reset for IRQ lines enable |
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