source: trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h

Last change on this file was 984, checked in by cfuguet, 11 years ago

bugfixes on vci_io_bridge:

Several bugfixes concerning the use of the IOMMU.

  • The control registers for the TLB prefetch buffer were either not set or set erroneously.
  • Add a new set/reset register between the WTI_RSP and the TLB FSMs. This register is used by the WTI_RSP to signal the completion of a MISS TLB transaction.
  • The MISS_WTI_CMD can issue transactions concerning a single word or an entire cache line. The first are used for WTI requests from external peripherals and the second are used for TLB MISS transactions.
  • Several programming errors concerning type casts. Some 64 bits variable were incorrectly cast and therefore, there was some information lost.
File size: 20.9 KB
Line 
1/* -*- c++ -*-
2 * File : vci_io_bridge.h
3 * Copyright (c) UPMC, Lip6, SoC
4 * Date : 16/04/2012
5 * Authors: Cassio Fraga, Alain Greiner
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: Cesar Fuguet Tortolero <cesar.fuguet-tortolero@lip6.fr>
28 */
29/////////////////////////////////////////////////////////////////////////////////
30// This TSAR component is a bridge to access external peripherals
31// connected to an external I/O bus (such as Hypertransport or PCIe).
32// It connects three VCI networks:
33//
34// - INT network : to receive both configuration requests from processors
35// or software driven data access to peripherals.
36// - RAM network : to send DMA transactions initiated by peripherals
37// directly to the RAM (or L3 caches).
38// - IOX network : to receive DMA transactions from peripherals, or to send
39// configuration or data transactions to peripherals.
40//
41// It supports two types of transactions from peripherals:
42// - DMA transactions to the RAM network,
43// - WTI transactions to the INT network.
44// Regarding transactions initiated by external peripherals, it provides
45// an - optional - IOMMU service : the 32 bits virtual address is translated
46// to a (up to) 40 bits physical address by a standard SoCLib generic TLB.
47// In case of TLB MISS, the DMA transaction is stalled until the TLB is updated.
48// In case of page fault or read_only violation (illegal access), a VCI error
49// is returned to the faulty peripheral, and a IOMMU WTI is sent.
50/////////////////////////////////////////////////////////////////////////////////
51// General Constraints:
52//
53// - All VCI fields have the same widths on the RAM and IOX networks,
54// and the VCI DATA field is 64 bits.
55// - Only the VCI DATA field differ between INT and IOX/RAM networks,
56// as the VCI DATA field is 32 bits.
57// - The common VCI ADDRESS width cannot be larger than 64 bits.
58// - All VCI transactions must be included in a single cache line.
59// - Page Tables must have the format required by the SoCLib generic_tlb.
60// - IO's segments must be the same in INT and IOX networks
61// - Write operations on IOMMU configuration registers (PTPR, ACTIVE) are
62// delayed until DMA_TLB FSM is IDLE. It should, preferably, be done before
63// starting any transfers. Pseudo register INVAL may be modified any time.
64////////////////////////////////////////////////////////////////////////////////
65
66
67///////TODO List///////////////////////////////////////////////////////////////
68// - Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit
69// (seulement 'data' et 'be')
70///////////////////////////////////////////////////////////////////////////////
71
72#ifndef SOCLIB_CABA_VCI_IO_BRIDGE_H
73#define SOCLIB_CABA_VCI_IO_BRIDGE_H
74
75#include <inttypes.h>
76#include <systemc>
77#include "caba_base_module.h"
78#include "generic_fifo.h"
79#include "generic_tlb.h"
80#include "mapping_table.h"
81#include "address_decoding_table.h"
82#include "address_masking_table.h"
83#include "static_assert.h"
84#include "vci_initiator.h"
85#include "vci_target.h"
86#include "transaction_tab_io.h"
87#include "../../../include/soclib/io_bridge.h"
88
89namespace soclib {
90namespace caba {
91
92using namespace soclib::common;
93
94///////////////////////////////////////////////////////////////////////////////////
95template<typename vci_param_int,
96 typename vci_param_ext>
97class VciIoBridge
98///////////////////////////////////////////////////////////////////////////////////
99 : public soclib::caba::BaseModule
100{
101 // Data and be fields have different widths on INT and EXT/IOC networks
102 typedef typename vci_param_ext::data_t ext_data_t;
103 typedef typename vci_param_int::data_t int_data_t;
104 typedef typename vci_param_ext::be_t ext_be_t;
105 typedef typename vci_param_int::be_t int_be_t;
106
107 // Other fields must be equal
108 typedef typename vci_param_int::fast_addr_t vci_addr_t;
109 typedef typename vci_param_int::srcid_t vci_srcid_t;
110 typedef typename vci_param_int::trdid_t vci_trdid_t;
111 typedef typename vci_param_int::pktid_t vci_pktid_t;
112 typedef typename vci_param_int::plen_t vci_plen_t;
113 typedef typename vci_param_int::cmd_t vci_cmd_t;
114 typedef typename vci_param_int::contig_t vci_contig_t;
115 typedef typename vci_param_int::eop_t vci_eop_t;
116 typedef typename vci_param_int::const_t vci_cons_t;
117 typedef typename vci_param_int::wrap_t vci_wrap_t;
118 typedef typename vci_param_int::clen_t vci_clen_t;
119 typedef typename vci_param_int::cfixed_t vci_cfixed_t;
120 typedef typename vci_param_int::rerror_t vci_rerror_t;
121
122 enum
123 {
124 CACHE_LINE_MASK = 0xFFFFFFFFC0ULL,
125 PPN1_MASK = 0x0007FFFF,
126 PPN2_MASK = 0x0FFFFFFF,
127 K_PAGE_OFFSET_MASK = 0x00000FFF,
128 M_PAGE_OFFSET_MASK = 0x001FFFFF,
129 PTE2_LINE_OFFSET = 0x00007000, // bits 12,13,14.
130 PTE1_LINE_OFFSET = 0x01E00000, // bits 21,22,23,24
131 };
132
133 // States for DMA_CMD FSM (from IOX to RAM)
134 enum dma_cmd_fsm_state
135 {
136 DMA_CMD_IDLE,
137 DMA_CMD_DMA_REQ,
138 DMA_CMD_WTI_IOX_REQ,
139 DMA_CMD_ERR_WAIT_EOP,
140 DMA_CMD_ERR_WTI_REQ,
141 DMA_CMD_ERR_RSP_REQ,
142 DMA_CMD_TLB_MISS_WAIT,
143 };
144
145 // States for DMA_RSP FSM
146 enum dma_rsp_fsm_state
147 {
148 DMA_RSP_IDLE_DMA,
149 DMA_RSP_IDLE_WTI,
150 DMA_RSP_IDLE_ERR,
151 DMA_RSP_PUT_DMA,
152 DMA_RSP_PUT_WTI,
153 DMA_RSP_PUT_ERR,
154 };
155
156 // States for TLB_MISS FSM
157 enum dma_tlb_fsm_state
158 {
159 TLB_IDLE,
160 TLB_MISS,
161 TLB_PTE1_GET,
162 TLB_PTE1_SELECT,
163 TLB_PTE1_UPDT,
164 TLB_PTE2_GET,
165 TLB_PTE2_SELECT,
166 TLB_PTE2_UPDT,
167 TLB_WAIT,
168 TLB_RETURN,
169 TLB_INVAL_CHECK,
170 };
171
172 // States for CONFIG_CMD FSM
173 enum config_cmd_fsm_state
174 {
175 CONFIG_CMD_IDLE,
176 CONFIG_CMD_WAIT,
177 CONFIG_CMD_HI,
178 CONFIG_CMD_LO,
179 CONFIG_CMD_PUT,
180 CONFIG_CMD_RSP,
181 };
182
183 // states for CONFIG_RSP FSM
184 enum config_rsp_fsm_state
185 {
186 CONFIG_RSP_IDLE_IOX,
187 CONFIG_RSP_IDLE_LOC,
188 CONFIG_RSP_PUT_LO,
189 CONFIG_RSP_PUT_HI,
190 CONFIG_RSP_PUT_UNC,
191 CONFIG_RSP_PUT_LOC,
192
193 };
194
195 // States for MISS_WTI_RSP FSM
196 enum miss_wti_rsp_state
197 {
198 MISS_WTI_RSP_IDLE,
199 MISS_WTI_RSP_WTI_IOX,
200 MISS_WTI_RSP_WTI_MMU,
201 MISS_WTI_RSP_MISS,
202 };
203
204 // PKTID values for TLB MISS and WTI transactions
205 enum pktid_values_e
206 {
207 PKTID_MISS = 0x0, // TSAR code for read data uncached
208 PKTID_WTI_IOX = 0x4, // TSAR code for write
209 PKTID_WTI_MMU = 0xC, // TSAR code for write
210 };
211
212 // Miss types for iotlb
213 enum tlb_miss_type_e
214 {
215 PTE1_MISS,
216 PTE2_MISS,
217 };
218
219public:
220 sc_in<bool> p_clk;
221 sc_in<bool> p_resetn;
222
223 soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_ram;
224
225 soclib::caba::VciTarget<vci_param_ext> p_vci_tgt_iox;
226 soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_iox;
227
228 soclib::caba::VciTarget<vci_param_int> p_vci_tgt_int;
229 soclib::caba::VciInitiator<vci_param_int> p_vci_ini_int;
230
231private:
232 const size_t m_words;
233
234 // INT & IOX Networks
235 std::list<soclib::common::Segment> m_int_seglist;
236 const vci_srcid_t m_int_srcid; // SRCID on INT network
237 std::list<soclib::common::Segment> m_iox_seglist;
238 const vci_srcid_t m_iox_srcid; // SRCID on IOX network
239
240 // INT & RAM srcid masking table
241 const AddressMaskingTable<uint32_t> m_srcid_gid_mask;
242 const AddressMaskingTable<uint32_t> m_srcid_lid_mask;
243
244 // TLB parameters
245 const size_t m_iotlb_ways;
246 const size_t m_iotlb_sets;
247
248 // debug variables
249 uint32_t m_debug_start_cycle;
250 bool m_debug_ok;
251 bool m_debug_activated;
252
253 ///////////////////////////////
254 // MEMORY MAPPED REGISTERS
255 ///////////////////////////////
256 sc_signal<uint32_t> r_iommu_ptpr; // page table pointer
257 sc_signal<bool> r_iommu_active; // iotlb mode
258 sc_signal<uint32_t> r_iommu_bvar; // bad vaddr
259 sc_signal<uint32_t> r_iommu_etr; // error type
260 sc_signal<uint32_t> r_iommu_bad_id; // faulty srcid
261 sc_signal<bool> r_iommu_wti_enable; // enable IOB WTI
262 sc_signal<uint32_t> r_iommu_wti_addr_lo; // IOMMU WTI paddr (32 lsb)
263 sc_signal<uint32_t> r_iommu_wti_addr_hi; // IOMMU WTI paddr (32 msb)
264
265 ///////////////////////////////////
266 // DMA_CMD FSM REGISTERS
267 ///////////////////////////////////
268 sc_signal<int> r_dma_cmd_fsm;
269 sc_signal<vci_addr_t> r_dma_cmd_paddr; // output paddr
270
271 sc_signal<bool> r_dma_cmd_to_miss_wti_cmd_req;
272 sc_signal<vci_addr_t> r_dma_cmd_to_miss_wti_cmd_addr;
273 sc_signal<vci_cmd_t> r_dma_cmd_to_miss_wti_cmd_cmd;
274 sc_signal<vci_srcid_t> r_dma_cmd_to_miss_wti_cmd_srcid;
275 sc_signal<vci_trdid_t> r_dma_cmd_to_miss_wti_cmd_trdid;
276 sc_signal<vci_trdid_t> r_dma_cmd_to_miss_wti_cmd_pktid;
277 sc_signal<int_data_t> r_dma_cmd_to_miss_wti_cmd_wdata;
278
279 sc_signal<bool> r_dma_cmd_to_dma_rsp_req;
280 sc_signal<vci_srcid_t> r_dma_cmd_to_dma_rsp_rsrcid;
281 sc_signal<vci_trdid_t> r_dma_cmd_to_dma_rsp_rtrdid;
282 sc_signal<vci_pktid_t> r_dma_cmd_to_dma_rsp_rpktid;
283 sc_signal<vci_rerror_t> r_dma_cmd_to_dma_rsp_rerror;
284 sc_signal<ext_data_t> r_dma_cmd_to_dma_rsp_rdata;
285
286 sc_signal<bool> r_dma_cmd_to_tlb_req;
287 sc_signal<uint32_t> r_dma_cmd_to_tlb_vaddr; // input vaddr
288
289 ///////////////////////////////////
290 // DMA_RSP FSM REGISTERS
291 ///////////////////////////////////
292 sc_signal<int> r_dma_rsp_fsm;
293
294 ///////////////////////////////////
295 // CONFIG_CMD FSM REGISTERS
296 ///////////////////////////////////
297 sc_signal<int> r_config_cmd_fsm;
298
299 sc_signal<bool> r_config_cmd_to_tlb_req;
300 sc_signal<uint32_t> r_config_cmd_to_tlb_vaddr;
301
302 sc_signal<bool> r_config_cmd_to_config_rsp_req;
303 sc_signal<bool> r_config_cmd_to_config_rsp_rerror;
304 sc_signal<int_data_t> r_config_cmd_to_config_rsp_rdata;
305 sc_signal<vci_srcid_t> r_config_cmd_to_config_rsp_rsrcid;
306 sc_signal<vci_trdid_t> r_config_cmd_to_config_rsp_rtrdid;
307 sc_signal<vci_pktid_t> r_config_cmd_to_config_rsp_rpktid;
308
309 sc_signal<ext_data_t> r_config_cmd_wdata;
310 sc_signal<ext_be_t> r_config_cmd_be;
311 sc_signal<vci_plen_t> r_config_cmd_cmd;
312 sc_signal<vci_addr_t> r_config_cmd_address;
313 sc_signal<vci_srcid_t> r_config_cmd_srcid;
314 sc_signal<vci_trdid_t> r_config_cmd_trdid;
315 sc_signal<vci_pktid_t> r_config_cmd_pktid;
316 sc_signal<vci_plen_t> r_config_cmd_plen;
317 sc_signal<vci_clen_t> r_config_cmd_clen;
318 sc_signal<vci_cons_t> r_config_cmd_cons;
319 sc_signal<vci_contig_t> r_config_cmd_contig;
320 sc_signal<vci_cfixed_t> r_config_cmd_cfixed;
321 sc_signal<vci_wrap_t> r_config_cmd_wrap;
322 sc_signal<vci_eop_t> r_config_cmd_eop;
323
324 TransactionTabIO m_iox_transaction_tab;
325
326 ///////////////////////////////////
327 // CONFIG_RSP FSM REGISTERS
328 ///////////////////////////////////
329 sc_signal<int> r_config_rsp_fsm;
330 sc_signal<vci_srcid_t> r_config_rsp_rsrcid;
331 sc_signal<vci_trdid_t> r_config_rsp_rtrdid;
332
333 ///////////////////////////////////
334 // TLB FSM REGISTERS
335 ///////////////////////////////////
336 sc_signal<int> r_tlb_fsm; // state register
337 sc_signal<bool> r_waiting_transaction; // Flag for returning from
338 sc_signal<int> r_tlb_miss_type;
339 sc_signal<bool> r_tlb_miss_error;
340
341 sc_signal<vci_addr_t> r_tlb_paddr; // physical address of pte
342 sc_signal<uint32_t> r_tlb_pte_flags; // pte1 or first word of pte2
343 sc_signal<uint32_t> r_tlb_pte_ppn; // second word of pte2
344 sc_signal<size_t> r_tlb_way; // selected way in tlb
345 sc_signal<size_t> r_tlb_set; // selected set in tlb
346
347 uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs
348 sc_signal<bool> r_tlb_buf_valid; // one valit flag for all PTEs
349 sc_signal<vci_addr_t> r_tlb_buf_tag; // cache line number
350 sc_signal<vci_addr_t> r_tlb_buf_vaddr; // vaddr for first PTE
351 sc_signal<bool> r_tlb_buf_big_page; // ???
352
353 sc_signal<bool> r_tlb_to_miss_wti_cmd_req;
354
355 ///////////////////////////////////
356 // MISS_WTI_RSP FSM REGISTERS
357 ///////////////////////////////////
358 sc_signal<int> r_miss_wti_rsp_fsm;
359 sc_signal<bool> r_miss_wti_rsp_error_wti; // VCI error on WTI
360 sc_signal<bool> r_miss_wti_rsp_error_miss; // VCI error on MISS
361 sc_signal<size_t> r_miss_wti_rsp_count; // flits counter
362
363 sc_signal<bool> r_miss_wti_rsp_to_dma_rsp_req;
364 sc_signal<vci_rerror_t> r_miss_wti_rsp_to_dma_rsp_rerror;
365 sc_signal<vci_srcid_t> r_miss_wti_rsp_to_dma_rsp_rsrcid;
366 sc_signal<vci_trdid_t> r_miss_wti_rsp_to_dma_rsp_rtrdid;
367 sc_signal<vci_pktid_t> r_miss_wti_rsp_to_dma_rsp_rpktid;
368
369 sc_signal<bool> r_miss_wti_rsp_to_tlb_done;
370
371 /////////////////////////////////////////////////////
372 // ALLOCATORS for CONFIG_RSP fifo & DMA_RSP fifo
373 /////////////////////////////////////////////////////
374 sc_signal<bool> r_alloc_fifo_config_rsp_local;
375
376
377 //////////////////////////////////////////////////////////////////
378 // IOTLB
379 //////////////////////////////////////////////////////////////////
380 GenericTlb<vci_addr_t> r_iotlb;
381
382
383 /////////////////////////
384 // FIFOs
385 /////////////////////////
386
387 // ouput FIFO to VCI INI port on RAM network (VCI command)
388 GenericFifo<vci_addr_t> m_dma_cmd_addr_fifo;
389 GenericFifo<vci_srcid_t> m_dma_cmd_srcid_fifo;
390 GenericFifo<vci_trdid_t> m_dma_cmd_trdid_fifo;
391 GenericFifo<vci_pktid_t> m_dma_cmd_pktid_fifo;
392 GenericFifo<ext_be_t> m_dma_cmd_be_fifo;
393 GenericFifo<vci_cmd_t> m_dma_cmd_cmd_fifo;
394 GenericFifo<vci_contig_t> m_dma_cmd_contig_fifo;
395 GenericFifo<ext_data_t> m_dma_cmd_data_fifo;
396 GenericFifo<vci_eop_t> m_dma_cmd_eop_fifo;
397 GenericFifo<vci_cons_t> m_dma_cmd_cons_fifo;
398 GenericFifo<vci_plen_t> m_dma_cmd_plen_fifo;
399 GenericFifo<vci_wrap_t> m_dma_cmd_wrap_fifo;
400 GenericFifo<vci_cfixed_t> m_dma_cmd_cfixed_fifo;
401 GenericFifo<vci_clen_t> m_dma_cmd_clen_fifo;
402
403 // output FIFO to VCI TGT port on IOX network (VCI response)
404 GenericFifo<ext_data_t> m_dma_rsp_data_fifo;
405 GenericFifo<vci_srcid_t> m_dma_rsp_rsrcid_fifo;
406 GenericFifo<vci_trdid_t> m_dma_rsp_rtrdid_fifo;
407 GenericFifo<vci_pktid_t> m_dma_rsp_rpktid_fifo;
408 GenericFifo<vci_eop_t> m_dma_rsp_reop_fifo;
409 GenericFifo<vci_rerror_t> m_dma_rsp_rerror_fifo;
410
411 // output FIFO to VCI INI port on IOX network (VCI command)
412 GenericFifo<vci_addr_t> m_config_cmd_addr_fifo;
413 GenericFifo<vci_srcid_t> m_config_cmd_srcid_fifo;
414 GenericFifo<vci_trdid_t> m_config_cmd_trdid_fifo;
415 GenericFifo<vci_pktid_t> m_config_cmd_pktid_fifo;
416 GenericFifo<ext_be_t> m_config_cmd_be_fifo;
417 GenericFifo<vci_cmd_t> m_config_cmd_cmd_fifo;
418 GenericFifo<vci_contig_t> m_config_cmd_contig_fifo;
419 GenericFifo<ext_data_t> m_config_cmd_data_fifo;
420 GenericFifo<vci_eop_t> m_config_cmd_eop_fifo;
421 GenericFifo<vci_cons_t> m_config_cmd_cons_fifo;
422 GenericFifo<vci_plen_t> m_config_cmd_plen_fifo;
423 GenericFifo<vci_wrap_t> m_config_cmd_wrap_fifo;
424 GenericFifo<vci_cfixed_t> m_config_cmd_cfixed_fifo;
425 GenericFifo<vci_clen_t> m_config_cmd_clen_fifo;
426
427 // output FIFO to VCI TGT port on INT network (VCI response)
428 GenericFifo<int_data_t> m_config_rsp_data_fifo;
429 GenericFifo<vci_srcid_t> m_config_rsp_rsrcid_fifo;
430 GenericFifo<vci_trdid_t> m_config_rsp_rtrdid_fifo;
431 GenericFifo<vci_pktid_t> m_config_rsp_rpktid_fifo;
432 GenericFifo<vci_eop_t> m_config_rsp_reop_fifo;
433 GenericFifo<vci_rerror_t> m_config_rsp_rerror_fifo;
434
435 // output FIFO to VCI_INI port on INT network (VCI command)
436 GenericFifo<vci_addr_t> m_miss_wti_cmd_addr_fifo;
437 GenericFifo<vci_srcid_t> m_miss_wti_cmd_srcid_fifo;
438 GenericFifo<vci_trdid_t> m_miss_wti_cmd_trdid_fifo;
439 GenericFifo<vci_pktid_t> m_miss_wti_cmd_pktid_fifo;
440 GenericFifo<int_be_t> m_miss_wti_cmd_be_fifo;
441 GenericFifo<vci_cmd_t> m_miss_wti_cmd_cmd_fifo;
442 GenericFifo<vci_contig_t> m_miss_wti_cmd_contig_fifo;
443 GenericFifo<int_data_t> m_miss_wti_cmd_data_fifo;
444 GenericFifo<vci_eop_t> m_miss_wti_cmd_eop_fifo;
445 GenericFifo<vci_cons_t> m_miss_wti_cmd_cons_fifo;
446 GenericFifo<vci_plen_t> m_miss_wti_cmd_plen_fifo;
447 GenericFifo<vci_wrap_t> m_miss_wti_cmd_wrap_fifo;
448 GenericFifo<vci_cfixed_t> m_miss_wti_cmd_cfixed_fifo;
449 GenericFifo<vci_clen_t> m_miss_wti_cmd_clen_fifo;
450
451 ////////////////////////////////
452 // Activity counters
453 ////////////////////////////////
454
455 uint32_t m_cpt_total_cycles; // total number of cycles
456
457 // TLB activity counters
458 uint32_t m_cpt_iotlb_read; // number of iotlb read
459 uint32_t m_cpt_iotlb_miss; // number of iotlb miss
460 uint32_t m_cost_iotlb_miss; // number of wait cycles (not treatment itself)
461 uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions
462 uint32_t m_cost_iotlbmiss_transaction; // cumulated duration tlb miss transactions
463
464 //Transaction Tabs (TRTs) activity counters
465 uint32_t m_cpt_trt_dma_full; // DMA TRT full when a new command arrives
466 uint32_t m_cpt_trt_dma_full_cost; // total number of cycles blocked
467 uint32_t m_cpt_trt_config_full; // Config TRT full when a new command arrives
468 uint32_t m_cpt_trt_config_full_cost; // total number of cycles blocked
469
470 // FSM activity counters
471 // unused on print_stats
472 uint32_t m_cpt_fsm_dma_cmd [32];
473 uint32_t m_cpt_fsm_dma_rsp [32];
474 uint32_t m_cpt_fsm_tlb [32];
475 uint32_t m_cpt_fsm_config_cmd [32];
476 uint32_t m_cpt_fsm_config_rsp [32];
477 uint32_t m_cpt_fsm_miss_wti_rsp [32];
478
479protected:
480
481 SC_HAS_PROCESS(VciIoBridge);
482
483public:
484
485 VciIoBridge(
486 sc_module_name insname,
487 const soclib::common::MappingTable &mt_ext, // external network
488 const soclib::common::MappingTable &mt_int, // internal network
489 const soclib::common::MappingTable &mt_iox, // iox network
490 const soclib::common::IntTab &int_tgtid, // INT network TGTID
491 const soclib::common::IntTab &int_srcid, // INT network SRCID
492 const soclib::common::IntTab &iox_tgtid, // IOX network TGTID
493 const soclib::common::IntTab &iox_srcid, // IOX network SRCID
494 const size_t dcache_words,
495 const size_t iotlb_ways,
496 const size_t iotlb_sets,
497 const uint32_t debug_start_cycle,
498 const bool debug_ok );
499
500 ~VciIoBridge();
501
502 void print_stats();
503 void clear_stats();
504 void print_trace(size_t mode = 0);
505
506
507private:
508
509 bool is_wti( vci_addr_t paddr );
510 void transition();
511 void genMoore();
512};
513
514}}
515
516#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */
517
518// Local Variables:
519// tab-width: 4
520// c-basic-offset: 4
521// c-file-offsets:((innamespace . 0)(inline-open . 0))
522// indent-tabs-mode: nil
523// End:
524
525// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
526
527
528
529
Note: See TracBrowser for help on using the repository browser.